A pn junction gate gallium oxide based modfet device and a method of manufacturing the same

Abstract

The application discloses a PN junction gate gallium oxide-based MODFET device and a preparation method thereof, which sequentially comprises a substrate, a channel layer, a spacer layer, a delta-doped layer and a barrier layer, and further comprises: a first ohmic contact area arranged on one side of end surfaces of the spacer layer, the delta-doped layer and the barrier layer; a second ohmic contact area arranged on the other side of the end surfaces of the spacer layer, the delta-doped layer and the barrier layer; the height of the first ohmic contact area and the second ohmic contact area is higher than the upper surface of the barrier layer; a PN junction structure arranged on part of the surface of the barrier layer; a dielectric layer structure arranged above the barrier layer, the PN junction structure, the first ohmic contact area and the second ohmic contact area; a source electrode arranged on the first ohmic contact area; a drain electrode arranged on the second ohmic contact area; and a gate electrode arranged on the PN junction structure and the dielectric layer structure, wherein the upper end of the gate electrode extends to both ends of the dielectric layer structure above the PN junction structure to form a field plate structure. The application can improve the reliability of the device.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor power devices and manufacturing technology, and particularly relates to a PN junction gate gallium oxide-based MODFET device and a preparation method thereof. BACKGROUND

[0002] Beta-phase gallium oxide (Ga2O3) is one of the most promising materials for next-generation power devices due to its wide bandgap (4.6-4.9 eV), high breakdown field (8 MV / cm) and high electron saturation velocity (1.8-2 x 10 7 cm / s). Due to the low mobility of gallium oxide, their channel mobility is limited. Modulation doped field effect transistor (MODFET) generates a modulation-doped two-dimensional electron gas (2DEG) at the beta-AlGa2O3 / Ga2O3 heterojunction through silicon delta doping, which significantly improves the channel mobility. Due to the presence of 2DEG, MODFET usually presents a constant on state, i.e. a depletion mode device, which is not conducive to the application of power devices. Enhancement mode devices do not require additional gate electrode negative voltage to turn off the device, which can significantly reduce the static power consumption and switching loss of the circuit in the off state. And because the performance of gallium oxide devices is excellent under high power conditions, they are often used in high output power application environments, which require constant off operation for safety and simplification of the driver circuit, so it is very important and meaningful to study and manufacture enhancement gallium oxide devices with excellent performance and reliability. With the increasing complexity of device design and the increasing integration, the energy saving and design simplicity of enhancement mode devices are becoming more and more prominent.

[0003] Since the P-type doping of gallium oxide has not been achieved effectively, the design of the current normally-off device is mainly through introducing P-type material or introducing a recessed gate structure. The P-type gate electrode structure normally-off device formed by P-type material (such as P-type gallium nitride) will cause the failure of the Schottky junction at high electric field, which will cause the sharp increase of the gate current due to the high tunneling current and the generation of defects under the Schottky depletion region at high electric field, thereby resulting in a lower gate breakdown voltage. The normally-off device formed by designing a recessed gate electrode structure, the etching process in the recessed gate technology can cause the degradation of the material surface quality, which can cause the device performance to decrease, such as increasing the gate leakage current and reducing the reliability of the device. With the increase of the depth of the recessed gate, the electric field peak of the area under the gate is enhanced, which can cause the device degradation at high electric field and the gate breakdown problem. The small gate breakdown voltage of the device will limit the gate drive voltage of the device, the small gate voltage swing will limit the application of the device. The existing means to realize the enhancement mode device all have obvious defects, which seriously hinder the practical application of the device, and need to be effectively solved. The breakthrough of this problem can greatly promote the gallium oxide device to enter the practical application stage faster and more widely, and promote the rapid development of the new material semiconductor industry in China. SUMMARY

[0004] Therefore, the purpose of the present application is to provide a PN junction gate gallium oxide based MODFET device which is reliable and can effectively reduce the gate leakage current and improve the gate breakdown voltage and the reliability of the device.

[0005] In order to achieve the above technical purpose, the technical scheme adopted by the present application is:

[0006] A PN junction gate gallium oxide based MODFET device comprises, from bottom to top, a substrate, a channel layer, a spacer layer, a delta-doped layer and a barrier layer, and further comprises:

[0007] A first ohmic contact region is arranged on one side of the end surface of the spacer layer, the delta-doped layer and the barrier layer;

[0008] A second ohmic contact region is arranged on the other side of the end surface of the spacer layer, the delta-doped layer and the barrier layer; the height of the first ohmic contact region and the second ohmic contact region is higher than the upper surface of the barrier layer;

[0009] A PN junction structure is arranged on part of the surface of the barrier layer;

[0010] A dielectric layer structure is arranged above the barrier layer, the PN junction structure, the first ohmic contact region and the second ohmic contact region;

[0011] A source electrode is arranged on the first ohmic contact region;

[0012] a drain electrode disposed on the second ohmic contact region;

[0013] a gate electrode disposed on the PN junction structure and the dielectric layer structure, a metal of an upper end of the gate electrode extending to both ends of the dielectric layer structure above the PN junction structure to form a field plate structure.

[0014] Further, the PN junction structure comprises a P-type gallium nitride layer and an N-type gallium nitride layer, the P-type gallium nitride layer is disposed on a part of the surface of the barrier layer, an upper surface of the P-type gallium nitride layer is provided with an intermediate groove, and the N-type gallium nitride layer is disposed in the intermediate groove on the upper surface of the P-type gallium nitride layer.

[0015] Further, the dielectric layer structure comprises a first dielectric layer and a second dielectric layer, the first dielectric layer is disposed on an upper surface of the first ohmic contact region and an upper surface of the barrier layer between a right end of the first ohmic contact region and a left end surface of the PN junction structure, and the second dielectric layer is disposed on an upper surface of the second ohmic contact region and an upper surface of the barrier layer between a left end of the second ohmic contact region and a right end surface of the PN junction structure, the first dielectric layer and the second dielectric layer extend upward near the side surface of the PN junction structure to cover the upper surface of the P-type gallium nitride layer of the PN junction structure.

[0016] Further, a distance between the PN junction structure and the first ohmic contact region is less than a distance between the PN junction structure and the second ohmic contact region.

[0017] Further, the width of the substrate and the channel layer is equal, the width of the spacer layer, the delta-doped layer and the barrier layer is equal, and the width of the channel layer is greater than the width of the spacer layer; the width of the upper end of the gate electrode is equal to a distance between left and right edges of the dielectric layer structure above the PN junction structure.

[0018] Further, the substrate is high-resistance or semi-insulating β-Ga2O3, and the type of the doping element includes any one of Mg, Fe, Zn, N and P; the doping concentration is 1×10 18 ~ 5×10 18 / cm -3 ;

[0019] The channel layer is an unintentionally doped β-Ga2O3 channel layer.

[0020] The spacer layer is an N-type doped β-(AlGa)2O3, the type of the doping element includes any one of Si, Sn and Ge, and the doping concentration is 1×10 18 ~ 5×10 18 / cm -3 , and the Al component is 0.15~0.3.

[0021] The delta-doped layer is N-type doped β-(AlGa)2O3, the doping element type includes Si, and the doping concentration is 1×10 19 ~5×10 19 / cm -3 , and the Al component is 0.15~0.3.

[0022] The barrier layer is N-type doped β-(AlGa)2O3, the doping element type includes any one of Si, Sn and Ge, and the doping concentration is 1×10 18 ~5×10 18 / cm -3 , and the Al component is 0.15~0.3.

[0023] The first and second ohmic contact regions are both N-type heavily doped β-Ga2O3, the doping element type includes any one of Si, Sn and Ge, and the doping concentration is about 1×10 20 ~5×10 20 cm -3 .

[0024] The P-type gallium nitride layer in the PN junction structure is P-type doped, the doping element type includes Mg, and the doping concentration is 1×10 18 ~5×10 19 / cm -3 ; and the N-type gallium nitride layer is N-type doped, the doping element type includes any one of Si, Sn and Ge, and the doping concentration is 1×10 18 ~2×10 19 / cm -3 .

[0025] The dielectric layer structure is formed by any one of Al2O3, SiO2, Si3N4 and HfO2;

[0026] The source electrode and the drain electrode are both formed by two metal layers combined by any one of Ni, Ti and Al and Au;

[0027] The gate electrode is formed by two metal layers of Ni and Au or two metal layers of Ti and Au.

[0028] Further, the thickness of the substrate is 250~600um;

[0029] The thickness of the channel layer is 150~360nm;

[0030] The thickness of the spacer layer is 3~8nm;

[0031] The thickness of the delta-doped layer is 1~2nm;

[0032] The thickness of the barrier layer is 15-30nm;

[0033] The thickness of the medium layer structure is 2-5nm;

[0034] The thickness of the P-type gallium nitride layer in the PN junction structure is 20-100nm, and the thickness of the N-type gallium nitride layer is 10-40nm;

[0035] The thickness of the first ohmic contact region and the second ohmic contact region is 50-100nm.

[0036] The application further provides a preparation method of the PN junction gate gallium oxide-based MODFET device.

[0037] In order to achieve the above technical purposes, the technical scheme adopted by the application is:

[0038] A preparation method of a PN junction gate gallium oxide-based MODFET device is based on the above-mentioned PN junction gate gallium oxide-based MODFET device, and specifically includes the following steps:

[0039] Step 1, pretreating the surface of the substrate in a reaction chamber;

[0040] Step 2, growing a channel layer on the upper surface of the substrate by homoepitaxy;

[0041] Step 3, growing a spacer layer on the upper surface of the channel layer by heteroepitaxy;

[0042] Step 4, growing a delta-doped layer and a barrier layer on the upper surface of the spacer layer by homoepitaxy from bottom to top;

[0043] Step 5, etching both ends of the barrier layer, and continuing to etch both ends of the delta-doped layer and the spacer layer along the etching direction until the upper surface of the channel layer is formed into two first grooves, growing a first ohmic contact region on the first groove at the left end, and growing a second ohmic contact region on the first groove at the right end;

[0044] Step 6, patterning and growing a PN junction structure in the middle of the upper surface of the barrier layer;

[0045] Step 7, depositing a medium layer structure on the surfaces of the barrier layer, the PN junction structure, the first ohmic contact region and the second ohmic contact region, and etching the upper surfaces of the left and right ends and the middle part of the medium layer structure respectively to leave out a second groove, a third groove and a fourth groove for a source electrode, a drain electrode and a gate electrode;

[0046] Step 8, depositing a source electrode on the second groove, and depositing a drain electrode on the third groove;

[0047] Step 9, depositing a gate electrode on the fourth groove to form a field plate structure on the surface of the PN junction structure.

[0048] Further, the step 6 is specifically: the PN junction structure comprises a P-type gallium nitride layer and an N-type gallium nitride layer, the P-type gallium nitride layer is grown on the surface of the barrier layer in a middle pattern, the patterned photoresist is formed by coating photoresist on the surface of the P-type gallium nitride layer, exposing and developing the photoresist to form a patterned photoresist, and etching the P-type gallium nitride layer to form a middle groove in the middle; the N-type gallium nitride layer is grown on the surface of the P-type gallium nitride layer in the middle groove, and the growth height of the N-type gallium nitride layer is flush with the surface of the P-type gallium nitride layer.

[0049] Further, the method for pretreating the surface of the substrate in the step 1 is standard RCA cleaning: the substrate is heated before starting growth to remove impurities adsorbed on the substrate; and the method for epitaxial growth adopts one of MOCVD, MBE and ALD.

[0050] By using the technical solution, the present application has the following beneficial effects compared with the prior art:

[0051] The present application inserts the PN junction structure with the field plate embedded between the gate electrode and the barrier layer, significantly improves the gate breakdown voltage of the device, and improves the gate reliability of the device. The P-type gallium nitride layer can deplete electrons, effectively block the 2DEG channel below, and the N-type gallium nitride layer and the P-type gallium nitride layer form a PN junction to generate a built-in electric field to regulate the depletion layer. When the gate electrode is forward biased, the PN junction is reverse biased, and the 2DEG channel below is depleted, which suppresses the diffusion of carriers, realizes the right shift of the threshold voltage, and because the PN junction depletion region extends to the N side and the P side, the device exhibits lower gate leakage current. The PN junction can withstand higher reverse bias under the same peak electric field, thereby improving the gate breakdown voltage of the device; but at the same time, the electric field aggregation still exists, and by embedding the field plate structure, an additional potential control layer is introduced in the electric field concentration area of the device to adjust the electric field distribution, which significantly reduces the edge electric field aggregation under the gate electrode; at the same time, the built-in electric field in the reverse biased PN junction can deplete holes to avoid current congestion at the boundary between the passivation layer and the PN junction. More uniform current distribution significantly improves the gate breakdown voltage of the device and improves the gate reliability of the device.

[0052] The present application forms a delta-doped layer and a spacer layer by delta-doping in the barrier layer, effectively improves the carrier concentration at the channel layer; in addition, the dielectric layer above the barrier layer effectively reduces the defect states on the surface of the device, reduces the leakage current of the device, and alleviates the current collapse effect.

[0053] The application effectively realizes the enhanced device, and on this basis, improves the gate electrode breakdown voltage of the device, increases the gate electrode voltage swing of the device, and improves the reliability and practicability of the device. BRIEF DESCRIPTION OF DRAWINGS

[0054] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the drawings needed to be used in the embodiments or the prior art description will be briefly introduced. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative effort on the basis of these drawings.

[0055] Figure 1 is a structure schematic diagram of a PN junction gate gallium oxide-based MODFET device provided by an embodiment of the present application.

[0056] Figure 2a is a schematic diagram of preparing a substrate in a preparation process of a PN junction gate gallium oxide-based MODFET device provided by an embodiment of the present application.

[0057] Figure 2b is a schematic diagram of preparing a channel layer in a preparation process of a PN junction gate gallium oxide-based MODFET device provided by an embodiment of the present application.

[0058] Figure 2c is a schematic diagram of preparing a spacer layer in a preparation process of a PN junction gate gallium oxide-based MODFET device provided by an embodiment of the present application.

[0059] Figure 2d is a schematic diagram of preparing a delta-doped layer in a preparation process of a PN junction gate gallium oxide-based MODFET device provided by an embodiment of the present application.

[0060] Figure 2e is a schematic diagram of preparing a barrier layer in a preparation process of a PN junction gate gallium oxide-based MODFET device provided by an embodiment of the present application.

[0061] Figure 2f is a schematic diagram of etching two ends of the barrier layer by using SiO2 as a mask in a preparation process of a PN junction gate gallium oxide-based MODFET device provided by an embodiment of the present application.

[0062] Figure 2g is a schematic diagram of etching out a first groove in a preparation process of a PN junction gate gallium oxide-based MODFET device provided by an embodiment of the present application.

[0063] Figure 2his a schematic view of preparing the first ohmic contact region and the second ohmic contact region in the preparation process of the PN junction gate gallium oxide based MODFET device provided by the embodiment of the present application.

[0064] Figure 2i is a schematic view of preparing the P-type gallium nitride layer in the preparation process of the PN junction gate gallium oxide based MODFET device provided by the embodiment of the present application.

[0065] Figure 2j is a schematic view of etching the intermediate groove in the preparation process of the PN junction gate gallium oxide based MODFET device provided by the embodiment of the present application.

[0066] Figure 2k is a schematic view of preparing the N-type gallium nitride layer in the preparation process of the PN junction gate gallium oxide based MODFET device provided by the embodiment of the present application.

[0067] Figure 2l is a schematic view of preparing the dielectric layer to etch the second groove, the third groove and the fourth groove in the preparation process of the PN junction gate gallium oxide based MODFET device provided by the embodiment of the present application.

[0068] Figure 2m is a schematic view of preparing the source electrode and the drain electrode in the preparation process of the PN junction gate gallium oxide based MODFET device provided by the embodiment of the present application.

[0069] Figure 2n is a schematic view of preparing the gate electrode in the preparation process of the PN junction gate gallium oxide based MODFET device provided by the embodiment of the present application.

[0070] Label explanation in the figure:

[0071] 1-substrate, 2-channel layer, 3-separation layer, 4-delta doped layer, 5-potential barrier layer, 6-first ohmic contact region, 7-second ohmic contact region, 8-PN junction structure, 81-P-type gallium nitride layer, 82-N-type gallium nitride layer, 9-dielectric layer structure, 91-first dielectric layer, 92-second dielectric layer, 10-source electrode, 11-drain electrode, 12-gate electrode, 13-first groove, 14-second groove, 15-third groove, 16-fourth groove, 17-intermediate groove. DETAILED DESCRIPTION

[0072] The present application will be further described below in conjunction with the accompanying drawings and embodiments. It is particularly pointed out that the following embodiments are only for illustrating the present application, but not for limiting the scope of the present application. Similarly, the following embodiments are only part of the embodiments of the present application, but not all the embodiments of the present application, and all other embodiments obtained by those skilled in the art without creative labor are within the scope of protection of the present application.

[0073] The PN junction gate gallium oxide-based MODFET device of the present application is a PN junction gate gallium oxide-based MODFET device with field plate embedding, which is reliable to implement, can effectively reduce the gate electrode leakage current and improve the gate electrode breakdown voltage and the reliability of the device.

[0074] Please refer to Figure 1 The present application provides a PN junction gate gallium oxide-based MODFET device, which comprises, from bottom to top, a substrate 1, a channel layer 2, a spacer layer 3, a delta-doped layer 4 and a barrier layer 5, wherein the width of the substrate 1 and the channel layer 2 is equal, i.e. the edges coincide; the width of the spacer layer 3, the delta-doped layer 4 and the barrier layer 5 is equal, and the width of the channel layer 2 is greater than the width of the spacer layer 3; further comprising:

[0075] A first ohmic contact region 6 is provided on one side of the end face of the spacer layer 3, the delta-doped layer 4 and the barrier layer 5;

[0076] A second ohmic contact region 7 is provided on the other side of the end face of the spacer layer 3, the delta-doped layer 4 and the barrier layer 5; the height of the first ohmic contact region 6 and the second ohmic contact region 7 is higher than the upper surface of the barrier layer 5;

[0077] A PN junction structure 8 is provided on part of the surface of the barrier layer 5;

[0078] A dielectric layer structure 9 is provided across the barrier layer 5, the PN junction structure 8, the first ohmic contact region 6 and the second ohmic contact region 7;

[0079] A source electrode 10 is provided on the first ohmic contact region 6;

[0080] A drain electrode 11 is provided on the second ohmic contact region 7;

[0081] A gate electrode 12 is provided on the PN junction structure 8 and the dielectric layer structure 9, the metal at the upper end of the gate electrode 12 extends to the two ends of the dielectric layer structure 9 above the PN junction structure 8 to form a field plate structure, which can be completed synchronously with the preparation of the gate electrode 12; wherein the width of the upper end of the gate electrode 12 is equal to the distance between the left and right edges of the dielectric layer structure 9 above the PN junction structure 8, i.e. the edges coincide.

[0082] The specific functions of the structures of the device are as follows:

[0083] The substrate 1:

[0084] The gallium oxide substrate 1 is the basis for the epitaxial growth of the channel layer 2, providing the physical support required for crystal growth. The lattice matching degree and the thermal expansion coefficient of the substrate 1 material gallium oxide are consistent with the epitaxial material gallium oxide forming the channel layer 2, which helps to achieve high-quality homoepitaxy and promote its application in the field of power electronics.

[0085] Channel layer 2:

[0086] Channel layer 2 participates in the formation of heterojunction, Ga2O3 and AlGaO form a heterojunction, due to spontaneous polarization and piezoelectric polarization effect, high electron concentration and high mobility 2DEG is generated at the interface. At the same time, the channel layer 2 is the transmission channel of two-dimensional electron gas (2DEG), responsible for carrying the current flow in the device; The 2DEG concentration in the channel layer 2 directly affects the threshold voltage of the device. By optimizing the parameters of the channel layer 2, such as thickness and doping concentration, the density of 2DEG can be adjusted, which in turn affects the opening and closing characteristics of the device. The material and structure design of the channel layer 2 has an important influence on the power bearing capacity of the device. Ga2O3 as a kind of super wide band gap material, its high critical breakdown field strength helps to improve the power bearing capacity of the device.

[0087] Spacer layer 3:

[0088] Spacer layer 3 participates in the formation of heterojunction, Ga2O3 and AlGaO form a heterojunction. In addition, spacer layer 3 can reduce the influence of ion scattering on the mobility and concentration of 2DEG in the channel, thereby optimizing the performance of the device.

[0089] δ Doping layer 4:

[0090] The introduction of δ doping layer 4 can avoid the formation of undesirable parallel conduction paths in channel layer 2, so as to effectively improve the 2DEG concentration formed at the heterojunction interface, thereby improving the surface concentration and mobility of carriers and improving the conductivity of the device.

[0091] Barrier layer 5:

[0092] Barrier layer 5 works together with dielectric layer to help reduce gate electrode 12 leakage current and improve breakdown voltage. The quality of barrier layer 5, especially the defects and trap states in it, will affect the current collapse effect of the device under dynamic working conditions. By optimizing the material and structure of channel layer 2, current collapse can be reduced and the dynamic performance of the device can be improved.

[0093] First ohmic contact region 6, second ohmic contact region 7:

[0094] First ohmic contact region 6 and second ohmic contact region 7 can reduce the height of the potential barrier between the semiconductor and the metal contact, improve the ohmic contact performance of the source and drain regions of the device, so as to realize low resistance ohmic contact, and reduce the ohmic contact process difficulty of the source electrode 10 and the drain electrode 11.

[0095] PN junction structure 8:

[0096] P-type semiconductors are formed by doping trivalent elements into intrinsic semiconductors, which replace tetravalent elements in the semiconductor lattice, creating holes. N-type semiconductors are formed by doping pentavalent elements, which provide extra electrons in the lattice. When P-type and N-type semiconductors are in contact, due to the concentration gradient, free electrons in the N-type semiconductor will diffuse to the P-type semiconductor, and holes in the P-type semiconductor will diffuse to the N-type semiconductor. As electrons and holes diffuse, they recombine near the contact interface, resulting in a decrease in charge carrier concentration in this region, forming a space charge region (also known as a depletion region) where there are no free charge carriers. The formation of the space charge region results in an internal electric field being generated on both sides of the PN junction, pointing from the N-type to the P-type semiconductor, which acts to hinder further diffusion. When a forward bias is applied to the PN junction (positive to the P-type and negative to the N-type), the internal electric field is weakened, allowing more electrons and holes to inject into the opposite region, thereby increasing the forward current. Conversely, when a reverse bias is applied (negative to the P-type and positive to the N-type), the internal electric field is enhanced, inhibiting the diffusion of charge carriers, resulting in a very small reverse current.

[0097] P-type gallium nitride is grown above the barrier layer 5, and a thin N-type gallium nitride epitaxial layer is added on top of the P-type gallium nitride to form a PN junction as part of the gate electrode 12. The P-type gallium nitride layer 81 can deplete electrons, effectively blocking the underlying 2DEG channel, and the N-type gallium nitride layer 82 can form a PN junction with the P-type gallium nitride layer 81 to generate an internal electric field to regulate the depletion layer. In this scheme, the N-type gallium nitride layer 82 is in contact with the gate electrode 12, and when the PN junction is reverse biased, the underlying 2DEG channel is depleted, inhibiting the diffusion of charge carriers, achieving a right shift in threshold voltage, and because the PN junction depletion region extends to the N and P sides, the device exhibits lower gate electrode 12 leakage current, and the PN junction can withstand higher reverse bias at the same peak electric field, thereby improving the gate electrode 12 breakdown voltage of the device.

[0098] Dielectric layer structure 9:

[0099] The dielectric layer can reduce the defect states on the surface of the device, reduce the leakage current of the device, and improve the breakdown voltage of the device, thereby improving the electrical properties of the device. The passivation layer helps to protect the device from environmental factors such as humidity and temperature changes, thereby improving the long-term stability and reliability of the device. In addition, the dielectric layer can form a field plate structure with the extended gate electrode 12.

[0100] Source electrode 10, drain electrode 11:

[0101] The source electrode 10 and the drain electrode 11 are the channels through which current enters and exits the semiconductor device, and the laminated metal is used to form an ohmic contact and form a closed circuit through the channel layer 2 for current transmission.

[0102] Gate electrode 12:

[0103] The gate electrode 12 controls the current flow between the source electrode 10 and the drain electrode 11 by electric field. The change of the gate electrode 12 voltage can adjust the formation and disappearance of the channel, thereby controlling the conduction state of the device. In the enhancement mode device, the gate electrode 12 needs to apply a positive voltage to induce and form a conductive channel. In the depletion mode device, the channel exists even if the gate electrode 12 voltage is zero, but the gate electrode 12 voltage can further adjust the conductivity of the channel.

[0104] Field plate structure:

[0105] The field plate structure can improve the breakdown voltage of the device by reducing the edge electric field of the gate electrode 12. The device with the field plate structure can reduce the probability of current collapse, because the field plate structure can reduce the probability of electron tunneling from the potential barrier layer 5 between the gate electrode 12 and the drain electrode 11 to the surface trap, hinder the formation of the virtual gate effect, weaken the virtual gate effect, and effectively inhibit the current collapse of the device.

[0106] The effect of embedding the field plate structure into the PN junction structure 8:

[0107] The addition of the PN junction under the gate electrode 12 can withstand higher reverse bias at the same peak electric field, but the electric field aggregation still exists. By embedding the field plate structure, the peak value of the edge electric field under the gate electrode 12 is significantly reduced; at the same time, the built-in electric field in the reverse biased PN junction can deplete holes, avoiding the crowding of current at the boundary between the dielectric layer and the PN junction. The more uniform current distribution significantly improves the gate electrode 12 breakdown voltage of the device and improves the gate electrode 12 reliability of the device.

[0108] In the embodiment, the PN junction structure 8 includes a P-type gallium nitride layer 81 and an N-type gallium nitride layer 82, the P-type gallium nitride layer 81 is arranged on part of the surface of the potential barrier layer 5, and an intermediate groove 17 is arranged on the upper surface of the P-type gallium nitride layer 81, and the N-type gallium nitride layer 82 is arranged in the intermediate groove 17 on the upper surface of the P-type gallium nitride layer 81.

[0109] In the embodiment, the dielectric layer structure 9 includes a first dielectric layer 91 and a second dielectric layer 92, the first dielectric layer 91 is arranged on the upper surface of the first ohmic contact area 6 and the upper surface of the potential barrier layer 5 between the right end of the first ohmic contact area 6 and the left end surface of the PN junction structure 8; the second dielectric layer 92 is arranged on the upper surface of the second ohmic contact area 7 and the upper surface of the potential barrier layer 5 between the left end of the second ohmic contact area 7 and the right end surface of the PN junction structure 8, and the first dielectric layer 91 and the second dielectric layer 92 extend upward near the side surface of the PN junction structure 8 and cover the upper surface of the P-type gallium nitride layer 81 of the PN junction structure 8.

[0110] In the embodiment, the interval between the PN junction structure 8 and the first ohmic contact region 6 is smaller than the interval between the PN junction structure 8 and the second ohmic contact region 7; the reason for such arrangement is that when the interval between the gate electrode 12 above the PN junction structure 8 and the drain electrode 11 above the second ohmic contact region 7 is too small, a significant electric field concentration phenomenon will occur; making the interval between the PN junction structure 8 and the first ohmic contact region 6 smaller than the interval between the PN junction structure 8 and the second ohmic contact region 7 is beneficial to alleviate the electric field concentration at the end of the drain electrode 11 and improve the withstand voltage performance of the device.

[0111] In the embodiment, the substrate 1 is high-resistance or semi-insulating β-Ga2O3, and the doping element type includes any one of Mg, Fe, Zn, N and P; the doping concentration is 1×10 18 ~ 5×10 18 / cm -3 ; wherein high resistance requires that the resistivity of the substrate 1 is more than 10 9 Ω·cm, and the high-resistance or semi-insulating substrate 1 can effectively reduce the leakage current, thereby improving the off-state leakage performance of the device;

[0112] The channel layer 2 is an unintentionally doped β-Ga2O3 channel layer 2;

[0113] The interval layer 3 is an N-type doped β-(AlGa)2O3, and the doping element type includes any one of Si, Sn and Ge, and the doping concentration is 1×10 18 ~ 5×10 18 / cm -3 ; selecting the doping concentration in this range can balance the compromise between the on-resistance and the breakdown voltage of the device; the Al component is 0.15~0.3, and with the increase of the Al component, the 2DEG can be improved, but the breakdown voltage of the device will be reduced;

[0114] The δ-doped layer 4 is an N-type doped β-(AlGa)2O3, and the doping element type includes Si, and the doping concentration is 1×10 19 ~ 5×10 19 / cm -3 , and the Al component is 0.15~0.3;

[0115] The barrier layer 5 is an N-type doped β-(AlGa)2O3, and the doping element type includes any one of Si, Sn and Ge, and the doping concentration is 1×10 18 ~ 5×10 18 / cm -3 , and the Al component is 0.15~0.3;

[0116] The first ohmic contact region 6 and the second ohmic contact region 7 are both N-type heavily doped β-Ga2O3, the doping element type of which includes any one of Si, Sn and Ge, and the doping concentration of which is 1×10 20 ~ 5×10 20 cm -3 In this concentration range, the heavily doped can effectively reduce the difficulty of the ohmic contact process of the device, and reduce the contact resistance. When the doping concentration is too high, the carrier concentration in the semiconductor material will reach saturation, and the process difficulty will be increased.

[0117] The dielectric layer structure 9 is formed by any one of Al2O3, SiO2, Si3N4 and HfO2. Al2O3, SiO2 and Si3N4 have low process cost, and can still provide sufficient insulation protection at a relatively thin layer thickness, and reduce the occurrence of leakage phenomenon. HfO2 has higher dielectric constant, and has more excellent insulation performance and thermal stability.

[0118] The P-type gallium nitride layer 81 in the PN junction structure 8 is P-type doped, the doping element type of which includes Mg, and the doping concentration of which is 1×10 18 ~ 5×10 19 / cm -3 The reason for selecting this range is that the doping concentration of the P-type gallium nitride layer 81 is too high, which will affect the hole injection of the gate electrode 12, so that the current density of the channel layer 2 is reduced. When the doping concentration is too low, the hindering effect on the electrons is insufficient, which may cause the device to fail in the normally-off type. The N-type gallium nitride layer 82 is N-type doped, the doping element type of which includes any one of Si, Sn and Ge, and the doping concentration of which is 1×10 18 ~ 2×10 19 / cm -3 The reason for selecting this range is that when the doping concentration of the N-type gallium nitride layer 82 is too high, the device may fail in the normally-off type, and when the doping concentration is too low, the depletion effect of the PN junction structure 8 may be insufficient.

[0119] The source electrode 10 and the drain electrode 11 are both formed by stacking two metal layers of any one of Ni, Ti and Al combined with Au. For example, the two metal layers are formed by stacking Ni and Au, or the two metal layers are formed by stacking Ti and Au, or the two metal layers are formed by stacking Al and Au. The reason for selecting this is that the metal Ni, Ti or Al generates a compound after annealing, thereby forming a good ohmic contact performance, and the metal Au provides stability and corrosion resistance.

[0120] The gate electrode 12 is formed by stacking Ni and Au or Ti and Au, and the reason for this selection is that the two metals Ni and Au or the two metals Ti and Au can provide better Schottky contact.

[0121] In this embodiment, the thickness of the substrate 1 is 250-600 um, and the reason for this selection is that the thickness of the substrate 1 directly affects the heat conduction performance of the power device, and a thicker substrate 1 can improve the thermal conductivity, thereby more effectively dissipating heat and improving the reliability of the device; however, a too thick substrate 1 will increase the resistance of the substrate 1, affecting the current transmission efficiency of the device. Therefore, as a preferred implementation option, the thickness of the substrate 1 is preferably 250-600 um.

[0122] The thickness of the channel layer 2 is 150-360 nm, and the reason for this selection is that a thicker channel layer 2 can reduce the resistance of the device, thereby improving the current carrying capacity and reducing power consumption; however, a too thick channel layer 2 will increase the switching time of the device, thereby reducing the switching frequency, and a thicker channel layer 2 is more prone to defects, increasing the process time and cost, so as a preferred implementation option, the thickness of the channel layer 2 is preferably 150-360 nm.

[0123] The thickness of the spacer layer 3 is 3-8 nm, and the reason for this selection is that the thickness of the spacer layer 3 is determined by the distance of the delta-doped layer 4 from the two-dimensional electron gas interface, and when the spacer layer 3 is thicker, the influence of the delta-doped layer 4 on the two-dimensional electron gas interface is reduced, and the electron density and mobility increase is not significant; when the spacer layer 3 is thinner, the delta-doped layer 4 is too close to the interface, which can cause uneven distribution of the electric field strength in the 2DEG region, increasing the scattering of carriers. Therefore, as a preferred implementation option, the thickness of the spacer layer 3 is preferably 3-8 nm.

[0124] The thickness of the delta-doped layer 4 is 1-2 nm, and the reason for this selection is that a thinner delta-doped layer 4 increases the electron density and mobility, significantly increasing the two-dimensional electron gas of the interface; however, if the delta-doped layer 4 is too thin, it can cause uneven doping effect, increase the parasitic capacitance, and affect the switching speed and frequency response of the device. As a preferred implementation option, the thickness of the delta-doped layer 4 is preferably 1-2 nm.

[0125] The thickness of the barrier layer 5 is 15-30 nm, and the reason for this selection is that increasing the thickness of the barrier layer 5 can increase the surface density of 2DEG, but beyond a certain thickness, the surface density tends to saturate; a too thick barrier layer 5 will increase the parasitic capacitance of the device, which can adversely affect the high frequency characteristics. As a preferred implementation option, the thickness of the barrier layer 5 is preferably 15-30 nm.

[0126] The thickness of the medium layer structure 9 is 2-5nm; the reason for selecting this range is that a thicker medium layer can effectively reduce the leakage current, but at the same time, it will also reduce the control ability of the gate electrode 12, which cannot effectively control the current in the channel layer 2, thereby reducing the switching speed and performance of the device; a thinner medium layer can produce a higher leakage current at high voltage, but it can still effectively store and transfer charges at low voltage, improving the signal response speed of the device. As a preferred implementation option, preferably, the thickness of the medium layer is 2-5nm.

[0127] The thickness of the P-type gallium nitride layer 81 in the PN junction structure 8 is 20-100nm, and the P-type gallium nitride layer 81 can effectively block electrons and increase the threshold voltage, but a P-type gallium nitride layer 81 that is too thick will affect the injection of carriers; when the P-type gallium nitride layer 81 is too thin, it cannot produce an effective depletion width with the N-type gallium nitride layer 82, therefore, the selected thickness of the P-type gallium nitride layer 81 is 20-100nm. The thickness of the N-type gallium nitride layer 82 is 10-40nm, and a N-type gallium nitride layer 82 that is too thick will weaken the blocking effect of the P-type gallium nitride layer 81 on electrons; but when the N-type gallium nitride layer 82 is too thin, it cannot produce an effective depletion width with the P-type gallium nitride layer 81, therefore, the selected thickness of the N-type gallium nitride layer 82 is 10-40nm.

[0128] The thickness of the first ohmic contact region 6 and the second ohmic contact region 7 is 50-100nm, and the total thickness of the first ohmic contact region 6 and the second ohmic contact region 7 should be greater than the sum of the thicknesses of the spacer layer 3, the delta-doped layer 4 and the barrier layer 5, in order to reduce the leakage current in the channel layer 2; a too thick ohmic contact region will increase the distance between the source electrode 10, the drain electrode 11 and the channel layer 2, reducing the modulation effect of the source electrode 10 and the drain electrode 11 on the channel layer 2.

[0129] As shown in Figures 2a-2n The application also provides a preparation method of a PN junction gate oxidized gallium-based MODFET device, which is prepared based on the above-mentioned PN junction gate oxidized gallium-based MODFET device, and specifically includes the following steps:

[0130] Step 1: pretreating the surface of the substrate 1 in a reaction chamber; wherein the method for pretreating the surface of the substrate 1 is standard RCA cleaning: heating the substrate 1 before starting growth to remove impurities adsorbed on the substrate 1;

[0131] Step 2: epitaxially growing a channel layer 2 on the surface of the substrate 1; the method for epitaxial growth is one of MOCVD, MBE and ALD;

[0132] Step 3, growing spacer layer 3 on the surface of channel layer 2 by epitaxy; the method of epitaxy uses one of MOCVD, MBE and ALD;

[0133] Step 4, growing δ-doped layer 4 and barrier layer 5 on the surface of spacer layer 3 by epitaxy from bottom to top; the method of epitaxy uses one of MOCVD, MBE and ALD;

[0134] Step 5, etching both ends of barrier layer 5, and continuing to etch both ends of δ-doped layer 4 and spacer layer 3 along the etching direction until the upper surface of channel layer 2 forms two first grooves 13, growing first ohmic contact region 6 on the first groove 13 at the left end, and growing second ohmic contact region 7 on the first groove 13 at the right end; the etching method is as follows: first, depositing a layer of SiO2, using photolithography process to make etching window pattern, and then using RIE equipment to etch SiO2 to form SiO2 mask, and using ICP or RIE method to etch barrier layer 5 to form aperture;

[0135] Step 6, patterning and growing PN junction structure 8 on the surface of barrier layer 5;

[0136] Step 7, depositing dielectric layer structure 9 on the surface of barrier layer 5, PN junction structure 8, first ohmic contact region 6 and second ohmic contact region 7 by using one of MOCVD, MBE and ALD, and etching the upper surface of both ends and middle part of dielectric layer structure 9 to leave out second groove 14, third groove 15 and fourth groove 16 for depositing source electrode 10, drain electrode 11 and gate electrode 12;

[0137] Step 8, depositing source electrode 10 on second groove 14, and depositing drain electrode 11 on third groove 15; source electrode 10 and drain electrode 11 are deposited by electron beam evaporation, and annealing process is performed to form good ohmic contact;

[0138] Step 9, depositing gate electrode 12 on fourth groove 16 to form field plate structure on the upper surface of PN junction structure 8; gate electrode 12 is deposited by electron beam evaporation to form good Schottky contact.

[0139] In the embodiment, the step 6 is specifically: the PN junction structure 8 comprises a P-type gallium nitride layer 81 and an N-type gallium nitride layer 82, the P-type gallium nitride layer 81 is patterned and grown in the middle of the upper surface of the barrier layer 5, the P-type gallium nitride layer 81 is coated with photoresist, exposed and developed to form a patterned photoresist, and the P-type gallium nitride layer 81 is etched with the patterned photoresist as a mask to form a middle recess 17 in the middle; the N-type gallium nitride layer 82 is grown on the upper surface of the P-type gallium nitride layer 81 in the middle recess, and the growth height of the N-type gallium nitride layer 82 is flush with the upper surface of the P-type gallium nitride layer 81.

[0140] The above merely describes some embodiments of the present application, and does not limit the protection scope of the present application, and any equivalent device or equivalent process transformation, or direct or indirect application in other related technical fields by using the content of the present application specification and drawings, are also included in the patent protection scope of the present application.

Claims

1. A PN junction gate gallium oxide-based MODFET device, characterized in that, From bottom to top, it includes: substrate, channel layer, spacer layer, delta-doped layer, and barrier layer, and also includes: The first ohmic contact region is disposed on one side of the end face of the spacer layer, the delta-doped layer and the barrier layer; The second ohmic contact region is disposed on the other side of the end face of the spacer layer, the delta-doped layer and the barrier layer; the height of the first ohmic contact region and the second ohmic contact region is higher than the upper surface of the barrier layer. A PN junction structure, disposed on a portion of the surface of the barrier layer; A dielectric layer structure is disposed across the barrier layer, PN junction structure, first ohmic contact region and second ohmic contact region; The source electrode is disposed on the first ohmic contact area; The drain electrode is disposed on the second ohmic contact area; A gate electrode is disposed on a PN junction structure and a dielectric layer structure. The metal at the upper end of the gate electrode extends to both ends of the dielectric layer structure located above the PN junction structure to form a field plate structure.

2. The PN junction gate gallium oxide-based MODFET device as described in claim 1, characterized in that, The PN junction structure includes a P-type gallium nitride layer and an N-type gallium nitride layer. The P-type gallium nitride layer is disposed on a portion of the surface of the barrier layer. The upper surface of the P-type gallium nitride layer has a central groove. The N-type gallium nitride layer is disposed within the central groove on the upper surface of the P-type gallium nitride layer.

3. The PN junction gate gallium oxide-based MODFET device as described in claim 2, characterized in that, The dielectric layer structure includes a first dielectric layer and a second dielectric layer. The first dielectric layer is disposed on the upper surface of the first ohmic contact region and on the upper surface of the barrier layer between the right end of the first ohmic contact region and the left end face of the PN junction structure. The second dielectric layer is disposed on the upper surface of the second ohmic contact region and on the upper surface of the barrier layer between the left end of the second ohmic contact region and the right end face of the PN junction structure. The first dielectric layer and the second dielectric layer extend upward near the side of the PN junction structure and cover the upper surface of the P-type gallium nitride layer of the PN junction structure.

4. The PN junction gate gallium oxide-based MODFET device as described in claim 1, characterized in that, The distance between the PN junction structure and the first ohmic contact area is smaller than the distance between the PN junction structure and the second ohmic contact area.

5. A PN junction gate gallium oxide-based MODFET device as described in claim 1, characterized in that, The widths of the substrate and the channel layer are equal, the widths of the spacer layer, the δ-doped layer and the barrier layer are equal, and the width of the channel layer is greater than the width of the spacer layer; the width of the upper end of the gate electrode is equal to the distance between the left and right edges of the dielectric layer structure located above the PN junction structure.

6. The PN junction gate gallium oxide-based MODFET device as described in claim 2, characterized in that, The substrate is a high-resistivity or semi-insulating β-Ga₂O₃, and its doping element includes any one of Mg, Fe, Zn, N, and P; the doping concentration is 1×10⁻⁶. 18 ~5×10 18 / cm -3 ; The channel layer is an unintentionally doped β-Ga2O3 channel layer; The spacer layer is N-type doped β-(AlGa)₂O₃, and the doping element can be any one of Si, Sn, and Ge, with a doping concentration of 1×10⁻⁶. 18 ~5×10 18 / cm -3 The Al component is 0.15–0.3%. The δ-doped layer is an N-type doped β-(AlGa)₂O₃ layer, and the doping element includes Si, with a doping concentration of 1×10⁻⁶. 19 ~5×10 19 / cm -3 The Al component is 0.15–0.3%. The barrier layer is N-type doped β-(AlGa)₂O₃, and the doping element can be any one of Si, Sn, and Ge, with a doping concentration of 1×10⁻⁶. 18 ~5×10 18 / cm -3 The Al component is 0.15–0.3%. Both the first and second ohmic contact regions are heavily N-type doped β-Ga₂O₃, with the doping element being any one of Si, Sn, and Ge, and the doping concentration being approximately 1 × 10⁻⁶. 20 ~5×10 20 cm -3 ; The P-type gallium nitride layer in the PN junction structure is P-type doped, and the doping element includes Mg with a doping concentration of 1×10⁻⁶. 18 ~5×10 19 / cm -3 The N-type gallium nitride layer is N-type doped, and the doping element includes any one of Si, Sn, and Ge, with a doping concentration of 1×10⁻⁶. 18 ~2×10 19 / cm -3 ; The dielectric layer structure is formed from any one of Al2O3, SiO2, Si3N4 and HfO2; The source electrode and drain electrode are both formed by stacking two metals, Ni, Ti and Al, and Au. The gate electrode is formed by stacking Ni and Au or Ti and Au metals.

7. A PN junction gate gallium oxide-based MODFET device as described in claim 2, characterized in that, The thickness of the substrate is 250–600 μm; The thickness of the channel layer is 150–360 nm; The thickness of the spacer layer is 3–8 nm; The thickness of the δ-doped layer is 1–2 nm; The thickness of the barrier layer is 15–30 nm; The thickness of the dielectric layer structure is 2–5 nm; The thickness of the P-type gallium nitride layer in the PN junction structure is 20–100 nm, and the thickness of the N-type gallium nitride layer is 10–40 nm. The thickness of both the first ohmic contact region and the second ohmic contact region is 50-100 nm.

8. A method for fabricating a PN junction gate gallium oxide-based MODFET device, characterized in that, The fabrication of a gallium oxide-based MODFET device with a PN junction gate according to any one of claims 1-7 specifically includes the following steps: Step 1: Pre-treat the substrate surface in the reaction chamber; Step 2: Homogeneously epitaxially grow a channel layer on the upper surface of the substrate; Step 3: Heterogeneous epitaxial growth of a spacer layer on the upper surface of the channel layer; Step 4: Homogeneously grow a δ-doped layer and a barrier layer sequentially from bottom to top on the upper surface of the spacer layer; Step 5: Etch both ends of the barrier layer, and continue etching both ends of the δ-doped layer and the spacer layer in sequence along the etching direction until the upper surface of the channel layer is formed to form two first grooves. Grow a first ohmic contact region on the first groove located at the left end and a second ohmic contact region on the first groove located at the right end. Step 6: Pattern and grow a PN junction structure in the middle of the upper surface of the barrier layer; Step 7: Deposit a dielectric layer structure on the surface of the barrier layer, PN junction structure, first ohmic contact region and second ohmic contact region, and etch the left and right ends and the upper surface of the middle part of the dielectric layer structure to leave the second, third and fourth grooves for depositing the source electrode, drain electrode and gate electrode. Step 8: Deposit a source electrode on the second groove and a drain electrode on the third groove; Step 9: Deposit a gate electrode on the fourth groove to form a field plate structure on the upper surface of the PN junction structure.

9. The method for fabricating a PN junction gate gallium oxide-based MODFET device as described in claim 8, characterized in that, Step 6 specifically involves: the PN junction structure includes a P-type gallium nitride layer and an N-type gallium nitride layer; a P-type gallium nitride layer is patterned and grown in the middle of the upper surface of the barrier layer; the patterning method is to coat the surface of the P-type gallium nitride layer with photoresist, expose and develop the photoresist to form a patterned photoresist, and use the patterned photoresist as a mask to etch the P-type gallium nitride layer to form a central groove located in the middle. An N-type gallium nitride layer is grown in the central groove on the upper surface of the P-type gallium nitride layer, and the growth height of the N-type gallium nitride layer is flush with the upper surface of the P-type gallium nitride layer.

10. The method for fabricating a PN junction gate gallium oxide-based MODFET device as described in claim 8, characterized in that, The method for pretreating the substrate surface in step 1 is standard RCA cleaning: the substrate is heated before growth begins to remove impurities adsorbed on the substrate; the epitaxial growth method is one of MOCVD, MBE and ALD.

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