Backside illuminated image sensor

Abstract

The embodiment of the invention relates to a backside illuminated image sensor. An image sensor and a method of manufacturing the image sensor are provided. One such method includes forming a structure including a semiconductor layer extending from a front side to a back side and a capacitive insulating wall extending through the semiconductor layer. The capacitive insulating wall includes a first insulating wall and a second insulating wall separated by a region of conductor or semiconductor material. The semiconductor layer and portions of the region of conductor or semiconductor material are selectively etched, and the first and second insulating walls have portions protruding outwardly beyond a backside of the semiconductor layer and a backside of the region of conductor or semiconductor material. A dielectric passivation layer is deposited on the backside of the structure, and portions of the dielectric passivation layer on the backside of the protruding portions of the first and second insulating walls are partially removed.

Description

[0001] Divisional Application Instructions

[0002] This application is a divisional application of the Chinese patent application with the application date of January 13, 2020, application number 202010033298.1, and name “Back-illuminated image sensor”. Technical Field

[0003] The present disclosure relates to backside illuminated image sensors and methods of making such sensors. Background Art

[0004] A back-illuminated image sensor generally comprises a semiconductor layer having a surface, called the front side, coated with a stack of insulating and conductive layers forming an interconnection structure, and a side of the semiconductor layer opposite to the front side, called the back side, intended to receive illumination originating from a scene whose image is desired to be acquired. The sensor comprises a plurality of pixels, for example arranged in an array, formed inside and above the semiconductor layer. Each pixel comprises in particular: a light detection region formed in the semiconductor layer, and one or more control transistors formed inside and above the semiconductor layer on the front side of the semiconductor layer. The pixels are interconnected via the interconnection structure. Summary of the invention

[0005] In one embodiment, the present disclosure provides a method for manufacturing an image sensor, the method comprising: forming a structure having a front side and a back side, the structure comprising a semiconductor layer extending from the front side of the structure to the back side and a capacitive insulating wall extending through the semiconductor layer from the front side to the back side of the structure, the capacitive insulating wall comprising a first insulating wall and a second insulating wall, the first insulating wall and the second insulating wall being separated by a region of conductor or semiconductor material; selectively etching portions of the semiconductor layer and the region of conductor or semiconductor material from the back side of the structure, after etching, each of the first and second insulating walls having a portion protruding outward beyond the back side of the semiconductor layer and the back side of the region of conductor or semiconductor material; depositing a dielectric passivation layer on the back side of the structure; and locally removing portions of the dielectric passivation layer on the back side of the protruding portions of the first and second insulating walls.

[0006] According to one embodiment, locally removing portions of the dielectric passivation layer includes: depositing a sacrificial layer on the dielectric passivation layer; and thinning the sacrificial layer to reach back sides of the protruding portions of the first and second insulating walls.

[0007] According to one embodiment, locally removing a portion of the dielectric passivation layer further comprises removing a portion of the sacrificial layer remaining after thinning the sacrificial layer.

[0008] According to one embodiment, the sacrificial layer is made of silicon nitride.

[0009] According to an embodiment, the method further comprises, after locally removing portions of the dielectric passivation layer, depositing an anti-reflection layer on a back side of the dielectric passivation layer and on back sides of the protruding portions of the first and second insulating walls.

[0010] According to one embodiment, a method includes depositing an antireflection layer on a back side of a dielectric passivation layer; and locally removing portions of the antireflection layer on a back side of protruding portions of the first and second insulating walls.

[0011] According to one embodiment, the anti-reflection layer comprises tantalum oxide.

[0012] According to one embodiment, the dielectric passivation layer includes a dielectric material having a dielectric constant greater than a dielectric constant of silicon oxide, aluminum oxide, or hafnium oxide.

[0013] According to one embodiment, the method includes oxidizing a back side of the semiconductor layer after forming the structure and before selectively etching the semiconductor layer and portions of the region of conductor or semiconductor material.

[0014] According to one embodiment, the semiconductor layer is made of single crystal silicon, the region of conductor or semiconductor material is made of polycrystalline silicon or amorphous silicon, and the first and second insulating walls are made of silicon oxide.

[0015] According to one embodiment, the capacitive insulating wall comprises a third insulating wall separating the region of conductive or semiconductive material into two distinct walls.

[0016] According to one embodiment, a structure includes an interconnect structure coating a front side of a semiconductor layer.

[0017] Another embodiment provides an image sensor, the image sensor comprising: a semiconductor layer having a front side and a back side, and a capacitive insulating wall extending from the front side to the back side of the semiconductor layer, the capacitive insulating wall comprising a first and a second insulating wall, the first and the second insulating wall being separated by a region of conductor or semiconductor material. Each of the first and the second insulating wall has a portion protruding from the back side of the semiconductor layer and from the back side of the region of conductor or semiconductor material. A dielectric passivation layer coats the back side of the semiconductor layer and the back side of the region of conductor or semiconductor material, and the back sides of the protruding portions of the first and the second insulating walls are not coated by the dielectric passivation layer.

[0018] According to one embodiment, the image sensor further includes an anti-reflection layer coating a back side of the dielectric passivation layer and back sides of the protruding portions of the first and second insulating walls.

[0019] According to one embodiment, the sensor further comprises an anti-reflection layer coating a back side of the dielectric passivation layer, and back sides of the protruding portions of the first and second insulating walls are not coated by the anti-reflection layer.

[0020] The foregoing and other features and advantages will be discussed in detail in the following non-limiting description of specific embodiments in conjunction with the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] Figure 1 is a simplified partial cross-sectional view of an example of a back-illuminated image sensor;

[0022] Figure 2 is a partial simplified cross-sectional view of another example of a back-illuminated image sensor;

[0023] Figure 3 illustrates a step of a method of manufacturing a back-illuminated image sensor according to one embodiment;

[0024] Figure 4 illustrates another step in manufacturing a backside illuminated image sensor according to one embodiment;

[0025] Figure 5 illustrates another step in manufacturing a backside illuminated image sensor according to one embodiment;

[0026] Figure 6 illustrates another step in manufacturing a backside illuminated image sensor according to one embodiment;

[0027] Figure 7 illustrates another step in manufacturing a backside illuminated image sensor according to one embodiment;

[0028] Figure 8 illustrates another step in manufacturing a backside illuminated image sensor according to one embodiment;

[0029] Fig. 9 illustrates another step in manufacturing a backside illuminated image sensor according to one embodiment;

[0030] Fig.10 illustrates another step in manufacturing a backside illuminated image sensor according to one embodiment;

[0031] Fig.11 Picture shows Figures 3 to 10 An alternative embodiment of the method illustrated in;

[0032] Fig.12 A and Fig.12 B shows Figures 3 to 10 Another alternative embodiment of the method illustrated in; and

[0033] Fig.13is a partially simplified cross-sectional view illustrating another example of a backside illuminated image sensor according to one embodiment. DETAILED DESCRIPTION

[0034] In different drawings, the same elements are designated by the same reference numerals. In particular, structural and / or functional elements common to different embodiments may be designated by the same reference numerals and may have the same structure, size and material properties.

[0035] For the sake of clarity, only those steps and elements useful for understanding the described embodiments are shown and described in detail. In particular, the formation of transistors and the formation of light detection areas for controlling the pixels of the described sensor are not described in detail, the described embodiments are compatible with the conventional structure of pixels of back-illuminated sensors.

[0036] Throughout this disclosure, the term “connected” is used to specify a direct electrical connection between circuit elements without intermediate elements other than conductors, while the term “coupled” is used to specify an electrical connection between circuit elements that may be direct or may be via one or more intermediate elements.

[0037] In the following description, when referring to terms that define absolute positions (such as terms "front", "rear", "up", "down", "left", "right", etc.) or relative positions (such as terms "above", "below", "upper", "lower", "side", etc.), or terms that define directions (such as terms "horizontal", "vertical", etc.), unless otherwise specified, they refer to the orientation of the drawings, and it should be understood that, in fact, the described device may be oriented differently.

[0038] The terms "approximately," "substantially," "approximately," and "about" are used herein to designate a tolerance of plus or minus 10%, preferably plus or minus 5%, of the value in question.

[0039] Figure 1 is a simplified partial cross-sectional view of an example of a backside-illuminated image sensor. Figure 1 The sensor includes a semiconductor layer 101 made of, for example, single-crystal silicon. Figure 1 The sensor also includes an interconnect structure 103 coating the upper surface or front side of the semiconductor layer 101 . Figure 1 The sensor includes a plurality of pixels Px formed in and on a semiconductor layer 101. Each pixel Px includes: at least one photosensitive region (not described in detail) formed in the semiconductor layer 101, and one or more control transistors (not described in detail) formed in and on the conductive layer 101. The pixels 101 are interconnected by conductive traces (not described in detail) formed in the interconnect structure 103. In operation, the sensor is illuminated on its lower surface or back side (i.e., on the side opposite to the interconnect structure 103), such as Figure 1 This is illustrated by arrow 104 .

[0040] Here we consider more specifically Figure 1 , the sensor comprising a capacitive insulating wall 105 extending vertically through the semiconductor layer 101 (from the front side to the back side of the layer 101). As an example, in each pixel, in a top view, the photosensitive area of ​​the pixel is completely surrounded by the annular capacitive insulating wall 105. Each capacitive insulating wall 105 comprises two vertical insulating walls 105a and 105b, which are separated by a vertical conductor or semiconductor region 105c, which is made of polysilicon or amorphous silicon, for example. For example, the regions 105a, 105b and 105c each extend across the entire thickness of the semiconductor layer 101 from the front side to the back side of the layer 101. Each of the insulating walls 105a and 105b has an outer lateral surface in contact with the semiconductor layer 101 and an inner lateral surface in contact with the region 105c. As an example, the insulating walls 105a and 105b are made of silicon oxide. In the example shown, each capacitive insulating wall 105 also includes a central insulating wall 105d, for example made of silicon oxide, which extends along the entire height of the wall and separates the conductor or semiconductor region 105c into two separate walls 105c1 and 105c2.

[0041] As an example, the thickness of the semiconductor layer 101 and therefore the height of the wall 105 is in the range from 1 μm to 20 μm, for example from 2 μm to 10 μm. The conductor or semiconductor regions 105c1 and 105c2 each have a width in the range from 10 nm to 100 nm, for example about 50 nm. The central insulating region 105d has a width in the range from 10 nm to 200 nm, for example about 50 nm. The outer insulating regions 105a and 105b each have a width in the range from 5 nm to 40 nm, for example about 15 nm.

[0042] In each capacitive insulating wall 105, the conductor or semiconductor wall 105c1 and / or 105c2 of the wall can be electrically connected via its front side to an application terminal of a bias potential formed in the interconnect structure 103 (not shown in detail in the figure), which enables biasing the capacitance formed between the semiconductor layer 101 and the wall 105c1 and / or the capacitance formed between the semiconductor layer 101 and the wall 105c2 during sensor operation.

[0043] A passivation layer 107 made of a dielectric material is provided on the back side of the sensor, the passivation layer 107 extending continuously substantially over the entire back surface of the sensor, i.e. on the back side of the semiconductor layer 101 and on the back side of the capacitive insulating wall 105. The layer 107 is, for example, made of a material different from that of the insulating walls 105a and 105b. As an example, the layer 107 is made of a material with a high dielectric constant, i.e. a material with a dielectric constant greater than that of silicon oxide, for example hafnium oxide (HfO2) or aluminum oxide (Al2O3).

[0044] exist Figure 1 In the example of FIG. 1 , the sensor further comprises an anti-reflection layer 109 , for example made of tantalum oxide (Ta 2 O 5 ), which coats the back side of the passivation layer 107 .

[0045] As required by the application, other layers not shown may be provided on the back side of the sensor, for example, a silicon oxide protection layer, a filter layer made of a colored resin, a layer of microlenses, etc.

[0046] In order to form Figure 1 A sensor of this type can start from a relatively thick initial substrate, for example made of silicon, the upper part of which is formed by the semiconductor layer 101 of the sensor.

[0047] Then, pixels Px, capacitive insulating walls 105, and interconnect structures 103 are formed inside and over semiconductor layer 101 from the front side of the substrate.

[0048] A support handle is then secured to the upper surface of the interconnect structure 103, after which the substrate is thinned from its lower surface or back side, for example by grinding and / or chemical thinning, possibly followed by a planarization or chemical mechanical polishing (CMP) step, until the back side of the semiconductor layer 101 and the back side of the capacitive insulating wall 105 are reached.

[0049] Then, the passivation layer 107 and possibly other backside layers of the sensor (on Figure 1 An anti-reflection layer 109 in the example of is deposited on the back side of the semiconductor layer 101 and the back side of the capacitive insulating wall 105 .

[0050] The support handle attached to the front side of the interconnect structure 103 may then be removed. As a variant, the support handle may remain as a mechanical support until the end of the method (and possibly in the final product). As a variant, the support handle may include an integrated circuit including transistors for controlling the sensor pixels.

[0051] In practice, it can be observed that the capacitance formed between the conductor or semiconductor wall 105c1 and the semiconductor layer 101 (separated by the insulating wall 105a), and the capacitance formed between the conductor or semiconductor wall 105c2 and the semiconductor layer 101 (separated by the insulating wall 105b) have a lower breakdown voltage. As an example, when the thickness of the insulating walls 105a and 105b is selected to obtain a theoretical breakdown voltage of 20V between the region 105c1 and the region 101 and between the region 105c2 and the region 101, it can be observed that in practice the actual breakdown voltage of the capacitor is about 10V. Above this voltage, breakdown can occur near the lower surface of the walls 105a and 105b.

[0052] In order to solve this problem, after the step of thinning the substrate 101 from the back side of the substrate 101 and before the step of depositing the dielectric passivation layer 107, a step of selectively partially etching the semiconductor layer 101 and the conductor or semiconductor regions 105c1 and 105c2 from the back side relative to the insulating regions 105a, 105b and 105d may be provided.

[0053] At the end of this etching step, the insulating layers 105a, 105b and 105d of the wall 105 have portions which protrude from the back side of the semiconductor layer 101 and from the back sides of the conductor or semiconductor regions 105c1 and 105c2.

[0054] Then, a passivation layer 107 is deposited on the back side of the semiconductor layer 101 and on the back sides of the conductor or semiconductor regions 105c1 and 105c2, and on the back sides and side surfaces of the protruding portions of the insulating regions 105a, 105b and 105d.

[0055] Possible additional backside layers of the sensor may then be deposited on the backside of layer 107 .

[0056] Figure 2 is a partially simplified cross-sectional view illustrating one example of a back-illuminated image sensor obtained by this method. Figure 2 An enlarged view of a portion of the sensor is shown with the vertical capacitive insulating wall 105 of the sensor centered. Figure 2 In the example, the sensor is oriented relative to Figure 1 In other words, Figure 2 In FIG, the back side (or illumination surface) of the sensor corresponds to its upper surface, and the front side of the sensor corresponds to its lower surface.

[0057] about Figure 2An advantage of the described manufacturing method and of the sensor obtained by this method is a significant improvement in the breakdown voltage of the capacitive insulating wall 105. This improvement can be explained in particular by the increase in the electrical path between the semiconductor layer 101 and the conductor or semiconductor region 105c1 or 105c2 via the interface between the insulating wall 105a or 105b and the passivation layer 107.

[0058] As an example, for the same dimensions, in particular for the same thickness of the insulating walls 105a and 105b of the wall 105, it can be observed that on the one hand the breakdown voltage of the capacitance formed between the region 105c1 and the layer 101 is increased by a factor of two, and on the other hand the breakdown voltage of the capacitance formed between the region 105c2 and the layer 101 is increased by a factor of two.

[0059] However, it is desirable to at least partially improve Figure 2 Certain aspects of backside-illuminated image sensors of the type described.

[0060] Figure 3 , Figure 4 , Figure 5 , Figure 6 , Figure 7 , Figure 8 , Fig. 9 and Fig.10 FIG. 1 is a partially simplified cross-sectional view illustrating steps of an example of a method for manufacturing a back-illuminated image sensor according to an embodiment. Figures 3 to 10 The steps of the manufacturing method are described sequentially, but it will be readily appreciated that in various embodiments the steps may be performed in any suitable order.

[0061] Figures 3 to 10 The sensors include Figure 1 and Figure 2 These elements will not be described in detail below. Figure 1 and Figure 2 It should be noted that Figures 3 to 10 The cross-sectional view has Figure 2 The cross-sectional view of FIG. 1 has the same orientation and shows an enlargement of the upper portion of the sensor centered with the vertical capacitive insulating wall 105 of the sensor.

[0062] Figure 3 The diagram shows an initial step in forming a structure comprising a semiconductor layer 101 and a capacitive insulating wall 105 extending from the front side of the semiconductor layer 101 (at Figures 3 to 10 The lower surface in the orientation Figures 3 to 10 ) extends vertically to the back side ( Figures 3 to 10To form this structure, as in the previously described example, it is possible to start with a relatively thick initial substrate, for example made of silicon, the front of which is formed by the semiconductor layer 101. Then, from the front side of the substrate, pixels Px, capacitive insulating walls 105 and interconnect structures 103 ( Figures 3 to 10 105). A support handle (not shown) is then fixed to the front side of the interconnect structure 103 (i.e. the surface of the interconnect structure 103 opposite to the substrate), after which the substrate is thinned from its back side, for example by grinding, to reach the back side of the semiconductor layer 101 and the back side of the capacitive insulating wall 105. The substrate thinning step may in particular comprise a chemical mechanical planarization or polishing (CMP), the goal of which is to obtain a substantially flat back surface after thinning. In other words, at the end of this step, the capacitive insulating wall 105 of the sensor is flush with the level of the back side of the semiconductor 101, to form a substantially flat back surface.

[0063] Figure 4 The diagram shows Figure 3 The step of partially removing or recessing the semiconductor layer 101 and the conductor or semiconductor regions 105c1 and 105c2 on the back side of the structure obtained at the end of the step of. During this step, the insulating regions 105a, 105b and 105d of the capacitive insulating wall 105 remain. To achieve this, Figure 3 The back side of the structure obtained at the end of the step of performing a partial etching of the semiconductor layer 101 and the conductive or semiconductor regions 105c1 and 105c2 selectively relative to the insulating regions 105a, 105b and 105d. Selective etching means that the speed of etching the material (s) forming the layer 101 and the regions 105c1 and 105c2 (e.g. silicon) is greater than the speed of etching the material (s) forming the regions 105a, 105b and 105d (e.g. silicon oxide), for example ten times greater, and preferably at least a hundred times greater. As an example, in Figure 4 The etching performed in the step is a plasma or dry etching step. As a variant, wet etching can be used. Figure 4 The thickness of the layer 101 removed in the step of and the thickness of the regions 105c1 and 105c2 are, for example, in the range from 5 nm to 200 nm, and preferably in the range from 10 nm to 50 nm. Figure 4 The etching performed in step 105 is a non-local etching, ie the semiconductor layer 101 and the regions 105c1 and 105c2 are thinned substantially across the entire surface of the sensor.

[0064] Therefore, in Figure 4At the end of the step of forming the capacitive insulating wall 105, on the back side of the structure, the conductor or semiconductor region 105c1 or 105c2 of the capacitive insulating wall 105 stops substantially at the same level as the back side of the semiconductor layer 101. However, the insulating layers 105a, 105b and 105d of the wall 105 have portions protruding from the back side of the semiconductor layer 101 and from the back sides of the conductor or semiconductor regions 105c1 and 105c2.

[0065] At the end of the step of selective partial etching of the layer 101 and of the regions 105c1 and 105c2, a step of chemically cleaning the back side of the sensor may be provided. During this step, a thin oxide layer (not shown) of native oxide or chemical oxide may be formed on the back side of the semiconductor layer 101 and on the back sides of the conductor and semiconductor regions 105c1 and 105c2, having a thickness of about 1 nm or less. As a variant, a specific step of oxidizing the back side of the semiconductor layer 101 may be provided, in order to obtain a slightly thicker oxide layer, for example with a thickness ranging from 1 nm to 5 nm.

[0066] Figure 5 The diagram shows the deposition step of the passivation layer 107 of the sensor. Figure 3 and Figure 4 The passivation layer 107 is deposited on and in contact with the back side of the structure obtained at the end of the step of . For example, the layer 107 is deposited by atomic layer deposition (ALD). More generally, any other conformal deposition method can be used so that the layer 107 follows the shape of the protrusion (relief) formed by the protruding parts of the insulating walls 105a, 105b and 105d of the wall 105. The passivation layer 107 is for example deposited continuously over the entire rear surface of the sensor. The thickness of the passivation layer 107 is for example less than the height of the protruding parts of the insulating walls 105a, 105b and 105d. As an example, the thickness of the passivation layer 107 is in the range from 2nm to 100nm, for example about 13nm.

[0067] Figure 6 The diagram shows Figure 3 , Figure 4 and Figure 5A step of depositing a sacrificial layer 201 on the upper surface of the structure obtained at the end of the step of . The layer 201 is made of a material that is selectively etchable relative to the material of the layer 107 (e.g., hafnium oxide or aluminum oxide) and relative to the material of the insulating walls 105a, 105b and 105d (e.g., silicon oxide). As an example, the sacrificial layer 201 is made of silicon nitride or resin, or of a metal (e.g., a metal from the group including copper, tungsten and aluminum). As a variant, the sacrificial layer 201 is made of silicon oxide deposited at a low temperature to have a density lower than that of the silicon oxide of the insulating walls 105a, 105b and 105d, and is therefore selectively etchable relative to the insulating walls 105a, 105b and 105d. The sacrificial layer 201 is, for example, continuously deposited on the entire rear surface of the sensor. The thickness of the sacrificial layer 201 is, for example, selected to be greater than the height of the protruding portions of the insulating walls 105a, 105b and 105d. As an example, the thickness of the sacrificial layer 201 is in the range from 10 nm to 200 nm, for example, about 50 nm.

[0068] Figure 7 The diagram shows thinning from the back side, for example by chemical mechanical planarization or polishing (CMP). Figure 3 , Figure 4 , Figure 5 and Figure 6 The structure obtained at the end of the step is a step to reach the back side of the insulating walls 105a, 105b and 105d. When reaching the back side of the protruding parts of the insulating walls 105a, 105b and 105d, the thinning is interrupted. Therefore, at the end of this step, the passivation layer 107 opposite to the back side of the insulating walls 105a, 105b and 105d is interrupted. However, the passivation layer 107 opposite to the back side of the semiconductor layer 101 and to the back side of the conductor or semiconductor regions 105c1 and 105c2 is retained, and the passivation layer 107 on the side of the protruding parts of the insulating walls 105a, 105b and 105d is retained. At the end of this step, the back side of the insulating walls 105a, 105b and 105d and the part of the layer 107 coating the sides of the insulating walls 105a, 105b and 105d are flush with the back side of the sacrificial layer 201, thereby forming a substantially flat rear surface of the sensor.

[0069] Figure 8 The step of removing the remaining portion of the sacrificial layer 201 opposite the back side of the semiconductor layer 101 and the back sides of the conductor or semiconductor regions 105c1 and 105c2 is illustrated. During this step, the sacrificial layer 201 is selectively removed relative to the passivation layer 107 and the insulating walls 105a, 105b and 105d. The sacrificial layer 201 can be removed by dry etching or wet etching.

[0070] Fig. 9 The diagram shows Figure 3, Figure 4 , Figure 5 , Figure 6 , Figure 7 and Figure 8 A step of depositing an antireflection layer 109, for example made of tantalum oxide, on the back side of the structure obtained at the end of the step of . More specifically, in this example, the layer 109 is deposited on and in contact with the back side of the passivation layer 107 opposite the semiconductor layer 101 and the conductor or semiconductor regions 105c1 and 105c2, and on and in contact with the back sides of the insulating walls 105a, 105b and 105d. The antireflection layer 109 is, for example, deposited continuously over the entire rear surface of the sensor. As an example, the layer 109 is deposited by atomic layer deposition (ALD). More generally, any other conformal deposition method can be used. As an example, the thickness of the antireflection layer 109 is in the range from 2 nm to 200 nm, for example about 47 nm.

[0071] Fig.10 The step of depositing a protective insulating layer 111, for example made of silicon oxide, is illustrated, which is over the back side of the antireflection layer 109 and in contact therewith. The protective layer 111 is for example deposited continuously over the entire rear surface of the sensor. As an example, the thickness of the protective layer 111 ranges from 15 nm to 400 nm.

[0072] As mentioned before, other layers (not shown) may be provided on the back side of the sensor, depending on the needs of the application, such as a filter layer made of a colored resin, a layer of microlenses, etc.

[0073] about Figures 3 to 10 An advantage of the described production method and the sensor obtained by this method is that the dark current detected by the sensor pixels is significantly reduced.

[0074] A possible explanation for this advantage is that the dielectric passivation layer 107 is not completely electrically insulating and is Figure 2 In a structure of the type described, parasitic charges may be conducted from the conductor or semiconductor regions 105c1 and 105c2 to the light detection region of the pixel formed in the semiconductor layer 101. Figures 3 to 10 In a sensor of the type obtained by the method, the interruption of the passivation layer 107 opposite the back side of the protruding portions of the insulating walls 105 a , 105 b and 105 d makes it possible to interrupt the conduction of parasitic charges via the layer 107 .

[0075] Fig.11 It is a graphic Figures 3 to 10 A simplified partial cross-sectional view of an alternative embodiment of the method illustrated in FIG. Fig.11 is with Figures 3 to 10 A view in the same section showing the sensor obtained at the end of the method.

[0076] Fig.11 Methods and Figures 3 to 10 The main difference between the methods is that Fig.11 In the example of Fig.11 Prior to the step of planarizing the back side of the sensor (shown in FIG. 1 ), an anti-reflection layer 109 is deposited on the back side of the passivation layer 107. Figure 7 ), the passivation layer 107 and the anti-reflection layer 109 opposite the back side of the insulating walls 105a, 105b and 105d are interrupted. After removing the sacrificial layer 201, the protective layer 111 can be deposited on and in contact with the back side of the anti-reflection layer 109 opposite the semiconductor layer 101 and the conductors or semiconductor regions 105c1 and 105c2, and deposited on and in contact with the exposed portion of the passivation layer 107 opposite the semiconductor layer 101 and the conductors or semiconductor regions 105c1 and 105c2, and deposited on and in contact with the back side of the insulating walls 105a, 105b and 105d. In this variant, the material of the sacrificial layer 201 is selected to be selectively etchable not only relative to the material of the layer 107 and relative to the material of the insulating walls 105a, 105b and 105d, but also relative to the material of the layer 109.

[0077] Fig.11 The advantage of the manufacturing method and the sensor obtained by this method is that by avoiding the conduction of parasitic charges from the conductor or semiconductor regions 105c1 and 105c2 to the semiconductor layer 101 via the layer 109, dark currents can be further reduced.

[0078] Fig.12 A and Fig.12 B shows Figures 3 to 10 Another variation of the method illustrated in FIG. Fig.12 A and Fig.12 B each shows an enlarged view of a portion of the sensor close to the back side of the sensor at the level of the insulating wall 105a of the vertical capacitive insulating wall 105 of the sensor (corresponding to the portion indicated by Figure 4 The portion defined by the frame 12 in FIG.

[0079] Fig.12 A shows that Figure 4 The back side of the sensor at the end of the step of selectively partially etching layer 101 and regions 105c1 and 105c2 as described. Fig.12As shown in FIG. 1A , it can be observed that, in practice, the etching of the layer 101 and of the regions 105c1 and 105c2 is not completely uniform. More specifically, depending on the type of method used to perform the etching, remnants of the material of the layer 101 and of the regions 105c1 and 105c2 may still be present in the immediate vicinity of the insulating walls 105a, 105b and 105d, for example due to shadow effects, selectivity effects, etc. This results in the formation of dot-like or bird's beak structures 301 in the layer 101 and / or in the regions 105c1 and 105c2, supported on the insulating walls 105a, 105b and 105c.

[0080] Fig.12 B shows the oxidation Figure 3 and Figure 4 The step of forming a relatively thick oxide layer 303 (thickness, for example, in the range from 1 nm to 10 nm, for example, about 5 nm) on the back side of the semiconductor layer 101 and on the back sides of the regions 105c1 and 105c2 of the capacitive insulating wall 105 is completed at the end of the step. Fig.12 This oxidation step results in a significant rounding or even suppression of the points of the bird's beak structure 301 at the interface with the insulating walls 105a, 105b and 105d, as shown in B. As an example, the oxidation step is performed by subjecting the back side of the sensor to an oxygen plasma, preferably at a temperature of less than 400° C., in order to avoid damaging the interconnect structure 103 of the sensor. As a variant, a chemical oxidation may be provided.

[0081] The remainder of the method is similar to that described previously. Figures 5 to 10 The same or similar description.

[0082] Fig.12 A and Fig.12 An advantage of the alternative embodiment of B is that it enables the voltage behavior of the capacitive insulating wall of the sensor to be further improved.

[0083] Of course, you can combine Fig.11 and Fig.12 A and Fig.12 Alternative embodiment of B.

[0084] Fig.13 is a partially simplified cross-sectional view illustrating another example of a backside illuminated image sensor according to one embodiment.

[0085] Fig.13 is with Fig.10 View in the same section. Fig.13 The sensor shows the Fig.10 The same elements of the sensor and through similar Figures 3 to 10 The manufacturing method described in the following will only be described in detail with respect to Fig.10 The difference between the sensors.

[0086] Fig.13 The sensor and Fig.10 The main difference between the sensors is that Fig.13 In the example of FIG. 1 , the capacitive insulating wall 105 does not include the central insulating wall 105d. Fig.13 In the example of , regions 105c1 and 105c2 are combined in a single central conductive or semiconductor region 105c. In other words, each capacitive insulating wall 105 includes: two insulating walls 105a and 105b, whose outer surfaces are in contact with the semiconductor layer 101; and a conductor or semiconductor region 105c, which forms a single central wall, and the side surfaces of the single central wall are in contact with the inner side surfaces of the insulating wall 105a and the inner side surfaces of the insulating wall 105b, respectively.

[0087] certainly, Fig.13 The variant can be Fig.11 Variations and / or Fig.12 A and Fig.12 A variant combination of B.

[0088] Various embodiments and variations have been described. It will be appreciated by those skilled in the art that certain features of these various embodiments and variations may be combined, and other variations will occur to those skilled in the art. In particular, the above embodiments are not limited to examples of numerical dimensions or examples of materials mentioned in this disclosure.

[0089] Such changes, modifications and improvements are intended to be part of this disclosure and are intended to fall within the spirit and scope of this disclosure. Therefore, the foregoing description is only exemplary and is not intended to limit the present invention. This disclosure is limited only by the appended claims and their equivalents.

[0090] The various embodiments described above can be combined to provide additional embodiments. These and other changes can be made to the embodiments according to the above detailed description. Generally, in the appended claims, the terms used should not be interpreted as limiting the claims to the specific embodiments disclosed in the specification and claims, but should be interpreted as including all possible embodiments and the full range of equivalents to which these claims are given. Therefore, the claims are not limited by this disclosure.

Claims

1. A method for manufacturing an image sensor, comprising: Forming a capacitive insulating wall in a semiconductor layer having opposite first and second surfaces, the forming the capacitive insulating wall comprising: forming a first insulating wall extending between the first surface and the second surface of the semiconductor layer; forming a second insulating wall extending between the first surface and the second surface of the semiconductor layer, the second insulating wall being laterally spaced apart from the first insulating wall by a first region of conductive or semiconductor material; A third insulating wall is formed extending between the first surface and the second surface of the semiconductor layer, the third insulating wall is laterally separated from the second insulating wall by the second region of the conductor or semiconductor material, and the first insulating wall, the second insulating wall, the third insulating wall, and the first region and the second region of the conductor or semiconductor material are coplanar with each other on the first surface of the semiconductor layer; forming protruding portions of the first insulating wall, the second insulating wall, and the third insulating wall by etching the semiconductor layer and the first and second regions of the conductor or semiconductor material from the first surface, the protruding portions extending outwardly beyond the back side of the semiconductor layer and the back sides of the first and second regions of the conductor or semiconductor material; forming a passivation layer on the back side of the semiconductor layer, the back sides of the first and second regions of the conductor or semiconductor material, and the back sides of the protruding portions of the first, second, and third insulating walls; and Portions of the passivation layer on the back sides of the protruding portions of the first, second, and third insulating walls are selectively removed.

2. The method according to claim 1, further comprising: An anti-reflection layer is formed on a back side of the passivation layer and on the back sides of the protruding portions of the first, second, and third insulating walls.

3. The method according to claim 2, further comprising: A protective layer is formed on the anti-reflection layer. 4 . The method of claim 1 , wherein after selectively removing the portion of the passivation layer, the passivation layer remains on sides of the protruding portions of the first, second, and third insulating walls.

5. The method according to claim 1, further comprising: forming a sacrificial layer on the passivation layer, The selectively removing the portion of the passivation layer includes thinning the sacrificial layer to expose the protruding portions of the first insulating wall, the second insulating wall, and the third insulating wall.

6. A device comprising: a first semiconductor layer having a first side and a second side; a first insulating layer extending from a first side of the first semiconductor layer and beyond a second side of the first semiconductor layer; a second semiconductor layer adjacent to the first insulating layer, the second semiconductor layer extending from the first side of the first semiconductor layer to the second side of the first semiconductor layer; a second insulating layer adjacent to the second semiconductor layer, the second insulating layer extending from the first side of the first semiconductor layer beyond the second side of the first semiconductor layer, A dielectric passivation layer coats the second side of the first semiconductor layer and a back surface of the second semiconductor layer, the first insulating layer and the second insulating layer being uncoated by the dielectric passivation layer. 7 . The device of claim 6 , further comprising a third insulating layer on the second side of the first semiconductor layer, an outer surface of the first insulating layer and an outer surface of the second insulating layer remaining uncoated by the third insulating layer.

8. The device of claim 7, further comprising an anti-reflection layer on the third insulating layer. 9 . The device of claim 8 , further comprising a first groove between the first insulating layer and the second insulating layer, the first groove extending beyond the second side of the first semiconductor layer.

10. The device of claim 9, wherein the first groove comprises a portion of an anti-reflective layer. The device of claim 10 , further comprising a fourth insulating layer on the anti-reflection layer.

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