Display device

Abstract

A display device is provided. The display device includes a first light emitting element disposed in a first pixel region on a substrate and including a first pixel electrode having an octagonal planar shape, a second light emitting element disposed in a second pixel region on the substrate and including a second pixel electrode, a third light emitting element disposed in a third pixel region on the substrate and including a third pixel electrode having an octagonal planar shape, and a pixel defining layer covering an edge of each of the first pixel electrode, the second pixel electrode, and the third pixel electrode. A virtual line extending to coincide with a side edge of the first pixel electrode defines a first virtual quadrilateral, and a virtual line extending to coincide with a side edge of a third pixel electrode adjacent to the first pixel electrode defines a second virtual quadrilateral. The first virtual quadrangle at least partially overlaps the second virtual quadrangle in a plan view.

Description

Technical Field

[0001] Embodiments generally relate to display devices and more particularly to display devices that provide visual information. Background Art

[0002] As information technology develops, the importance of display devices as a communication medium between users and information has been emphasized. Therefore, the use of display devices such as liquid crystal display devices, organic light emitting display devices, plasma display devices, and the like is increasing.

[0003] Meanwhile, the display device may include a plurality of pixels, and each of the plurality of pixels may include at least one transistor and an organic light emitting element electrically connected to the at least one transistor.

[0004] For example, a technique for depositing a light emitting layer included in an organic light emitting element on a substrate may include a process using a fine metal mask (FMM), a photolithography process without using a fine metal mask, or the like. Summary of the invention

[0005] Embodiments provide a display device capable of preventing a reduction in light emitting efficiency.

[0006] The display device according to the embodiment of the present disclosure includes a substrate, a first light-emitting element, a second light-emitting element, a third light-emitting element and a pixel defining layer, the substrate includes a first pixel region, a second pixel region and a third pixel region emitting light of different colors, the first light-emitting element is arranged in the first pixel region on the substrate and includes a first pixel electrode having an octagonal plane shape, the second light-emitting element is arranged in the second pixel region on the substrate and includes a second pixel electrode, the third light-emitting element is arranged in the third pixel region on the substrate and includes a third pixel electrode having an octagonal plane shape, the pixel defining layer covers the edges of the first pixel electrode, the second pixel electrode and the third pixel electrode, and defines a first pixel opening, a second pixel opening and a third pixel opening respectively exposing at least a portion of the first pixel electrode, the second pixel electrode and the third pixel electrode. A virtual first line extending to overlap with each of a plurality of first sides extending in a first direction of the first pixel electrode and a virtual second line extending to overlap with each of a plurality of second sides extending in a second direction perpendicular to the first direction of the first pixel electrode define a first virtual quadrilateral. A virtual third line extending to coincide with each of a plurality of first sides extending in the first direction of a third pixel electrode adjacent to the first pixel electrode and a virtual fourth line extending to coincide with each of a plurality of second sides extending in the second direction of the third pixel electrode define a second virtual quadrilateral. The first virtual quadrilateral at least partially overlaps the second virtual quadrilateral in a plan view.

[0007] In an implementation, the second pixel electrode may have a rectangular, circular, or octagonal planar shape.

[0008] In an embodiment, the first pixel region may emit red light, the second pixel region may emit green light, and the third pixel region may emit blue light.

[0009] In an embodiment, a length of a side of the first pixel electrode extending parallel to the first side of the second pixel electrode may be shorter than a length of a side of the third pixel electrode extending parallel to the second side of the second pixel electrode.

[0010] In an embodiment, the length of the third side of the first pixel electrode connecting the first side and the second side of the first pixel electrode may be the same as the length of the third side of the third pixel electrode connecting the first side and the second side of the third pixel electrode and extending parallel to the third side of the first pixel electrode.

[0011] In an embodiment, the length of the first side of the second pixel electrode extending parallel to the second side of the first pixel electrode may be the same as the length of the second side of the first pixel electrode. The length of the second side of the second pixel electrode extending parallel to the first side of the third pixel electrode is the same as the length of the first side of the third pixel electrode.

[0012] In an embodiment, the planar shape of the first pixel opening may substantially correspond to the planar shape of the first pixel electrode, the planar shape of the second pixel opening may substantially correspond to the planar shape of the second pixel electrode, and the planar shape of the third pixel opening may substantially correspond to the planar shape of the third pixel electrode.

[0013] In an embodiment, the first light emitting element may further include a first light emitting layer disposed in the first pixel opening, the second light emitting element may further include a second light emitting layer disposed in the second pixel opening, and the third light emitting element may further include a third light emitting layer disposed in the third pixel opening.

[0014] In an embodiment, the display device may further include a first transistor connected to the first pixel electrode through the first contact hole, a second transistor connected to the second pixel electrode through the second contact hole, and a third transistor connected to the third pixel electrode through the third contact hole.

[0015] In an implementation, each of the first contact hole, the second contact hole, and the third contact hole may have a rectangular planar shape.

[0016] In an embodiment, the first contact hole may not overlap the first light emitting layer in plan view, the second contact hole may not overlap the second light emitting layer in plan view, and the third contact hole may not overlap the third light emitting layer in plan view.

[0017] In an embodiment, at least one contact hole among the first, second, and third contact holes may be positioned at an edge of a pixel electrode disposed adjacent to the at least one contact hole among the first, second, and third pixel electrodes.

[0018] In an embodiment, at least one pixel electrode among the first pixel electrode, the second pixel electrode, and the third pixel electrode may include a protrusion positioned in one side, and in a plan view, at least one contact hole among the first contact hole, the second contact hole, and the third contact hole that is arranged adjacent to the at least one pixel electrode may partially overlap with the protrusion.

[0019] In an embodiment, at least one contact hole among the first, second, and third contact holes may be positioned at a center of a pixel electrode adjacent to the at least one contact hole among the first, second, and third pixel electrodes.

[0020] In an implementation, at least one contact hole may overlap the pixel defining layer in a plan view.

[0021] In an embodiment, the display device may further include a conductive pattern filling each of the first contact hole, the second contact hole, and the third contact hole, contacting each of the first pixel electrode, the second pixel electrode, and the third pixel electrode, and including a conductive material different from the conductive material of the first pixel electrode, the second pixel electrode, and the third pixel electrode.

[0022] In an embodiment, the first contact hole, the second contact hole, and the third contact hole may at least partially overlap the first light emitting layer, the second light emitting layer, and the third light emitting layer, respectively, in a plan view.

[0023] In an embodiment, a size of the first pixel electrode may be substantially the same as a size of the third pixel electrode.

[0024] In an embodiment, each of the plurality of side edges of the first pixel electrode facing the second pixel electrode may be recessed toward the center of the first pixel electrode, and each of the plurality of side edges of the third pixel electrode facing the second pixel electrode may be recessed toward the center of the third pixel electrode. The second pixel electrode may have an octagonal or circular planar shape.

[0025] In an implementation, each of a plurality of side edges of the third pixel electrode facing the second pixel electrode may be recessed toward a center of the third pixel electrode, and the electrode of the second pixel may have an octagonal or circular planar shape.

[0026] In an embodiment, virtual lines extending in a third direction between the first direction and the second direction and in a fourth direction perpendicular to the third direction may define a virtual square. The center of the first pixel electrode may be positioned at first vertices of the virtual square facing each other, the center of the third pixel electrode may be positioned at second vertices of the virtual square facing each other, and the second pixel electrode may be positioned at the center of the virtual square.

[0027] The display device according to the embodiment of the present disclosure includes a substrate, a first light-emitting element, a second light-emitting element, a third light-emitting element and a pixel defining layer, the substrate includes a first pixel region, a second pixel region and a third pixel region emitting light of different colors, the first light-emitting element is arranged in the first pixel region on the substrate and includes a first pixel electrode having a polygonal plane shape, the second light-emitting element is arranged in the second pixel region on the substrate and includes a second pixel electrode, the third light-emitting element is arranged in the third pixel region on the substrate and includes a third pixel electrode having a polygonal plane shape, the pixel defining layer covers the edge of each of the first pixel electrode, the second pixel electrode and the third pixel electrode, and defines a first pixel opening, a second pixel opening and a third pixel opening respectively exposing at least a portion of the first pixel electrode, the second pixel electrode and the third pixel electrode. One of the first pixel electrode and the third pixel electrode may have a quadrilateral plane shape including a chamfered corner portion.

[0028] In an implementation, the other of the first pixel electrode and the third pixel electrode may have a quadrangular or octagonal planar shape.

[0029] In an embodiment, a virtual first line extending to coincide with each of a plurality of first sides extending in a first direction of one of the first pixel electrode and the third pixel electrode and a virtual second line extending to coincide with each of a plurality of second sides extending in a second direction perpendicular to the first direction of one of the first pixel electrode and the third pixel electrode may define a virtual quadrilateral. The virtual quadrilateral may at least partially overlap the other of the first pixel electrode and the third pixel electrode in a plan view.

[0030] In an embodiment, when the first pixel electrode includes a chamfered corner portion and the third pixel electrode has a quadrangular planar shape, the chamfered corner portion of the first pixel electrode may surround at least a portion of corner portions of the third pixel electrode facing each other in a plan view.

[0031] In an implementation, the second pixel electrode may have a quadrilateral planar shape.

[0032] In an embodiment, the display device may further include a first transistor connected to the first pixel electrode through the first contact hole, a second transistor connected to the second pixel electrode through the second contact hole, and a third transistor connected to the third pixel electrode through the third contact hole.

[0033] In an embodiment, at least one contact hole among the first, second, and third contact holes may be positioned at an edge of a pixel electrode adjacent to the at least one contact hole among the first, second, and third pixel electrodes.

[0034] In an embodiment, at least one pixel electrode among the first pixel electrode, the second pixel electrode, and the third pixel electrode may include a protrusion positioned in one side, and in a plan view, at least one contact hole among the first contact hole, the second contact hole, and the third contact hole adjacent to the at least one pixel electrode may partially overlap with the protrusion.

[0035] In an embodiment, at least one contact hole among the first, second, and third contact holes may be positioned at a center of a pixel electrode adjacent to the at least one contact hole among the first, second, and third pixel electrodes.

[0036] In a display device according to an embodiment of the present disclosure, each of the first pixel electrode disposed in the first pixel region emitting red light and the third pixel electrode disposed in the third pixel region emitting blue light may have an octagonal plane shape, and the second pixel electrode disposed in the second pixel region emitting green light may have a quadrilateral plane shape. A first virtual quadrilateral defined by a virtual line extending to coincide with a side extending in a diagonal direction of the first pixel electrode may at least partially overlap with a second virtual quadrilateral defined by a virtual line extending to coincide with a side extending in a diagonal direction of the third pixel electrode. Therefore, it is possible to prevent the luminous efficiency of the display device from being reduced.

[0037] Alternatively, in the display device according to the embodiment of the present disclosure, one of the first pixel electrode and the third pixel electrode may have a quadrilateral planar shape including a chamfered corner portion, and the other of the first pixel electrode and the third pixel electrode may have a quadrilateral or octagonal planar shape. Therefore, it is possible to prevent the luminous efficiency of the display device from being reduced. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] The illustrative, non-limiting embodiments will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings.

[0039] Figure 1 is a plan view showing a display device according to an embodiment of the present disclosure.

[0040] Figure 2 It is shown Figure 1 An enlarged plan view of an example of a portion of the display area.

[0041] Figure 3 It is used to explain Figure 2 A plan view of a first pixel electrode, a second pixel electrode and a third pixel electrode.

[0042] Figure 4 It is used to explain Figure 2 A plan view of the relationship between the first pixel electrode, the first pixel opening and the first contact hole, and the relationship between the second pixel electrode, the second pixel opening and the second contact hole.

[0043] Figure 5 It is used to explain Figure 2 A plan view of the relationship between a third pixel electrode, a third pixel opening and a third contact hole.

[0044] Figure 6 is along Figure 2 A cross-sectional view taken along line II'.

[0045] Figure 7 and Figure 8 It is shown Figure 2 A plan view of an example of a first contact hole, a second contact hole, and a third contact hole.

[0046] Fig. 9 yes Figure 1 An enlarged plan view of another example of a portion of a display area.

[0047] Fig.10 is along Fig. 9 A cross-sectional view taken along line II-II'.

[0048] Fig.11 It is shown Fig. 9 A plan view of an example of a first contact hole, a second contact hole, and a third contact hole.

[0049] Fig.12 , Fig.13 , Fig.14 , Fig.15 , Fig.16 , Fig.17 and Fig.18 It is shown Figure 2 and Fig. 9 FIG. 1 is a plan view of an example of a plan shape of each of the first pixel electrode, the second pixel electrode, and the third pixel electrode. DETAILED DESCRIPTION

[0050] Hereinafter, a display device according to an embodiment of the present disclosure will be explained in detail with reference to the accompanying drawings. In the accompanying drawings, the same reference numerals are used for the same components, and redundant descriptions of the same components will be omitted.

[0051] Figure 1 is a plan view showing a display device according to an embodiment of the present disclosure.

[0052] Reference Figure 1 , a display device DD according to an embodiment of the present disclosure may include a display area DA and a non-display area NDA. The display area DA may be an area capable of displaying an image by generating light or adjusting the transmittance of light provided from an external light source. The non-display area NDA may be an area where an image is not displayed. The non-display area NDA may be positioned around the display area DA. For example, the non-display area NDA may completely surround the display area DA.

[0053] A plurality of pixels P may be arranged in the display area DA. The plurality of pixels P may be arranged in a matrix along a first direction DR1 and a second direction DR2 crossing the first direction DR1.

[0054] Each of the plurality of pixels P may include at least one transistor generating a driving current and an organic light emitting element electrically connected to the transistor and receiving the driving current. The organic light emitting element may emit light based on the driving current. When each of the plurality of pixels P emits light through the organic light emitting element, the display area DA may display an image.

[0055] One pixel P may display one predetermined basic color. In other words, one pixel P may be the smallest unit that can display a color independently of other pixels P. For example, one pixel P may display any one color among red, green, and blue.

[0056] The non-display area NDA may include a pad area PDA. The pad area PDA may be positioned away from one side of the display area DA. For example, the pad area PDA may have a shape extending in the first direction DR1.

[0057] A plurality of signal lines may be disposed in the non-display area NDA, and a plurality of pad electrodes PDE may be disposed in the pad area PDA. The signal lines may electrically connect the pad electrodes PDE and the plurality of pixels P. For example, the signal lines may include data signal lines, scan signal lines, emission control signal lines, power supply voltage lines, and the like.

[0058] The pad electrodes PDE may be disposed to be spaced apart from each other in the first direction DR1. For example, each of the plurality of pad electrodes PDE may include metal, alloy, metal nitride, conductive metal oxide, transparent conductive material, and the like. These can be used alone or in combination with each other.

[0059] In this specification, a plane may be defined by a first direction DR1 and a second direction DR2 intersecting the first direction DR1. For example, the first direction DR1 may be perpendicular to the second direction DR2.

[0060] Figure 2 It is shown Figure 1 An enlarged plan view of an example of a portion of the display area.

[0061] Reference Figure 2 , the display area DA may include a first pixel area PX1 , a second pixel area PX2 , and a third pixel area PX3 . Figure 1 The plurality of pixels P shown in FIG. 1 may be disposed in the first pixel region PX1 , the second pixel region PX2 , and the third pixel region PX3 , respectively.

[0062] Each of the first pixel region PX1, the second pixel region PX2, and the third pixel region PX3 may represent an area at which light emitted from the organic light emitting element is emitted to the outside of the display device DD. For example, the first pixel region PX1 may emit a first light, the second pixel region PX2 may emit a second light, and the third pixel region PX3 may emit a third light. In an embodiment, the first light may be red light, the second light may be green light, and the third light may be blue light. However, the present disclosure is not limited thereto. For example, the first pixel region PX1, the second pixel region PX2, and the third pixel region PX3 may be combined to emit yellow light, cyan light, and magenta light.

[0063] The first pixel region PX1, the second pixel region PX2, and the third pixel region PX3 may emit four or more colors of light. For example, the first pixel region PX1, the second pixel region PX2, and the third pixel region PX3 may be combined to emit at least one of yellow light, cyan light, and magenta light in addition to red light, green light, and blue light. In addition, the first pixel region PX1, the second pixel region PX2, and the third pixel region PX3 may be combined to emit white light.

[0064] The first pixel region PX1, the second pixel region PX2, and the third pixel region PX3 may be arranged in a matrix along the first direction DR1 and the second direction DR2. In an embodiment, the first pixel region PX1, the second pixel region PX2, and the third pixel region PX3 may be arranged in a diamond shape. shape. For example, the third pixel region PX3 and the first pixel region PX1 may be alternately arranged in the first row 1N, and the second pixel region PX2 may be arranged at a predetermined interval in the second row 2N adjacent to the first row 1N. In addition, the first pixel region PX1 and the third pixel region PX3 may be alternately arranged in the third row 3N adjacent to the second row 2N, and the second pixel region PX2 may be arranged at a predetermined interval in the fourth row 4N adjacent to the third row 3N. The arrangement of these pixel regions may be repeated until the Nth row (where N is a natural number).

[0065] The second pixel region PX2 arranged in the second row 2N may be arranged adjacent to the first pixel region PX1 arranged in the first row 1N and the third row 3N in the third direction DR3 or the fourth direction DR4, and may be arranged adjacent to the third pixel region PX3 arranged in the first row 1N and the third row 3N in the third direction DR3 or the fourth direction DR4. Therefore, the third pixel region PX3 and the first pixel region PX1 may be alternately arranged in the first column 1M, and the second pixel region PX2 may be arranged at a predetermined interval in the second column 2M arranged adjacent to the first column 1M. In addition, the first pixel region PX1 and the third pixel region PX3 may be alternately arranged in the third column 3M arranged adjacent to the second column 2M, and the second pixel region PX2 may be arranged at a predetermined interval in the fourth column 4M arranged adjacent to the third column 3M. The arrangement of these pixel regions may be repeated until the Mth column (where M is a natural number).

[0066] Here, the third direction DR3 may be a direction between the first direction DR1 and the second direction DR2, and the fourth direction DR4 may be perpendicular to the third direction DR3.

[0067] A first pixel electrode PE1 may be disposed in each of the plurality of first pixel regions PX1, a second pixel electrode PE2 may be disposed in each of the plurality of second pixel regions PX2, and a third pixel electrode PE3 may be disposed in each of the plurality of third pixel regions PX3. The first pixel electrode PE1, the second pixel electrode PE2, and the third pixel electrode PE3 may be disposed to be spaced apart from each other.

[0068] Each of the first pixel electrode PE1, the second pixel electrode PE2, and the third pixel electrode PE3 may have various polygonal planar shapes. In an embodiment, each of the first pixel electrode PE1 and the third pixel electrode PE3 may have an octagonal planar shape, and the second pixel electrode PE2 may have a quadrilateral (e.g., rectangular) planar shape. In this case, each corner of the rectangle may have a right angle or be rounded with a predetermined curvature. However, embodiments of the present disclosure are not limited thereto. A detailed description of the planar shape of each of the first pixel electrode PE1, the second pixel electrode PE2, and the third pixel electrode PE3 will be described later.

[0069] The first pixel electrode PE1 may be electrically connected to the first transistor (eg, Figure 6 The second pixel electrode PE2 may be electrically connected to the second transistor (eg, the first transistor TR1) through the second contact hole CNT2. Figure 6 The third pixel electrode PE3 may be electrically connected to the third transistor (eg, the second transistor TR2) through the third contact hole CNT3. Figure 6 The third transistor TR3).

[0070] At least one of the first contact hole CNT1, the second contact hole CNT2, and the third contact hole CNT3 may be positioned at an edge of a pixel electrode disposed adjacent to the at least one contact hole among the first pixel electrode PE1, the second pixel electrode PE2, and the third pixel electrode PE3. In an embodiment, the first contact hole CNT1, the second contact hole CNT2, and the third contact hole CNT3 may be positioned at edges of the first pixel electrode PE1, the second pixel electrode PE2, and the third pixel electrode PE3, respectively. In this case, for example, each of the first pixel electrode PE1, the second pixel electrode PE2, and the third pixel electrode PE3 may not include a protrusion positioned in one side. That is, each of the first pixel electrode PE1 and the third pixel electrode PE3 may have a complete octagonal plane shape that does not include a protrusion, and the second pixel electrode PE2 may have a complete quadrilateral plane shape that does not include a protrusion.

[0071] Each of the first contact hole CNT1, the second contact hole CNT2, and the third contact hole CNT3 may have a polygonal plan shape. In an embodiment, each of the first contact hole CNT1, the second contact hole CNT2, and the third contact hole CNT3 may have a rectangular or elliptical plan shape. In this case, the rectangular plan shape may include a plurality of corners each having a right angle or a rounded corner.

[0072] A pixel defining layer PDL may be disposed in the display area DA. Specifically, the pixel defining layer PDL may be disposed to cover an edge of each of the first pixel electrode PE1, the second pixel electrode PE2, and the third pixel electrode PE3.

[0073] The pixel defining layer PDL may define: a first pixel opening OP1 exposing at least a portion of the first pixel electrode PE1 in the first pixel region PX1, a second pixel opening OP2 exposing at least a portion of the second pixel electrode PE2 in the second pixel region PX2, and a third pixel opening OP3 exposing at least a portion of the third pixel electrode PE3 in the third pixel region PX3. For example, the pixel defining layer PDL may include an inorganic insulating material and / or an organic insulating material. Alternatively, the pixel defining layer PDL may include an inorganic insulating material and / or an organic insulating material containing a light blocking material.

[0074] In an embodiment, the pixel defining layer PDL may overlap the first, second, and third contact holes CNT1, CNT2, and CNT3 in a plan view. That is, the pixel defining layer PDL may cover the first, second, and third contact holes CNT1, CNT2, and CNT3.

[0075] In an embodiment, the plane shape of the first pixel opening OP1 may substantially correspond to the plane shape of the first pixel electrode PE1, the plane shape of the second pixel opening OP2 may substantially correspond to the plane shape of the second pixel electrode PE2, and the plane shape of the third pixel opening OP3 may substantially correspond to the plane shape of the third pixel electrode PE3. That is, except for the peripheries of the first contact hole CNT1, the second contact hole CNT2, and the third contact hole CNT3, the side edges of the first pixel opening OP1, the second pixel opening OP2, and the third pixel opening OP3 may be parallel to the side edges of the first pixel electrode PE1, the second pixel electrode PE2, and the third pixel electrode PE3, respectively. In other words, each of the first pixel opening OP1 and the third pixel opening OP3 may have a substantially octagonal plane shape, and the second pixel opening OP2 may have a substantially quadrilateral plane shape.

[0076] A first light emitting layer (eg, Figure 6 A first light emitting layer EML1) may be provided in the second pixel opening OP2. Figure 6 A second light emitting layer EML2) may be provided in the third pixel opening OP3, and a third light emitting layer (eg, Figure 6 The third light-emitting layer EML3).

[0077] The size of the first pixel opening OP1 may be substantially the same as the size of the first pixel region PX1, the size of the second pixel opening OP2 may be substantially the same as the size of the second pixel region PX2, and the size of the third pixel opening OP3 may be substantially the same as the size of the third pixel region PX3. That is, the first light emitting layer, the second light emitting layer, and the third light emitting layer respectively disposed in the first pixel opening OP1, the second pixel opening OP2, and the third pixel opening OP3 may correspond to the first pixel region PX1, the second pixel region PX2, and the third pixel region PX3, respectively.

[0078] Figure 3 It is used to explain Figure 2 A plan view of a first pixel electrode, a second pixel electrode and a third pixel electrode.

[0079] Reference Figure 2 and Figure 3 , the size of the first pixel electrode PE1, the size of the second pixel electrode PE2, and the size of the third pixel electrode PE3 may be different from each other. In an embodiment, the size of the third pixel electrode PE3 may be larger than the size of the first pixel electrode PE1, and the size of the first pixel electrode PE1 may be larger than the size of the second pixel electrode PE2. However, embodiments of the present disclosure are not limited thereto.

[0080] As described above, the first pixel electrode PE1 may be disposed in the first pixel region PX1, the second pixel electrode PE2 may be disposed in the second pixel region PX2, and the third pixel electrode PE3 may be disposed in the third pixel region PX3. Therefore, the arrangement of the first pixel electrode PE1, the second pixel electrode PE2, and the third pixel electrode PE3 may be substantially the same as the arrangement of the first pixel region PX1, the second pixel region PX2, and the third pixel region PX3.

[0081] In an embodiment, a virtual line VL extending in the first direction DR1 and the second direction DR2 may define a virtual square, the center of the first pixel electrode PE1 may be positioned at the first vertex P1 of the virtual square facing each other, the center of the third pixel electrode PE3 may be positioned at the second vertex P2 of the virtual square facing each other, and the second pixel electrode PE2 may be positioned at the center of the virtual square.

[0082] A virtual first line VL1 extending to coincide with each of a plurality of first sides S11 of the first pixel electrode PE1 extending in the third direction DR3 and a virtual second line VL2 extending to coincide with each of a plurality of second sides S12 of the first pixel electrode PE1 extending in the fourth direction DR4 may define a first virtual quadrilateral VS1 (e.g., a square).

[0083] Similarly, a virtual third line VL3 extending to coincide with each of a plurality of first side edges S31 extending in the third direction DR3 of a third pixel electrode PE3 adjacent to the first pixel electrode PE1 and a virtual fourth line VL4 extending to coincide with each of a plurality of second side edges S32 extending in the fourth direction DR4 of the third pixel electrode PE3 may define a second virtual quadrilateral VS2 (e.g., a square).

[0084] In an embodiment, the first virtual quadrilateral VS1 may partially overlap the second virtual quadrilateral VS2 in a plan view.

[0085] The first pixel electrode PE1 may include two first sides S11, two second sides S12, and four third sides S13. The first sides S11 of the first pixel electrode PE1 may face each other, the second sides S12 of the first pixel electrode PE1 may face each other, and the third sides S13 of the first pixel electrode PE1 disposed near opposite corners of the first virtual quadrilateral VS1 may face each other. Each of the plurality of first sides S11 of the first pixel electrode PE1 may extend in the third direction DR3, each of the plurality of second sides S12 may extend in the fourth direction DR4, and each of the plurality of third sides S13 may extend in the first direction DR1 or the second direction DR2.

[0086] Likewise, the third pixel electrode PE3 may include two first sides S31, two second sides S32, and four third sides S33. The first sides S31 of the third pixel electrode PE3 may face each other, the second sides S32 of the third pixel electrode PE3 may face each other, and the third sides S33 of the third pixel electrode PE3 disposed near the opposite corners of the second virtual quadrilateral VS2 may face each other. Each of the plurality of first sides S31 of the third pixel electrode PE3 may extend in the third direction DR3, each of the plurality of second sides S32 may extend in the fourth direction DR4, and each of the plurality of third sides S33 may extend in the first direction DR1 or the second direction DR2.

[0087] The second pixel electrode PE2 may include two first sides S21 and two second sides S22. The two first sides S21 of the second pixel electrode PE2 may face each other, and the two second sides S22 may face each other. Each of the plurality of first sides S21 of the second pixel electrode PE2 may extend in the fourth direction DR4 or the third direction DR3, and each of the plurality of second sides S22 may extend in the third direction DR3 or the fourth direction DR4.

[0088] The first side S21 of the second pixel electrode PE2 may be parallel to the second side S12 or the first side S11 of the first pixel electrode PE1, and the second side S22 of the second pixel electrode PE2 may be parallel to the first side S31 or the second side S32 of the third pixel electrode PE3. In an embodiment, a length L12 or L11 of each of the plurality of second sides S12 or the plurality of first sides S11 of the first pixel electrode PE1 may be shorter than a length L31 or L32 of each of the plurality of first sides S31 or the plurality of second sides S32 of the third pixel electrode PE3.

[0089] The first side S11 of the first pixel electrode PE1 may be parallel to the first side S31 of the third pixel electrode PE3, and the second side S12 of the first pixel electrode PE1 may be parallel to the second side S32 of the third pixel electrode PE3. For example, the length L11 of each of the plurality of first sides S11 of the first pixel electrode PE1 may be substantially the same as the length L12 of each of the plurality of second sides S12 of the first pixel electrode PE1, and the length L31 of each of the plurality of first sides S31 of the third pixel electrode PE3 may be substantially the same as the length L32 of each of the plurality of second sides S32 of the third pixel electrode PE3.

[0090] In an embodiment, the length L21 of each of the plurality of first sides S21 of the second pixel electrode PE2 may be substantially the same as the length L12 or L11 of each of the plurality of second sides S12 or the plurality of first sides S11 of the first pixel electrode PE1, and the length L22 of each of the plurality of second sides S22 of the second pixel electrode PE2 may be substantially the same as the length L31 or L32 of each of the plurality of first sides S31 or the plurality of second sides S32 of the third pixel electrode PE3. That is, the length L21 of each of the plurality of first sides S21 of the second pixel electrode PE2 may be shorter than the length L22 of each of the plurality of second sides S22 of the second pixel electrode PE2.

[0091] The third side S13 of the first pixel electrode PE1 may be parallel to the third side S33 of the third pixel electrode PE3. In an embodiment, the length L13 of each of the third sides S13 of the first pixel electrode PE1 may be substantially the same as the length L33 of each of the third sides S33 of the third pixel electrode PE3.

[0092] Figure 4 It is used to explain Figure 2 A plan view of the relationship between the first pixel electrode, the first pixel opening and the first contact hole, and the relationship between the second pixel electrode, the second pixel opening and the second contact hole. Figure 5 It is used to explain Figure 2A plan view of the relationship between a third pixel electrode, a third pixel opening and a third contact hole.

[0093] Reference Figure 4 and Figure 5 In an embodiment, a shortest distance D11 between an edge of the first pixel opening OP1 and an edge of the first pixel electrode PE1 may be longer than a shortest distance D12 between an edge of the first pixel opening OP1 and an edge of the first contact hole CNT1 .

[0094] Likewise, in an embodiment, the shortest distance D31 between the edge of the third pixel opening OP3 and the edge of the third pixel electrode PE3 may be longer than the shortest distance D32 between the edge of the third pixel opening OP3 and the edge of the third contact hole CNT3 .

[0095] In an embodiment, the shortest distance D21 between the edge of the second pixel electrode PE2 and the edge of the second contact hole CNT2 in the third direction DR3 may be longer than the shortest distance D22 between the edge of the second pixel electrode PE2 and the edge of the second contact hole CNT2 in the fourth direction DR4. That is, the shortest distance D21 between the first side S21 of the second pixel electrode PE2 and the edge of the second contact hole CNT2 may be longer than the shortest distance D22 between the second side S22 of the second pixel electrode PE2, which is longer than the first side S21, and the edge of the second contact hole CNT2.

[0096] Figure 6 is along Figure 2 A cross-sectional view taken along line II'.

[0097] Reference Figure 6 According to an embodiment of the present disclosure, a display device DD may include a substrate SUB, a buffer layer BUF, a first transistor TR1, a second transistor TR2, and a third transistor TR3, a gate insulating layer GI, an interlayer insulating layer ILD, a via insulating layer VIA, a first light emitting element LED1, a second light emitting element LED2, and a third light emitting element LED3, a pixel defining layer PDL, and an encapsulation layer TFE.

[0098] Here, the first transistor TR1 may include a first active pattern ACT1, a first gate electrode GE1, a first source electrode SE1, and a first drain electrode DE1, the second transistor TR2 may include a second active pattern ACT2, a second gate electrode GE2, a second source electrode SE2, and a second drain electrode DE2, and the third transistor TR3 may include a third active pattern ACT3, a third gate electrode GE3, a third source electrode SE3, and a third drain electrode DE3.

[0099] In addition, the first light-emitting element LED1 may include a first pixel electrode PE1, a first light-emitting layer EML1 and a common electrode CE, the second light-emitting element LED2 may include a second pixel electrode PE2, a second light-emitting layer EML2 and a common electrode CE, and the third light-emitting element LED3 may include a third pixel electrode PE3, a third light-emitting layer EML3 and a common electrode CE.

[0100] As described above, the display device DD may include a display area DA including a first pixel region PX1, a second pixel region PX2, and a third pixel region PX3. Since the display device DD includes the display area DA including the first pixel region PX1, the second pixel region PX2, and the third pixel region PX3, the substrate SUB may also include the first pixel region PX1, the second pixel region PX2, and the third pixel region PX3.

[0101] The substrate SUB may include a transparent material or an opaque material. The substrate SUB may be made of a transparent resin substrate. Examples of transparent resin substrates include polyimide substrates. In this case, the polyimide substrate may include a first organic layer, a first barrier layer, a second organic layer, and the like. Alternatively, the substrate SUB may include a quartz substrate, a synthetic quartz substrate, a calcium fluoride substrate, a fluorine-doped quartz substrate, a soda-lime glass substrate, an alkali-free glass substrate, and the like. These can be used alone or in combination with each other.

[0102] The buffer layer BUF may be disposed on the substrate SUB. The buffer layer BUF can prevent metal atoms or impurities from diffusing from the substrate SUB to the first transistor TR1, the second transistor TR2, and the third transistor TR3. In addition, when the surface of the substrate SUB is uneven, the buffer layer BUF can improve the flatness of the surface of the substrate SUB. For example, the buffer layer BUF may include an inorganic insulating material such as silicon oxide (SiO x ), Silicon Nitride (SiN x ), silicon oxynitride (SiO x N y ) and the like. These can be used alone or in combination with each other.

[0103] The first active pattern ACT1, the second active pattern ACT2, and the third active pattern ACT3 may be disposed on the buffer layer BUF. Each of the first active pattern ACT1, the second active pattern ACT2, and the third active pattern ACT3 may include a metal oxide semiconductor, an inorganic semiconductor (e.g., amorphous silicon, polycrystalline silicon), or an organic semiconductor. Each of the first active pattern ACT1, the second active pattern ACT2, and the third active pattern ACT3 may include a source region, a drain region, and a channel region positioned between the source region and the drain region. The first active pattern ACT1, the second active pattern ACT2, and the third active pattern ACT3 may be formed by the same process and may include the same material.

[0104] The metal oxide semiconductor may include a binary compound (AB) containing indium (In), zinc (Zn), gallium (Ga), tin (Sn), titanium (Ti), aluminum (Al), hafnium (Hf), zirconium (Zr), magnesium (Mg), and the like. x ), three-component compound (AB x C y ), four-component compound (AB x C y D z ) and the like. For example, the metal oxide semiconductor may include zinc oxide (ZnO x ), gallium oxide (GaO x ), tin oxide (SnO x ), indium oxide (InO x ), indium gallium oxide (IGO), indium zinc oxide (IZO), indium tin oxide (ITO), indium zinc tin oxide (IZTO), indium gallium zinc oxide (IGZO), and the like. These can be used alone or in combination with one another.

[0105] The gate insulating layer GI may be disposed on the buffer layer BUF. The gate insulating layer GI may fully cover the first active pattern ACT1, the second active pattern ACT2, and the third active pattern ACT3, and may have a substantially flat upper surface without generating steps around the first active pattern ACT1, the second active pattern ACT2, and the third active pattern ACT3. Alternatively, the gate insulating layer GI may cover the first active pattern ACT1, the second active pattern ACT2, and the third active pattern ACT3, and may be disposed with a uniform thickness along the contour of each of the first active pattern ACT1, the second active pattern ACT2, and the third active pattern ACT3. For example, the gate insulating layer GI may include an inorganic material such as silicon oxide (SiO x ), Silicon Nitride (SiN x ), Silicon Carbide (SiC x ), silicon oxynitride (SiO x N y), Silicon Oxycarbide (SiO x C y ) and the like. These can be used alone or in combination with each other.

[0106] The first gate electrode GE1, the second gate electrode GE2, and the third gate electrode GE3 may be disposed on the gate insulating layer GI. The first gate electrode GE1 may overlap the channel region of the first active pattern ACT1, the second gate electrode GE2 may overlap the channel region of the second active pattern ACT2, and the third gate electrode GE3 may overlap the channel region of the third active pattern ACT3.

[0107] Each of the first gate electrode GE1, the second gate electrode GE2, and the third gate electrode GE3 may include a metal, an alloy, a metal nitride, a conductive metal oxide, a transparent conductive material, and the like. Examples of metals may include silver (Ag), molybdenum (Mo), aluminum (Al), tungsten (W), copper (Cu), nickel (Ni), chromium (Cr), titanium (Ti), tantalum (Ta), platinum (Pt), scandium (Sc), and the like. Examples of conductive metal oxides may include indium tin oxide, indium zinc oxide, and the like. In addition, examples of metal nitrides may include aluminum nitride (AlN x ), tungsten nitride (WN x ), chromium nitride (CrN x ) and the like. These can be used alone or in combination with each other.

[0108] The first gate electrode GE1 , the second gate electrode GE2 , and the third gate electrode GE3 may be formed by the same process, and may include the same material.

[0109] The interlayer insulating layer ILD may be disposed on the gate insulating layer GI. The interlayer insulating layer ILD may fully cover the first gate electrode GE1, the second gate electrode GE2, and the third gate electrode GE3, and may have a substantially flat upper surface without generating steps around the first gate electrode GE1, the second gate electrode GE2, and the third gate electrode GE3. Alternatively, the interlayer insulating layer ILD may cover the first gate electrode GE1, the second gate electrode GE2, and the third gate electrode GE3, and may be disposed with a uniform thickness along the contour of each of the first gate electrode GE1, the second gate electrode GE2, and the third gate electrode GE3. For example, the interlayer insulating layer ILD may include an inorganic material such as silicon oxide, silicon nitride, silicon carbide, silicon oxynitride, silicon oxycarbide, and the like. These can be used alone or in combination with each other.

[0110] The first source electrode SE1, the second source electrode SE2, and the third source electrode SE3 may be disposed on the interlayer insulating layer ILD. The first source electrode SE1 may be connected to the source region of the first active pattern ACT1 through a contact hole formed through the gate insulating layer GI and the interlayer insulating layer ILD. The second source electrode SE2 may be connected to the source region of the second active pattern ACT2 through a contact hole formed through the gate insulating layer GI and the interlayer insulating layer ILD. The third source electrode SE3 may be connected to the source region of the third active pattern ACT3 through a contact hole formed through the gate insulating layer GI and the interlayer insulating layer ILD.

[0111] The first drain electrode DE1, the second drain electrode DE2, and the third drain electrode DE3 may be disposed on the interlayer insulating layer ILD. The first drain electrode DE1 may be connected to the drain region of the first active pattern ACT1 through a contact hole formed through the gate insulating layer GI and the interlayer insulating layer ILD. The second drain electrode DE2 may be connected to the drain region of the second active pattern ACT2 through a contact hole formed through the gate insulating layer GI and the interlayer insulating layer ILD. The third drain electrode DE3 may be connected to the drain region of the third active pattern ACT3 through a contact hole formed through the gate insulating layer GI and the interlayer insulating layer ILD.

[0112] For example, each of the first source electrode SE1, the second source electrode SE2, and the third source electrode SE3 may include a metal, an alloy, a metal nitride, a conductive metal oxide, a transparent conductive material, and the like. These can be used alone or in combination with each other. The first drain electrode DE1, the second drain electrode DE2, and the third drain electrode DE3 may be formed by the same process as the first source electrode SE1, the second source electrode SE2, and the third source electrode SE3, and may include the same material as the first source electrode SE1, the second source electrode SE2, and the third source electrode SE3.

[0113] Therefore, a first transistor TR1 including a first active pattern ACT1, a first gate electrode GE1, a first source electrode SE1 and a first drain electrode DE1 may be set on a substrate SUB, a second transistor TR2 including a second active pattern ACT2, a second gate electrode GE2, a second source electrode SE2 and a second drain electrode DE2 may be set on the substrate SUB, and a third transistor TR3 including a third active pattern ACT3, a third gate electrode GE3, a third source electrode SE3 and a third drain electrode DE3 may be set on the substrate SUB.

[0114] The via insulating layer VIA may be disposed on the interlayer insulating layer ILD. The via insulating layer VIA may sufficiently cover the first, second, and third source electrodes SE1, SE2, and SE3 and the first, second, and third drain electrodes DE1, DE2, and DE3. The via insulating layer VIA may have a substantially flat upper surface.

[0115] The via insulating layer VIA may include an organic material. For example, the via insulating layer VIA may include an organic material such as phenolic resin, polyacrylate resin, polyimide resin, polyamide resin, siloxane resin, epoxy resin, and the like. These can be used alone or in combination with each other.

[0116] The first pixel electrode PE1, the second pixel electrode PE2, and the third pixel electrode PE3 may be disposed on the via insulating layer VIA. The first pixel electrode PE1 may overlap the first pixel region PX1, the second pixel electrode PE2 may overlap the second pixel region PX2, and the third pixel electrode PE3 may overlap the third pixel region PX3.

[0117] The first pixel electrode PE1 can be connected to the first drain electrode DE1 through a first contact hole CNT1 formed through the via insulating layer VIA, the second pixel electrode PE2 can be connected to the second drain electrode DE2 through a second contact hole CNT2 formed through the via insulating layer VIA, and the third pixel electrode PE3 can be connected to the third drain electrode DE3 through a third contact hole CNT3 formed through the via insulating layer VIA.

[0118] Accordingly, the first pixel electrode PE1 may be electrically connected to the first transistor TR1 through the first contact hole CNT1, the second pixel electrode PE2 may be electrically connected to the second transistor TR2 through the second contact hole CNT2, and the third pixel electrode PE3 may be electrically connected to the third transistor TR3 through the third contact hole CNT3.

[0119] For example, each of the first pixel electrode PE1, the second pixel electrode PE2, and the third pixel electrode PE3 may include a metal, an alloy, a metal nitride, a conductive metal oxide, a transparent conductive material, and the like. These can be used alone or in combination with each other. In an embodiment, each of the first pixel electrode PE1, the second pixel electrode PE2, and the third pixel electrode PE3 may have a stacked structure including ITO / Ag / ITO. The first pixel electrode PE1, the second pixel electrode PE2, and the third pixel electrode PE3 may be formed by the same process and may include the same material.

[0120] The pixel defining layer PDL may be disposed on the via insulating layer VIA. The pixel defining layer PDL may cover an edge of each of the first pixel electrode PE1, the second pixel electrode PE2, and the third pixel electrode PE3. In addition, the pixel defining layer PDL may define a first pixel opening OP1, a second pixel opening OP2, and a third pixel opening OP3 that expose at least a portion of an upper surface of a corresponding one of the first pixel electrode PE1, the second pixel electrode PE2, and the third pixel electrode PE3.

[0121] As described above, the pixel defining layer PDL may overlap the first, second, and third contact holes CNT1, CNT2, and CNT3 in a plan view. That is, the pixel defining layer PDL may cover the first, second, and third contact holes CNT1, CNT2, and CNT3 in a plan view.

[0122] The first light emitting layer EML1 may be disposed on the first pixel electrode PE1, the second light emitting layer EML2 may be disposed on the second pixel electrode PE2, and the third light emitting layer EML3 may be disposed on the third pixel electrode PE3. Specifically, the first light emitting layer EML1 may be disposed in the first pixel opening OP1, the second light emitting layer EML2 may be disposed in the second pixel opening OP2, and the third light emitting layer EML3 may be disposed in the third pixel opening OP3.

[0123] Each of the first light emitting layer EML1, the second light emitting layer EML2, and the third light emitting layer EML3 may include an organic material that emits light of a preset color. For example, the first light emitting layer EML1 may include an organic material that generates red light, the second light emitting layer EML2 may include an organic material that generates green light, and the third light emitting layer EML3 may include an organic material that generates blue light.

[0124] In an embodiment, in a plan view, the first light emitting layer EML1 may not overlap with the first contact hole CNT1, the second light emitting layer EML2 may not overlap with the second contact hole CNT2, and the third light emitting layer EML3 may not overlap with the third contact hole CNT3. That is, in a plan view, the first light emitting layer EML1 may be spaced apart from the first contact hole CNT1, the second light emitting layer EML2 may be spaced apart from the second contact hole CNT2, and the third light emitting layer EML3 may be spaced apart from the third contact hole CNT3.

[0125] For example, each of the first, second, and third light emitting layers EML1, EML2, and EML3 may be formed using a fine metal mask (FMM). Alternatively, each of the first, second, and third light emitting layers EML1, EML2, and EML3 may be formed by a photolithography process without using a fine metal mask.

[0126] The common electrode CE may be disposed on the pixel defining layer PDL and the first, second, and third light emitting layers EML1, EML2, and EML3. For example, the common electrode CE may include metal, alloy, metal nitride, conductive metal oxide, transparent conductive material, and the like. These can be used alone or in combination with each other.

[0127] Therefore, the first light-emitting element LED1 including the first pixel electrode PE1, the first light-emitting layer EML1 and the common electrode CE can be set in the first pixel area PX1 on the substrate SUB, the second light-emitting element LED2 including the second pixel electrode PE2, the second light-emitting layer EML2 and the common electrode CE can be set in the second pixel area PX2 on the substrate SUB, and the third light-emitting element LED3 including the third pixel electrode PE3, the third light-emitting layer EML3 and the common electrode CE can be set in the third pixel area PX3 on the substrate SUB.

[0128] The encapsulation layer TFE may be disposed on the common electrode CE. The encapsulation layer TFE can prevent impurities, moisture, external air and the like from penetrating from the outside into the first light-emitting element LED1, the second light-emitting element LED2 and the third light-emitting element LED3. The encapsulation layer TFE may include at least one inorganic layer and at least one organic layer. For example, the inorganic layer may include silicon oxide, silicon nitride, silicon oxynitride and the like. These can be used alone or in combination with each other. The organic layer may include a cured polymer such as polyacrylate.

[0129] Figure 7 and Figure 8 It is shown Figure 2 A plan view of an example of a first contact hole, a second contact hole, and a third contact hole.

[0130] Reference Figure 7 As described above, at least one of the first contact hole CNT1, the second contact hole CNT2, and the third contact hole CNT3 may be positioned at an edge of a pixel electrode adjacent to the at least one contact hole among the first pixel electrode PE1, the second pixel electrode PE2, and the third pixel electrode PE3.

[0131] In an embodiment, at least one of the first pixel electrode PE1, the second pixel electrode PE2, and the third pixel electrode PE3 may include a protrusion positioned in one side, and a contact hole may be positioned in the protrusion. For example, the first pixel electrode PE1 may include a first protrusion PP1, in which a first contact hole CNT1 is positioned, the second pixel electrode PE2 may include a second protrusion PP2, in which a second contact hole CNT2 is positioned in one side of the second protrusion PP2, and the third pixel electrode PE3 may include a third protrusion PP3, in which a third contact hole CNT3 is positioned in one side of the third protrusion PP3.

[0132] Specifically, the first, second, and third contact holes CNT1, CNT2, and CNT3 may partially overlap the first, second, and third protrusions PP1, PP2, and PP3, respectively, in a plan view. Therefore, each of the first, second, and third pixel electrodes PE1, PE2, and PE3 may have an asymmetric shape with respect to the center.

[0133] Reference Figure 8 , in an embodiment, at least one contact hole among the first contact hole CNT1, the second contact hole CNT2, and the third contact hole CNT3 may be positioned at the center of a pixel electrode adjacent to the at least one contact hole among the first pixel electrode PE1, the second pixel electrode PE2, and the third pixel electrode PE3. For example, the first contact hole CNT1 may be positioned at the center of the first pixel electrode PE1, the second contact hole CNT2 may be positioned at the center of the second pixel electrode PE2, and the third contact hole CNT3 may be positioned at the center of the third pixel electrode PE3. In this case, the first contact hole CNT1, the second contact hole CNT2, and the third contact hole CNT3 may overlap with the pixel defining layer PDL in a plan view. That is, the pixel defining layer PDL may cover the first contact hole CNT1, the second contact hole CNT2, and the third contact hole CNT3.

[0134] However, embodiments of the present disclosure are not limited thereto, and the position of the contact hole in the pixel electrode may be changed.

[0135] Fig. 9 yes Figure 1 An enlarged plan view of another example of a portion of a display area. Fig.10 is along Fig. 9 A cross-sectional view taken along line II-II'.

[0136] Reference Fig. 9 and Fig.10 According to an embodiment of the present disclosure, the display device DD may include a substrate SUB, a buffer layer BUF, a first transistor TR1, a second transistor TR2 and a third transistor TR3, a gate insulating layer GI, an interlayer insulating layer ILD, a via insulating layer VIA, a first conductive pattern CP1, a second conductive pattern CP2 and a third conductive pattern CP3, a first light emitting element LED1, a second light emitting element LED2 and a third light emitting element LED3, a pixel defining layer PDL and an encapsulation layer TFE.

[0137] The display area DA of the display device DD may include a first pixel area PX1 , a second pixel area PX2 , and a third pixel area PX3 . Fig. 9 The arrangement of the first pixel region PX1, the second pixel region PX2 and the third pixel region PX3 may be similar to Figure 2The arrangements of the first pixel region PX1 , the second pixel region PX2 , and the third pixel region PX3 are substantially the same.

[0138] The first contact hole CNT1, the second contact hole CNT2, and the third contact hole CNT3 may be formed through the via insulating layer VIA. In an embodiment, the first contact hole CNT1 may be filled with the first conductive pattern CP1, the second contact hole CNT2 may be filled with the second conductive pattern CP2, and the third contact hole CNT3 may be filled with the third conductive pattern CP3. Therefore, the first conductive pattern CP1 may be connected to the first drain electrode DE1, the second conductive pattern CP2 may be connected to the second drain electrode DE2, and the third conductive pattern CP3 may be connected to the third drain electrode DE3.

[0139] The first conductive pattern CP1 , the second conductive pattern CP2 , and the third conductive pattern CP3 may be formed by the same process, and may include the same material.

[0140] In an embodiment, the first conductive pattern CP1, the second conductive pattern CP2, and the third conductive pattern CP3 may be formed by a chemical mechanical polishing (CMP) process. Thus, each of the first conductive pattern CP1, the second conductive pattern CP2, and the third conductive pattern CP3 may have a substantially flat upper surface.

[0141] The first pixel electrode PE1 may be disposed in the first pixel region PX1 on the via insulating layer VIA, the second pixel electrode PE2 may be disposed in the second pixel region PX2 on the via insulating layer VIA, and the third pixel electrode PE3 may be disposed in the third pixel region PX3 on the via insulating layer VIA.

[0142] The first pixel electrode PE1 may contact the first conductive pattern CP1, the second pixel electrode PE2 may contact the second conductive pattern CP2, and the third pixel electrode PE3 may contact the third conductive pattern CP3. Accordingly, the first pixel electrode PE1 may be electrically connected to the first transistor TR1 through the first conductive pattern CP1, the second pixel electrode PE2 may be electrically connected to the second transistor TR2 through the second conductive pattern CP2, and the third pixel electrode PE3 may be electrically connected to the third transistor TR3 through the third conductive pattern CP3.

[0143] Fig. 9 The shapes, sizes and arrangements of the first pixel electrode PE1, the second pixel electrode PE2 and the third pixel electrode PE3 may be different from those of the Figure 2 and Figure 3 The shapes, sizes and arrangements of the first pixel electrode PE1, the second pixel electrode PE2 and the third pixel electrode PE3 are substantially the same.

[0144] In an embodiment, the first conductive pattern CP1, the second conductive pattern CP2, and the third conductive pattern CP3 may include a conductive material different from that of the first pixel electrode PE1, the second pixel electrode PE2, and the third pixel electrode PE3. That is, the first conductive pattern CP1, the second conductive pattern CP2, and the third conductive pattern CP3 may be formed by a process different from that of the first pixel electrode PE1, the second pixel electrode PE2, and the third pixel electrode PE3.

[0145] In an embodiment, the first light emitting layer EML1, the second light emitting layer EML2, and the third light emitting layer EML3 may at least partially overlap with the first contact hole CNT1, the second contact hole CNT2, and the third contact hole CNT3, respectively, in a plan view. That is, the first contact hole CNT1, the second contact hole CNT2, and the third contact hole CNT3 may not be covered by the pixel defining layer PDL. In other words, by filling the first contact hole CNT1, the second contact hole CNT2, and the third contact hole CNT3 with the first conductive pattern CP1, the second conductive pattern CP2, and the third conductive pattern CP3, respectively, the first light emitting layer EML1, the second light emitting layer EML2, and the third light emitting layer EML3 can be arranged to overlap with the first contact hole CNT1, the second contact hole CNT2, and the third contact hole CNT3, respectively.

[0146] However, the embodiments of the present disclosure are not limited thereto, and the first, second, and third contact holes CNT1, CNT2, and CNT3 may be covered by the pixel defining layer PDL.

[0147] In an embodiment, the planar shape of the first pixel opening OP1 may substantially correspond to the planar shape of the first pixel electrode PE1, the planar shape of the second pixel opening OP2 may substantially correspond to the planar shape of the second pixel electrode PE2, and the planar shape of the third pixel opening OP3 may substantially correspond to the planar shape of the third pixel electrode PE3. The sides of the first pixel opening OP1, the second pixel opening OP2, and the third pixel opening OP3 may be parallel to the sides of the first pixel electrode PE1, the second pixel electrode PE2, and the third pixel electrode PE3, respectively. In other words, each of the first pixel opening OP1 and the third pixel opening OP3 may have a substantially octagonal planar shape, and the second pixel opening OP2 may have a substantially quadrilateral planar shape.

[0148] Fig.11 It is shown Fig. 9 A plan view of an example of a first contact hole, a second contact hole, and a third contact hole.

[0149] Refer again Fig. 9, at least one of the first contact hole CNT1, the second contact hole CNT2, and the third contact hole CNT3 may be positioned at an edge of a pixel electrode adjacent to the at least one contact hole among the first pixel electrode PE1, the second pixel electrode PE2, and the third pixel electrode PE3. In this case, for example, the pixel electrode may not include a protrusion positioned in one side. Alternatively, as Figure 7 As shown in , the pixel electrode may include a protrusion positioned in one side, and at least one contact hole may be positioned in the protrusion. In this case, at least one contact hole may partially overlap with the protrusion in a plan view.

[0150] Reference Fig.11 In an embodiment, at least one contact hole among the first contact hole CNT1, the second contact hole CNT2, and the third contact hole CNT3 may be positioned at the center of a pixel electrode adjacent to the at least one contact hole among the first pixel electrode PE1, the second pixel electrode PE2, and the third pixel electrode PE3.

[0151] For example, the first contact hole CNT1 may be positioned at the center of the first pixel electrode PE1, the second contact hole CNT2 may be positioned at the center of the second pixel electrode PE2, and the third contact hole CNT3 may be positioned at the center of the third pixel electrode PE3. In this case, the first contact hole CNT1, the second contact hole CNT2, and the third contact hole CNT3 may overlap with the first pixel opening OP1, the second pixel opening OP2, and the third pixel opening OP3, respectively, in a plan view. That is, the first contact hole CNT1, the second contact hole CNT2, and the third contact hole CNT3 may overlap with the first light-emitting layer, the second light-emitting layer, and the third light-emitting layer (for example, Fig.10 The first light-emitting layer EML1, the second light-emitting layer EML2 and the third light-emitting layer EML3 overlap.

[0152] However, embodiments of the present disclosure are not limited thereto, and the position of the contact hole in the pixel electrode may be changed.

[0153] Fig.12 , Fig.13 , Fig.14 , Fig.15 , Fig.16 , Fig.17 and Fig.18 It is shown Figure 2 and Fig. 9 FIG. 1 is a plan view of an example of a plan shape of each of the first pixel electrode, the second pixel electrode, and the third pixel electrode.

[0154] Reference Fig.12In an embodiment, each of the first pixel electrode PE1 and the third pixel electrode PE3 may have an octagonal planar shape, and the second pixel electrode PE2 may have an octagonal planar shape. That is, the first pixel electrode PE1, the second pixel electrode PE2, and the third pixel electrode PE3 may have different sizes but have the same octagonal planar shape.

[0155] Reference Fig.13 In an embodiment, each of the first pixel electrode PE1 and the third pixel electrode PE3 may have an octagonal planar shape, and the second pixel electrode PE2 may have a circular planar shape.

[0156] Reference Fig.14 In an embodiment, each of the first pixel electrode PE1 and the third pixel electrode PE3 may have an octagonal planar shape, and the second pixel electrode PE2 may have a rectangular planar shape. In this case, the size of the first pixel electrode PE1 and the size of the third pixel electrode PE3 may be substantially the same.

[0157] Reference Fig.15 , each of the first pixel electrode PE1, the second pixel electrode PE2, and the third pixel electrode PE3 may have a polygonal planar shape. In an embodiment, the first pixel electrode PE1 may have a quadrilateral (e.g., square or rhombus) planar shape including a chamfered corner portion, the third pixel electrode PE3 may have a quadrilateral (e.g., square or rhombus) or octagonal planar shape, and the second pixel electrode PE2 may have a quadrilateral (e.g., rectangular) planar shape. Specifically, the chamfered corner portion of the first pixel electrode PE1 may surround at least a portion of the corner portions of the third pixel electrode PE3 facing each other in a plan view.

[0158] A virtual first line VL1' extending to coincide with a first side of the first pixel electrode PE1 extending in the third direction DR3 and a virtual second line VL2' extending to coincide with a second side of the first pixel electrode PE1 may define a virtual quadrilateral VS'. In an embodiment, the virtual quadrilateral VS' may at least partially overlap an adjacent third pixel electrode PE3 in a plan view.

[0159] Reference Fig.16, each of the first pixel electrode PE1, the second pixel electrode PE2, and the third pixel electrode PE3 may have a polygonal planar shape. In an embodiment, the first pixel electrode PE1 may have a quadrilateral (e.g., square or rhombus) planar shape, the third pixel electrode PE3 may have a quadrilateral (e.g., square or rhombus) planar shape including a chamfered corner portion, and the second pixel electrode PE2 may have a quadrilateral (e.g., rectangle) or octagonal planar shape. Specifically, the chamfered corner portion of the third pixel electrode PE3 may surround at least a portion of the corner portions of the first pixel electrode PE1 facing each other in a plan view.

[0160] A virtual first line VL1" extending to coincide with a first side of the third pixel electrode PE3 extending in the third direction DR3 and a virtual second line VL2" extending to coincide with a second side of the third pixel electrode PE3 may define a virtual quadrilateral VS". In an embodiment, the virtual quadrilateral VS" may at least partially overlap with the adjacent first pixel electrode PE1 in a plan view.

[0161] Reference Fig.17 , each of the first pixel electrode PE1, the second pixel electrode PE2, and the third pixel electrode PE3 may have an octagonal planar shape. In an embodiment, each of the plurality of side edges of the first pixel electrode PE1 facing the second pixel electrode PE2 may be recessed toward the center of the first pixel electrode PE1, and each of the plurality of side edges of the third pixel electrode PE3 facing the second pixel electrode PE2 may be recessed toward the center of the third pixel electrode PE3. However, embodiments of the present disclosure are not limited thereto, and the second pixel electrode PE2 may have a circular planar shape.

[0162] Reference Fig.18 , each of the first pixel electrode PE1, the second pixel electrode PE2, and the third pixel electrode PE3 may have an octagonal planar shape. In an embodiment, each of a plurality of side edges of the third pixel electrode PE3 facing the second pixel electrode PE2 may be recessed toward the center of the third pixel electrode PE3. However, embodiments of the present disclosure are not limited thereto, and the second pixel electrode PE2 may have a circular planar shape.

[0163] Refer again Figures 1 to 18In the display device DD according to the embodiment of the present disclosure, each of the first pixel electrode PE1 disposed in the first pixel region PX1 emitting red light and the third pixel electrode PE3 disposed in the third pixel region PX3 emitting blue light may have an octagonal plane shape, and the second pixel electrode PE2 disposed in the second pixel region PX2 emitting green light may have a quadrilateral plane shape. A first virtual quadrilateral VS1 defined by virtual lines (e.g., virtual first lines VL1 and virtual second lines VL2) extending to coincide with the sides of the first pixel electrode PE1 extending in the diagonal direction (e.g., the third direction DR3 and the fourth direction DR4) may at least partially overlap with a second virtual quadrilateral VS2 defined by virtual lines (e.g., virtual third lines VL3 and virtual fourth lines VL4) extending to coincide with the sides of the third pixel electrode PE3 extending in the diagonal direction. Therefore, it is possible to prevent the luminous efficiency of the display device DD from being reduced.

[0164] Alternatively, in the display device DD according to the embodiment of the present disclosure, one of the first pixel electrode PE1 and the third pixel electrode PE3 may have a quadrilateral planar shape including a chamfered corner portion, and the other of the first pixel electrode PE1 and the third pixel electrode PE3 may have a quadrilateral or octagonal planar shape. Therefore, it is possible to prevent the luminous efficiency of the display device DD from being reduced.

[0165] The present disclosure can be applied to various display devices. For example, the present disclosure can be applied to various display devices, such as display devices for vehicles, ships and aircraft, display devices for portable communication devices, display devices for exhibitions or information transmission, medical display devices and the like.

[0166] The foregoing is an illustration of the embodiments and should not be construed as limiting thereof. Although some embodiments have been described, it will be readily appreciated by those skilled in the art that many modifications can be made to the embodiments without substantially departing from the novel teachings and advantages of the inventive concept. Accordingly, all such modifications are intended to be included within the scope of the inventive concept as defined in the claims. Therefore, it should be understood that the foregoing is an illustration of various embodiments and should not be construed as being limited to the specific embodiments disclosed, and it should be understood that modifications to the disclosed embodiments as well as other embodiments are intended to be included within the scope of the appended claims.

Claims

1. A display device, comprising: a substrate including a first pixel region, a second pixel region, and a third pixel region that emit light of different colors; a first light emitting element, the first light emitting element being disposed in the first pixel region on the substrate and comprising a first pixel electrode having an octagonal planar shape; a second light emitting element, the second light emitting element being disposed in the second pixel region on the substrate and comprising a second pixel electrode; a third light emitting element, the third light emitting element being disposed in the third pixel region on the substrate and comprising a third pixel electrode having an octagonal planar shape; as well as a pixel defining layer, the pixel defining layer covering edges of the first pixel electrode, the second pixel electrode, and the third pixel electrode, and defining a first pixel opening, a second pixel opening, and a third pixel opening respectively exposing at least a portion of the first pixel electrode, the second pixel electrode, and the third pixel electrode, wherein a virtual first line extending to coincide with each of a plurality of first sides of the first pixel electrode extending in a first direction and a virtual second line extending to coincide with each of a plurality of second sides of the first pixel electrode extending in a second direction perpendicular to the first direction define a first virtual quadrilateral, wherein a virtual third line extending to coincide with each of a plurality of first sides of the third pixel electrode adjacent to the first pixel electrode extending in the first direction and a virtual fourth line extending to coincide with each of a plurality of second sides of the third pixel electrode extending in the second direction define a second virtual quadrilateral, and The first virtual quadrilateral at least partially overlaps with the second virtual quadrilateral in a plan view.

2. The display device according to claim 1, wherein: The second pixel electrode has a rectangular, circular or octagonal plane shape.

3. The display device according to claim 1, wherein: The first pixel region emits red light, the second pixel region emits green light, and the third pixel region emits blue light.

4. The display device according to claim 1, wherein: A length of a side of the first pixel electrode extending parallel to the first side of the second pixel electrode is shorter than a length of a side of the third pixel electrode extending parallel to the second side of the second pixel electrode.

5. The display device according to claim 1, wherein: The length of the third side of the first pixel electrode connecting the first side and the second side of the first pixel electrode is the same as the length of the third side of the third pixel electrode connecting the first side and the second side of the third pixel electrode and extending parallel to the third side of the first pixel electrode.

6. The display device according to claim 1, wherein: The length of the first side of the second pixel electrode extending parallel to the second side of the first pixel electrode is the same as the length of the second side of the first pixel electrode, and The length of the second side of the second pixel electrode extending parallel to the first side of the third pixel electrode is the same as the length of the first side of the third pixel electrode.

7. The display device according to claim 1, wherein: The planar shape of the first pixel opening corresponds to the planar shape of the first pixel electrode, the planar shape of the second pixel opening corresponds to the planar shape of the second pixel electrode, and the planar shape of the third pixel opening corresponds to the planar shape of the third pixel electrode.

8. The display device according to claim 1, wherein: The first light emitting element further includes a first light emitting layer disposed in the first pixel opening. The second light emitting element further includes a second light emitting layer disposed in the second pixel opening, and Wherein, the third light-emitting element further includes a third light-emitting layer arranged in the third pixel opening.

9. The display device according to claim 8, further comprising: a first transistor, the first transistor being connected to the first pixel electrode through a first contact hole; a second transistor, the second transistor being connected to the second pixel electrode through a second contact hole; as well as A third transistor is connected to the third pixel electrode through a third contact hole.

10. The display device according to claim 9, wherein: Each of the first contact hole, the second contact hole, and the third contact hole has a rectangular planar shape.

11. The display device according to claim 9, wherein: The first contact hole does not overlap with the first light emitting layer in the plan view, the second contact hole does not overlap with the second light emitting layer in the plan view, and the third contact hole does not overlap with the third light emitting layer in the plan view.

12. The display device according to claim 9, wherein: At least one of the first contact hole, the second contact hole, and the third contact hole is positioned at an edge of a pixel electrode disposed adjacent to the at least one contact hole among the first pixel electrode, the second pixel electrode, and the third pixel electrode.

13. The display device according to claim 9, wherein: At least one pixel electrode among the first pixel electrode, the second pixel electrode, and the third pixel electrode includes a protrusion positioned in one side, and Wherein, in the plan view, at least one contact hole among the first contact hole, the second contact hole and the third contact hole, which is arranged to be adjacent to the at least one pixel electrode, partially overlaps with the protrusion.

14. The display device according to claim 9, wherein: At least one contact hole among the first contact hole, the second contact hole, and the third contact hole is positioned at a center of a pixel electrode adjacent to the at least one contact hole among the first pixel electrode, the second pixel electrode, and the third pixel electrode.

15. The display device according to claim 14, wherein: The at least one contact hole overlaps the pixel defining layer in the plan view.

16. The display device according to claim 9, further comprising: A conductive pattern filling each of the first contact hole, the second contact hole and the third contact hole, contacting each of the first pixel electrode, the second pixel electrode and the third pixel electrode, and including a conductive material different from a conductive material of the first pixel electrode, the second pixel electrode and the third pixel electrode.

17. The display device according to claim 16, wherein: The first contact hole, the second contact hole, and the third contact hole at least partially overlap with the first light emitting layer, the second light emitting layer, and the third light emitting layer, respectively, in the plan view.

18. The display device according to claim 1, wherein: The size of the first pixel electrode is the same as the size of the third pixel electrode.

19. The display device according to claim 1, wherein: Each of the plurality of sides of the first pixel electrode facing the second pixel electrode is recessed toward the center of the first pixel electrode, and each of the plurality of sides of the third pixel electrode facing the second pixel electrode is recessed toward the center of the third pixel electrode, and Wherein, the second pixel electrode has an octagonal or circular planar shape.

20. The display device according to claim 1, wherein: Each of the plurality of side edges of the third pixel electrode facing the second pixel electrode is recessed toward the center of the third pixel electrode, and Wherein, the second pixel electrode has an octagonal or circular planar shape.

21. The display device according to claim 1, wherein: Virtual lines extending in a third direction between the first direction and the second direction and in a fourth direction perpendicular to the third direction define a virtual square, and The center of the first pixel electrode is positioned at the first vertices of the virtual square facing each other, the center of the third pixel electrode is positioned at the second vertices of the virtual square facing each other, and the second pixel electrode is positioned at the center of the virtual square.

22. A display device, comprising: a substrate including a first pixel region, a second pixel region, and a third pixel region that emit light of different colors; a first light emitting element, the first light emitting element being disposed in the first pixel region on the substrate and comprising a first pixel electrode having a polygonal planar shape; a second light emitting element, the second light emitting element being disposed in the second pixel region on the substrate and comprising a second pixel electrode; a third light emitting element, the third light emitting element being disposed in the third pixel region on the substrate and comprising a third pixel electrode having a polygonal planar shape; as well as a pixel defining layer covering an edge of each of the first pixel electrode, the second pixel electrode, and the third pixel electrode and defining a first pixel opening, a second pixel opening, and a third pixel opening respectively exposing at least a portion of the first pixel electrode, the second pixel electrode, and the third pixel electrode, Among them, one of the first pixel electrode and the third pixel electrode has a quadrilateral planar shape including a chamfered corner portion.

23. The display device according to claim 22, wherein: The other of the first pixel electrode and the third pixel electrode has a quadrilateral or octagonal planar shape.

24. The display device according to claim 23, wherein: A virtual first line extending to coincide with each of a plurality of first sides of the one of the first pixel electrode and the third pixel electrode extending in a first direction and a virtual second line extending to coincide with each of a plurality of second sides of the one of the first pixel electrode and the third pixel electrode extending in a second direction perpendicular to the first direction define a virtual quadrilateral, and The virtual quadrilateral at least partially overlaps with the other of the first pixel electrode and the third pixel electrode in a plan view.

25. The display device according to claim 23, wherein: When the first pixel electrode includes the chamfered corner portion and the third pixel electrode has a quadrangular planar shape, the chamfered corner portion of the first pixel electrode surrounds at least a portion of corner portions of the third pixel electrode facing each other in a plan view.

26. The display device according to claim 22, wherein: The second pixel electrode has a quadrilateral planar shape.

27. The display device according to claim 22, further comprising: a first transistor, the first transistor being connected to the first pixel electrode through a first contact hole; a second transistor, the second transistor being connected to the second pixel electrode through a second contact hole; as well as A third transistor is connected to the third pixel electrode through a third contact hole.

28. The display device according to claim 27, in, At least one contact hole among the first contact hole, the second contact hole, and the third contact hole is positioned at an edge of a pixel electrode adjacent to the at least one contact hole among the first pixel electrode, the second pixel electrode, and the third pixel electrode.

29. The display device according to claim 27, wherein: At least one pixel electrode among the first pixel electrode, the second pixel electrode, and the third pixel electrode includes a protrusion positioned in one side, and In a plan view, at least one contact hole among the first contact hole, the second contact hole and the third contact hole, which is adjacent to the at least one pixel electrode, partially overlaps with the protrusion.

30. The display device according to claim 27, wherein: At least one contact hole among the first contact hole, the second contact hole, and the third contact hole is positioned at a center of a pixel electrode adjacent to the at least one contact hole among the first pixel electrode, the second pixel electrode, and the third pixel electrode.

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