Display device

Abstract

The present disclosure relates to a display device, and more particularly, to a display device capable of improving a color gamut and minimizing a thickness of a filling layer. The display device includes: a substrate; a transistor disposed on the substrate; a pixel electrode connected to the transistor; a light emitting layer disposed on the pixel electrode; a common electrode disposed on the light emitting layer; a color filter disposed on the common electrode; a lens disposed on the color filter; and a filling layer disposed on the lens, in which the first color filter and the lens are in direct contact with each other.

Description

[0001] This application claims priority to and all rights arising from Korean Patent Application No. 10-2023-0100462 filed in the Korean Intellectual Property Office on August 1, 2023, the entire contents of which are incorporated herein by reference. Technical Field

[0002] The present disclosure relates to a display device, and more particularly, to a display device capable of improving a color gamut and minimizing a thickness of a filling layer, and an optical device including the display device. Background Art

[0003] A head mounted display (HMD) is an image display device that is worn on the user's head in the form of glasses or a helmet and focuses on a distance close to the user's eyes. The head mounted display can realize virtual reality (VR) or augmented reality (AR).

[0004] A head-mounted display uses multiple lenses to magnify and display an image displayed on a small display device. Therefore, the display device applied to the head-mounted display needs to provide a high-resolution image, for example, an image with a resolution of 3000 pixels per inch (PPI) or more. To this end, an organic light-emitting diode on silicon (OLEDoS) that can achieve a high resolution and small size of an organic light-emitting display device is used as a display device applied to a head-mounted display. OLEDoS is a device that displays an image by disposing an organic light-emitting diode (OLED) on a semiconductor wafer substrate on which a complementary metal oxide semiconductor (CMOS) is disposed. Summary of the invention

[0005] Aspects of the present disclosure provide a display device and an optical device capable of improving a color gamut and minimizing a thickness of a filling layer.

[0006] According to a disclosed embodiment, a display device includes: a substrate; a transistor disposed on the substrate; a pixel electrode connected to the transistor; a light-emitting layer disposed on the pixel electrode; a common electrode disposed on the light-emitting layer; a first color filter disposed on the common electrode; a lens disposed on the first color filter; and a filling layer disposed on the lens, wherein the first color filter and the lens are in direct contact with each other.

[0007] In an embodiment, the difference between the refractive index of the lens and the refractive index of the filling layer is 0.1 to 0.2.

[0008] In an embodiment, the refractive index of the lens is greater than the refractive index of the filling layer.

[0009] In an embodiment, the lens has a refractive index of 1.61.

[0010] In an embodiment, the lens has a cone angle of 60 to 70 degrees.

[0011] In an embodiment, the lens has a thickness less than 1.5 μm.

[0012] In an embodiment, the distance between adjacent lenses is greater than or equal to 0.3 μm.

[0013] In an embodiment, the filling layer has a refractive index of 1.41 to 1.51.

[0014] In an embodiment, the filling layer comprises epoxy resin.

[0015] In an embodiment, the filling layer has a thickness of 3 μm.

[0016] In an embodiment, the display device further includes a second buffer layer, and the second buffer layer is disposed between the lens and the filling layer.

[0017] In an embodiment, the second buffer layer has a refractive index of 1.4 to 1.7.

[0018] In an embodiment, the second buffer layer has a Thickness.

[0019] In an embodiment, the second buffer layer has a surface energy greater than or equal to 60 mN / m.

[0020] In an embodiment, the second buffer layer includes SiO x N y .

[0021] In an embodiment, the display device further includes an encapsulation layer disposed between the common electrode and the first color filter.

[0022] In an embodiment, the encapsulation layer includes at least one inorganic film and at least one organic film disposed at different layers.

[0023] In an embodiment, the encapsulation layer further includes a first buffer layer disposed between the at least one inorganic film and the at least one organic film of the encapsulation layer.

[0024] In an embodiment, the first buffer layer has a refractive index of 1.4 to 1.7.

[0025] In an embodiment, the display device further includes a second color filter disposed adjacent to the first color filter and overlapping the first color filter in a plan view.

[0026] In an embodiment, a thickness of an overlapping portion of the first color filter and the second color filter is equal to a thickness of the lens.

[0027] In an embodiment, a width of an overlapping portion of the first color filter and the second color filter is less than or equal to 0.2 μm.

[0028] According to a disclosed embodiment, a display device includes: a substrate; a transistor disposed on the substrate; a pixel electrode connected to the transistor; a light-emitting layer disposed on the pixel electrode; a common electrode disposed on the light-emitting layer; a color filter disposed on the common electrode; a lens disposed on the color filter; and a filling layer disposed on the lens, wherein the filling layer has a refractive index of 1.41 to 1.51.

[0029] In an embodiment, the difference between the refractive index of the lens and the refractive index of the filling layer is 0.1 to 0.2.

[0030] In an embodiment, the refractive index of the lens is greater than the refractive index of the filling layer.

[0031] In an embodiment, the lens has a refractive index of 1.61.

[0032] In an embodiment, the lens has a cone angle of 60 to 70 degrees.

[0033] In an embodiment, the color filter and the lens are in direct contact with each other.

[0034] According to the disclosed embodiment, the optical device includes: a display device; and a light path conversion component, on the display device, wherein the display device includes: a substrate; a transistor, arranged on the substrate; a pixel electrode, connected to the transistor; a light-emitting layer, arranged on the pixel electrode; a common electrode, arranged on the light-emitting layer; a color filter, arranged on the common electrode; a lens, arranged on the color filter; and a filling layer, arranged on the lens, the color filter and the lens are in direct contact with each other.

[0035] According to the display device of the present disclosure, the color gamut can be improved and the thickness of the filling layer can be minimized.

[0036] The effects of the present disclosure are not limited to the above-described effects, and other effects not described herein will become apparent to those skilled in the art from the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] The above and other aspects and features of the present disclosure will become more apparent by describing in detail exemplary embodiments of the present disclosure with reference to the accompanying drawings, in which:

[0038] Figure 1 is an exploded perspective view showing a display device according to an exemplary embodiment;

[0039] Figure 2 It is shown Figure 1 An example layout diagram of a display panel shown in FIG.

[0040] Figure 3 is a block diagram illustrating a display device according to an exemplary embodiment;

[0041] Figure 4is an equivalent circuit diagram of a first pixel according to an exemplary embodiment;

[0042] Figure 5 is a layout diagram showing pixels of a display area according to an exemplary embodiment;

[0043] Figure 6 It is shown along Figure 5 A cross-sectional view of an example of a display device taken along line AA';

[0044] Figure 7 is a perspective view showing a head mounted display device according to an exemplary embodiment;

[0045] Figure 8 It is shown Figure 7 An exploded perspective view of an example of a display unit of a head mounted display device;

[0046] Fig. 9 is a perspective view showing a head mounted display device according to an exemplary embodiment;

[0047] Fig.10 is a plan view of a display device according to an exemplary embodiment;

[0048] Fig.11 It is along Fig.10 A cross-sectional view of a display device according to an exemplary embodiment taken along line II';

[0049] Fig.12 It is along Fig.10 A cross-sectional view of a display device according to an exemplary embodiment taken along line II';

[0050] Fig.13 It is along Fig.10 A cross-sectional view of a display device according to an exemplary embodiment taken along line II';

[0051] Fig.14 is a diagram for describing front light efficiency of a display device according to a refractive index of a filling layer and a cone angle of a lens;

[0052] Fig.15 is a diagram for describing the side light efficiency (or side brightness ratio) of a display device according to the refractive index of a filling layer and the cone angle of a lens;

[0053] Fig.16 is a view for describing a front chromatic aberration of a display device according to a refractive index of a filling layer and a cone angle of a lens; and

[0054] Fig.17 It is a view for describing the lateral chromatic aberration of a display device according to the refractive index of a filling layer and the cone angle of a lens. DETAILED DESCRIPTION

[0055] The present invention will now be described more fully hereinafter with reference to the accompanying drawings, in which preferred embodiments of the invention are shown. However, the present invention may be implemented in different forms and should not be construed as limited to the embodiments set forth herein. On the contrary, these embodiments are provided so that this disclosure will be thorough and complete and will fully convey the scope of the invention to those skilled in the art.

[0056] It will also be understood that when a layer is referred to as being "on" another layer or substrate, it can be directly on the other layer or substrate, or intervening layers may also be present. Throughout the specification, like reference numerals denote like components. In the drawings, the thickness of layers and regions are exaggerated for clarity.

[0057] Although the terms "first", "second", etc. can be used to describe various elements here, these elements should not be limited by these terms. These terms can be used to distinguish an element from another element. Therefore, without departing from the teaching of one or more embodiments, the first element discussed below can be referred to as the second element. Describing an element as a "first" element may not require or imply the presence of a second element or other elements. The terms "first", "second", etc. can also be used to distinguish between different categories or groups of elements here. For simplicity, the terms "first", "second", etc. can represent "first category (or first group)", "second category (or second group)", etc. respectively.

[0058] The features of the various embodiments of the present disclosure may be combined in part or in whole. As will be clearly understood by those skilled in the art, various interactions and operations are technically feasible. The various embodiments may be practiced individually or in combination.

[0059] Hereinafter, specific exemplary embodiments will be described with reference to the accompanying drawings.

[0060] Figure 1 is an exploded perspective view illustrating a display device according to an exemplary embodiment. Figure 2 It is shown Figure 1 Layout diagram of an example of a display panel shown in . Figure 3 is a block diagram illustrating a display device according to an exemplary embodiment.

[0061] Reference Figure 1 and Figure 2, the display device 10 according to the exemplary embodiment is a device for displaying a moving image or a still image. The display device 10 according to the exemplary embodiment can be applied to a portable electronic device (such as a mobile phone, a smart phone, a tablet personal computer (PC), a mobile communication terminal, an electronic notebook, an electronic book, a portable multimedia player (PMP), a navigation and an ultra-mobile PC (UMPC)). For example, the display device 10 can be applied to a display unit of a television, a laptop computer, a monitor, a billboard, or an Internet of Things (IOT) device. Alternatively, the display device 10 can be applied to a smart watch, a watch phone, and a head-mounted display (HMD) for realizing virtual reality and augmented reality.

[0062] The display device 10 according to an exemplary embodiment includes a display panel 100 , a heat dissipation layer 200 , a circuit board 300 , a timing control circuit 400 , and a power supply circuit 500 .

[0063] The display panel 100 may be formed in a planar shape similar to a quadrilateral. For example, the display panel 100 may have a planar shape similar to a quadrilateral having short sides in a first direction DR1 and long sides in a second direction DR2 intersecting the first direction DR1. In the display panel 100, a corner where a short side extending in the first direction DR1 and a long side extending in the second direction DR2 meet may be rounded (rounded) to have a predetermined curvature, or may be formed at a right angle. The planar shape of the display panel 100 is not limited to a quadrilateral, and may be formed to have other polygonal, circular, or elliptical shapes. The planar shape of the display device 10 may follow the planar shape of the display panel 100, but exemplary embodiments of the present specification are not limited thereto.

[0064] like Figure 2 As shown in , the display panel 100 includes a display area DAA where an image is displayed and a non-display area NDA where no image is displayed.

[0065] The display area DAA includes a plurality of pixels PX, a plurality of scan lines SL, a plurality of emission control lines EL, and a plurality of data lines DL.

[0066] Each of the plurality of pixels PX includes a light emitting element that emits light. The plurality of pixels PX may be arranged in a matrix form in a first direction DR1 and a second direction DR2. A plurality of scan lines SL and a plurality of emission control lines EL may extend in the first direction DR1 and may be arranged in the second direction DR2. A plurality of data lines DL may extend in the second direction DR2 and may be arranged in the first direction DR1.

[0067] The plurality of scan lines SL include a plurality of write scan lines GWL, a plurality of control scan lines GCL, and a plurality of bias scan lines EBL. The plurality of emission control lines EL include a plurality of first emission control lines EL1 and a plurality of second emission control lines EL2.

[0068] Multiple unit pixels UPX (see Figure 5 ) includes a plurality of pixels PX1, PX2 and PX3 (see Figure 6 Each of the plurality of pixels PX1, PX2, and PX3 may include Figure 4 The plurality of pixel transistors shown in the figure may be formed by a semiconductor process and may be disposed on a semiconductor substrate ( Figure 6 For example, a plurality of pixel transistors may be formed by a complementary metal oxide semiconductor (CMOS).

[0069] Each of the plurality of pixels PX1, PX2, and PX3 may be connected to any one of the plurality of write scan lines GWL, any one of the plurality of control scan lines GCL, any one of the plurality of bias scan lines EBL, any one of the plurality of first emission control lines EL1, any one of the plurality of second emission control lines EL2, and any one of the plurality of data lines DL. Each of the plurality of pixels PX1, PX2, and PX3 may receive a data voltage supplied from the data line DL in response to a write scan signal of the write scan line GWL, and may emit light from the light emitting element according to the data voltage.

[0070] The non-display area NDA includes a scan driving area SDA, a data driving area DDA and a pad (also called “pad” or “bonding pad”) area PDA.

[0071] The scan driving area SDA may be an area in which the scan driver 610 and the emission driver 620 are disposed. Figure 2 , the scan driver 610 is disposed on the left side of the display area DAA, and the emission driver 620 is disposed on the right side of the display area DAA, but the exemplary embodiments of the present specification are not limited thereto. For example, the scan driver 610 and the emission driver 620 may be disposed on both the left and right sides of the display area DAA.

[0072] The scan driver 610 includes a plurality of scan transistors, and the emission driver 620 includes a plurality of light emitting transistors. The plurality of scan transistors and the plurality of light emitting transistors may be formed by a semiconductor process and may be formed on a semiconductor substrate ( Figure 6For example, a plurality of scanning transistors and a plurality of light emitting transistors may be formed by CMOS.

[0073] The scan driver 610 may include a write scan signal output unit 611, a control scan signal output unit 612, and a bias scan signal output unit 613. Each of the write scan signal output unit 611, the control scan signal output unit 612, and the bias scan signal output unit 613 may receive a scan timing control signal SCS from the timing control circuit 400. The write scan signal output unit 611 may generate a write scan signal according to the scan timing control signal SCS of the timing control circuit 400, and sequentially output the write scan signal to the write scan line GWL. The control scan signal output unit 612 may generate a control scan signal according to the scan timing control signal SCS, and sequentially output the control scan signal to the control scan line GCL. The bias scan signal output unit 613 may generate a bias scan signal according to the scan timing control signal SCS, and sequentially output the bias scan signal to the bias scan line EBL.

[0074] The emission driver 620 includes a first emission control driver 621 and a second emission control driver 622. Each of the first emission control driver 621 and the second emission control driver 622 may receive an emission timing control signal ECS from the timing control circuit 400. The first emission control driver 621 may generate a first emission control signal according to the emission timing control signal ECS, and sequentially output the first emission control signal to the first emission control line EL1. The second emission control driver 622 may generate a second emission control signal according to the emission timing control signal ECS, and sequentially output the second emission control signal to the second emission control line EL2.

[0075] The data driving area DDA may be an area in which the data driver 700 is disposed. The data driver 700 may include a plurality of data transistors, and the plurality of data transistors may be formed by a semiconductor process and may be formed on a semiconductor substrate ( Figure 6 For example, a plurality of data transistors may be formed of CMOS.

[0076] The data driver 700 may receive the digital video data DATA and the data timing control signal DCS from the timing control circuit 400. The data driver 700 converts the digital video data DATA into an analog data voltage according to the data timing control signal DCS, and outputs the converted analog data voltage to the data line DL. In this case, the pixels PX1, PX2, and PX3 may be selected by the write scan signal of the scan driver 610, and the data voltage may be supplied to the selected pixels PX1, PX2, and PX3.

[0077] The pad area PDA includes a plurality of pads PD arranged in the first direction DR1. Each of the plurality of pads PD may be removed by removing an insulating layer (eg, a cover layer ( Figure 6 The CVL) and polarizing plate (not shown) in the embodiment are exposed.

[0078] The heat dissipation layer 200 may overlap the display panel 100 in the third direction DR3 which is the thickness direction of the display panel 100. The heat dissipation layer 200 may be provided on one surface (e.g., the rear surface) of the display panel 100. The heat dissipation layer 200 serves to dissipate heat generated from the display panel 100. The heat dissipation layer 200 may include a metal layer having high thermal conductivity such as graphite, silver (Ag), copper (Cu), or aluminum (Al).

[0079] The circuit board 300 may be electrically connected to the plurality of pads PD in the pad area PDA of the display panel 100 by using a conductive adhesive member such as an anisotropic conductive film. The circuit board 300 may be a flexible printed circuit board having a flexible material or a flexible film. Figure 1 , the circuit board 300 is shown unfolded, but the circuit board 300 may be bent. In this case, one end of the circuit board 300 may be disposed on the rear surface of the display panel 100. The one end of the circuit board 300 may be an opposite end of the circuit board 300 connected to the other end of the plurality of pads PD in the pad area PDA.

[0080] The timing control circuit 400 may receive digital video data DATA and a timing signal from the outside. The timing control circuit 400 may generate a scan timing control signal SCS, an emission timing control signal ECS, and a data timing control signal DCS for controlling the display panel 100 according to the timing signal. The timing control circuit 400 may output the scan timing control signal SCS to the scan driver 610 and the emission timing control signal ECS to the emission driver 620. The timing control circuit 400 may output the digital video data DATA and the data timing control signal DCS to the data driver 700.

[0081] The power supply circuit 500 can generate a plurality of panel driving voltages by converting an external power voltage. For example, the power supply circuit 500 can generate a first driving voltage VSS, a second driving voltage VDD, and a third driving voltage VINT, and supply the first driving voltage VSS, the second driving voltage VDD, and the third driving voltage VINT to the display panel 100. Figure 4 Description of the first driving voltage VSS, the second driving voltage VDD, and the third driving voltage VINT.

[0082] Each of the timing control circuit 400 and the power supply circuit 500 may be formed as an integrated circuit (IC) and attached to one surface of the circuit board 300. The scan timing control signal SCS, the emission timing control signal ECS, the digital video data DATA, and the data timing control signal DCS of the timing control circuit 400 may be supplied to the display panel 100 through the circuit board 300. The first driving voltage VSS, the second driving voltage VDD, and the third driving voltage VINT of the power supply circuit 500 may be supplied to the display panel 100 through the circuit board 300.

[0083] Figure 4 is an equivalent circuit diagram of a first pixel according to an exemplary embodiment.

[0084] Reference Figure 4 , the first pixel PX1 may be connected to the write scan line GWL, the control scan line GCL, the bias scan line EBL, the first emission control line EL1, the second emission control line EL2, and the data line DL. In addition, the first pixel PX1 may be connected to a first drive voltage line VSL to which a first drive voltage VSS corresponding to a low potential voltage is applied, a second drive voltage line VDL to which a second drive voltage VDD corresponding to a high potential voltage is applied, and a third drive voltage line VIL to which a third drive voltage VINT corresponding to an initialization voltage is applied. That is, the first drive voltage line VSL may be a low potential voltage line, the second drive voltage line VDL may be a high potential voltage line, and the third drive voltage line VIL may be an initialization voltage line. In this case, the first drive voltage VSS may be a voltage lower than the third drive voltage VINT. The second drive voltage VDD may be a voltage higher than the third drive voltage VINT.

[0085] The first pixel PX1 includes a plurality of transistors T1 to T6 , a light emitting element ED, a first capacitor C1 , and a second capacitor C2 .

[0086] The light emitting element ED emits light according to the driving current flowing through the channel of the first transistor T1. The amount of light emitted from the light emitting element ED may be proportional to the driving current. The light emitting element ED may be disposed between the fourth transistor T4 and the first driving voltage line VSL. The first electrode of the light emitting element ED may be connected to the drain electrode of the fourth transistor T4, and the second electrode thereof may be connected to the first driving voltage line VSL. The first electrode of the light emitting element ED may be an anode electrode, and the second electrode of the light emitting element ED may be a cathode electrode. The light emitting element ED may be an organic light emitting diode including a first electrode, a second electrode, and an organic light emitting layer disposed between the first electrode and the second electrode, but the exemplary embodiments of the present specification are not limited thereto. For example, the light emitting element ED may be an inorganic light emitting device including a first electrode, a second electrode, and an inorganic semiconductor disposed between the first electrode and the second electrode. In this case, the light emitting element ED may be a micro light emitting diode.

[0087] The first transistor T1 may be a driving transistor that controls a source-drain current (also referred to as a "driving current") flowing between a source electrode and a drain electrode according to a voltage applied to a gate electrode. The first transistor T1 includes a gate electrode connected to a first node N1, a source electrode connected to a drain electrode of the sixth transistor T6, and a drain electrode connected to a second node N2.

[0088] The second transistor T2 may be connected between one electrode of the first capacitor C1 and the data line DL. The second transistor T2 is turned on in response to a write scan signal of the write scan line GWL, and connects one electrode of the first capacitor C1 to the data line DL. Therefore, the data voltage of the data line DL may be applied to one electrode of the first capacitor C1. The second transistor T2 includes a gate electrode connected to the write scan line GWL, a source electrode connected to the data line DL, and a drain electrode connected to one electrode of the first capacitor C1.

[0089] The third transistor T3 may be connected between the first node N1 and the second node N2. The third transistor T3 is turned on in response to a control scan signal of the control scan line GCL, and connects the first node N1 to the second node N2. Therefore, since the gate electrode and the drain electrode of the first transistor T1 are connected, the first transistor T1 may operate like a diode. The third transistor T3 includes a gate electrode connected to the control scan line GCL, a source electrode connected to the second node N2, and a drain electrode connected to the first node N1.

[0090] The fourth transistor T4 may be connected between the second node N2 and the third node N3. The fourth transistor T4 is turned on by the first emission control signal of the first emission control line EL1, and connects the second node N2 to the third node N3. Therefore, the driving current of the first transistor T1 may be supplied to the light emitting element ED. The fourth transistor T4 includes a gate electrode connected to the first emission control line EL1, a source electrode connected to the second node N2, and a drain electrode connected to the third node N3.

[0091] The fifth transistor T5 may be connected between the third node N3 and the third driving voltage line VIL. The fifth transistor T5 is turned on by the bias scan signal of the bias scan line EBL, and connects the third node N3 to the third driving voltage line VIL. Therefore, the third driving voltage VINT of the third driving voltage line VIL may be applied to the first electrode of the light emitting element ED. The fifth transistor T5 includes a gate electrode connected to the bias scan line EBL, a source electrode connected to the third node N3, and a drain electrode connected to the third driving voltage line VIL.

[0092] The sixth transistor T6 may be connected between the source electrode of the first transistor T1 and the second drive voltage line VDL. The sixth transistor T6 is turned on by the second emission control signal of the second emission control line EL2, and connects the source electrode of the first transistor T1 to the second drive voltage line VDL. Therefore, the second drive voltage VDD of the second drive voltage line VDL may be applied to the source electrode of the first transistor T1. The sixth transistor T6 includes a gate electrode connected to the second emission control line EL2, a source electrode connected to the second drive voltage line VDL, and a drain electrode connected to the source electrode of the first transistor T1.

[0093] The first capacitor C1 is formed between the first node N1 and the drain electrode of the second transistor T2. The first capacitor C1 includes one electrode connected to the drain electrode of the second transistor T2 and the other electrode connected to the first node N1.

[0094] The second capacitor C2 is connected between the gate electrode of the first transistor T1 and the second driving voltage line VDL. The second capacitor C2 includes one electrode connected to the gate electrode of the first transistor T1 and the other electrode connected to the second driving voltage line VDL.

[0095] The first node N1 is a contact point of the gate electrode of the first transistor T1, the drain electrode of the third transistor T3, the other electrode of the first capacitor C1, and one electrode of the second capacitor C2. The second node N2 is a contact point of the drain electrode of the first transistor T1, the source electrode of the third transistor T3, and the source electrode of the fourth transistor T4. The third node N3 is a contact point of the drain electrode of the fourth transistor T4, the source electrode of the fifth transistor T5, and the first electrode of the light emitting element ED.

[0096] Each of the first transistor T1 to the sixth transistor T6 may be a metal oxide semiconductor field effect transistor (MOSFET). For example, each of the first transistor T1 to the sixth transistor T6 may be a P-type MOSFET, but the exemplary embodiments of the present specification are not limited thereto. Each of the first transistor T1 to the sixth transistor T6 may be an N-type MOSFET. Alternatively, some of the first transistor T1 to the sixth transistor T6 may be a P-type MOSFET, and the other transistors of the first transistor T1 to the sixth transistor T6 may be an N-type MOSFET.

[0097] exist Figure 4 FIG. 4 shows that the first pixel PX1 includes six transistors T1 to T6 and two capacitors C1 and C2, but it should be noted that the equivalent circuit diagram of the first pixel PX1 is not limited to Figure 4 For example, the number of transistors and capacitors of the first pixel PX1 is not limited to Figure 4 The quantity shown in .

[0098] In addition, the equivalent circuit diagram of the second pixel PX2 and the equivalent circuit diagram of the third pixel PX3 can be compared with the reference Figure 4 The equivalent circuit diagram of the first pixel PX1 described above is substantially the same. Therefore, description of the equivalent circuit diagram of the second pixel PX2 and the equivalent circuit diagram of the third pixel PX3 are omitted in this specification.

[0099] Figure 5 is a layout diagram showing pixels of a display area according to an exemplary embodiment.

[0100] Reference Figure 5 Each of the plurality of unit pixels UPX includes a first emission area EA1 as a emission area of ​​a first pixel PX1, a second emission area EA2 as a emission area of ​​a second pixel PX2, and a third emission area EA3 as a emission area of ​​a third pixel PX3.

[0101] Each of the first light emitting area EA1, the second light emitting area EA2, and the third light emitting area EA3 may have a quadrilateral plane shape (such as a rectangle, a square, or a rhombus). For example, the first light emitting area EA1 may have a rectangular plane shape having a short side in the first direction DR1 and a long side in the second direction DR2. In addition, each of the second light emitting area EA2 and the third light emitting area EA3 may have a rectangular plane shape having a long side in the first direction DR1 and a short side in the second direction DR2.

[0102] The length of the first light emitting area EA1 in the first direction DR1 may be smaller than the length of the second light emitting area EA2 in the first direction DR1 and may be smaller than the length of the third light emitting area EA3 in the first direction DR1. The length of the second light emitting area EA2 in the first direction DR1 and the length of the third light emitting area EA3 in the first direction DR1 may be substantially the same.

[0103] The length of the first light emitting area EA1 in the second direction DR2 may be greater than the sum of the lengths of the second light emitting area EA2 and the third light emitting area EA3 in the second direction DR2. The length of the second light emitting area EA2 in the second direction DR2 may be longer than the length of the third light emitting area EA3 in the second direction DR2.

[0104] exist Figure 5 , each of the first light emitting area EA1, the second light emitting area EA2, and the third light emitting area EA3 has a quadrilateral plane shape, but the exemplary embodiments of the present specification are not limited thereto. For example, each of the first light emitting area EA1, the second light emitting area EA2, and the third light emitting area EA3 may have a polygonal, circular, or elliptical plane shape other than a quadrilateral shape.

[0105] In each of the plurality of unit pixels UPX, the first light emitting region EA1 and the second light emitting region EA2 may be disposed adjacent to each other in the first direction DR1. In addition, the first light emitting region EA1 and the third light emitting region EA3 may be disposed adjacent to each other in the first direction DR1. In addition, the second light emitting region EA2 and the third light emitting region EA3 may be disposed adjacent to each other in the second direction DR2. The area of ​​the first light emitting region EA1, the area of ​​the second light emitting region EA2, and the area of ​​the third light emitting region EA3 may be different.

[0106] The first light emitting area EA1 emits light of a first color, the second light emitting area EA2 emits light of a second color, and the third light emitting area EA3 emits light of a third color. Here, the light of the first color may be light in a blue band, the light of the second color may be light in a green band, and the light of the third color may be light in a red band. For example, the blue band may indicate that the main peak wavelength of the light is included in a band of approximately 370nm to 460nm, the green band may indicate that the main peak wavelength of the light is included in a band of approximately 480nm to 560nm, and the red band may indicate that the main peak wavelength of the light is included in a band of approximately 600nm to 750nm.

[0107] exist Figure 5, each of the plurality of unit pixels UPX includes three emission areas EA1, EA2, and EA3, but the exemplary embodiments of the present specification are not limited thereto. That is, each of the plurality of unit pixels UPX may also include four emission areas.

[0108] In addition, the arrangement of the light emitting regions of the plurality of unit pixels UPX is not limited to Figure 5 For example, the light emitting regions of the plurality of unit pixels UPX may be arranged in a stripe structure in which the light emitting regions are arranged in a first direction DR1, in which the light emitting regions have a diamond arrangement, or in which the light emitting regions have a stripe arrangement. A structure or a hexagonal structure in which a light emitting area having a hexagonal planar shape is arranged.

[0109] Figure 6 It is shown along Figure 5 A cross-sectional view of an example of a display device taken along line AA′.

[0110] Reference Figure 6 , the display panel 100 includes a semiconductor backplane SBP, a light emitting element backplane EBP, a light emitting element layer EMTL, an encapsulation layer TFE, an optical layer OPL, a cover layer CVL and a polarizing plate (not shown).

[0111] The semiconductor backplane SBP includes a semiconductor substrate SSUB including a plurality of source regions and a plurality of drain regions of a plurality of pixel transistors PTR, a plurality of semiconductor insulating films covering the plurality of pixel transistors PTR, and a plurality of contact terminals CTE electrically connected to the plurality of pixel transistors PTR, respectively. Figure 4 The first transistor T1 to the sixth transistor T6 are described.

[0112] The semiconductor substrate SSUB may be a silicon substrate, a germanium substrate or a silicon germanium substrate. The semiconductor substrate SSUB may be a substrate doped with a first type of impurity. A plurality of wells WA may be provided in the semiconductor substrate SSUB. The plurality of wells WA may be regions doped with a second type of impurity. The second type of impurity may be different from the first type of impurity described above. For example, when the first type of impurity is a P type impurity, the second type of impurity may be an N type impurity. Alternatively, when the first type of impurity is an N type impurity, the second type of impurity may be a P type impurity.

[0113] Each of the plurality of wells WA includes a source region SA corresponding to a source electrode of the pixel transistor PTR, a drain region DA corresponding to a drain electrode of the pixel transistor PTR, and a channel region CH disposed between the source region SA and the drain region DA.

[0114] Each of the source region SA and the drain region DA may be a region heavily doped with first type impurities. The gate electrode GE of the pixel transistor PTR may overlap the well WA in the third direction DR3. The channel region CH may overlap the gate electrode GE in the third direction DR3. The source region SA may be disposed on one side of the gate electrode GE, and the drain region DA may be disposed on the other side of the gate electrode GE.

[0115] Each of the plurality of wells WA further includes a first lightly doped region disposed between the channel region CH and the source region SA and a second lightly doped region disposed between the channel region CH and the drain region DA. The first lightly doped region may be a region having an impurity concentration lower than that of the source region SA. The second lightly doped region may be a region having an impurity concentration lower than that of the drain region DA. The distance between the source region SA and the drain region DA may be increased by the first lightly doped region and the second lightly doped region. Therefore, since the length of the channel region CH of each of the pixel transistors PTR may be increased, punch-through and hot carrier phenomena caused by a short channel may be prevented.

[0116] A gate insulating layer (not shown) may be provided between the semiconductor substrate SSUB and the gate electrode GE. A first semiconductor insulating film SINS1 may be provided on the semiconductor substrate SSUB. The first semiconductor insulating film SINS1 may be formed of silicon nitride (SiN), silicon carbonitride (SiCN), or silicon oxide (SiO x )-based inorganic film, but the exemplary embodiments of the present specification are not limited thereto.

[0117] The second semiconductor insulating film SINS2 may be disposed on the first semiconductor insulating film SINS1. The second semiconductor insulating film SINS2 may include silicon oxide (SiO x )-based inorganic film, but the exemplary embodiments of the present specification are not limited thereto.

[0118] A plurality of contact terminals CTE may be disposed on the second semiconductor insulating film SINS2. Each of the plurality of contact terminals CTE may be connected to any one of the gate electrode GE, the source region SA, and the drain region DA of each of the plurality of pixel transistors PTR through a contact hole formed through the first semiconductor insulating film SINS1 and the second semiconductor insulating film SINS2. The plurality of contact terminals CTE may be formed of any one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), or an alloy including any one of them.

[0119] The third semiconductor insulating film SINS3 may be disposed on the plurality of contact terminals CTE. The upper surface of each of the plurality of contact terminals CTE may be exposed through a contact hole formed through the third semiconductor insulating film SINS3. The third semiconductor insulating film SINS3 may be formed of silicon oxide (SiO x )-based inorganic film, but the exemplary embodiments of the present specification are not limited thereto.

[0120] The semiconductor substrate SSUB may be replaced by a glass substrate or a polymer resin substrate (such as polyimide). In this case, the pixel transistor PTR may be disposed on the glass substrate or the polymer resin substrate. The glass substrate may be a rigid substrate that is not bent, and the polymer resin substrate may be a flexible substrate that can be bent or folded.

[0121] The light emitting element back plate EBP includes first to eighth metal layers ML1 to ML8, reflective electrodes RL1 to RL4, a plurality of vias VA1 to VA10, and a step layer STPL. In addition, the light emitting element back plate EBP includes a plurality of interlayer insulating films INS1 to INS10 disposed between the first to eighth metal layers ML1 to ML8.

[0122] The first metal layer ML1 to the eighth metal layer ML8 are used to realize the Figure 4 . That is, only the first to sixth transistors T1 to T6 are formed in the semiconductor backplane SBP, and the first to sixth transistors T1 to T6 and the first capacitor C1 and the second capacitor C2 are connected through the first to eighth metal layers ML1 to ML8. In addition, the drain region corresponding to the drain electrode of the fourth transistor T4, the source region corresponding to the source electrode of the fifth transistor T5, and the first electrode of the light emitting element ED are also connected through the first to eighth metal layers ML1 to ML8.

[0123] The first interlayer insulating film INS1 may be disposed on the semiconductor backplane SBP. Each of the first via holes VA1 may be formed through the first interlayer insulating film INS1 and connected to the contact terminal CTE exposed from the semiconductor backplane SBP. Each of the first metal layers ML1 may be disposed on the first interlayer insulating film INS1 and may be connected to the first via holes VA1.

[0124] The second interlayer insulating film INS2 may be disposed on the first interlayer insulating film INS1 and the first metal layer ML1. Each of the second vias VA2 may be connected to the first metal layer ML1 via a contact hole formed through the second interlayer insulating film INS2. Each of the second metal layers ML2 may be disposed on the second interlayer insulating film INS2 and may be connected to the second vias VA2.

[0125] The third interlayer insulating film INS3 may be disposed on the second interlayer insulating film INS2 and the second metal layer ML2. Each of the third vias VA3 may be connected to the second metal layer ML2 via a contact hole formed through the third interlayer insulating film INS3. Each of the third metal layers ML3 may be disposed on the third interlayer insulating film INS3 and may be connected to the third vias VA3.

[0126] The fourth interlayer insulating film INS4 may be disposed on the third interlayer insulating film INS3 and the third metal layer ML3. Each of the fourth vias VA4 may be connected to the third metal layer ML3 via a contact hole formed through the fourth interlayer insulating film INS4. Each of the fourth metal layers ML4 may be disposed on the fourth interlayer insulating film INS4 and may be connected to the fourth vias VA4.

[0127] The fifth interlayer insulating film INS5 may be disposed on the fourth interlayer insulating film INS4 and the fourth metal layer ML4. Each of the fifth vias VA5 may be connected to the fourth metal layer ML4 via a contact hole formed through the fifth interlayer insulating film INS5. Each of the fifth metal layers ML5 may be disposed on the fifth interlayer insulating film INS5 and may be connected to the fifth vias VA5.

[0128] The sixth interlayer insulating film INS6 may be disposed on the fifth interlayer insulating film INS5 and the fifth metal layer ML5. Each of the sixth vias VA6 may be connected to the fifth metal layer ML5 via a contact hole formed through the sixth interlayer insulating film INS6. Each of the sixth metal layers ML6 may be disposed on the sixth interlayer insulating film INS6 and may be connected to the sixth vias VA6.

[0129] The seventh interlayer insulating film INS7 may be disposed on the sixth interlayer insulating film INS6 and the sixth metal layer ML6. Each of the seventh vias VA7 may be connected to the sixth metal layer ML6 via a contact hole formed through the seventh interlayer insulating film INS7. Each of the seventh metal layers ML7 may be disposed on the seventh interlayer insulating film INS7 and may be connected to the seventh via VA7.

[0130] The eighth interlayer insulating film INS8 may be disposed on the seventh interlayer insulating film INS7 and the seventh metal layer ML7. Each of the eighth vias VA8 may be connected to the seventh metal layer ML7 via a contact hole formed through the eighth interlayer insulating film INS8. Each of the eighth metal layers ML8 may be disposed on the eighth interlayer insulating film INS8 and may be connected to the eighth via VA8.

[0131] The first metal layer ML1 to the eighth metal layer ML8 and the first via hole VA1 to the eighth via hole VA8 may be formed of substantially the same material. The first metal layer ML1 to the eighth metal layer ML8 and the first via hole VA1 to the eighth via hole VA8 may be formed of any one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni) and neodymium (Nd) or an alloy including any one thereof. The first via hole VA1 to the eighth via hole VA8 may be formed of substantially the same material. The first interlayer insulating film INS1 to the eighth interlayer insulating film INS8 may be formed of silicon oxide (SiO x )-based inorganic film, but the exemplary embodiments of the present specification are not limited thereto.

[0132] The thickness of the first metal layer ML1, the thickness of the second metal layer ML2, the thickness of the third metal layer ML3, the thickness of the fourth metal layer ML4, the thickness of the fifth metal layer ML5, and the thickness of the sixth metal layer ML6 may be respectively greater than the thickness of the first via VA1, the thickness of the second via VA2, the thickness of the third via VA3, the thickness of the fourth via VA4, the thickness of the fifth via VA5, and the thickness of the sixth via VA6. Each of the thickness of the second metal layer ML2, the thickness of the third metal layer ML3, the thickness of the fourth metal layer ML4, the thickness of the fifth metal layer ML5, and the thickness of the sixth metal layer ML6 may be greater than the thickness of the first metal layer ML1. The thickness of the second metal layer ML2, the thickness of the third metal layer ML3, the thickness of the fourth metal layer ML4, the thickness of the fifth metal layer ML5, and the thickness of the sixth metal layer ML6 may be substantially the same. For example, the thickness of the first metal layer ML1 may be approximately Each of the thickness of the second metal layer ML2, the thickness of the third metal layer ML3, the thickness of the fourth metal layer ML4, the thickness of the fifth metal layer ML5, and the thickness of the sixth metal layer ML6 may be approximately And each of the thickness of the first via hole VA1, the thickness of the second via hole VA2, the thickness of the third via hole VA3, the thickness of the fourth via hole VA4, the thickness of the fifth via hole VA5, and the thickness of the sixth via hole VA6 may be approximately

[0133] Each of the thickness of the seventh metal layer ML7 and the thickness of the eighth metal layer ML8 may be greater than each of the thickness of the first metal layer ML1, the thickness of the second metal layer ML2, the thickness of the third metal layer ML3, the thickness of the fourth metal layer ML4, the thickness of the fifth metal layer ML5, and the thickness of the sixth metal layer ML6. Each of the thickness of the seventh metal layer ML7 and the thickness of the eighth metal layer ML8 may be greater than each of the thickness of the seventh via VA7 and the thickness of the eighth via VA8. Each of the thickness of the seventh via VA7 and the thickness of the eighth via VA8 may be greater than each of the thickness of the first via VA1, the thickness of the second via VA2, the thickness of the third via VA3, the thickness of the fourth via VA4, the thickness of the fifth via VA5, and the thickness of the sixth via VA6. The thickness of the seventh metal layer ML7 and the thickness of the eighth metal layer ML8 may be substantially the same. For example, each of the thickness of the seventh metal layer ML7 and the thickness of the eighth metal layer ML8 may be approximately Each of the thickness of the seventh via hole VA7 and the thickness of the eighth via hole VA8 may be approximately

[0134] The ninth interlayer insulating film INS9 may be disposed on the eighth interlayer insulating film INS8 and the eighth metal layer ML8. The ninth interlayer insulating film INS9 may be formed of silicon oxide (SiO x )-based inorganic film, but the exemplary embodiments of the present specification are not limited thereto.

[0135] Each of the ninth via holes VA9 may be connected to the eighth metal layer ML8 via a contact hole formed through the ninth interlayer insulating film INS9. The ninth via hole VA9 may be formed of any one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), or an alloy including any one of them. The thickness of the ninth via hole VA9 may be approximately

[0136] Each of the first reflective electrodes RL1 may be disposed on the ninth interlayer insulating film INS9 and may be connected to the ninth via hole VA9. The first reflective electrode RL1 may be formed of any one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), or an alloy including any one thereof.

[0137] Each of the second reflective electrodes RL2 may be disposed on the first reflective electrode RL1. The second reflective electrode RL2 may be formed of any one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), or an alloy including any one thereof. For example, the second reflective electrode RL2 may be formed of titanium nitride (TiN).

[0138] In the first pixel PX1, the step layer STPL may be disposed on the second reflective electrode RL2. The step layer STPL may not be disposed in each of the second pixel PX2 and the third pixel PX3. The thickness of the step layer STPL may be set in consideration of the wavelength of the light of the first color and the distance from the intermediate layer IL to the fourth reflective electrode RL4, so as to facilitate reflection of the light of the first color emitted from the intermediate layer IL of the first pixel PX1. The step layer STPL may be made of silicon carbon nitride (SiCN) or silicon oxide (SiO x )-based inorganic film is formed, but the embodiments of the present specification are not limited thereto. The thickness of the step layer STPL may be approximately

[0139] In the first pixel PX1, the third reflective electrode RL3 may be disposed on the second reflective electrode RL2 and the step layer STPL. In the second pixel PX2 and the third pixel PX3, the third reflective electrode RL3 may be disposed on the second reflective electrode RL2. The third reflective electrode RL3 may be formed of any one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), or an alloy including any one thereof.

[0140] At least one of the first reflective electrode RL1, the second reflective electrode RL2, and the third reflective electrode RL3 may be omitted.

[0141] Each of the fourth reflective electrodes RL4 may be disposed on the third reflective electrode RL3. The fourth reflective electrode RL4 may be a layer that reflects light from the first to third intermediate layers IL. The fourth reflective electrode RL4 may include a metal having a high reflectivity to efficiently reflect light from the intermediate layer IL. The fourth reflective electrode RL4 may be formed of aluminum (Al), a stacked structure of aluminum and titanium (Ti / Al / Ti), a stacked structure of aluminum and ITO (ITO / Al / ITO), an APC alloy that is an alloy of silver (Ag), palladium (Pd), and copper (Cu), and a stacked structure of an APC alloy and ITO (ITO / APC / ITO), but exemplary embodiments of the present specification are not limited thereto. The thickness of each of the fourth reflective electrodes RL4 may be approximately 1000 Å.

[0142] The tenth interlayer insulating film INS10 may be disposed on the ninth interlayer insulating film INS9 and the fourth reflective electrode RL4. The tenth interlayer insulating film INS10 may be formed of silicon oxide (SiO x )-based inorganic film, but the exemplary embodiments of the present specification are not limited thereto.

[0143] Each of the tenth via holes VA10 may be connected to the fourth reflective electrode RL4 via a contact hole formed through the tenth interlayer insulating film INS10. The tenth via hole VA10 may be formed of any one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), or an alloy including any one thereof. Due to the step layer STPL, the thickness of the tenth via hole VA10 in the first pixel PX1 may be less than the thickness of the tenth via hole VA10 in each of the second pixel PX2 and the third pixel PX3. For example, the thickness of the tenth via hole VA10 in the first pixel PX1 may be approximately And the thickness of the tenth via hole VA10 in each of the second pixel PX2 and the third pixel PX3 may be approximately

[0144] The light emitting element layer EMTL may be disposed on the light emitting element backplane EBP and may include light emitting elements ED, a pixel defining layer PDL, and a plurality of trenches TRC, each of the light emitting elements ED including a first electrode AND, an intermediate layer IL, and a second electrode CAT.

[0145] The first electrode AND of each of the light emitting elements ED may be disposed on the tenth interlayer insulating film INS10 and may be connected to the tenth via VA10. The first electrode AND of each of the light emitting elements ED may be connected to the drain area DA or the source area SA of the pixel transistor PTR through the tenth via VA10, the first to fourth reflective electrodes RL1 to RL4, the first to ninth vias VA1 to VA9, the first to eighth metal layers ML1 to ML8, and the contact terminal CTE. The first electrode AND of each of the light emitting elements ED may be formed of any one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), or an alloy including any one of them. For example, the first electrode AND of each of the light emitting elements ED may be formed of titanium nitride (TiN).

[0146] The pixel definition film PDL may be disposed on the first electrode AND of each of the light emitting elements ED. The pixel definition film PDL may cover the edge of the first electrode AND and expose the center of the first electrode AND of each of the light emitting elements ED. The pixel definition film PDL is used to separate the first light emitting area EA1, the second light emitting area EA2, and the third light emitting area EA3.

[0147] The first light emitting region EA1 may be defined as a region where the first electrode AND, the intermediate layer IL, and the second electrode CAT are sequentially stacked in the first pixel PX1 to emit light. The second light emitting region EA2 may be defined as a region where the first electrode AND, the intermediate layer IL, and the second electrode CAT are sequentially stacked in the second pixel PX2 to emit light. The third light emitting region EA3 may be defined as a region where the first electrode AND, the intermediate layer IL, and the second electrode CAT are sequentially stacked in the third pixel PX3 to emit light.

[0148] The pixel definition film PDL may include first to third pixel definition films PDL1, PDL2, and PDL3. The first pixel definition film PDL1 may be disposed on the edge of the first electrode AND of each of the light emitting elements ED, the second pixel definition film PDL2 may be disposed on the first pixel definition film PDL1, and the third pixel definition film PDL3 may be disposed on the second pixel definition film PDL2. The first pixel definition film PDL1, the second pixel definition film PDL2, and the third pixel definition film PDL3 may be formed of silicon oxide (SiO x )-based inorganic film, but the exemplary embodiments of the present specification are not limited thereto. Each of the thickness of the first pixel defining film PDL1, the thickness of the second pixel defining film PDL2, and the thickness of the third pixel defining film PDL3 may be approximately

[0149] Each of the plurality of trenches TRC may be formed through the first pixel defining film PDL1 , the second pixel defining film PDL2 , the third pixel defining film PDL3 , and the tenth interlayer insulating film INS10 .

[0150] At least one trench TRC may be provided between pixels PX1, PX2, and PX3 adjacent to each other. Figure 6 2 shows that two trenches TRC are disposed between pixels PX1 , PX2 , and PX3 that are adjacent to each other, but exemplary embodiments of the present specification are not limited thereto.

[0151] The intermediate layer IL may include a first intermediate layer IL1 , a second intermediate layer IL2 , and a third intermediate layer IL3 .

[0152] The intermediate layer IL may have a series structure including a plurality of intermediate layers IL1, IL2, and IL3 emitting different lights. For example, the intermediate layer IL may include a first intermediate layer IL1 emitting light of a first color, a second intermediate layer IL2 emitting light of a third color, and a third intermediate layer IL3 emitting light of a second color. The first intermediate layer IL1, the second intermediate layer IL2, and the third intermediate layer IL3 may be sequentially stacked.

[0153] The first intermediate layer IL1 may have a structure in which a first hole transport layer, a first organic light emitting layer emitting light of a first color, and a first electron transport layer are sequentially stacked. The second intermediate layer IL2 may have a structure in which a second hole transport layer, a second organic light emitting layer emitting light of a third color, and a second electron transport layer are sequentially stacked. The third intermediate layer IL3 may have a structure in which a third hole transport layer, a third organic light emitting layer emitting light of a second color, and a third electron transport layer are sequentially stacked.

[0154] A first charge generation layer for supplying holes to the second intermediate layer IL2 and electrons to the first intermediate layer IL1 may be disposed between the first intermediate layer IL1 and the second intermediate layer IL2. A second charge generation layer for supplying holes to the third intermediate layer IL3 and electrons to the second intermediate layer IL2 may be disposed between the second intermediate layer IL2 and the third intermediate layer IL3.

[0155] The first intermediate layer IL1 may be disposed on the first electrode AND and the pixel defining film PDL, and may be disposed on the bottom surface of each of the grooves TRC. Due to the groove TRC, the first intermediate layer IL1 may be disconnected between mutually adjacent pixels PX1, PX2, and PX3. The second intermediate layer IL2 may be disposed on the first intermediate layer IL1. Due to the groove TRC, the second intermediate layer IL2 may be disconnected between mutually adjacent pixels PX1, PX2, and PX3. The third intermediate layer IL3 may be disposed on the second intermediate layer IL2. Due to the groove TRC, the third intermediate layer IL3 may be disconnected between mutually adjacent pixels PX1, PX2, and PX3. That is, each of the plurality of grooves TRC may be a structure for disconnecting the first to third intermediate layers IL1, IL2, and IL3 of the light emitting element layer EMTL between mutually adjacent pixels PX1, PX2, and PX3.

[0156] In order to stably disconnect the first to third intermediate layers IL1, IL2, and IL3 of the light emitting element layer EMTL between the adjacent pixels PX1, PX2, and PX3, the depth of each of the plurality of grooves TRC may be greater than the depth of the pixel defining film PDL. The depth of each of the plurality of grooves TRC represents the length of each of the plurality of grooves TRC in the third direction DR3. The height of the pixel defining film PDL represents the length of the pixel defining film PDL in the third direction DR3.

[0157] In order to disconnect the first to third intermediate layers IL1, IL2 and IL3 of the light emitting element layer EMTL between adjacent pixels PX1, PX2 and PX3, other structures may exist instead of the trench TRC. For example, instead of the trench TRC, a partition wall having an inverted tapered shape may be provided on the pixel defining film PDL.

[0158] The number of the intermediate layers IL1, IL2 and IL3 emitting different light is not limited to Figure 6 . For example, the intermediate layer IL may include two intermediate layers. In this case, one of the two intermediate layers may be substantially the same as the first intermediate layer IL1, and the other thereof may include a second hole transport layer, a second organic light emitting layer, a third organic light emitting layer, and a second electron transport layer. In this case, a charge generation layer for supplying electrons to one intermediate layer and holes to the other intermediate layer may be provided between the two intermediate layers.

[0159] In addition, Figure 6 , it is shown that the first to third intermediate layers IL1, IL2, and IL3 are all arranged in the first light-emitting area EA1, the second light-emitting area EA2, and the third light-emitting area EA3, but the exemplary embodiments of the present specification are not limited thereto. For example, the first intermediate layer IL1 may be arranged in the first light-emitting area EA1, and may not be arranged in the second light-emitting area EA2 and the third light-emitting area EA3. In addition, the second intermediate layer IL2 may be arranged in the second light-emitting area EA2, and may not be arranged in the first light-emitting area EA1 and the third light-emitting area EA3. In addition, the third intermediate layer IL3 may be arranged in the third light-emitting area EA3, and may not be arranged in the first light-emitting area EA1 and the second light-emitting area EA2. In this case, the first to third color filters CF1, CF2, and CF3 of the optical layer OPL may be omitted.

[0160] The second electrode CAT may be disposed on the third intermediate layer IL3. The second electrode CAT may be disposed on the third intermediate layer IL3 in each of the plurality of trenches TRC. The second electrode CAT may be formed of a transparent conductive material (TCO) capable of transmitting light, such as ITO or IZO, or a semi-transmissive conductive material, such as magnesium (Mg), silver (Ag), or an alloy of magnesium (Mg) and silver (Ag). When the second electrode CAT is formed of a semi-transmissive conductive material, the light emitting efficiency in each of the first to third pixels PX1, PX2, and PX3 may be increased through a microcavity.

[0161] The encapsulation layer TFE may be disposed on the light emitting element layer EMTL. The encapsulation layer TFE may include one or more inorganic films TFE1 and TFE3 to prevent oxygen or moisture from penetrating into the light emitting element layer EMTL. In addition, the encapsulation layer TFE may include at least one organic film to protect the light emitting element layer EMTL from foreign matter such as dust. For example, the encapsulation layer TFE may include a first encapsulation inorganic film TFE1, an encapsulation organic film TFE2, and a second encapsulation inorganic film TFE3.

[0162] The first encapsulation inorganic film TFE1 may be disposed on the second electrode CAT, the encapsulation organic film TFE2 may be disposed on the first encapsulation inorganic film TFE1, and the second encapsulation inorganic film TFE3 may be disposed on the encapsulation organic film TFE2. The first encapsulation inorganic film TFE1 and the second encapsulation inorganic film TFE3 may be formed as a silicon nitride layer (SiN x ), silicon oxynitride layer (SiON), silicon oxide layer (SiO x ), titanium oxide layer (TiO x ) and aluminum oxide layer (AlO x ) in which one or more inorganic films are alternately stacked. The encapsulating organic film TFE2 may be a single layer. In addition, the encapsulating organic film TFE2 may be an organic film made of acryl resin, epoxy resin, phenolic resin, polyamide resin or polyimide resin.

[0163] The adhesive layer ADL may be a layer for adhering the encapsulation layer TFE and the optical layer OPL. The adhesive layer ADL may be a double-sided adhesive member. In addition, the adhesive layer ADL may be a transparent adhesive member such as a transparent adhesive or a transparent adhesive resin.

[0164] The optical layer OPL includes a plurality of color filters CF1, CF2, and CF3, a plurality of lenses LNS, and a filling layer FIL. The plurality of color filters CF1, CF2, and CF3 may include first to third color filters CF1, CF2, and CF3. The first to third color filters CF1, CF2, and CF3 may be disposed on the adhesive layer ADL.

[0165] The first color filter CF1 may overlap the first light emitting area EA1 of the first pixel PX1. The first color filter CF1 may transmit light of the first color (i.e., light in the blue band). The blue band may be approximately 370 nm to 460 nm. Therefore, the first color filter CF1 may transmit light of the first color among the light emitted from the first light emitting area EA1.

[0166] The second color filter CF2 may overlap the second light emitting area EA2 of the second pixel PX2. The second color filter CF2 may transmit light of the second color (i.e., light in the green band). The green band may be approximately 480 nm to 560 nm. Therefore, the second color filter CF2 may transmit light of the second color among the light emitted from the second light emitting area EA2.

[0167] The third color filter CF3 may overlap the third light emitting area EA3 of the third pixel PX3. The third color filter CF3 may transmit light of a third color (i.e., light in a red band). The red band may be approximately 600nm to 750nm. Therefore, the third color filter CF3 may transmit light of a third color among the light emitted from the third light emitting area EA3.

[0168] Each of the plurality of lenses LNS may be disposed on each of the first color filter CF1, the second color filter CF2, and the third color filter CF3. Each of the plurality of lenses LNS may be a structure for increasing the ratio of light guided to the front of the display device 10. Each of the plurality of lenses LNS may have a cross-sectional shape convex in an upward direction.

[0169] The filling layer FIL may be disposed on the plurality of lenses LNS. The filling layer FIL may have a predetermined refractive index so that light travels in a third direction DR3 at an interface between the plurality of lenses LNS and the filling layer FIL. In addition, the filling layer FIL may be a planarization layer. The filling layer FIL may be an organic film made of an acryl resin, an epoxy resin, a phenolic resin, a polyamide resin, or a polyimide resin.

[0170] The cover layer CVL may be disposed on the filling layer FIL. The cover layer CVL may be a glass substrate or a resin such as a polymer resin. When the cover layer CVL is a glass substrate, the cover layer CVL may be attached to the filling layer FIL. In this case, the filling layer FIL may be used to adhere the cover layer CVL. When the cover layer CVL is a glass substrate, the cover layer CVL may be used as a packaging substrate. When the cover layer CVL is a resin such as a polymer resin, the cover layer CVL may be directly applied to the filling layer FIL.

[0171] A polarizing plate (not shown) may be provided on one surface of the cover layer CVL. The polarizing plate may be a structure for preventing visibility degradation caused by reflection of external light. The polarizing plate may include a linear polarizing plate and a phase delay film. For example, the phase delay film may be a λ / 4 (quarter wave) plate, but the exemplary embodiments of the present specification are not limited thereto. However, when visibility degradation caused by reflection of external light is sufficiently improved by the first to third color filters CF1, CF2, and CF3, the polarizing plate may also be omitted.

[0172] Figure 7 is a perspective view illustrating a head mounted display device according to an exemplary embodiment. Figure 8 It is shown Figure 7 An exploded perspective view of an example of a display unit of a head-mounted display device.

[0173] Reference Figure 7 and Figure 8 According to an exemplary embodiment, a head-mounted display device 1000 as an optical device includes a first display device 10_1, a second display device 10_2, a display device accommodating portion 1100, an accommodating portion cover 1200, optical path conversion members 1210, 1220, 1510 and 1520, a head-mounted band 1300, an intermediate frame 1400, a control circuit board 1600 and a connector 1610.

[0174] The optical path conversion member may include a first eyepiece lens 1210 , a second eyepiece lens 1220 , a first optical member 1510 , and a second optical member 1520 .

[0175] The first display device 10_1 provides an image to the left eye of the user, and the second display device 10_2 provides an image to the right eye of the user. Figures 1 to 6 The display devices 10 described are substantially the same, and thus descriptions of the first display device 10_1 and the second display device 10_2 are omitted.

[0176] The first optical member 1510 may be disposed between the first display device 10_1 and the first eyepiece lens 1210. The second optical member 1520 may be disposed between the second display device 10_2 and the second eyepiece lens 1220. Each of the first optical member 1510 and the second optical member 1520 may include at least one convex lens.

[0177] The middle frame 1400 may be disposed between the first display device 10_1 and the control circuit board 1600, and may be disposed between the second display device 10_2 and the control circuit board 1600. The middle frame 1400 is used to support and fix the first display device 10_1, the second display device 10_2, and the control circuit board 1600.

[0178] The control circuit board 1600 may be disposed between the middle frame 1400 and the display device receiving portion 1100. The control circuit board 1600 may be connected to the first display device 10_1 and the second display device 10_2 through the connector 1610. The control circuit board 1600 may convert an image source input from the outside into digital video data DATA, and may transmit the digital video data DATA to the first display device 10_1 and the second display device 10_2 through the connector 1610.

[0179] The control circuit board 1600 may transmit digital video data DATA corresponding to a left-eye image optimized for the user's left eye to the first display device 10_1, and may transmit digital video data DATA corresponding to a right-eye image optimized for the user's right eye to the second display device 10_2. Alternatively, the control circuit board 1600 may transmit the same digital video data DATA to the first display device 10_1 and the second display device 10_2.

[0180] The display device accommodating portion 1100 is used to accommodate the first display device 10_1, the second display device 10_2, the middle frame 1400, the first optical member 1510, the second optical member 1520, the control circuit board 1600, and the connector 1610. The accommodating portion cover 1200 is provided to cover one open surface of the display device accommodating portion 1100. The accommodating portion cover 1200 may include a first eyepiece lens 1210 disposed in an area corresponding to the left eye of the user and a second eyepiece lens 1220 disposed in an area corresponding to the right eye of the user. Figure 7 and Figure 8 2 shows that the first eyepiece lens 1210 and the second eyepiece lens 1220 are separately provided, but the exemplary embodiments of the present specification are not limited thereto. The first eyepiece lens 1210 and the second eyepiece lens 1220 may be integrated.

[0181] The first eyepiece lens 1210 may be aligned with the first display device 10_1 and the first optical member 1510, and the second eyepiece lens 1220 may be aligned with the second display device 10_2 and the second optical member 1520. Therefore, the user may view the image of the first display device 10_1 magnified as a virtual image by the first optical member 1510 through the first eyepiece lens 1210, and may view the image of the second display device 10_2 magnified as a virtual image by the second optical member 1520 through the second eyepiece lens 1220.

[0182] The head-mounted strap 1300 is used to fix the display unit 1700 to the user's head so that the first eyepiece lens 1210 and the second eyepiece lens 1220 of the receiving portion cover 1200 are respectively disposed in front of the left eye and the right eye of the user. When the display device receiving portion 1100 is implemented with light weight and small size, the head-mounted display device 1000 may include Fig. 9 The eyeglass frame shown in FIG. 1 is used to replace the headband 1300.

[0183] In addition, the head mounted display device 1000 may further include a battery for supplying power, an external storage slot for accommodating an external memory, and an external connection port and a wireless communication module for receiving an image source. The external connection port may be a universal serial bus (USB) terminal, a display port, or a high-definition multimedia interface (HDMI) terminal, and the wireless communication module may be a 5G communication module, a 4G communication module, a Wi-Fi module, or a Bluetooth module.

[0184] Fig. 9 is a perspective view illustrating a head mounted display device according to an exemplary embodiment.

[0185] Reference Fig. 9 The head mounted display device 1000_1 according to an exemplary embodiment may be a glasses type display device in which the display device accommodating portion 1200_1 is implemented with light weight and small size. The head mounted display device 1000_1 according to an exemplary embodiment may include a display device 10_3, a left eye lens 1010, a right eye lens 1020, a support frame 1030, glasses frame legs 1040 and 1050, an optical member 1060, an optical path conversion member 1070, and a display device accommodating portion 1200_1.

[0186] The display device accommodating portion 1200_1 may accommodate the display device 10_3, the optical member 1060, and the optical path conversion member 1070. When the image displayed on the display device 10_3 is enlarged by the optical member 1060 and the optical path thereof is converted by the optical path conversion member 1070, the image may be provided to the right eye of the user through the right eye lens 1020. Thus, the user may view an augmented reality image in which a virtual image displayed on the display device 10_3 and a real image viewed through the right eye lens 1020 are combined through the right eye.

[0187] exist Fig. 91030, but the exemplary embodiments of the present specification are not limited thereto. For example, the display device accommodating portion 1200_1 may be disposed at the left distal end of the supporting frame 1030, and in this case, the image of the display device 10_3 may be provided to the left eye of the user. Alternatively, the display device accommodating portion 1200_1 may be disposed at both the left distal end and the right distal end of the supporting frame 1030. In this case, the user may view the image displayed on the display device 10_3 through both the left eye and the right eye of the user.

[0188] Fig.10 is a plan view of a display device according to an exemplary embodiment.

[0189] like Fig.10 As shown in , the display device 10 may include a first pixel PX1, a second pixel PX2, and a third pixel PX3. The first pixel PX1, the second pixel PX2, and the third pixel PX3 may form a unit pixel. In other words, the unit pixel may include the first pixel PX1, the second pixel PX2, and the third pixel PX3 disposed adjacent to each other.

[0190] The first pixel PX1 to the third pixel PX3 of the unit pixel may be pixels providing light of different colors (or wavelengths). For example, the first pixel PX1 may emit light of a first color, the second pixel PX2 may emit light of a second color, and the third pixel PX3 may emit light of a third color. Here, the first color may be any one of red, green, and blue, the second color may be another color different from the first color among the above red, green, and blue, and the third color may be another color different from the first color and the second color among the above red, green, and blue.

[0191] The first pixel PX1 may include a first pixel electrode AND1 , the second pixel PX2 may include a second pixel electrode AND2 , and the third pixel PX3 may include a third pixel electrode AND3 .

[0192] The first pixel electrode AND1, the second pixel electrode AND2, and the third pixel electrode AND3 may be disposed adjacent to each other. For example, the first pixel electrode AND1 and the second pixel electrode AND2 may be disposed adjacent to each other in the first direction DR1, the second pixel electrode AND2 and the third pixel electrode AND3 may be disposed adjacent to each other in the second direction DR2, and the third pixel electrode AND3 and the first pixel electrode AND1 may be disposed adjacent to each other in the second direction DR2.

[0193] The first pixel electrode AND1 to the third pixel electrode AND3 may have different sizes. For example, the area of ​​the third pixel electrode AND3 may be greater than the sum of the area of ​​the first pixel electrode AND1 and the area of ​​the second pixel electrode AND2. In this case, the third pixel PX3 including the third pixel electrode AND3 may provide blue light, the first pixel PX1 including the first pixel electrode AND1 may provide red light, and the second pixel PX2 including the second pixel electrode AND2 may provide green light. At the same time, as described above, when the third pixel PX3 provides blue light, the first pixel PX1 provides red light, and the second pixel PX2 provides green light, the area of ​​the second pixel electrode AND2 may be greater than the area of ​​the first pixel electrode AND1 and smaller than the area of ​​the third pixel electrode AND3.

[0194] A portion of the first pixel electrode AND1 (e.g., an edge of the first pixel electrode AND1), a portion of the second pixel electrode AND2 (e.g., an edge of the second pixel electrode AND2), and a portion of the third pixel electrode AND3 (e.g., an edge of the third pixel electrode AND3) may be formed by a bank ( Fig.11 In other words, a portion of the first pixel electrode AND1 (e.g., an edge of the first pixel electrode AND1), a portion of the second pixel electrode AND2 (e.g., an edge of the second pixel electrode AND2), and a portion of the third pixel electrode AND3 (e.g., an edge of the third pixel electrode AND3) may partially overlap with the bank PDL.

[0195] The exposed areas of the first pixel electrode AND1, the second pixel electrode AND2, and the third pixel electrode AND3 that are not covered by the bank PDL may be defined as a first light emitting area EA1, a second light emitting area EA2, and a third light emitting area EA3, respectively. For example, the first light emitting area EA1 may be a light emitting area of ​​a first pixel PX1 including the first pixel electrode AND1, the second light emitting area EA2 may be a light emitting area of ​​a second pixel PX2 including the second pixel electrode AND2, and the third light emitting area EA3 may be a light emitting area of ​​a third pixel PX3 including the third pixel electrode AND3.

[0196] Fig.11 It is along Fig.10 1 is a cross-sectional view of a display device according to an exemplary embodiment taken along line II′.

[0197] like Fig.11 As shown in , the display device 10 may include a driving circuit layer DCL, a light emitting element layer EMTL, an encapsulation layer ENC, a color filter layer CFL, a lens layer LSL, and a cover layer CVL.

[0198] The substrate SUB may be a silicon substrate, a germanium substrate or a silicon germanium substrate. The substrate SUB may be a substrate SUB doped with first type impurities.

[0199] The well W may be disposed in the substrate SUB. The well W may be a region doped with a second type of impurity. The second type of impurity may be different from the first type of impurity described above. For example, when the first type of impurity is a P-type impurity, the second type of impurity may be an N-type impurity. On the other hand, when the first type of impurity is an N-type impurity, the second type of impurity may be a P-type impurity.

[0200] The source region S, drain region D, and channel region CH of the transistor TR may be arranged in the well W. For example, the source region S (or source electrode) and drain region D (or drain electrode) of the transistor TR may be arranged in the well W. Each of the source region S and the drain region D may be a region doped with the second type of impurities described above. The gate electrode G of the transistor TR may intersect and overlap the well W. In a plan view, the well W intersecting the gate electrode G may be defined as two regions, and the source region S may be arranged in one of the two regions, and the drain region D may be arranged in the other region. In other words, in the well W, the source region S and the drain region D may be arranged on both sides of the channel region CH, respectively, and the channel region CH is placed between the source region S and the drain region D. The channel region CH of the transistor TR may be arranged in the region of the well W overlapping the gate electrode G. Fig.11 The transistor TR shown in FIG. 1 may be, for example, Figure 4 The fourth transistor T4.

[0201] On the other hand, the source region S may include a first lightly doped region having a relatively lower impurity concentration than other portions of the source region S. In other words, a portion of the source region S may include impurities at a lower concentration than other portions of the source region S. The drain region D may include a second lightly doped region having a relatively lower impurity concentration than other portions of the drain region D. In other words, a portion of the drain region D may include impurities at a lower concentration than other portions of the drain region D.

[0202] The first lightly doped region and the second lightly doped region may be disposed close to the channel region CH of the transistor TR. For example, the first lightly doped region may be disposed close to the channel region CH to overlap with a first spacer (not shown) disposed on one side of the gate electrode G, and the second lightly doped region may be disposed close to the channel region CH to overlap with a second spacer (not shown) disposed on the other side of the gate electrode G. In this way, the distance between the highly doped impurity region of the source region S and the highly doped impurity region of the drain region D may be increased by the first lightly doped region and the second lightly doped region, and as the distance increases, the length of the channel region CH may eventually increase. Therefore, punch-through and hot carrier phenomena caused by a short channel may be prevented.

[0203] An interlayer insulating film INS may be disposed on the substrate SUB.

[0204] The passivation film PAS may be provided on the interlayer insulating film INS.

[0205] The light emitting element layer EMTL may be disposed on the passivation film PAS. The light emitting element layer EMTL may include, for example, a first light emitting element ED1, a second light emitting element ED2, and a third light emitting element ED3 disposed in different light emitting regions. For example, the first light emitting element ED1 of the light emitting element layer EMTL may be disposed in the first light emitting region EA1, the second light emitting element ED2 of the light emitting element layer EMTL may be disposed in the second light emitting region EA2, and the third light emitting element ED3 of the light emitting element layer EMTL may be disposed in the third light emitting region EA3.

[0206] Each of the first light emitting element ED1 , the second light emitting element ED2 , and the third light emitting element ED3 may emit white light.

[0207] The first light emitting element ED1 may include a first pixel electrode AND1 (or a first anode electrode), a light-providing layer LPL, and a common electrode CAT stacked in the third direction DR3. Figure 6 The AND corresponds to the first electrode set on the left.

[0208] The second light emitting element ED2 may include a second pixel electrode AND2 (or a second anode electrode), a light-supplying layer LPL, and a common electrode CAT stacked in the third direction DR3. Figure 6 The AND corresponds to the first electrode set in the middle.

[0209] The third light emitting element ED3 may include a third pixel electrode AND3 (or a third anode electrode), a light-providing layer LPL, and a common electrode CAT stacked in the third direction DR3. Figure 6 The AND corresponds to the first electrode set on the right side.

[0210] Here, the light supply layer LPL and the common electrode CAT may be common layers commonly used for each of the light emitting elements ED1 to ED3. In other words, the plurality of light emitting elements ED1 to ED3 of the light emitting element layer EMTL may share the light supply layer LPL and the common electrode CAT.

[0211] The light-providing layer LPL may include a plurality of light-emitting layers providing light of different colors, and the plurality of light-emitting layers may be stacked along the third direction DR3. White light may be generated by mixing light of different colors from the plurality of light-emitting layers. On the other hand, the light-providing layer LPL may further include a charge generation layer.

[0212] The light providing layer LPL can be Figure 6In this case, the light providing layer LPL may have Figure 6 The same structure of the intermediate layer IL.

[0213] Each of the first pixel electrode AND1 , the second pixel electrode AND2 , and the third pixel electrode AND3 may be connected to each source region S of each transistor TR through the pixel connection electrode PCE.

[0214] The first pixel electrode AND1 may be disposed to correspond to the first light emitting region EA1, the second pixel electrode AND2 may be disposed to correspond to the second light emitting region EA2, and the third pixel electrode AND3 may be disposed to correspond to the third light emitting region EA3.

[0215] A bank PDL (or a pixel defining film) may be disposed on the first pixel electrode AND1 , the second pixel electrode AND2 , and the third pixel electrode AND3 .

[0216] The bank PDL may define each light emitting area of ​​each of the pixels PX1 to PX3 (e.g., the first light emitting area EA1 of the first pixel PX1, the second light emitting area EA2 of the second pixel PX2, and the third light emitting area EA3 of the third pixel PX3). To this end, the bank PDL may be provided to expose a partial area of ​​each of the first pixel electrode AND1, the second pixel electrode AND2, and the third pixel electrode AND3 on the passivation film PAS. The bank PDL may cover the edges of the first pixel electrode AND1, the second pixel electrode AND2, and the third pixel electrode AND3. The bank PDL may be formed as an organic film made of an acryl resin, an epoxy resin, a phenolic resin, a polyamide resin, or a polyimide resin.

[0217] The light-providing layer LPL may be disposed on each of the pixel electrodes AND1, AND2, and AND3 and the bank PDL. For example, the light-providing layer LPL may be disposed on the first pixel electrode AND1, the second pixel electrode AND2, the third pixel electrode AND3, and the bank PDL.

[0218] The PDL can be Figure 6 The bank PDL may have a Figure 6 The pixel definition film PDL has the same structure.

[0219] The light providing layer LPL may include a plurality of light emitting units. For example, the light providing layer LPL may include a first light emitting unit, a second light emitting unit, and a third light emitting unit stacked in the third direction DR3. Each light emitting unit may provide light of different wavelengths. For example, the first light emitting unit, the second light emitting unit, and the third light emitting unit may emit light of different colors. For example, the light providing layer LPL may have a series structure in which a plurality of light emitting units providing light of different colors are stacked in a vertical direction (e.g., in the third direction DR3).

[0220] The first light emitting unit may be disposed on each of the pixel electrodes AND1, AND2, and AND3. The first light emitting unit may include a first light emitting layer, a hole transport layer, an organic material layer, and an electron transport layer.

[0221] The second light emitting unit may be disposed on the first light emitting unit. The second light emitting unit may include a second light emitting layer, a hole transport layer, an organic material layer, and an electron transport layer.

[0222] The third light emitting unit may be disposed on the second light emitting unit. The third light emitting unit may include a third light emitting layer, a hole transport layer, an organic material layer, and an electron transport layer.

[0223] Each of the light emitting elements ED1, ED2, and ED3 can provide white light by mixing light of a first color (e.g., blue) from a first light emitting unit, light of a second color (e.g., red) from a second light emitting unit, and light of a third color (e.g., green) from a third light emitting unit. For example, each of the first light emitting element ED1, the second light emitting element ED2, and the third light emitting element ED3 can emit white light.

[0224] In addition, in addition to the above-mentioned light-emitting units, the light-providing layer LPL may further include at least one charge generating layer. For example, the charge generating layer may be arranged between the light-emitting units adjacent to each other along the third direction DR3. The charge generating layer may include, for example, a first charge generating layer and a second charge generating layer stacked in the third direction DR3. In this case, the first charge generating layer may be arranged between the first light-emitting unit and the second light-emitting unit, and the second charge generating layer may be arranged between the second light-emitting unit and the third light-emitting unit.

[0225] On the other hand, each charge generation layer may include a negative charge generation layer and a positive charge generation layer. For example, the first charge generation layer may include a first negative charge generation layer and a first positive charge generation layer stacked in the third direction DR3, and the second charge generation layer may include a second negative charge generation layer and a second positive charge generation layer stacked in the third direction DR3.

[0226] The common electrode CAT may be disposed on the light providing layer LPL. For example, the common electrode CAT may be disposed on the light providing layer LPL to overlap with the first pixel electrode AND1, the second pixel electrode AND2, the third pixel electrode AND3, the first light emitting area EA1, the second light emitting area EA2, the third light emitting area EA3, and the embankment PDL. In the top emission structure, the common electrode CAT may be formed of a transparent conductive material (TCO) capable of transmitting light (such as ITO or IZO) or a semi-transmissive conductive material (such as magnesium (Mg), silver (Ag), or an alloy of magnesium (Mg) and silver (Ag)). When the common electrode CAT is formed of a semi-transmissive conductive material, the luminous efficiency may be increased by the microcavity. The common electrode CAT may be overlapped with the above-mentioned Figure 6 The common electrode CAT may have a Figure 6 The second electrode CAT has the same structure.

[0227] The cap layer CPL may be disposed on the common electrode CAT. The cap layer CPL may include an inorganic insulating material. In an exemplary embodiment, the cap layer CPL may include aluminum oxide, titanium oxide, tantalum oxide, hafnium oxide, zinc oxide, silicon oxide, silicon nitride, and / or silicon oxynitride.

[0228] The encapsulation layer ENC may be disposed on the cover layer CPL. The encapsulation layer ENC may cover the upper surface and the side surface of the light emitting element layer EMTL, and may protect the light emitting element layer EMTL. The encapsulation layer ENC may include at least one inorganic film and at least one organic film for encapsulating the light emitting element layer EMTL. The encapsulation layer ENC may include one or more inorganic films TFE1 and TFE3 to prevent oxygen or moisture from penetrating into the light emitting element layer EMTL. In addition, the encapsulation layer TFE may include at least one organic film to protect the light emitting element layer EMTL from foreign matter such as dust. For example, the encapsulation layer TFE may include a first encapsulation inorganic film TFE1, an encapsulation organic film TFE2, and a second encapsulation inorganic film TFE3.

[0229] The first encapsulation inorganic film TFE1 may be disposed on the cap layer CPL, the encapsulation organic film TFE2 may be disposed on the first encapsulation inorganic film TFE1, and the second encapsulation inorganic film TFE3 may be disposed on the encapsulation organic film TFE2. The first encapsulation inorganic film TFE1 and the second encapsulation inorganic film TFE3 may be formed as a multilayer film in which one or more inorganic films of a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, and an aluminum oxide layer are alternately stacked. The encapsulation organic film TFE2 may be an organic film made of an acryl resin, an epoxy resin, a phenolic resin, a polyamide resin, or a polyimide resin.

[0230] In addition, the display device 10 may include a plurality of color filters CF1, CF2, and CF3 disposed in the emission areas EA1, EA2, and EA3. Each of the plurality of color filters CF1, CF2, and CF3 may be disposed to correspond to the emission areas EA1, EA2, and EA3. For example, the color filters CF1, CF2, and CF3 may be disposed on the encapsulation layer ENC to correspond to the emission areas EA1, EA2, and EA3.

[0231] The color filters CF1, CF2, and CF3 may include a first color filter CF1, a second color filter CF2, and a third color filter CF3 that are respectively arranged to correspond to different light-emitting areas EA1, EA2, and EA3. The color filters CF1, CF2, and CF3 may include a colorant (such as a dye or a pigment) that absorbs light in a band other than light in a specific band, and may be arranged to correspond to the color of light emitted from the light-emitting areas EA1, EA2, and EA3. For example, the first color filter CF1 may be a red color filter that is arranged to overlap with the first light-emitting area EA1 and transmits only a red first light. The second color filter CF2 may be a green color filter that is arranged to overlap with the second light-emitting area EA2 and transmits only a green second light, and the third color filter CF3 may be a blue color filter that is arranged to overlap with the third light-emitting area EA3 and transmits only a blue third light.

[0232] A plurality of color filters CF1, CF2, and CF3 may be arranged to partially overlap with other adjacent color filters CF1, CF2, and CF3. On the other hand, in the overlapping region between the color filters, the thickness of the overlapping portion of the adjacent color filters may be, for example, 1.5 μm. Here, the thickness of the overlapping portion of the adjacent color filters may be the length in the third direction DR3. In addition, in the overlapping region between the adjacent color filters, the width of the overlapping portion of the adjacent color filters may be, for example, less than or equal to 0.2 μm. Here, the width of the overlapping portion of the adjacent color filters may be the size in the first direction DR1 or the second direction DR2. Different color filters CF1, CF2, and CF3 may overlap each other in the region corresponding to the bank PDL, and the overlapping region of the color filters CF1, CF2, and CF3 is a region that does not overlap with the luminous regions EA1, EA2, and EA3. In the display device 10, since the color filters CF1, CF2, and CF3 are arranged to overlap each other, the intensity of the reflected light caused by the external light may be reduced. Furthermore, by adjusting the arrangement, shape, and area of ​​the color filters CF1, CF2, and CF3 in a plan view, the color of the reflected light caused by the external light can also be controlled.

[0233] On the other hand, although not shown, the display device 10 according to the exemplary embodiment may further include a light blocking layer disposed between adjacent color filters (e.g., between the first color filter CF1 and the second color filter CF2 or between the second color filter CF2 and the third color filter CF3) on the encapsulation layer ENC. The light blocking layer may include a plurality of holes disposed in a region corresponding to each of the light emitting regions EA1, EA2, and EA3. For example, a first hole of the light blocking layer may be disposed in a region corresponding to the first light emitting region EA1, a second hole of the light blocking layer may be disposed in a region corresponding to the second light emitting region EA2, and a third hole of the light blocking layer may be disposed in a region corresponding to the third light emitting region EA3. The area or size of the hole of the light blocking layer may be larger than the area or size of the light emitting regions EA1, EA2, and EA3 defined by the embankment PDL. Since the hole of the light blocking layer is formed to be larger than the light emitting regions EA1, EA2, and EA3, the light emitted from the light emitting regions EA1, EA2, and EA3 may be visually recognized by the user not only from the front side of the display device 10 but also from the side surface thereof.

[0234] In an exemplary embodiment, each of the color filters CF1, CF2, and CF3 covers the hole of the light blocking layer and has an area larger than the area of ​​the hole, and may have an area spaced apart from other color filters CF1, CF2, and CF3 on the light blocking layer. A plurality of color filters CF1, CF2, and CF3 may be spaced apart from other adjacent color filters CF1, CF2, and CF3 on the light blocking layer.

[0235] The lens layer LSL may be disposed on the color filter layer CFL. The lens layer LSL may be in direct contact with (or in contact with, or directly connected to) the color filter layer CFL on the color filter layer CFL. For example, the lens layer LSL may be in direct contact with the plurality of color filters CF1, CF2, and CF3. The lens layer LSL may include a plurality of lenses LNS (e.g., a plurality of micro lenses) and a filling layer FIL.

[0236] Each of the plurality of lenses LNS may be disposed on each of the first color filter CF1, the second color filter CF2, and the third color filter CF3. Each of the plurality of lenses LNS may be a structure for increasing the proportion of light directed to the front of the display device 10. Each of the plurality of lenses LNS may have a cross-sectional shape that is convex in an upward direction (e.g., a light emitting direction or a third direction DR3). For example, the distance d (e.g., the shortest distance) between adjacent lenses LNS may be greater than or equal to 0.3 μm. Here, the distance d between adjacent lenses LNS may be a dimension in the first direction DR1 or the second direction DR2. In addition, the thickness tk1 (e.g., the maximum thickness) of the lens LNS may be less than, for example, 1.5 μm. Here, the thickness tk1 of the lens LNS may be the length of the lens LNS in the third direction DR3. In addition, the cone angle θ of the lens LNS may be 60 to 70 degrees. Here, the cone angle θ of the lens LNS may refer to an angle between a tangent line formed at an edge of the lens LNS and a lower surface of the lens LNS (e.g., an interface between the lens LNS and the color filter layer CFL). In addition, the lens LNS may have a refractive index of, for example, 1.61. On the other hand, the thickness tk1 of the lens LNS may be the same as the thickness of the overlapping portion of the adjacent color filters described above. For example, when the thickness of the lens LNS is 1.5 μm, the thickness of the overlapping portion of the adjacent color filters (e.g., the first color filter CF1 and the second color filter CF2) may also be 1.5 μm.

[0237] The filling layer FIL may be disposed on the plurality of lenses LNS. The filling layer FIL may have a predetermined refractive index so that light travels in a third direction DR3 at an interface between the plurality of lenses LNS and the filling layer FIL. In addition, the filling layer FIL may be a planarization layer. The filling layer FIL may be an organic film made of an acryl resin, an epoxy resin, a phenolic resin, a polyamide resin, or a polyimide resin. The filling layer FIL may have a refractive index smaller than that of the above-mentioned lens LNS. In this case, the difference between the refractive index of the filling layer FIL and the refractive index of the lens LNS may be, for example, 0.1 to 0.2. For example, the filling layer FIL may have a refractive index of 1.41 to 1.51. In an exemplary embodiment, the refractive index of the above-mentioned lens LNS may be 1.61, and the refractive index of the filling layer FIL may be 1.51. In an exemplary embodiment, the filling layer FIL may have a thickness tk2 of 3 μm.

[0238] The cover layer CVL may be disposed on the filling layer FIL. The cover layer CVL may be a glass substrate or a resin such as a polymer resin. When the cover layer CVL is a glass substrate, the cover layer CVL may be attached to the filling layer FIL. In this case, the filling layer FIL may be used to adhere the cover layer CVL. When the cover layer CVL is a glass substrate, the cover layer CVL may be used as a packaging substrate. When the cover layer CVL is a resin such as a polymer resin, the cover layer CVL may be directly applied to the filling layer FIL.

[0239] As described above, when the refractive index of the lens LNS is 1.61 and the refractive index of the filling layer FIL is 1.51, the condition that the color gamut of the display device 10 can be improved and the thickness tk2 of the filling layer FIL can be minimized can be satisfied. In other words, when the refractive index of the lens LNS and the refractive index of the filling layer FIL are satisfied, the color gamut of the display device 10 can be improved even if the thickness tk2 of the filling layer FIL is thick. Therefore, the filling layer FIL can be formed to have a sufficient thickness so as not to cause an unfilled defect of the filling material, and a reduction in the color gamut of the display device 10 can be prevented. Here, the thickness tk2 (e.g., the maximum thickness) of the filling layer FIL can refer to the length of the filling layer FIL in the third direction DR3.

[0240] Fig.12 It is along Fig.10 1 is a cross-sectional view of a display device according to an exemplary embodiment taken along line II′.

[0241] Fig.12 The display device 10 and Fig.11 The display device 10 is different in that Fig.12 The display device 10 further includes a buffer layer BF, and this difference will be mainly described as follows.

[0242] like Fig.12 As shown in , the lens layer LSL may further include a buffer layer BF.

[0243] The buffer layer BF may be disposed between the plurality of lenses LNS and the filling layer FIL. In addition, the buffer layer BF may be disposed between adjacent lenses LNS. For example, the lens layer LSL may further include a buffer layer BF disposed between the plurality of lenses LNS and the filling layer FIL and between adjacent lenses LNS.

[0244] The buffer layer BF may have a high surface energy so that the spreadability of the filling layer FIL disposed thereon may be improved. For example, the buffer layer BF may have a surface energy of 60 mN / m or greater. The spreadability of the filling layer FIL may be improved by the buffer layer BF having such a high surface energy, and therefore, while keeping the thickness tk2 of the filling layer FIL low, the film density of the filling layer FIL may be improved. Therefore, even if the thickness tk2 of the filling layer FIL is low, the unfilled defect of the filling material of the filling layer FIL may be prevented. In addition, since the thickness tk2 of the filling layer FIL is reduced, the color gamut of the display device 10 may also be improved. Here, the thickness tk2 of the filling layer FIL may refer to the length of the filling layer FIL in the third direction DR3.

[0245] The buffer layer BF may have a refractive index of 1.4 to 1.7. For example, the buffer layer BF may have a refractive index of 1.4 to 1.7 at a wavelength of 550 nm.

[0246] The buffer layer BF may have a thickness less than When the buffer layer BF has a thickness less than When the thickness tk3 of the buffer layer BF is tk3, the buffer layer BF having the thickness tk3 may have a light transmittance of 85%. Here, the thickness tk3 of the buffer layer BF may refer to the length of the buffer layer BF in the third direction DR3.

[0247] The buffer layer BF may include, for example, SiO x 、SiN y or SiO x N y Here, x may be greater than or equal to 0 and less than or equal to 1. In addition, y may be greater than or equal to 0 and less than or equal to 1.

[0248] The buffer layer BF may be formed using a plasma enhanced chemical vapor deposition (PECVD) method. In this case, the temperature during the process of forming the buffer layer BF may be 70°C to 300°C.

[0249] When the refractive index of the lens LNS is 1.61, the refractive index of the filling layer FIL is 1.51, and the refractive index of the buffer layer BF is 1.4 to 1.7, the conditions that the color gamut of the display device 10 can be further improved and the thickness tk2 of the filling layer FIL can be minimized can be satisfied.

[0250] Fig.13 It is along Fig.10 1 is a cross-sectional view of a display device according to an exemplary embodiment taken along line II′.

[0251] Fig.13 The display device 10 and Fig.11 The display device 10 is different in that Fig.13 The display device 10 also includes a first buffer layer BF1 and a second buffer layer BF2, and the difference will be mainly described as follows.

[0252] The first buffer layer BF1 may be disposed between the first encapsulation inorganic film TFE1 and the encapsulation organic film TFE2. For example, the encapsulation layer ENC may further include a first buffer layer BF1 disposed between the first encapsulation inorganic film TFE1 and the encapsulation organic film TFE2.

[0253] The first buffer layer BF1 may have a refractive index of about 1.4 to about 1.7. The first buffer layer BF1 may have a high surface energy so that the spreadability of the encapsulating organic film TFE2 disposed thereon may be improved. For example, the first buffer layer BF1 may have a surface energy of 60 mN / m or more. The spreadability of the encapsulating organic film TFE2 may be improved by the first buffer layer BF1 having such a high surface energy, and thus, the film density of the encapsulating organic film TFE2 may be improved while keeping the thickness of the encapsulating organic film TFE2 low. The first buffer layer BF1 may have a surface energy of less than 100 mN / m. The thickness is tk4.

[0254] Since the second buffer layer BF2 is Fig.12 The buffer layer BF is the same as that of the second buffer layer BF2, so for the sake of brevity, the description of the second buffer layer BF2 is omitted.

[0255] Fig.14 is a view for describing the front light efficiency of a display device according to the refractive index of a filling layer and the cone angle of a lens.

[0256] exist Fig.14 , the horizontal axis means the cone angle θ of the lens LNS, and the vertical axis means the front light efficiency of the display device.

[0257] exist Fig.14 , the first curve CL1 represents the front light efficiency of the first display device 10_1 according to the cone angle θ of the lens LNS in the first display device 10_1 to which a filling layer FIL having a refractive index of 1.41 is applied, and the second curve CL2 represents the front light efficiency of the second display device 10_2 according to the cone angle θ of the lens LNS in the second display device 10_2 to which a filling layer FIL having a refractive index of 1.51 is applied.

[0258] Fig.14 The front light efficiency of the display device in refers to, for example, the front light efficiency of the display device for green light.

[0259] like Fig.14As shown in , when the cone angle θ of the lens LNS is about 40 degrees to about 60 degrees, it can be seen that the front light efficiency of the first display device 10_1 is better than the front light efficiency of the second display device 10_2. On the other hand, when the cone angle θ of the lens LNS is about 70 degrees, it can be seen that the front light efficiency of the second display device 10_2 is better than the front light efficiency of the first display device 10_1.

[0260] Fig.15 It is a view for describing the side light efficiency (or side brightness ratio) of a display device according to the refractive index of a filling layer and the cone angle of a lens.

[0261] exist Fig.15 , the horizontal axis means the cone angle θ of the lens, and the vertical axis means the side light efficiency of the display device.

[0262] exist Fig.15 , a first curve CL1 represents the side light efficiency (or side brightness ratio) of the first display device 10_1 according to the cone angle θ of the lens LNS in the first display device 10_1 to which a filling layer FIL having a refractive index of 1.41 is applied, and a second curve CL2 represents the side light efficiency (or side brightness ratio) of the second display device 10_2 according to the cone angle θ of the lens LNS in the second display device 10_2 to which a filling layer FIL having a refractive index of 1.51 is applied. Here, the side angle may be defined by an angle formed between a vertical line passing through the center of the screen of the display device and an oblique line passing through the center of the screen of the display device to form a specific angle with the vertical line passing through the center of the screen of the display device. For example, the angle formed by the center vertical line and the oblique line may be 35 degrees.

[0263] Fig.15 The side light efficiency of the display device in the embodiment means, for example, the side light efficiency of the display device for green light.

[0264] like Fig.15 As shown in , when the cone angle θ of the lens LNS is about 40 degrees to about 60 degrees, it can be seen that the side light efficiency of the second display device 10_2 is better than the side light efficiency of the first display device 10_1. On the other hand, when the cone angle θ of the lens LNS is about 70 degrees, it can be seen that the side light efficiency of the first display device 10_1 is substantially the same as the side light efficiency of the second display device 10_2.

[0265] Fig.16 It is a view for describing the front chromatic aberration of a display device according to the refractive index of a filling layer and the cone angle of a lens.

[0266] exist Fig.16 , the horizontal axis means the cone angle θ of the lens LNS, and the vertical axis means the front chromatic aberration of the display device.

[0267] exist Fig.16 , the first curve CL1 represents the front chromatic aberration of the first display device 10_1 according to the cone angle θ of the lens LNS in the first display device 10_1 to which a filling layer FIL having a refractive index of 1.41 is applied, and the second curve CL2 represents the front chromatic aberration of the second display device 10_2 according to the cone angle θ of the lens LNS in the second display device 10_2 to which a filling layer FIL having a refractive index of 1.51 is applied.

[0268] Fig.16 The front chromatic aberration of the display device in the context means, for example, the front chromatic aberration of the display device with respect to green light.

[0269] like Fig.16 As shown in , it can be seen that the front chromatic aberration of the second display device 10_2 is lower than the front chromatic aberration of the first display device 10_1 regardless of the cone angle θ of the lens LNS. In other words, it can be seen that the color gamut of the second display device 10_2 is better than the color gamut of the first display device 10_1.

[0270] Fig.17 It is a view for describing the lateral chromatic aberration of a display device according to the refractive index of a filling layer and the cone angle of a lens.

[0271] exist Fig.17 , the horizontal axis means the cone angle θ of the lens LNS, and the vertical axis means the lateral chromatic aberration of the display device.

[0272] exist Fig.17 , a first curve CL1 represents the lateral chromatic aberration of the first display device 10_1 according to the cone angle θ of the lens LNS in the first display device 10_1 to which a filling layer FIL having a refractive index of 1.41 is applied, and a second curve CL2 represents the lateral chromatic aberration of the second display device 10_2 according to the cone angle θ of the lens LNS in the second display device 10_2 to which a filling layer FIL having a refractive index of 1.51 is applied. Here, the side angle may be defined by an angle formed between a vertical line passing through the center of the screen of the display device and an oblique line passing through the center of the screen to form a specific angle with the vertical line. For example, the angle formed by the central vertical line and the oblique line may be 35 degrees.

[0273] Fig.17 The lateral chromatic aberration of the display device in the invention means, for example, the lateral chromatic aberration of the display device with respect to green light.

[0274] like Fig.17 As shown in , it can be seen that the side chromatic aberration of the second display device 10_2 is lower than the side chromatic aberration of the first display device 10_1 regardless of the cone angle θ of the lens LNS. In other words, it can be seen that the color gamut of the second display device 10_2 is better than the color gamut of the first display device 10_1.

[0275] Although some example embodiments of the present disclosure have been described above, these are merely examples and do not limit the present disclosure. In addition, without departing from the features of the present disclosure, those skilled in the art may change and modify the present disclosure in various ways. For example, the components described in the example embodiments of the present disclosure may be modified. Differences associated with these modifications and applications should be interpreted as being within the scope of the present disclosure as defined by the claims.

Claims

1. A display device, comprising: substrate; A transistor, disposed on the substrate; a pixel electrode connected to the transistor; A light-emitting layer is arranged on the pixel electrode; A common electrode is disposed on the light-emitting layer; A first color filter is disposed on the common electrode; a lens, disposed on the first color filter; as well as A filling layer is arranged on the lens, Wherein, the first color filter and the lens are in direct contact with each other.

2. The display device according to claim 1, wherein: The difference between the refractive index of the lens and the refractive index of the filling layer is 0.1 to 0.

2.

3. The display device according to claim 1, wherein: The refractive index of the lens is greater than the refractive index of the filling layer.

4. The display device according to claim 1, wherein: The lens has a refractive index of 1.

61.

5. The display device according to claim 1, wherein: The lens has a cone angle of 60 to 70 degrees.

6. The display device according to claim 1, wherein: The lens has a thickness of less than 1.5 μm.

7. The display device according to claim 1, wherein: The distance between adjacent lenses is greater than or equal to 0.3 μm.

8. The display device according to claim 1, wherein: The filling layer has a refractive index of 1.41 to 1.

51.

9. The display device according to claim 1, wherein: The filling layer includes epoxy resin.

10. The display device according to claim 1, wherein: The filling layer had a thickness of 3 μm. 11 . The display device according to claim 1 , further comprising a second buffer layer, wherein the second buffer layer is disposed between the lens and the filling layer.

12. The display device according to claim 11, wherein: The second buffer layer has a refractive index of 1.4 to 1.

7.

13. The display device according to claim 11, wherein: The second buffer layer has a thickness less than Thickness.

14. The display device according to claim 11, wherein: The second buffer layer has a surface energy greater than or equal to 60 mN / m.

15. The display device according to claim 11, wherein: The second buffer layer includes SiO x N y . 16 . The display device of claim 1 , further comprising an encapsulation layer disposed between the common electrode and the first color filter.

17. The display device according to claim 16, wherein: The encapsulation layer includes at least one inorganic film and at least one organic film disposed at different layers.

18. The display device according to claim 17, wherein: The encapsulation layer further includes a first buffer layer disposed between the at least one inorganic film and the at least one organic film of the encapsulation layer.

19. The display device according to claim 18, wherein: The first buffer layer has a refractive index of 1.4 to 1.

7. 20 . The display device of claim 1 , further comprising a second color filter disposed adjacent to the first color filter and overlapping the first color filter in a plan view.

21. The display device according to claim 20, wherein: The thickness of the overlapping portion of the first color filter and the second color filter is equal to the thickness of the lens.

22. The display device according to claim 20, wherein: A width of an overlapping portion of the first color filter and the second color filter is less than or equal to 0.2 μm.

23. A display device, comprising: substrate; A transistor, disposed on the substrate; a pixel electrode connected to the transistor; A light-emitting layer is arranged on the pixel electrode; A common electrode is disposed on the light-emitting layer; a color filter, disposed on the common electrode; A lens, disposed on the color filter; as well as A filling layer is arranged on the lens, Wherein, the filling layer has a refractive index of 1.41 to 1.

51.

24. The display device according to claim 23, wherein: The difference between the refractive index of the lens and the refractive index of the filling layer is 0.1 to 0.

2.

25. The display device according to claim 23, wherein: The refractive index of the lens is greater than the refractive index of the filling layer.

26. The display device according to claim 23, wherein: The lens has a refractive index of 1.

61.

27. The display device according to claim 23, wherein: The lens has a cone angle of 60 to 70 degrees.

28. The display device according to claim 23, wherein: The color filter and the lens are in direct contact with each other.

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