Edge computing device and method and internet of things system

Abstract

The invention provides an edge computing device and method and an Internet of Things system, the edge computing device comprises a processing unit and a programmable logic unit, the programmable logic unit comprises a first memory, a second memory, an instruction distribution module and a data acquisition module, the processing unit receives an instruction from a cloud, writes the instruction into the first memory, and transmits the instruction to the second memory; reading data from the field device from the second memory, and sending the data to the cloud; the instruction distribution module reads an instruction from the first memory and sends the instruction to the field device, and the data acquisition module acquires data of the field device and stores the data in the second memory; wherein the programmable logic unit generates a first time base signal and a second time base signal, the instruction distribution module designs a first state machine, the data acquisition module designs a second state machine, and the processing unit, the first memory and the instruction distribution module realize instruction distribution based on the first time base signal and the first state machine; and the processing unit, the second memory and the data acquisition module realize data transmission based on the second time base signal and the second state machine.

Description

Edge computing device, method, and Internet of Things system Technical Field

[0001] The present application relates to the field of Internet of Things technology, and in particular to an edge computing device, method, and Internet of Things system. Background Art

[0002] With the development of IoT (Internet of Things) technology, all physical objects are eager to connect to the internet. Research on remote control and data analysis applications for IoT field devices (i.e., physical objects) is becoming increasingly extensive and in-depth. Physical objects are typically sensed and processed by microcontrollers (MCUs), which are used to implement user control, data collection, and data processing. To achieve the Internet of Everything, multiple MCU-based sensing and processing units need to be connected together to form an organic grid system. If thousands of MCU-based IoT field device units are connected and combined to form a system, it will be difficult for users to obtain the status of IoT field devices and interact with specific IoT field device units through thousands of MCU chips. This direct connection between users and multiple field devices presents users with a massive amount of raw data, and the collection, processing, and interaction processes pose a significant challenge to communication and computing resources.

[0003] Summary of the Invention

[0004] A brief overview of the present invention is provided below to provide a basic understanding of certain aspects of the present invention. It should be understood that this overview is not an exhaustive overview of the present invention. It is not intended to identify key or important aspects of the present invention, nor is it intended to limit the scope of the present invention. Its purpose is simply to present certain concepts in a simplified form as a prelude to the more detailed description discussed later.

[0005] In view of this, the present disclosure provides an edge computing device that can conveniently enable user interaction with multiple on-site devices.

[0006] According to a first aspect of an embodiment of the present application, an edge computing device is provided, comprising a processing unit and a programmable logic unit, wherein the programmable logic unit comprises a first memory, a second memory, an instruction distribution module and a data acquisition module,

[0007] The processing unit receives instructions from the cloud and writes the instructions into the first memory, and reads data from the field device from the second memory and sends the data to the cloud;

[0008] The instruction distribution module reads the instruction from the first memory and sends the instruction to the corresponding field device, and the data acquisition module acquires data from the field device and stores the data in the second memory;

[0009] In which, the programmable logic unit generates a periodic first time base signal and a second time base signal respectively, a first state machine is designed in the instruction distribution module, and a second state machine is designed in the data acquisition module. In the downlink direction, the processing unit, the first memory and the instruction distribution module realize downlink instruction distribution based on the first time base signal and the first state machine; in the uplink direction, the processing unit, the second memory and the data acquisition module realize uplink data transmission based on the second time base signal and the second state machine.

[0010] This approach allows multiple field devices to be connected to the cloud service, and status information can be collected from all of them. Furthermore, user commands from the cloud or any other cloud-connected device can be sent to specific field devices, enabling user interaction with multiple field devices. By using two memories and designing a state machine in each of the command distribution module and data acquisition module, simultaneous uplink and downlink data transmission is possible.

[0011] Optionally, in an example of the above aspect, starting from each falling edge of the first time base signal, the processing unit starts to write instructions from the cloud into the first memory, and the write operation ends at a certain moment of the low level of the current cycle of the first time base signal. During this process, the first state machine of the instruction distribution module is in an idle state; at the next rising edge of the first time base signal, the instruction distribution module starts to read the instructions from the first memory and cache the instructions in the first cache, and the first state machine is in a reading state; then, the instruction distribution module distributes the instructions cached in the first cache to the corresponding field devices in sequence, and the first state machine is in a distribution state; after all instructions are distributed, the state machine enters an idle state and waits to enter the reading state of the next cycle.

[0012] Optionally, in an example of the above aspect, at each rising edge of the second time base signal, the processing unit starts to read the data of the previous cycle from the second memory, and the reading operation ends at a certain moment of the high level of the current cycle, and the processing unit sends the data to the cloud; during this high level period, the data acquisition module collects data from all field devices and stores the data in the second buffer, and the second state machine is in the data acquisition state; starting from the falling edge of the high level period of the second time base signal, the data acquisition module writes the data cached in the second buffer to the second memory, and the second state machine is in the data writing state; after the write operation ends, the second state machine enters the idle state and waits to enter the data acquisition state of the next cycle.

[0013] In this way, the state machine design enables the processing unit and the programmable logic unit to alternately access the memory under the control of a time-base signal. The time-base signal is user-configurable, allowing the edge device's status data and user instructions from the cloud to be transmitted at a configurable update rate.

[0014] Optionally, in an example of the above aspect, the first time base signal and the second time base signal are periodic square wave signals, and the periods of the first time base signal and the second time base signal are equal or unequal.

[0015] Optionally, in an example of the above aspect, the periods of the first time base signal and the second time base signal are determined according to the update frequency and data volume requirements of the instructions and the data, respectively.

[0016] In this way, the time-based signal is user-configurable, which enables the status data of the edge device and user instructions from the cloud to be transmitted at the configured update rate.

[0017] Optionally, in an example of the above aspect, the processing unit communicates with the cloud through the Internet of Things main control unit.

[0018] Optionally, in an example of the above aspect, the Internet of Things main control unit communicates with the cloud via the MQTT protocol.

[0019] In this way, users can access, analyze and control a large number of field devices through the cloud.

[0020] Optionally, in an example of the above aspect, the first memory and the second memory are dual-port block memories.

[0021] According to a second aspect of an embodiment of the present application, an edge computing method is provided, including:

[0022] In the downlink direction, receiving instructions from the cloud and writing the instructions into a first memory, reading the instructions from the first memory, and sending the instructions to a corresponding field device;

[0023] In the uplink direction, collecting data from the field device and storing the data in a second memory, reading data from the field device from the second memory and sending the data to the cloud,

[0024] Wherein, in the downlink direction, downlink instruction distribution is implemented based on the first time base signal and the first state machine; in the uplink direction, uplink data transmission is implemented based on the second time base signal and the second state machine.

[0025] According to a third aspect of an embodiment of the present application, there is provided an Internet of Things system, comprising: a cloud, a field device, and the edge computing device as described above;

[0026] Wherein, the cloud and the field device communicate via the edge computing.

[0027] As can be seen from the above technical solution, the edge computing device of the present disclosure can preprocess data collected by field devices. The edge computing device includes both a serial computing structure, namely a processing unit, and a parallel computing structure, namely a programmable logic unit. The processing unit is specialized for serial calculations, such as multiplication and accumulation; the programmable logic unit is specialized for parallel calculations, such as multi-stage pipeline calculations. This allows for the rational allocation and utilization of computing resources based on different real-time and latency requirements, resulting in optimal processing of collected data. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] FIG1 is a schematic diagram of an Internet of Things system according to an embodiment of the present disclosure;

[0029] FIG2 is a block diagram of an exemplary configuration of an edge computing device according to an embodiment of the present disclosure;

[0030] FIG3 shows a timing diagram of an instruction distribution mechanism of an instruction distribution module in an edge computing device according to an embodiment of the present disclosure;

[0031] FIG4 shows a timing diagram of a data acquisition mechanism of a data acquisition module in an edge computing device according to an embodiment of the present disclosure;

[0032] FIG5 is a schematic diagram of memory allocation of a first memory according to an embodiment of the present disclosure;

[0033] FIG6 is a schematic diagram of memory allocation of a first memory according to another embodiment of the present disclosure;

[0034] FIG7 is a schematic diagram of memory allocation of a second memory according to an embodiment of the present disclosure;

[0035] FIG8 is a schematic diagram of memory allocation of a second memory according to another embodiment of the present disclosure;

[0036] FIG9 is a flowchart of an exemplary process of an edge computing method 900 according to an embodiment of the present disclosure.

[0037] List of reference numerals:

[0038] 100: IoT System 102: Cloud 200: Edge Computing Devices

[0039] 104: Field device 106: IoT control unit 108: Communication interface

[0040] PS: Processing unit PL: Programmable logic unit BRAM1: First memory

[0041] BRAM2: Second memory CD: Command distribution module DC: Data acquisition module

[0042] TB1: First time base signal TB2: Second time base signal SM1: First state machine

[0043] SM2: Second state machine Idle: Idle state RE: Rising edge

[0044] Read: Read status Push: Distribute status FE: Falling edge

[0045] Written: write status Offset: offset Offset0-Offset9: offset address

[0046] Content: Command content C0, C1...: Converter 0, C01, C02...: Command

[0047] Converter 1

[0048] ID 0-ID9: Identifiers U0, U1...: Field devices U01, U02,...U15...: Commands

[0049] Collect: Collection status 900: Edge computing method S902, S904: Steps DETAILED DESCRIPTION

[0050] In order to enable those skilled in the art to better understand the technical solutions in the embodiments of the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the embodiments of the present application, all other embodiments obtained by ordinary technicians in this field should fall within the scope of protection of the embodiments of the present application.

[0051] MCU chips are usually used to control and process data from sensors, thereby producing an MCU-based IoT field device unit, such as an intelligent sensor unit (Daniel Sygnat, Johannes Baumer, Cost improved intelligent sensor, US20210123176), a fault detection unit (Fang Z, Huang Z, Zhu Y, Detector temperature control and fault detection system, CN112965550-A), a vehicle speed detection unit (Sumit Jaiswal, Rajiv Chithambaran, Intelligent transportation system, host processor vehicle and method thereof, US20180069724 A1), and a power conversion unit (Hayashi Y, Power conversion device, US11063526 B2).

[0052] To build the IoT systems currently under extensive research, multiple MCU-based IoT field device units are combined or cascaded together to form a massive network. For example, smart sensor units are combined to create a smart furniture system; fault detection units are combined to create a maintenance system; speed detection units are combined to create an intelligent transportation system; and power converter units are combined and cascaded to create a smart grid system. When thousands of MCU-based units are combined and cascaded together, the raw status data becomes increasingly large. Cloud computing is a reasonable method for processing this massive amount of data. Although each unit has an MCU as its own controller, it is not practical to use all MCUs as edge computing nodes.

[0053] To establish an IoT system that can handle multiple MCU-based sensing and processing units, the present disclosure proposes an edge computing device that can interact with multiple IoT field device units. On the one hand, status data from multiple units can be collected, pre-processed, and sent to the cloud for processing; on the other hand, users can send instructions to specific units through the cloud. In the following description, the MCU-based IoT field device unit is referred to as a field device. The field device uses an MCU as a controller to collect field data. For example, the field device can be various sensors, power converters, etc.

[0054] The edge computing device and the Internet of Things system according to the embodiments of the present disclosure will be described below with reference to the accompanying drawings.

[0055] FIG1 is a schematic diagram of an Internet of Things system according to an embodiment of the present disclosure.

[0056] As shown in Figure 1, the Internet of Things system 100 includes a cloud 102, an edge computing device 200, and multiple field devices 104. The cloud 102 and the edge computing device 200 can communicate through the Internet of Things control unit 106, and the edge computing device 200 and the field devices 104 can communicate through the communication interface 108.

[0057] Specifically, the IoT control unit 106 may receive user instructions from the cloud 102 via the MQTT (Message Queuing Telemetry Transport) protocol, and send the instructions to the edge computing device 200 via the SPI (Serial Peripheral Interface) protocol or any other inter-chip communication protocol.

[0058] User instructions may come from the cloud or other user terminal devices connected to the cloud, such as smartphones, tablets, etc.

[0059] The communication interface 108 between the edge computing device 200 and the field device 104 can be encoded and decoded using different communication methods such as optical fiber communication, Bluetooth communication, and wireless communication.

[0060] The edge computing device 200 can be viewed as a bridge between the cloud 102 and multiple field devices 104. The core tasks of the edge computing device include command transmission, data acquisition, and data preprocessing. The structure and operation of the edge computing device 200 will be described in detail below with reference to FIG2.

[0061] FIG2 is a block diagram of an exemplary configuration of an edge computing device 200 according to an embodiment of the present disclosure.

[0062] As shown in FIG2 , the edge computing device 200 includes a processing unit PS and a programmable logic unit PL.

[0063] The main component of the processing unit PS is a CPU, and the processing unit mainly performs serial calculations.

[0064] The programmable logic unit (PL) is implemented using a programmable logic device (PL), such as an FPGA, CPLD, or HDPLD. Those skilled in the art can select an appropriate type of device as needed. The technical solution disclosed herein is not limited to the specific type of programmable logic device. The programmable logic unit (PL) is primarily used for parallel computing.

[0065] The programmable logic unit PL includes a first memory BRAM1, a second memory BRAM2, a command distribution module CD and a data acquisition module DC.

[0066] The processing unit PS is used to receive instructions from the cloud 102 and write the instructions into the first memory BRAM1 . The instruction distribution module CD reads instructions from the first memory BRAM1 and sends the instructions to the corresponding field device 104 .

[0067] On the other hand, the data acquisition module DC acquires data from the field device 104 and stores the data in the second memory BRAM2 ; the processing unit PS reads data from the field device 104 from the second memory BRAM2 and sends the data to the cloud 102 .

[0068] Specifically, the CPU in the processing unit PS reads data from the second memory BRAM2 at a fixed frequency, so that the processing unit can send the data to the Internet of Things control unit through the SPI communication protocol or any other inter-chip communication protocol at a specific frequency, and then the Internet of Things control unit can send the data of all field devices to the cloud through the MQTT protocol.

[0069] The programmable logic unit PL generates a periodic first time base signal TB1 and a second time base signal TB2 respectively, a first state machine SM1 is designed in the instruction distribution module CD, and a second state machine SM2 is designed in the data acquisition module DC. In the downlink direction, the processing unit PS, the first memory BRAM1 and the instruction distribution module CD realize downlink instruction distribution based on the first time base signal TB1 and the first state machine SM1; in the uplink direction, the processing unit PS, the second memory BRAM2 and the data acquisition module DC realize uplink data transmission based on the second time base signal TB2 and the second state machine SM2.

[0070] The first memory and the second memory may be dual-port block memories, or any other memories capable of reading and writing.

[0071] FIG3 shows a timing diagram of an instruction distribution mechanism in an instruction distribution module CD of an edge computing device according to an embodiment of the present disclosure.

[0072] As described above, the processing unit PS, the first memory BRAM1 and the instruction distribution module CD implement downlink instruction distribution based on the first time base signal TB1 and the first state machine SM1.

[0073] Specifically, starting from each falling edge FE of the first time base signal TB1, the processing unit PS starts to write the instructions from the cloud 102 into the first memory BRAM1, and the write operation ends at a certain moment of the low level of the current cycle of the first time base signal TB1. During this process, the first state machine SM1 of the instruction distribution module CD is in the idle state Idle; at the next rising edge RE of the first time base signal TB1, the instruction distribution module CD starts to read the instructions from the first memory BRAM1 and cache the instructions in a first buffer (not shown in the figure), and the first state machine SM1 is in the reading state Read; then, the instruction distribution module CD distributes the instructions cached in the first buffer to the corresponding field devices in sequence, and the first state machine SM1 is in the distribution state Push; after all instructions are distributed, the first state machine SM1 enters the idle state Idle and waits to enter the reading state of the next cycle.

[0074] In this process, the instruction distribution module CD cyclically distributes instructions from the cloud to each field device at the cycle of the first time base signal TB1. The user can set the appropriate cycle of the first time base signal TB1 to set the frequency of instruction distribution as needed.

[0075] FIG4 shows a timing diagram of the data acquisition mechanism in the data acquisition module DC.

[0076] As described above, the processing unit PS, the second memory BRAM2 and the data acquisition module DC implement uplink data transmission based on the second time base signal TB2 and the second state machine SM2.

[0077] Specifically, at each rising edge RE of the second time base signal TB2, the processing unit PS starts to read the data of the previous cycle from the second memory BRAM2, and the reading operation ends at a certain moment of the high level of the current cycle, and the processing unit PS sends the data to the cloud; during this high level period, the data acquisition module DC collects data from all field devices and caches the data in a second buffer (not shown in the figure), and the second state machine SM2 is in the data acquisition state Collect; starting from the falling edge FE of the high level period of the second time base signal TB2, the data acquisition module DC writes the data cached in the second buffer to the second memory BRAM2, and the second state machine SM2 is in the data writing state Written; after the write operation is completed, the second state machine enters the idle state Idle, and waits to enter the data acquisition state of the next cycle.

[0078] During this process, the data acquisition module DC cycles through data collection from various field devices, based on the period of the second timebase signal TB2. Users can adjust the data update frequency by setting an appropriate period of the second timebase signal TB2 based on the amount of data from the field devices. The period of the second timebase signal TB2 can be equal to or different from the period of the first timebase signal TB1.

[0079] FIG5 takes the field device being a power converter as an example to illustrate how to distribute and store instructions from the cloud in the first memory.

[0080] For example, the field device is a plurality of power converters, each power converter has two stages, the first stage is an NPC (neutral point clamping) structure for realizing AC-DC function, and the second stage is a CLLC (two inductors and two capacitors) structure for realizing DC-DC function. The instruction content Content for converter 0C0 is stored in the address Offset0-Offset4 with a bias Offset of 0-4, the instruction content Content for converter 1C1 is stored in the address Offset5-Offset9 with a bias Offset of 5-9, and the instruction content Content for converter 2 can be stored in the address Offset10-Offset14 with a bias Offset of 10-14 (not shown in the figure), and so on. For converter C0, the first instruction C01 of converter C0 represents an NPC instruction, including information such as NPC control mode, reset signal, enable signal, pre-charge instruction, voltage setting, etc. The second instruction C02 is a CLLC instruction, including information such as CLLC control module, power flow direction, enable signal, voltage setting, current setting, etc. The next three addresses are reserved for future use, such as instructions for other architectures besides NPC and CLLC. Each instruction has a corresponding identifier, ID 0-ID 4, to indicate the instruction data. The same applies to instructions for other converters.

[0081] FIG. 6 shows a memory allocation mechanism in the first memory for a general field device.

[0082] Figure 6 is similar to Figure 5. Offset0-Offset9... represent offset addresses, and U0, U1... represent field devices. All field device instructions (U01, U02, ..., U15...) are arranged one after another in the memory address space. Each field device has a fixed address span. For example, the address span in Figure 6 is 5, but it can be configured to any other length depending on the number of user instructions. Within each address span, the first, second, third, and so on, instructions for a field device are arranged sequentially within that address span.

[0083] Those skilled in the art will appreciate that the memory allocation method shown in FIG. 6 can be used for any type of field device to store instructions for each field device, which will not be described in detail here.

[0084] FIG7 is an example of a field device being a power converter to illustrate how the data collected from the power converter is distributed and stored in the second memory. Similarly, the AC-DC and DC-DC conversion of the power converter with an NPC and CLLC two-stage structure is taken as an example. The status data of converter 0C0 is stored in the addresses Offset0-Offset9 with a bias of 0-9, the status data of converter 1C1 is stored in the addresses Offset0-Offset9 with a bias of 10-19, and the status data of converter 2 is stored in the addresses with a bias of 20-29 (not shown in the figure), and so on. For each converter, NPC status data includes DC voltage value, active current value, passive current value, error code, output vector, etc., which are stored in the addresses whose data are identified as ID0, ID1, ID2 and ID3. CLLC status data includes DC voltage value, high-voltage side current, low-voltage side current, error state, etc., which are stored in the addresses whose data are identified as ID4, ID5, ID6 and ID7. For each converter, the addresses identified as data ID8 and ID9 are reserved for future use by structures other than NPC and CLLC.

[0085] Those skilled in the art will appreciate that the field device may be any type of field device. FIG8 shows a memory allocation mechanism in the second memory for a general field device.

[0086] Figure 8 is similar to Figure 7. Offset0-Offset19... represent offset addresses, and U0, U1... represent field devices. All field device instructions (U01, U02, ..., U19...) are arranged one after another in the memory address space. Each field device has a fixed address span. For example, the address span in Figure 8 is 10. Users can configure the address span to any other length based on the amount of data collected by the field device. Each field device can include multiple sensed parameters, and each parameter can have multiple status values. All of this status data is sequentially arranged within a single address span.

[0087] Those skilled in the art will appreciate that the memory allocation method shown in FIG. 8 can be used for any type of field device to store data from each field device, which will not be described in detail here.

[0088] In the process of describing the edge computing device in the embodiment above, it is obvious that some processing or methods are also disclosed. Below, an overview of these methods is given without repeating some of the details discussed above. However, it should be noted that although these methods are disclosed in the process of describing the edge computing device, these methods do not necessarily adopt the above-mentioned components, or are not necessarily performed by these components. For example, the embodiment of the edge computing device can be partially or completely implemented by hardware and / or firmware, and the edge computing methods discussed below can also be fully implemented by computer executable programs, although these methods can also adopt the hardware and / or firmware of the data relay device.

[0089] FIG9 is a flowchart of an exemplary process of an edge computing method 900 according to an embodiment of the present disclosure.

[0090] First, in box S902 , in the downlink direction, an instruction is received from the cloud 102 and written into the first memory BRAM1 , the instruction is read from the first memory BRAM1 , and the instruction is sent to the corresponding field device 104 .

[0091] Next, in block S904 , in the uplink direction, data of the field device 104 is collected and stored in the second memory BRAM2 , data from the field device 104 is read from the second memory BRAM2 , and the data is sent to the cloud 102 .

[0092] In the downlink direction, downlink instruction distribution is implemented based on the first time base signal TB1 and the first state machine SM1; in the uplink direction, uplink data transmission is implemented based on the second time base signal TB2 and the second state machine SM2.

[0093] Here, the first time base signal and the second time base signal as well as the first state machine and the second state machine may be generated by a programmable logic controller for the downlink and the uplink, respectively.

[0094] Specifically, implementing downlink instruction distribution based on the first time base signal TB1 and the first state machine SM1 includes:

[0095] From each falling edge of the first time base signal TB1, the instructions from the cloud 102 are written into the first memory BRAM1, and the write operation ends at a certain moment of the low level of the current cycle of the first time base signal TB1. During this process, the first state machine SM1 is in the idle state Idle; at the next rising edge of the first time base signal TB1, the instructions are read from the first memory BRAM1 and cached in the first cache. The first state machine SM1 is in the read state Read; then, the instructions cached in the first cache are distributed to the corresponding field devices 104 in turn, and the first state machine SM1 is in the distribution state Push; after all the instructions are distributed, the first state machine enters the idle state Idle and waits to enter the read state Read of the next cycle.

[0096] Specifically, in the uplink direction, implementing uplink data transmission based on the second time base signal TB2 and the second state machine SM2 includes:

[0097] At each rising edge of the second time base signal TB2, data of the previous cycle is read from the second memory BRAM2, and the reading operation ends at a certain moment of the high level of the current cycle, and the data is sent to the cloud 102; during this high level period, data is collected from all field devices 104, and the data is stored in the second buffer, and the second state machine SM2 is in the data collection state Collect; starting from the falling edge of the high level period of the second time base signal TB2, the data cached in the second buffer is written to the second memory BRAM2, and the second state machine SM2 is in the data writing state Written; after the write operation is completed, the second state machine SM2 enters the idle state Idle, and waits to enter the data collection state Collect of the next cycle.

[0098] The specific operation process of the data relay method according to the present disclosure may be the same as or similar to the relevant parts of the embodiment of the edge computing device 200 of the present disclosure described with reference to Figures 1 to 8, and will not be described in detail here.

[0099] The edge computing device and method and the Internet of Things system according to the present disclosure have at least one or more of the following advantages.

[0100] According to the edge computing device disclosed herein, two dual-port block memories are used, and a state machine is designed in the instruction distribution module and the data acquisition module respectively, which can realize the simultaneous transmission of uplink and downlink data.

[0101] Two memories serve as data exchange media between the processing unit and the programmable logic unit. The processing unit is connected to the cloud via the IoT master control unit. This allows users to access, analyze, and control a large number of field devices through the cloud.

[0102] The edge computing device of the present disclosure can connect multiple field devices to a cloud service and collect status information from all field devices. At the same time, user instructions from the cloud or any other cloud-connected device can be sent to a specific field device, thereby enabling user interaction with multiple field devices.

[0103] The state machine design enables the processing unit and programmable logic unit to alternately access the memory under the control of a user-configurable timebase signal, which enables the edge device's status data and user instructions from the cloud to be transmitted at a configurable update rate.

[0104] According to the edge computing device disclosed in the present invention, data collected by field equipment can be preprocessed. The edge computing device includes both a serial computing structure, namely a processing unit, and a parallel computing structure, namely a programmable logic unit. The processing unit is specifically used for serial computing, such as multiplication and accumulation; the programmable logic unit is specifically used for parallel computing, such as pipeline computing. This allows computing resources to be reasonably allocated and utilized according to different needs, and optimal computing can be performed.

[0105] It should be noted that not all modules in the above device structure diagrams are required, and some modules can be omitted according to actual needs. The execution order of each operation is not fixed and can be adjusted as needed. The system structure described in the above embodiments can be a physical structure or a logical structure. That is, some modules may be implemented by the same physical entity, or some modules may be implemented by multiple physical entities, or may be implemented by certain components in multiple independent devices.

[0106] In the above embodiments, the hardware module can be implemented mechanically or electrically. For example, a hardware module can include a permanent dedicated circuit or logic (such as a dedicated processor, FPGA or ASIC) to complete the corresponding operation. The hardware module can also include programmable logic or circuits (such as a general-purpose processor or other programmable processors), which can be temporarily set by software to complete the corresponding operation. The specific implementation method (mechanical method, or dedicated permanent circuit, or temporarily set circuit) can be determined based on cost and time considerations.

[0107] The present application has been presented and described in detail above through the accompanying drawings and preferred embodiments. However, the present application is not limited to these disclosed embodiments. Based on the above multiple embodiments, those skilled in the art can know that the code review methods in the above different embodiments can be combined to obtain more embodiments of the present application, and these embodiments are also within the scope of protection of the present application.

Claims

1. An edge computing device (200), comprising a processing unit (PS) and a programmable logic unit (PL), wherein: The programmable logic unit (PL) includes a first memory (BRAM1), a second memory (BRAM2), a command distribution module (CD) and a data acquisition module (DC). The processing unit (PS) receives instructions from the cloud (102) and writes the instructions into the first memory (BRAM1), and reads data from the field device (104) from the second memory (BRAM2) and sends the data to the cloud (102); The instruction distribution module (CD) reads the instruction from the first memory (BRAM1) and sends the instruction to the corresponding field device (104); the data acquisition module (DC) acquires data from the field device (104) and stores the data in the second memory (BRAM2); The programmable logic unit (PL) generates a periodic first time base signal (TB1) and a second time base signal (TB2), respectively; a first state machine (SM1) is designed in the instruction distribution module (CD); and a second state machine (SM2) is designed in the data acquisition module (DC); in the downlink direction, the processing unit (PS), the first memory (BRAM1) and the instruction distribution module (CD) implement downlink instruction distribution based on the first time base signal (TB1) and the first state machine (SM1); in the uplink direction, the processing unit (PS), the second memory (BRAM2) and the data acquisition module (DC) implement uplink data transmission based on the second time base signal (TB2) and the second state machine (SM2).

2. The edge computing device (200) according to claim 1, wherein: Starting from each falling edge of the first time base signal (TB1), the processing unit (PS) starts to write the instructions from the cloud (102) into the first memory (BRAM1), and the write operation ends at a certain moment of the low level of the current cycle of the first time base signal (TB1). During this process, the first state machine (SM1) of the instruction distribution module (CD) is in an idle state (Idle); at the next rising edge of the first time base signal (TB1), the instruction distribution module (CD) starts to read the instructions from the first memory (BRAM1) and cache the instructions in the first cache, and the first state machine (SM1) is in a read state (Read); then, the instruction distribution module (CD) distributes the instructions cached in the first cache to the corresponding field devices (104) in sequence, and the first state machine (SM1) is in a distribution state (Push); after all instructions are distributed, the first state machine enters an idle state (Idle) and waits to enter the read state (Read) of the next cycle.

3. The edge computing device (200) according to claim 1, wherein: At each rising edge of the second time base signal (TB2), the processing unit (PS) starts to read the data of the previous cycle from the second memory (BRAM2), and the reading operation ends at a certain moment of the high level of the current cycle, and the processing unit (PS) sends the data to the cloud (102); during the high level period, the data acquisition module (DC) collects data from all field devices (104) and stores the data in the second buffer, and the second state machine (SM2) is in the data acquisition state (Collect); starting from the falling edge of the high level period of the second time base signal (TB2), the data acquisition module (DC) writes the data cached in the second buffer to the second memory (BRAM2), and the second state machine (SM2) is in the data writing state (Written); after the writing operation ends, the second state machine (SM2) enters the idle state (Idle) and waits to enter the data acquisition state (Collect) of the next cycle.

4. The edge computing device (200) according to any one of claims 1 to 3, wherein: The first time base signal (TB1) and the second time base signal (TB2) are periodic square wave signals, and the periods of the first time base signal (TB1) and the second time base signal (TB2) are equal or unequal.

5. The edge computing device (200) according to any one of claims 1 to 3, wherein: The periods of the first time base signal (TB1) and the second time base signal (TB2) are determined according to the update frequency and data volume requirements of the instructions and the data, respectively.

6. The edge computing device (200) according to any one of claims 1 to 3, wherein: The processing unit (PS) communicates with the cloud (102) via the Internet of Things main control unit (106).

7. The edge computing device (200) according to any one of claims 1 to 3, wherein: The Internet of Things main control unit (106) communicates with the cloud (102) via the MQTT protocol.

8. The edge computing device (200) according to any one of claims 1 to 3, wherein: The first memory (BRAM1) and the second memory (BRAM2) are dual-port block memories.

9. Edge computing methods, including: In the downlink direction, receiving instructions from the cloud (102), writing the instructions into the first memory (BRAM1), reading the instructions from the first memory (BRAM1), and sending the instructions to the corresponding field device (104); In the uplink direction, collecting data from the field device (104) and storing the data in a second memory (BRAM2), reading data from the field device (104) from the second memory (BRAM2), and sending the data to the cloud (102), In the downlink direction, downlink instruction distribution is realized based on the first time base signal (TB1) and the first state machine (SM1); in the uplink direction, uplink data transmission is realized based on the second time base signal (TB2) and the second state machine (SM2).

10. The edge computing method according to claim 9, wherein: Implementing downlink instruction distribution based on a first time base signal (TB1) and a first state machine (SM1) includes: From each falling edge of the first time base signal (TB1), the instructions from the cloud (102) are written into the first memory (BRAM1), and the writing operation ends at a certain moment of the low level of the current cycle of the first time base signal (TB1). During this process, the first state machine (SM1) is in an idle state (Idle); at the next rising edge of the first time base signal (TB1), the instructions are read from the first memory (BRAM1) and cached in the first cache, and the first state machine (SM1) is in a read state (Read); then, the instructions cached in the first cache are distributed to the corresponding field devices (104) in sequence, and the first state machine (SM1) is in a distribution state (Push); after all the instructions are distributed, the first state machine enters an idle state (Idle) and waits to enter the read state (Read) of the next cycle.

11. The edge computing method according to claim 9, wherein: In the uplink direction, implementing uplink data transmission based on the second time base signal (TB2) and the second state machine (SM2) includes: At each rising edge of the second time base signal (TB2), data of the previous cycle is read from the second memory (BRAM2), and the reading operation ends at a certain moment of the high level of the current cycle, and the data is sent to the cloud (102); during the high level period, data is collected from all field devices (104) and stored in the second buffer, and the second state machine (SM2) is in the data collection state (Collect); starting from the falling edge of the high level period of the second time base signal (TB2), the data cached in the second buffer is written to the second memory (BRAM2), and the second state machine (SM2) is in the data writing state (Written); after the writing operation ends, the second state machine (SM2) enters the idle state (Idle) and waits to enter the data collection state (Collect) of the next cycle.

12. The edge computing method according to any one of claims 9 to 11, wherein: The first time base signal (TB1) and the second time base signal (TB2) are periodic square wave signals, and the periods of the first time base signal (TB1) and the second time base signal (TB2) are equal or unequal.

13. The edge computing method according to any one of claims 9 to 11, wherein: The periods of the first time base signal (TB1) and the second time base signal (TB2) are determined according to the update frequency and data volume requirements of the instructions and the data, respectively.

14. An Internet of Things system (100), comprising: A cloud (102), a field device (104), and an edge computing device (200) as claimed in any one of claims 1 to 8, The cloud (102) and the field device (104) communicate via the edge computing device (200).

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