Method and device for automatically adjusting terminal resistance of test channel

Abstract

The invention belongs to the technical field of chip testing, and particularly discloses an automatic adjusting method and device for a terminal resistor of a test channel, and the method comprises the steps: when the resistance value of the terminal resistor in a CH test loop is an expected value, determining the resistance value of a parasitic resistor on a transmission line between an output pin of a DUT and the terminal resistor based on the pre-measured resistance value of the parasitic resistor on the transmission line between the output pin of the DUT and the terminal resistor; determining the magnitude and direction of PMU compensation current; and based on the determined magnitude and direction of the PMU compensation current, applying the PMU compensation current through a PMU current source connected in parallel with the terminal resistor, and adjusting the sensing value of the terminal resistor to be an expected value. According to the invention, the original PMU in the test equipment outputs the current with the proper size and direction, the effect that the load terminal resistance value which is perceived to be changed by the DUT is created, and the measurement error caused by parasitic resistance on a transmission line is eliminated through the PMU in the equipment under the condition that the cost is not increased, so that the measurement precision of the subsequent direct current test is improved.

Description

Technical Field

[0001] The present application belongs to the field of chip testing technology, and more specifically, relates to a method and device for automatically adjusting the terminal resistance of a test channel. Background Art

[0002] One of the many tests performed by Automatic Test Equipment (ATE) is to test the DC characteristics of the output channel (CH) of the device under test (DUT). DC testing means setting certain pins on the DUT to output static 0 or 1 and connecting the corresponding terminal resistors to test whether the DUT can output the appropriate voltage.

[0003] ATE must be very accurate, so the tolerances between thousands of CHs within the ATE under specified load conditions must also be very tight, and the tolerances between multiple ATE devices on the line must also be tight. If the load resistance of Device 1 and Device 2 is outside the baseline, then the test results of the same DUT on Device 1 and Device 2 may be different.

[0004] On the one hand, there are usually many parasitic resistors between the DUT output pin and the terminal resistor, and the terminal resistor itself also has errors, making it difficult to adjust the terminal resistor to the required value. On the other hand, when the ATE signal reception uses the terminal resistor in the chip (IC) instead of discrete resistors, it is more difficult to match the resistor accuracy.

[0005] A simple way to solve the above problem is to connect a variable resistor in parallel to compensate for the terminal resistance. By adjusting the variable resistor at the factory and measuring the resistance to match the resistance of the entire signal line to the expected value, the resistance change between CHs can be suppressed very accurately. However, this method is very cumbersome and time-consuming; it cannot be automated and cannot be measured and calibrated during regular maintenance during equipment operation.

[0006] Another problem arises when testing needs to be performed under different resistance conditions. For example, if testing needs to be performed under terminal resistance conditions of 110Ω, 100Ω, 90Ω, and 80Ω, the only way to deal with it is to use switches to install all resistors or install a variable resistor IC. Variable resistor ICs can create a wide range of resistance conditions, but due to the characteristics of the components, their accuracy is very low and it is difficult to achieve the accuracy requirements required by test equipment. Summary of the invention

[0007] In view of the defects existing in the related art, the embodiments of the present application provide a method and device for automatically adjusting the terminal resistance of a test channel, aiming to solve the problem in the related art that the terminal resistance of the test channel is difficult to meet the test requirements and accuracy of the test equipment.

[0008] In a first aspect, an embodiment of the present application provides a method for automatically adjusting the terminal resistance of a test channel, comprising:

[0009] When the resistance value of the terminal resistor in the CH test loop is an expected value, the magnitude and direction of the PMU compensation current are determined based on the resistance value of the parasitic resistance on the transmission line between the output pin of the DUT and the terminal resistor measured in advance;

[0010] Based on the determined magnitude and direction of the PMU compensation current, the PMU compensation current is applied through a PMU current source connected in parallel with the terminal resistor, and the sensed value of the terminal resistor is adjusted to a desired value.

[0011] In some embodiments, determining the magnitude and direction of the PMU compensation current includes:

[0012] Determine a first output voltage of the DUT when the terminal resistor is disconnected, and a second output voltage and a first output current of the DUT when the terminal resistor is connected;

[0013] Determining a resistance value of an output resistor of the DUT based on the first output voltage, the second output voltage, the first output current, and a resistance value of the parasitic resistor;

[0014] Based on the resistance value of the output resistor, determine the second output current when the resistance value of the equivalent terminal resistance external to the DUT in the CH test loop is an expected value; the resistance value of the equivalent terminal resistance is the sum of the resistance values ​​of the parasitic resistance and the terminal resistance in the CH test loop;

[0015] The magnitude and direction of the PMU compensation current are determined based on the first output current, the second output current, the parasitic resistance and the output resistance.

[0016] In some embodiments, determining a resistance value of an output resistor of a DUT includes:

[0017] Determine a first resistance value based on a difference between the first output voltage and the second output voltage, and the first output current;

[0018] The resistance value of the output resistor is determined based on the first resistance value and the resistance value of the parasitic resistor.

[0019] In some embodiments, the first resistance satisfies the following calculation formula:

[0020]

[0021] Where R1 represents the first resistance, R sRepresents the output resistance, R p represents the parasitic resistance, V1 represents the first output voltage, V2 represents the second output voltage, I real Represents the first output current.

[0022] In some embodiments, the second output current when the resistance of the equivalent terminal resistance external to the DUT in the CH test loop is an expected value satisfies the following calculation formula:

[0023]

[0024] Among them, I ideal Represents the second output current, V high and V low Respectively represent the high and low levels of the positive and negative electrodes of the DUT, R real represents the expected value, R s Represents the output resistance.

[0025] In some embodiments, the magnitude of the PMU compensation current is determined to satisfy the following calculation formula:

[0026]

[0027] Among them, I cal Indicates the PMU compensation current, I ideal Represents the second output current, I real represents the first output current, R s Represents the output resistance, R p Represents parasitic resistance, R real Indicates expected value.

[0028] In some embodiments, determining the direction of the PMU compensation current includes:

[0029] When I cal When it is a positive value, it is determined that the direction of the PMU compensation current is opposite to the direction of the current passing through the terminal resistor;

[0030] When I cal When it is a negative value, it is determined that the direction of the PMU compensation current is the same as the direction of the current passing through the terminal resistor.

[0031] In a second aspect, an embodiment of the present application further provides an automatic adjustment device for a terminal resistance of a test channel, comprising:

[0032] A first determining unit, configured to determine the magnitude and direction of the PMU compensation current based on the resistance value of the parasitic resistance on the transmission line between the output pin of the DUT and the terminal resistor measured in advance when the resistance value of the terminal resistor in the CH test loop is an expected value;

[0033] The second determining unit is configured to apply the PMU compensation current through a PMU current source connected in parallel with the terminal resistor based on the determined magnitude and direction of the PMU compensation current, so as to adjust the sensed value of the terminal resistor to the expected value.

[0034] In a third aspect, an embodiment of the present application further provides an electronic device, comprising: at least one memory for storing programs; and at least one processor for executing the programs stored in the memory. When the program stored in the memory is executed, the processor is used to execute the method described in the first aspect or any possible implementation of the first aspect.

[0035] In a fourth aspect, an embodiment of the present application further provides a computer-readable storage medium, which stores a computer program. When the computer program runs on a processor, the processor executes the method described in the first aspect or any possible implementation of the first aspect.

[0036] In a fifth aspect, an embodiment of the present application further provides a computer program product, which, when executed on a processor, enables the processor to execute the method described in the first aspect or any possible implementation of the first aspect.

[0037] The method and device for automatically adjusting the terminal resistance of the test channel provided in the embodiment of the present application output a current of appropriate size and direction through the original PMU in the test equipment, thereby creating an effect of a load terminal resistance value that is sensed by the DUT as a change, and eliminating the measurement error caused by parasitic resistance on the transmission line through the PMU in the equipment without increasing the cost, thereby improving the measurement accuracy of subsequent DC tests. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] In order to more clearly illustrate the technical solutions in the present application or related technologies, the following is a brief introduction to the drawings required for use in the embodiments or related technical descriptions. Obviously, the drawings described below are some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0039] Figure 1 It is a schematic diagram of a CH test circuit under an ideal state provided by an embodiment of the present application;

[0040] Figure 2 This is one of the flow charts of the method for automatically adjusting the terminal resistance of the test channel provided in the embodiment of the present application;

[0041] Figure 3 is a schematic diagram of a flow chart for determining the magnitude and direction of a PMU compensation current provided in an embodiment of the present application;

[0042] Figure 4 Schematic diagram of a CH test loop with parasitic resistance provided in an embodiment of the present application;

[0043] Figure 5 This is a second flow chart of a method for determining a compensation current of a channel terminal resistance provided in an embodiment of the present application;

[0044] Figure 6 1 is a schematic diagram of a CH test circuit when the DUT external equivalent terminal resistance is 100Ω provided in an embodiment of the present application;

[0045] Figure 7 Schematic diagram of a CH test loop for applying compensation current to a PMU provided in an embodiment of the present application;

[0046] Figure 8 It is a schematic diagram of a CH test circuit in which the terminal resistance of the test channel can be automatically adjusted provided in an embodiment of the present application;

[0047] Fig. 9 is a schematic diagram of the structure of an automatic adjustment device for the terminal resistance of a test channel provided in an embodiment of the present application;

[0048] Fig.10 It is a schematic diagram of the structure of an electronic device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0049] In order to make the purpose, technical solution and advantages of the present application more clearly understood, the present application is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and are not used to limit the present application.

[0050] Figure 1 Schematic diagram of the CH test circuit under the ideal state provided by the embodiment of the present application, such as Figure 1 As shown in the figure, in the DC test, the positive electrode of the DUT is set to a high level and the negative electrode is set to a low level. The output voltage is read using the PMU without connecting the terminal resistor, and the output voltage is read with the terminal resistor connected to test the driving capability of the pin.

[0051] This can verify whether the pin can output the expected voltage under the specified load conditions, so as to check whether the output drive circuit can switch from high level to low level normally, whether it can output the expected voltage, whether the output resistance is sufficient, etc.

[0052] When performing a DUT output voltage test under a set terminal resistance load condition, the PMU's job is to measure the voltage without sourcing any current. Figure 1For example, in an ideal state, the current through the DUT is 25mA, the output voltages at both ends of the DUT are 3.75V and 1.25V, respectively, with a difference of 2.5V; the voltages at both ends of the PMU are 3.75V and 1.25V, respectively, with a difference of 2.5V. At this time, the actual value and perceived value of the terminal resistance are both 100Ω.

[0053] However, there are usually a lot of parasitic resistances between the output pins of the DUT and the terminal resistors, such as those introduced by the printed circuit board (PCB), cables, relays, etc., and the terminal resistors themselves also have certain errors. ATE generally reduces resistance errors by unifying the length of PCB wires and using the most accurate resistors with a tolerance of 0.1% or even less, but it is difficult to completely eliminate these errors. Moreover, when using devices such as relays, especially semiconductor devices such as photo relays or field effect transistors, it is even more difficult to eliminate the large on-resistance tolerance that occurs during the device manufacturing process.

[0054] At the same time, since the DC test uses the terminal resistance inside the chip, compared with the discrete resistor with an accuracy of 0.1%, the terminal resistance inside the semiconductor usually has an accuracy of 10-20%, and it is very difficult to match the resistance accuracy, which will cause greater errors during the DC test process.

[0055] By connecting a variable resistor in parallel to compensate for the terminal resistance, adjusting the variable resistor at the factory, and measuring the resistance to match the resistance of the entire signal line with the expected value, the resistance change between different CHs can be accurately suppressed. However, this method is very cumbersome and time-consuming; it cannot be automated and cannot be measured and calibrated during regular maintenance during equipment operation.

[0056] Furthermore, when testing is required under different resistance conditions, all resistors need to be installed through switches or a variable resistor needs to be installed, but due to the characteristic limitations of the components, it is difficult to achieve the accuracy requirements required by the test equipment.

[0057] In response to the above-mentioned problems existing in the related technology, an embodiment of the present application provides a method and device for automatically adjusting the terminal resistance of a test channel. Without increasing the cost of the device, the original PMU in the equipment is used to output a current of appropriate size and direction to create an effect that is perceived by the DUT as a change in the load terminal resistance value.

[0058] Figure 2 This is one of the flow charts of the method for automatically adjusting the terminal resistance of the test channel provided in the embodiment of the present application, such as Figure 2 As shown, the method comprises at least the following steps:

[0059] S201. When the resistance value of the terminal resistor in the CH test loop is an expected value, the magnitude and direction of the PMU compensation current are determined based on the pre-measured resistance value of the parasitic resistor on the transmission line between the output pin of the DUT and the terminal resistor.

[0060] Specifically, consider using the existing PMU in the test equipment to solve the problem of measurement accuracy caused by parasitic resistance. The PMU outputs an appropriate current to create an effect that is perceived by the DUT as a change in the load terminal resistance value.

[0061] The value of the parasitic resistance on the transmission line between the output pin of the DUT and the terminal resistor can be measured in advance, which can be considered as a calibration work during the equipment shipment inspection, and can be obtained through automated measurement during regular maintenance.

[0062] The parasitic resistance on the transmission line between the output pin of the DUT and the terminal resistor is the resistance that needs to be corrected by the PMU compensation current. When the resistance value of the terminal resistor in the CH test loop is the expected value, that is, the DC test is performed under the condition that the actual resistance value of the terminal resistor is the expected value, the purpose of applying the PMU compensation current is to eliminate the error caused by the parasitic resistance in the CH test loop. Therefore, the magnitude and direction of the PMU compensation current can be determined by using the resistance value of the parasitic resistor obtained in advance.

[0063] S202 . Based on the determined magnitude and direction of the PMU compensation current, apply the PMU compensation current through a PMU current source connected in parallel with the terminal resistor, and adjust the sensed value of the terminal resistor to a desired value.

[0064] Specifically, after the magnitude and direction of the PMU compensation current are calculated, in the CH test loop, a PMU compensation current of corresponding magnitude and direction is applied through a PMU current source connected in parallel with the terminal resistance to adjust the perceived value of the terminal resistance, so that the actual value and perceived value of the terminal resistance are both expected values.

[0065] Among them, the perceived value of the terminal resistance is the equivalent resistance value of the DUT external in the CH test loop. Before the PMU compensation current is applied, it specifically refers to the sum of the resistance values ​​of the DUT external parasitic resistance and the terminal resistance in the CH test loop; after the PMU compensation current is applied, it specifically refers to the sum of the resistance values ​​of the DUT external parasitic resistance and the adjusted terminal resistance in the CH test loop.

[0066] The automatic adjustment method of the test channel terminal resistance provided in the embodiment of the present application utilizes the existing PMU in the equipment to output a current of appropriate size and direction without increasing the cost of the device, thereby eliminating the measurement error caused by the parasitic resistance on the transmission line and creating an effect that is perceived by the DUT as a change in the load terminal resistance value, thereby improving the measurement accuracy of subsequent DC tests.

[0067] Figure 3 is a flow chart of determining the magnitude and direction of the PMU compensation current provided by an embodiment of the present application, such as Figure 3 As shown, determining the magnitude and direction of the PMU compensation current in S201 specifically includes:

[0068] S301, determining a first output voltage of the DUT when the terminal resistor is disconnected, and a second output voltage and a first output current of the DUT when the terminal resistor is connected.

[0069] Specifically, in the CH test loop, the terminal resistor is disconnected and the first output voltage V1 of the DUT is measured; the terminal resistor is connected and the second output voltage V2 and the first output current I of the DUT are measured. real When the terminal resistor is connected, the CH test circuit meets the following conditions:

[0070]

[0071] Among them, I real Represents the first output current, V high and V low Respectively represent the high and low levels of the positive and negative electrodes of the DUT, R real Represents the expected value of the terminal resistance, R s Represents the output resistance of the DUT, R p Represents the parasitic resistance on the transmission line.

[0072] S302 : Determine the resistance value of the output resistance of the DUT based on the first output voltage, the second output voltage, the first output current, and the resistance value of the parasitic resistance.

[0073] Specifically, the difference in the DUT output voltage when the terminal resistance is disconnected and connected is the sum of all parasitic resistances R in the CH test loop. p and the DUT output resistance R s The sum of the voltages due to the parasitic resistance R p The resistance value of the DUT has been obtained in advance, and the output resistance R of the DUT can be calculated by combining the first output current. s resistance value.

[0074] In some embodiments, determining the output resistance of the DUT includes:

[0075] Determine a first resistance value based on a difference between the first output voltage and the second output voltage, and the first output current;

[0076] The resistance value of the output resistor is determined based on the first resistance value and the resistance value of the parasitic resistor.

[0077] In some embodiments, the first resistance satisfies:

[0078]

[0079] Where R1 represents the first resistance, R s Represents the output resistance, R p represents the parasitic resistance, V1 represents the first output voltage, V2 represents the second output voltage, I real Represents the first output current.

[0080] That is:

[0081]

[0082] S303 , based on the resistance value of the output resistor, determine a second output current when the resistance value of the equivalent terminal resistance external to the DUT in the CH test loop is an expected value.

[0083] The equivalent terminal resistance is the sum of the parasitic resistance and the terminal resistance in the CH test loop.

[0084] Specifically, under the condition that the output resistance value of the DUT is known, the second output current can be calculated when the resistance value of the equivalent terminal resistance connected to the DUT is the expected value without applying the PMU compensation current. Before applying the PMU compensation current, the resistance value of the equivalent terminal resistance connected to the DUT is the sum of the parasitic resistance in the CH test loop and the terminal resistance.

[0085] That is, it is confirmed that there is no parasitic resistance in the CH test loop and the terminal resistance is the current value under the ideal state where the resistance is the expected value.

[0086] In some embodiments, the second output current satisfies:

[0087]

[0088] Among them, I ideal Represents the second output current, V high and V low Respectively represent the high and low levels of the positive and negative electrodes of the DUT, R real represents the expected value, R s Represents the output resistance.

[0089] Among them, R real satisfy:

[0090] R real =R target +2R s

[0091] Among them, R target It indicates the actual resistance value of the terminal resistor when the parasitic resistance on the transmission line is taken into account but the perceived value of the terminal resistor is the expected value.

[0092] S304: Determine the magnitude and direction of the PMU compensation current based on the first output current, the second output current, the parasitic resistance, and the output resistance.

[0093] Specifically, after determining the second output current when the resistance of the external equivalent terminal resistance of the DUT is the expected value, the magnitude and direction of the PMU compensation current are calculated.

[0094] In some embodiments, the magnitude of the PMU compensation current satisfies the following calculation formula:

[0095]

[0096] Among them, I cal Indicates the PMU compensation current, I ideal Represents the second output current, I real represents the first output current, R s Represents the output resistance, R p Represents parasitic resistance, R real Indicates expected value.

[0097] In some embodiments, determining the direction of the PMU compensation current specifically includes:

[0098] When I cal When it is a positive value, it is determined that the direction of the PMU compensation current is opposite to the direction of the current passing through the terminal resistor;

[0099] When I cal When it is a negative value, it is determined that the direction of the PMU compensation current is the same as the direction of the current passing through the terminal resistor.

[0100] Specifically, when I cal When it is a positive value, it means that the resistance of the terminal resistor needs to be reduced to make the sensed value the expected value, and the direction of the PMU compensation current is opposite to the direction of the current passing through the terminal resistor; when I cal When it is a negative value, it means that the resistance of the terminal resistor needs to be increased so that the sensed value is the expected value, and the direction of the PMU compensation current is determined to be the same as the direction of the current passing through the terminal resistor.

[0101] After adding the PMU compensation current, the perceived value of the terminal resistance is the equivalent value of the parasitic resistance in the CH test loop, the terminal resistance, and the PMU correction value.

[0102] It should be noted that even if the resistance of the terminal resistor in the CH test loop is unknown, the current output of the PMU can be adjusted by software to evenly calibrate the deviation of the terminal resistance between the device and the channel. No hardware modulation is required, which greatly simplifies the steps and improves efficiency.

[0103] The technical solution provided in the embodiment of the present application is further illustrated below by using a specific example.

[0104] Figure 4 is a schematic diagram of a CH test circuit with parasitic resistance provided in an embodiment of the present application, such as Figure 4 As shown, compared to Figure 1 ,Due to the existence of parasitic resistance, the current through the DUT and the output voltage across the PMU have changed, and the perceived value of the terminal resistance connected to the DUT is no longer the expected 100Ω.

[0105] At this time, the current through the DUT is 23.81mA, and the output voltages at both ends of the DUT are 3.809V and 1.191V, respectively, with a difference of 2.618V. The voltages measured by the PMU at both ends are 1.310V and 3.691V, respectively, with a difference of 2.381V, and the perceived value of the terminal resistance of the DUT is 110Ω (actual resistance value of the terminal resistance + parasitic resistance value).

[0106] In this case, the PMU applies a compensation current to make the current through the DUT and the voltage across the DUT the same as the voltage and current values ​​of the ideal CH loop test. First, the magnitude and direction of the compensation current applied by the PMU need to be calculated.

[0107] Figure 5 FIG. 2 is a flow chart of a method for determining a compensation current of a channel terminal resistance provided in an embodiment of the present application. Figure 5 As shown, the method comprises the following steps:

[0108] Step 1: Disconnect the terminal resistor and measure the first output voltage V1 of the DUT.

[0109] Step 2: Connect the terminal resistor and measure the second output voltage V2 and the first output current I of the DUT. real .

[0110] Step 3: Calculate the output resistance R of the DUT s .

[0111] The difference between the first output voltage V1 and the second output voltage V2 is the parasitic resistance R on the two transmission lines between the DUT output pin and the terminal resistor. p and the DUT output resistance R s The parasitic resistance R on the transmission line between the DUT output pin and the terminal resistor p Can be measured in advance.

[0112] like Figure 4 As shown, the difference between the output voltages at both ends of the DUT is 2.618V, and the first output current I realis 23.81mA, so we get:

[0113]

[0114] Parasitic resistance R p is 5Ω, then the output resistance R s is 50Ω.

[0115] Step 4: Calculate the expected current when the DUT external equivalent terminal resistance is the expected value.

[0116] The equivalent terminal resistance value is the sum of the actual resistance value of the terminal resistance and the parasitic resistance value in the test circuit.

[0117] like Figure 4 As shown in the figure, when the PMU compensation current is not applied, the first output current I of the DUT is measured. real 23.81mA, V high and V low 5V and 0V respectively, the actual resistance of the terminal resistance is 100Ω (that is, the expected value R real ), the output resistance of the DUT R s is 50Ω, the parasitic resistance R p is 5Ω, then:

[0118]

[0119] Calculate the second output current I when the DUT theoretically has an external equivalent terminal resistance of 100Ω in the CH test loop ideal ,satisfy:

[0120]

[0121] Figure 6 : is a schematic diagram of a CH test circuit when the DUT external equivalent terminal resistance is 100Ω provided in an embodiment of the present application, such as Figure 6 As shown, in the CH test loop, the following conditions are met:

[0122] R target +2R p =100Ω

[0123] Therefore, the actual resistance value R when the terminal resistance perception value is 100Ω target The second output current I is calculated from this when the theoretical external equivalent terminal resistance of the DUT in the CH test loop is 100Ω. ideal is 25mA.

[0124] Step 5: Calculate the magnitude and direction of the PMU compensation current.

[0125] In order to eliminate the influence of parasitic resistance in DC test, make the perceived value of terminal resistance the expected value, and make the current through DUT and the voltage across DUT the same as the voltage and current values ​​of ideal CH loop test, the PMU compensation current is applied to adjust the resistance value of DUT external equivalent terminal resistance. PMU compensation current I cal Should meet:

[0126]

[0127] According to the above formula, I cal The size is 2.5mA. If the calculated I cal is a positive value, indicating that the PMU compensation current I cal The direction of the current should be opposite to the direction of the current passing through the terminal resistor; if the calculated I cal A negative value indicates that the PMU compensation current I cal The direction of the current should be the same as the direction of the current through the terminal resistor.

[0128] Step 6: Apply compensation current using a PMU current source in parallel with the terminal resistor.

[0129] Figure 7 is a schematic diagram of a CH test circuit for applying a compensation current to a PMU provided in an embodiment of the present application, such as Figure 7 As shown, a PMU current source connected in parallel with the terminal resistor is used to apply a current of 2.5 mA in the same direction as the current passing through the terminal resistor.

[0130] At this time, the current through the DUT is 25mA, and the output voltages at both ends of the DUT are 3.75V and 1.25V, respectively, with a difference of 2.5V. The voltages measured by the PMU at both ends are 1.375V and 3.625V, respectively, with a difference of 2.25V. The actual resistance and perceived value of the terminal resistor are both 100Ω.

[0131] At this time, the current through the DUT and the voltage across the DUT are the same as the voltage and current values ​​of the ideal CH loop test. That is, the PMU applies a current of 2.5mA in the same direction as the DUT, and can adjust the terminal resistance of the DUT to the set value.

[0132] Figure 8 is a schematic diagram of a CH test circuit in which the terminal resistance of the test channel can be automatically adjusted according to an embodiment of the present application, such as Figure 8 As shown, a PMU compensation current of appropriate magnitude and direction is applied through a PMU current source connected in parallel with the terminal resistor, so that the actual resistance value and the perceived value of the terminal resistor are both expected values.

[0133] Fig. 9is a schematic diagram of the structure of the automatic adjustment device for the terminal resistance of the test channel provided in the embodiment of the present application, such as Fig. 9 As shown, the device at least includes:

[0134] A first determining unit 901 is used to determine the magnitude and direction of the PMU compensation current based on the resistance value of the parasitic resistance on the transmission line between the output pin of the DUT and the terminal resistor measured in advance when the resistance value of the terminal resistor in the CH test loop is an expected value;

[0135] The second determining unit 902 is configured to apply the PMU compensation current through a PMU current source connected in parallel with the terminal resistor based on the determined magnitude and direction of the PMU compensation current, so as to adjust the sensed value of the terminal resistor to a desired value.

[0136] In some embodiments, the first determining unit 901 specifically includes:

[0137] A first determination module is used to determine a first output voltage of the DUT when the terminal resistor is disconnected, and a second output voltage and a first output current of the DUT when the terminal resistor is connected;

[0138] A second determination module, configured to determine a resistance value of an output resistor of the DUT based on the first output voltage, the second output voltage, the first output current, and a resistance value of the parasitic resistor;

[0139] A third determination module is used to determine the second output current when the resistance value of the equivalent terminal resistance external to the DUT in the CH test loop is an expected value based on the resistance value of the output resistance; the resistance value of the equivalent terminal resistance is the sum of the resistance values ​​of the parasitic resistance and the terminal resistance in the CH test loop;

[0140] The fourth determination module is used to determine the magnitude and direction of the PMU compensation current when the resistance value of the terminal resistance is an expected value based on the first output current, the second output current, the parasitic resistance and the output resistance.

[0141] In some embodiments, the second determination module is specifically configured to:

[0142] Determine a first resistance value based on a difference between the first output voltage and the second output voltage, and the first output current;

[0143] The resistance value of the output resistor is determined based on the first resistance value and the resistance value of the parasitic resistor.

[0144] In some embodiments, the first resistance satisfies the following calculation formula:

[0145]

[0146] Where R1 represents the first resistance, R s Represents the output resistance, R prepresents the parasitic resistance, V1 represents the first output voltage, V2 represents the second output voltage, I real Represents the first output current.

[0147] In some embodiments, the second output current when the resistance of the equivalent terminal resistance external to the DUT in the CH test loop is an expected value satisfies the following calculation formula:

[0148]

[0149] Among them, I ideal Represents the second output current, V high and V low Respectively represent the high and low levels of the positive and negative electrodes of the DUT, R real represents the expected value, R s Represents the output resistance.

[0150] In some embodiments, when the resistance of the terminal resistor is determined to be an expected value, the magnitude of the PMU compensation current satisfies the following calculation formula:

[0151]

[0152] Among them, I cal Indicates the PMU compensation current, I ideal Represents the second output current, I real represents the first output current, R s Represents the output resistance, R p Represents parasitic resistance, R real Indicates expected value.

[0153] In some embodiments, the fourth determination module is specifically configured to:

[0154] When I cal When it is a positive value, it is determined that the direction of the PMU compensation current is opposite to the direction of the current passing through the terminal resistor;

[0155] When I cal When it is a negative value, it is determined that the direction of the PMU compensation current is the same as the direction of the current passing through the terminal resistor.

[0156] It can be understood that the detailed functional implementation of each of the above-mentioned units / modules can be found in the introduction of the aforementioned method embodiment, and will not be repeated here.

[0157] It should be understood that the above-mentioned device is used to execute the method in the above-mentioned embodiment. The implementation principle and technical effect of the corresponding program module in the device are similar to those described in the above-mentioned method. The working process of the device can refer to the corresponding process in the above-mentioned method, which will not be repeated here.

[0158] Based on the method in the above embodiment, an embodiment of the present application provides an electronic device. The device may include: at least one memory for storing programs and at least one processor for executing the programs stored in the memory. When the program stored in the memory is executed, the processor is used to execute the method described in the above embodiment.

[0159] Fig.10 is a schematic diagram of the structure of an electronic device provided in an embodiment of the present application, such as Fig.10 As shown, the electronic device may include: a processor 1001, a communication interface 1002, a memory 1003 and a communication bus 1004, wherein the processor 1001, the communication interface 1002 and the memory 1003 communicate with each other through the communication bus 1004. The processor 1001 may call the software instructions in the memory 1003 to execute the method described in the above embodiment.

[0160] In addition, the logic instructions in the above-mentioned memory 1003 can be implemented in the form of software functional units and can be stored in a computer-readable storage medium when sold or used as an independent product. Based on this understanding, the technical solution of the present application, or the part that contributes to the relevant technology or the part of the technical solution, can be embodied in the form of a software product, which is stored in a storage medium and includes a number of instructions for a computer device (which can be a personal computer, a server, or a network device, etc.) to perform all or part of the steps of the method described in each embodiment of the present application.

[0161] Based on the method in the above embodiment, an embodiment of the present application provides a computer-readable storage medium, which stores a computer program. When the computer program runs on a processor, the processor executes the method in the above embodiment.

[0162] Based on the method in the above embodiment, an embodiment of the present application provides a computer program product. When the computer program product runs on a processor, the processor executes the method in the above embodiment.

[0163] It is understandable that the processor in the embodiment of the present application may be a central processing unit (CPU), or other general-purpose processors, digital signal processors (DSP), application-specific integrated circuits (ASIC), field programmable gate arrays (FPGA) or other programmable logic devices, transistor logic devices, hardware components or any combination thereof. The general-purpose processor may be a microprocessor or any conventional processor.

[0164] The method steps in the embodiments of the present application can be implemented by hardware, or by a processor executing software instructions. The software instructions can be composed of corresponding software modules, and the software modules can be stored in random access memory (Random Access Memory, RAM), flash memory, read-only memory (Read-Only Memory, ROM), programmable read-only memory (Programmable ROM, PROM), erasable programmable read-only memory (Erasable PROM, EPROM), electrically erasable programmable read-only memory (Electrically EPROM, EEPROM), registers, hard disks, mobile hard disks, CD-ROMs or any other form of storage medium known in the art. An exemplary storage medium is coupled to the processor so that the processor can read information from the storage medium and can write information to the storage medium. Of course, the storage medium can also be a component of the processor. The processor and the storage medium can be located in an ASIC.

[0165] In the above embodiments, it can be implemented in whole or in part by software, hardware, firmware or any combination thereof. When implemented using software, it can be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on a computer, the process or function described in the embodiment of the present application is generated in whole or in part. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. The computer instructions can be stored in a computer-readable storage medium or transmitted through the computer-readable storage medium. The computer instructions can be transmitted from a website site, a computer, a server or a data center to another website site, a computer, a server or a data center by wired (e.g., coaxial cable, optical fiber, digital subscriber line (DSL)) or wireless (e.g., infrared, wireless, microwave, etc.) mode. The computer-readable storage medium can be any available medium that a computer can access or a data storage device such as a server or a data center that includes one or more available media integration. The available medium can be a magnetic medium (e.g., a floppy disk, a hard disk, a tape), an optical medium (e.g., a DVD), or a semiconductor medium (e.g., a solid-state drive (SSD)), etc.

[0166] It should be understood that the various numerical numbers involved in the embodiments of the present application are only used for the convenience of description and are not used to limit the scope of the embodiments of the present application.

[0167] It will be easily understood by those skilled in the art that the above description is only a preferred embodiment of the present application and is not intended to limit the present application. Any modifications, equivalent substitutions and improvements made within the spirit and principles of the present application shall be included in the scope of protection of the present application.

Claims

1. A method for automatically adjusting the terminal resistance of a test channel, characterized in that: include: When the resistance value of the terminal resistor in the CH test loop is an expected value, the magnitude and direction of the PMU compensation current are determined based on the resistance value of the parasitic resistor on the transmission line between the output pin of the DUT and the terminal resistor measured in advance; Based on the determined magnitude and direction of the PMU compensation current, the PMU compensation current is applied through a PMU current source connected in parallel with the terminal resistor, and the sensed value of the terminal resistor is adjusted to the expected value.

2. The automatic adjustment method according to claim 1, characterized in that: Determining the magnitude and direction of the PMU compensation current includes: Determine a first output voltage of the DUT when the terminal resistor is disconnected, and a second output voltage and a first output current of the DUT when the terminal resistor is connected; Determining a resistance value of an output resistor of the DUT based on the first output voltage, the second output voltage, the first output current, and a resistance value of the parasitic resistor; Based on the resistance value of the output resistor, determine the second output current when the resistance value of the equivalent terminal resistance external to the DUT in the CH test loop is the expected value; the resistance value of the equivalent terminal resistance is the sum of the resistance values ​​of the parasitic resistance and the terminal resistance in the CH test loop; The magnitude and direction of the PMU compensation current are determined based on the first output current, the second output current, the parasitic resistance, and the output resistance.

3. The automatic adjustment method of the test channel terminal resistance according to claim 2 is characterized in that: Determining the output resistance of the DUT includes: determining a first resistance value based on a difference between the first output voltage and the second output voltage, and the first output current; The resistance value of the output resistor is determined based on the first resistance value and the resistance value of the parasitic resistor.

4. The automatic adjustment method of the test channel terminal resistance according to claim 3 is characterized in that: The first resistance satisfies the following calculation formula: Wherein, R1 represents the first resistance value, R s represents the output resistance, R p represents the parasitic resistance, V1 represents the first output voltage, V2 represents the second output voltage, I real represents the first output current.

5. The method for automatically adjusting the terminal resistance of a test channel according to claim 2, characterized in that: The second output current when the resistance of the equivalent terminal resistance external to the DUT in the CH test loop is the expected value satisfies the following calculation formula: Among them, I ideal represents the second output current, V high and V low Respectively represent the high and low levels of the positive and negative electrodes of the DUT, R real represents the expected value, R s represents the output resistance.

6. The method for automatically adjusting the terminal resistance of a test channel according to claim 2, characterized in that: The magnitude of the PMU compensation current is determined to satisfy the following calculation formula: Among them, I cal represents the PMU compensation current, I ideal represents the second output current, I real represents the first output current, R s represents the output resistance, R p represents the parasitic resistance, R real represents the expected value.

7. The method for automatically adjusting the terminal resistance of a test channel according to claim 6, characterized in that: Determining the direction of the PMU compensation current includes: When I cal When it is a positive value, it is determined that the direction of the PMU compensation current is opposite to the direction of the current passing through the terminal resistor; When I cal When it is a negative value, it is determined that the direction of the PMU compensation current is the same as the direction of the current passing through the terminal resistor.

8. An automatic adjustment device for testing the terminal resistance of a channel, characterized in that: include: A first determining unit, configured to determine the magnitude and direction of the PMU compensation current based on the resistance value of the parasitic resistance on the transmission line between the output pin of the DUT and the terminal resistor measured in advance when the resistance value of the terminal resistor in the CH test loop is an expected value; The second determining unit is configured to apply the PMU compensation current through a PMU current source connected in parallel with the terminal resistor based on the determined magnitude and direction of the PMU compensation current, so as to adjust the sensed value of the terminal resistor to the expected value.

9. An electronic device / image signal generator / network device / transmitter / terminal / base station / industrial computer, characterized in that: include: at least one memory for storing a computer program; At least one processor is used to execute the program stored in the memory. When the program stored in the memory is executed, the processor is used to execute the method according to any one of claims 1 to 7.

10. A computer-readable storage medium storing a computer program, characterized in that: When the computer program runs on a processor, the processor is caused to execute the method according to any one of claims 1 to 7.

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