Subway TCMS central office IAI test system and method

Abstract

The invention provides a subway TCMS central office IAI test system and method. The system comprises a to-be-tested IAI board card, a test board and an upper computer. The test board comprises a power interface, a first circuit, a second circuit, a third circuit, a fourth circuit, a fifth circuit, a test board processor, a serial port, an interface configuration circuit and a network port; the IAI board card to be tested comprises a power supply module, a conversion circuit, a first board card processor, a dual-port RAM, a second board card processor, a starting EPROM, an HDLC link and a link interface. According to the invention, off-line testing can be carried out on the IAI board card of the metro TCMS central office, whether the function of the board card is normal or not is tested, and a fault point is clearly positioned through four state lamps on an upper computer interface; a current signal output by the test board current source can simulate a handle signal of a train, and the credibility of board card testing is improved.

Description

Technical Field

[0001] The present invention relates to the technical field of rail vehicle detection, and in particular to a subway TCMS central bureau IAI test system and method. Background Art

[0002] At present, there are many types of rail transit trains, and there are certain functional differences between the TCMS (Train Control and Management System) of different types of trains. Therefore, at this stage, most of the functional tests of TCMS systems still use manual offline simulation tests, but most of them are based on overall functional tests.

[0003] Although some manufacturers have proposed virtual verification technology based on semi-physical simulation experimental models, due to cost and technical feasibility considerations, physical simulation experimental models only account for a small part of the entire system functional test, and the rest of the simulation modeling is still based on mechanism modeling, which brings uncertainty to the accuracy and confidence of the train TCMS system functional test.

[0004] As a professional equipment dedicated to rail transit, most subway train TCMS are imported, and their communication protocols, internal structures, device functions and other information are not open to the public. When the train is out of warranty, vehicle maintenance is particularly difficult, and there is no equipment on the market for independent closed-loop testing of TCMS central station IAI boards. Summary of the invention

[0005] In view of the defects in the prior art, the object of the present invention is to provide a subway TCMS central bureau IAI test system and method.

[0006] A subway TCMS central bureau IAI test system provided according to the present invention comprises:

[0007] IAI board to be tested, test board and host computer;

[0008] The test board includes a power interface, a first circuit, a second circuit, a third circuit, a fourth circuit, a fifth circuit, a test board processor, a serial port, an interface configuration circuit and a network port;

[0009] The IAI board to be tested includes a power module, a conversion circuit, a first board processor, a dual-port RAM, a second board processor, a startup EPROM, an HDLC link and a link interface;

[0010] One end of the power interface is connected to the power module, and the other end is connected to the third circuit, the fourth circuit and the fifth circuit inside the test board;

[0011] The first circuit and the second circuit are respectively connected to the conversion circuit;

[0012] One end of the first card processor is connected to the conversion circuit, and the other end is connected to the dual-port RAM;

[0013] The second board processor is respectively connected to the dual-port RAM, the boot EPROM, the HDLC link, the serial port and the test board processor;

[0014] One end of the link interface is connected to the HDLC link, and the other end is connected to the interface configuration circuit;

[0015] The host computer is connected to the network port and is connected to a status light; the status light indicates different logical output states by displaying green or red.

[0016] Preferably, the test board processor includes a Cortex-M7 processor; the first board processor includes an HD64F7044 processor, and the second board processor includes an MC68360 processor; the third circuit includes 24V / 15V, supplies 24V through the power interface, and transfers out 15V that is not common to the ground and is used to power the analog circuit op amp inside the test board; the fourth circuit includes 24V / 5V, supplies 24V through the power interface, transfers out 5V and is used to power the analog circuit chip inside the test board; the fifth circuit includes 5V / 3.3V, transfers 3.3V from the 5V transferred from the fourth circuit, and is used to power the Cortex-M7 processor inside the test board, as well as the network port driver chip.

[0017] Preferably, the Cortex-M7 processor drives and controls two AD421BRZ chips so that the first circuit and the second circuit form a current source circuit; the power supply module includes three groups, and each group of power supply modules corresponds one-to-one to the third circuit, the fourth circuit and the fifth circuit respectively.

[0018] Preferably, the conversion circuit includes a first conversion circuit and a second conversion circuit, and the structures of the two conversion circuits are completely consistent; the conversion circuit converts the current of the first circuit and the second circuit into a voltage signal for collection and calculation by the HD64F7044 processor, and uses two identical preset resistors in parallel at the input end and the 4-20mA current source output by the test board to form a ring loop; the preset resistor is used as the differential input end of the two-stage operational amplifier circuit, the positive end of the first-stage operational amplifier circuit is connected to a 2.5V reference voltage for calculation, and the output voltage value of the first-stage operational amplifier is the sum of 2.5V and the negative value of the resistor voltage at both ends of the resistor; the voltage output of the first-stage operational amplifier enters the negative input end of the second-stage operational amplifier, the positive end of the second-stage operational amplifier circuit is connected to a 2.5V reference voltage for calculation, the voltage value of the output end of the second-stage operational amplifier is the difference between 2.5V and the output value of the first-stage operational amplifier, which is simplified to the voltage value at both ends of the parallel resistor, and 4-20mA is converted into a voltage value with an amplitude range of 0-2.5V through the two-stage operational amplifier; the ratio of 4-20mA to 0-2.5V is half of the two identical preset resistance values.

[0019] Preferably, the dual-port RAM is used for data transmission between the HD64F7044 processor and the MC68360 processor; the HD64F7044 processor and the MC68360 processor have two sets of completely independent data buses, address buses, chip select lines, interrupt signals and BUSY signals, and the access rights when the two processors access the same address unit at the same time are determined by the arbitration mechanism of the dual-port RAM chip itself, and the arbitration results are fed back to the dual processors through corresponding tags for them to decide whether to give up the access.

[0020] Preferably, the HDLC link is used by the MC68360 processor for data transmission and communication between boards in the TCMS module, and the HDLC four-level link peripherals thereon are all enabled; each frame of data sent by the HDLC link includes six fields of five types, namely, a flag field, an address field, a control field, an information field and a frame check field.

[0021] Preferably, the link interface is used for the interactive interface between the HDLC four-level link on the MC68360 chip and the TCMS module bus backplane, and for data communication with the HDLC communication board in the module.

[0022] Preferably, the boot EPROM is used to store the MC68360 running program, and the HDLC link cross-level transmission is realized by writing a program, and the function of reading the analog-to-digital conversion value is read through the dual-port RAM, and the HEX file generated by the program is burned into the EPROM.

[0023] Preferably, the serial port includes a first serial port and a second serial port; the first serial port is used to send and receive HDLC data converted by the HDLC protocol chip; the second serial port is used to receive two-way 4-20mA current analog-to-digital conversion values ​​sent by the MC68360 processor;

[0024] The network port is connected to the Cortex-M7 processor and the computer end through the Ethernet transmission chip and the network port transformer, and is used for communication between the host computer and the processor.

[0025] A subway TCMS central bureau IAI testing method provided by the present invention includes:

[0026] Step S1: Connect the test board and the interface of the IAI board to be tested, connect the IAI board to be tested to the host computer through a network cable, take out the original IAI direct-insert EPROM, insert the test EPROM, and supply power to the power interface; initialize the test board and the IAI board to be tested;

[0027] Step S2: two 4-20mA current values ​​are set by the host computer, so that the current source circuit of the test board outputs the corresponding current to drive the IAI board to be tested; the IAI board collects and converts it into voltage data and transmits it back to the host computer, the host computer displays the voltage value and converts it into a current value according to the ratio value, and compares it with the set original current value to see if it is the same;

[0028] Step S3: The host computer periodically sends a 2K-byte random data packet to the Cortex-M7 processor. The first serial port communicates with the IAI through the link configuration circuit for the HDLC four-level link. After the last level of the MC68360 processor receives the data packet, it returns to the first-level HDLC link along the original path and sends it to the Cortex-M7 processor through the link configuration circuit. The data packet is sent to the host computer. After the host computer receives the data packet, it compares it with the sent data packet to check whether it is consistent.

[0029] Step S4: The host computer feedbacks whether the IAI test is normal according to the color of the status light, and performs "AND" on the judgment logic of step S2 and step S3; if the status light is green, it means it is normal, and the logic is "1", if the status light is red, it means it is wrong, and the logic is "0";

[0030] Step S5: Take out the IAI test EPROM, insert the original EPROM, and end the test process.

[0031] Compared with the prior art, the present invention has the following beneficial effects:

[0032] 1. The present invention can perform offline testing on the IAI board of the subway TCMS central bureau to test whether the board functions normally and clearly locate the fault point through the four status lights on the upper computer interface; the current signal output by the current source of the test board can simulate the handle signal of the train, thereby improving the credibility of the board test.

[0033] 2. Compared with the overall self-check function provided by the manufacturer, the present invention has a more comprehensive test process and a wider coverage point, and replaces the actual hardware circuit with a host computer, which is convenient for technicians to debug operations and has good practicality.

[0034] 3. The host computer of the present invention periodically sends data packets to the IAI board through the network port. After receiving the data through the HDLC link inside the MC68360, the data is sent to the Cortex-M7 processor. The processor communicates with the host computer through the network port. The host computer compares the sent and read-back data, and finally achieves the purpose of real-time diagnosis.

[0035] Other beneficial effects of the present invention will be explained in the specific implementation manner through the introduction of specific technical features and technical solutions. Through the introduction of these technical features and technical solutions, those skilled in the art should be able to understand the beneficial technical effects brought about by the technical features and technical solutions. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] Other features, objects and advantages of the present invention will become more apparent from the detailed description of non-limiting embodiments made with reference to the following drawings:

[0037] Figure 1 It is a schematic diagram of the IAI board detection structure of the subway train TCMS central bureau in the present invention.

[0038] Figure 2 This is a 4-20mA circuit diagram of the device in the present invention.

[0039] Figure 3 This is the IAI board conversion circuit diagram of the present invention.

[0040] Figure 4 This is a diagram of the HDLC cross-level link device in the present invention.

[0041] Figure 5 This is a network port driving circuit diagram of the device in the present invention.

[0042] Figure 6 The figure is a flow chart of the TCMS central office IAI board detection method in the present invention. DETAILED DESCRIPTION

[0043] The present invention is described in detail below in conjunction with specific embodiments. The following embodiments will help those skilled in the art to further understand the present invention, but are not intended to limit the present invention in any form. It should be noted that, for those of ordinary skill in the art, several changes and improvements can also be made without departing from the concept of the present invention. These all belong to the protection scope of the present invention.

[0044] Reference Figure 1 As shown, a subway train TCMS central bureau IAI board test system includes:

[0045] Power interface, 24V / 15V, 24V / 5V, 5V / 3.3V, two 4~20mA circuits, power module, conversion circuit, HD64F7044 processor, dual-port RAM, MC68360 processor, boot EPROM, HDLC link, link interface, interface configuration circuit, serial port, Cortex-M7 processor, network port, host computer interface.

[0046] One end of the power interface is connected to the IAI board power module, and the other end is connected to the 24V / 15V, 24V / 5V, and 5V / 3.3V circuits inside the test board; two 4-20mA circuits are connected to the conversion circuit, one end of the HD64F7044 processor is connected to the conversion circuit, and the other end is connected to the dual-port RAM; the MC68360 processor is connected to the dual-port RAM and to the boot EPROM, and is also connected to the HDLC link and the serial port of the test board and the serial port of the Cortex-M7 processor; one end of the link interface is connected to the HDLC link, and the other end is connected to the interface configuration circuit; the host computer interface is connected to the network port.

[0047] The 24V / 15V circuit is supplied with 24V through the power interface, and 15V is transferred out without common ground. 15V is used to power the analog circuit op amp inside the test board; the 24V / 5V circuit is supplied with 24V through the power interface, and 5V is transferred out. 5V is used to power the analog circuit chip inside the test board; the 5V / 3.3V circuit is supplied with 5V through the 24V, and 3.3V is transferred out. 3.3V is used to power the Cortex-M7 processor inside the test board and the network port driver chip.

[0048] The two 4-20mA circuits are driven by the Cortex-M7 processor to control two AD421BRZ chips to form a precise current source circuit; there are three groups of power modules inside IAI, one group supplies 24V through the power interface and outputs ±15V, and the ±15V is used to power the operational amplifiers of the analog computing circuit inside the IAI board; another group supplies 24V through the power interface and outputs 5V, and the 5V is used to power the internal HD64F7044 processor and MC68360 processor digital circuit system; the last group supplies 24V through the power interface and outputs +15V, which outputs high-precision 2.5V, which is used as the reference voltage for the AD acquisition circuit inside the HD64F7044 processor and the operating voltage for the conversion circuit.

[0049] The conversion circuit is divided into the first conversion circuit and the second conversion circuit. The structures of the two conversion circuits are exactly the same. The conversion circuit converts the two 4-20mA currents into voltage signals with an amplitude range of 0-2.5V for collection and calculation by the HD64F7044 processor.

[0050] The above conversion circuit uses two identical high-precision resistors connected in parallel at the input end and the 4-20mA current source output by the test board to form a ring loop. The high-precision resistor serves as the differential input end of the two-stage operational amplifier circuit. The positive end of the first-stage operational amplifier circuit is connected to a 2.5V reference voltage for calculation. The output voltage value of the first-stage operational amplifier is the sum of 2.5V and the negative value of the resistor voltage at both ends of the resistor. The voltage output of the first-stage operational amplifier enters the negative input end of the second-stage operational amplifier. The positive end of the second-stage operational amplifier circuit is connected to a 2.5V reference voltage for calculation. The voltage value at the output end of the second-stage operational amplifier is the difference between 2.5V and the output value of the first-stage operational amplifier, which is simplified to the voltage value at both ends of the parallel resistor. The two-stage operational amplifier converts 4-20mA into a voltage value with an amplitude range of 0-2.5V.

[0051] The above ratio value of 4-20mA to 0-2.5V is half of the value of two identical high-precision resistors.

[0052] Dual-port RAM is used for data transmission between HD64F7044 processor and MC68360 processor. HD64F7044 and MC68360 processors have two sets of completely independent data buses, address buses, chip select lines, interrupt signals and BUSY signals. The arbitration mechanism of the dual-port RAM chip itself determines the access rights when two processors access the same address unit at the same time, and feeds back the arbitration results to the dual processors through corresponding tags for them to decide whether to give up the access.

[0053] Dual-port RAM data transmission is mainly used by the HD64F7044 processor to collect the voltage value of 4-20mA after passing through the conversion circuit in real time. The processor performs analog-to-digital AD conversion inside the processor to store the digital value in the dual-port RAM, and writes data to the address 0x7E, thereby triggering an interrupt to the MC68360 processor. The MC68360 processor enters the interrupt processing function to read the data in the RAM. After the reading is completed, the data in 0x7E is read once to clear the interrupt flag.

[0054] HDLC link is the communication method used by MC68360 to transmit data between boards in TCMS module. All HDLC four-level link peripherals on MC68360 are enabled. Each time a frame of data is sent through HDLC link, it consists of six fields with a total of five types, namely flag field (F), address field (A), control field (C), information field (I), and frame check field (FCS).

[0055] The link interface is the interactive interface between the MC68360 on-chip HDLC four-level link and the TCMS module bus backplane, and is used for data communication with the HDLC communication board in the module. The link configuration circuit refers to writing the internal running program of the MC68360 outside the operating environment of the original TCMS system, cross-linking and cascading the HDLC link, and the last link data output is converted to RS232 data through the HDLC protocol conversion chip.

[0056] The startup EPROM is used to store the MC68360 running program. By writing the program, the cross-level transmission of the HDLC link is realized, and the analog-to-digital conversion value is read through the dual-port RAM. The HEX file generated by the program is burned into the EPROM.

[0057] The serial port includes a first serial port and a second serial port. The first serial port is used for sending and receiving HDLC data converted by the HDLC protocol chip; the second serial port is used for receiving two-channel 4-20mA current analog-to-digital conversion values ​​sent by MC68360.

[0058] The network port connects the Cortex-M7 processor and the computer through the Ethernet transmission chip and the network port transformer, which is used for communication between the host computer and the processor.

[0059] The host computer is used to display the two-way 4-20mA current setting values, as well as the collected voltage values ​​and the converted current values; at the same time, it periodically sends random data packets to the HDLC link, reads back the data sent back by the HDLC link, and compares the results.

[0060] The specific test process is as follows:

[0061] Step 1: Connect the interface of the test board and IAI board. The test board is connected to the host computer through a network cable. Take out the original IAI plug-in EPROM, insert the test EPROM, power the power interface, power the test board and IAI board, and perform a read and write test on the 1M byte RAM space from 0x00000 to 0xFFFFF of MC68360. After completion, load the test EPROM content into RAM and run it. After IAI and the test board are initialized, the communication status light on the host computer interface flashes to indicate normal communication.

[0062] Step 2: The host computer interface sets two 4-20mA current values, and the current source circuit of the test board outputs the corresponding current to drive the IAI board. The IAI board collects and converts it into voltage data and transmits it back to the host computer. The host computer displays the voltage value and converts it into current value according to the proportional value, and compares it with the set original current value to see if it is the same;

[0063] Among them, the voltage data transmitted back to the host computer by the IAI board is sent by MC68360 to the second serial port of the Cortex-M7 processor through the serial port. After the second serial port receives the data, it is sent to the host computer through the network port.

[0064] The host computer detects the current loops in sequence. First, the first current loop is detected. When the error between the set current value and the feedback current value is within 5%, it is considered to be consistent and the output logic is "1". Otherwise, an error is prompted and the output logic is "0". Secondly, the second current loop is detected. The detection method is the same as the first loop.

[0065] The host computer interface is connected to a total of four status lights. The first two status lights are used to feedback the two current loop detection results according to the output logic. Green represents normal, the logic is "1", and red represents error, the logic is "0".

[0066] Step 3: The host computer periodically sends 2K-byte random data packets to the Cortex-M7 processor. The first serial port of the processor communicates with IAI via the HDLC four-level link through the link configuration circuit. After the last level of the MC68360 processor receives the data packet, it returns to the first-level HDLC link and sends it to the Cortex-M7 processor via the link configuration circuit. The processor sends the data packet to the host computer. After receiving the data packet, the host computer compares it with the sent data packet to check whether it is consistent.

[0067] When the software compares the data packet received by the host computer and the data packet sent, and the data packet is completely consistent, the HDLC level 4 link function is normal and the output logic is "1". Otherwise, the host computer reports an error and outputs a logic "0".

[0068] The host computer interface uses the third status light to feedback the HDLC test results according to the output logic. Green represents normal, the logic is "1", and red represents error, the logic is "0";

[0069] Step 4: The upper computer interface uses the fourth status light to feedback whether the IAI test is normal. The judgment logic of the above steps 2 and 3 is "ANDed". Green represents normal, the logic is "1", and red represents error, the logic is "0".

[0070] Step 5: Turn off the power, unplug the test device, take out the IAI test EPROM, and insert the original EPROM.

[0071] The present invention can perform offline testing on the IAI board of the subway TCMS central bureau to test whether the board functions normally and clearly locate the fault point through four status lights on the upper computer interface; the current signal output by the current source of the test board can simulate the handle signal of the train, thereby improving the credibility of the board test.

[0072] The above are basic embodiments of the present invention. The technical solution of the present invention is further described below through two preferred embodiments.

[0073] Example 1

[0074] like Figure 1 As shown, a subway train TCMS central bureau IAI board detection system provided by the present invention comprises:

[0075] Power interface, 24V / 15V, 24V / 5V, 5V / 3.3V, two 4~20mA circuits, power module, conversion circuit, HD64F7044 processor, dual-port RAM, MC68360 processor, boot EPROM, HDLC link, link interface, interface configuration circuit, serial port, Cortex-M7 processor, network port, host computer interface.

[0076] One end of the power interface is connected to the IAI board power module, and the other end is connected to the 24V / 15V, 24V / 5V, and 5V / 3.3V circuits inside the test board; two 4-20mA circuits are connected to the conversion circuit, one end of the HD64F7044 processor is connected to the conversion circuit, and the other end is connected to the dual-port RAM; the MC68360 processor is connected to the dual-port RAM, and is connected to the boot EPROM, and is also connected to the HDLC link and the serial port of the test board and the serial port of the Cortex-M7 processor. One end of the link interface is connected to the HDLC link, and the other end is connected to the interface configuration circuit; the upper computer interface is connected to the network port; the 24V / 15V circuit is powered by 24V through the power interface, and 15V is transferred out of the ground. The 15V is used to power the analog circuit op amp inside the test board. The 24V / 5V circuit is powered by 24V through the power interface, and 5V is transferred out. 5V is used to power the analog circuit chip inside the test board; the 5V / 3.3V circuit is powered by 5V transferred out by 24V, and 3.3V is used to power the Cortex-M7 processor inside the test board and the network port driver chip. The two 4-20mA circuits are driven by the Cortex-M7 processor to control two AD421BRZ chips to form a precise current source circuit.

[0077] like Figure 2 As shown in the figure, one of the internal structures is given. The processor controls the DATA, CLOCK and LATCH pins of the AD421BRZ chip through three EL817 optocouplers. The DATA pin is used to receive serial data, the CLOCK pin is used to receive the data clock, and the rising edge is valid. The LATCH pin is used to latch and update the data output on the rising edge.

[0078] The processor performs digital-to-analog conversion on the AD421BRZ and outputs current through the LOOPRTN_8 pin, which is set to I PROG The current output is scaled by the operational amplifier circuit. Due to the virtual short and virtual open characteristics of the operational amplifier, the output current I O formula:

[0079]

[0080] In the above formula, since the circuit design U1-R1 and U1-R2 are both 100R, I O Twice as much as I PROG , I O Output 4~20mA current.

[0081] There are three groups of power modules inside IAI:

[0082] The first group supplies 24V through the power interface and outputs ±15V, which is used to power the operational amplifier of the analog computing circuit inside the IAI board;

[0083] The second group supplies 24V through the power interface and transfers out 5V, which is used to power the internal HD64F7044 processor and the MC68360 processor digital circuit system;

[0084] The third group, which is supplied by the power interface 24V and outputs +15V, outputs high-precision 2.5V, which is used as the reference voltage for the AD acquisition circuit inside the HD64F7044 processor and the operating voltage for the conversion circuit.

[0085] The conversion circuit is divided into a first conversion circuit and a second conversion circuit, and the structures of the two conversion circuits are completely consistent.

[0086] like Figure 3 As shown, the conversion circuit converts two 4-20mA currents into voltage signals with an amplitude range of 0-2.5V for collection and calculation by the HD64F7044 processor.

[0087] The conversion circuit uses two identical high-precision resistors RL1 and RL2 connected in parallel at the input end and the 4-20mA current source output by the test board to form a ring loop to convert the current signal into a voltage signal:

[0088]

[0089] In the formula, RL1=RL2=250Ω, so:

[0090] Ui+-Ui-=I O ×125

[0091] The above high-precision resistor is used as the differential input terminal of the two-stage op amp circuit. The positive terminal of the first-stage op amp circuit is connected to the 2.5V reference voltage for calculation. The output voltage value of the first-stage op amp is the sum of 2.5V and the negative value of the resistor voltage at both ends of the resistor:

[0092] U O 1=2.5+Ui--Ui+

[0093] The voltage output of the first-stage op amp enters the negative input terminal of the second-stage op amp. The positive terminal of the second-stage op amp circuit is connected to the 2.5V reference voltage for calculation. The voltage value at the output terminal of the second-stage op amp is the difference between 2.5V and the output value of the first-stage op amp, which is simplified to the voltage value across the parallel resistor. The two-stage op amp converts 4-20mA into a voltage value with an amplitude range of 0-2.5V:

[0094] U O 2=2.5-U O 1=Ui+-Ui-=I O ×125

[0095] The ratio of 4-20 mA to 0-2.5 V is half of the value of two identical high-precision resistors.

[0096] Dual-port RAM is used for data transmission between HD64F7044 processor and MC68360 processor. HD64F7044 and MC68360 processors have two sets of completely independent data buses, address buses, chip select lines, interrupt signals and BUSY signals, and the arbitration mechanism of the dual-port RAM chip itself determines the access rights when two processors access the same address unit at the same time, and feeds back the arbitration results to the dual processors through corresponding tags for them to decide whether to give up the access.

[0097] Dual-port RAM data transmission is mainly used by the HD64F7044 processor to collect the voltage value of 4-20mA after passing through the conversion circuit in real time. The processor performs analog-to-digital AD conversion inside the processor to store the digital value in the dual-port RAM, and writes data to the address 0x7E, thereby triggering an interrupt to the MC68360 processor. The MC68360 processor enters the interrupt processing function to read the data in the RAM. After the reading is completed, the data in 0x7E is read once to clear the interrupt flag.

[0098] The HDLC link is the communication method used by MC68360 for data transmission between boards in the TCMS module. All the on-chip HDLC four-level link peripherals of MC68360 are enabled.

[0099] Each time the above HDLC link sends a frame of data, it consists of six fields of five types, namely, flag field (F), address field (A), control field (C), information field (I), and frame check field (FCS).

[0100] The link interface is the interactive interface between the MC68360 on-chip HDLC four-level link and the TCMS module bus backplane, and is used to communicate data with the HDLC communication board in the module. The link configuration circuit refers to writing the MC68360 internal operating program outside the operating environment of the original TCMS system to perform cross-cascade transmission on the HDLC link.

[0101] like Figure 4 As shown, the left side "inside" indicates the side close to MC68360, and the right side "outside" indicates the side close to the protocol conversion chip. The last level HDLC4 link data output is converted into RS232 type data through the HDLC protocol conversion chip.

[0102] When data is sent from "outside" to "inside", the data link is:

[0103] RX4BUF→TX4BUF→RX2BUF→TX2BUF→RX3BUF→TX3BUF→RX1BUF

[0104] If there is data in RX1BUF, it will be sent back directly along the original path, and the data will be sent from "inside" to "outside". The link is:

[0105] RX1BUF→TX1BUF→RX3BUF→TX3BUF→RX2BUF→TX2BUF→RX4BUF→TX4

[0106] BUF

[0107] The startup EPROM is used to store the MC68360 running program. By writing the program, the cross-level transmission of the HDLC link is realized, and the analog-to-digital conversion value is read through the dual-port RAM. The HEX file generated by the program is burned into the EPROM.

[0108] The first serial port is used to send and receive HDLC data after the data is converted by the HDLC protocol chip;

[0109] The second serial port is used to receive the two-way 4~20mA current analog-to-digital conversion values ​​sent by MC68360.

[0110] like Figure 5 As shown in the figure, the network port connects the Cortex-M7 processor and the computer through the Ethernet transmission chip and the network port transformer, which is used for communication between the host computer and the processor. The Cortex-M7 processor integrates a powerful 10Mbps / 100Mbps Ethernet controller. The Ethernet module uses DP83848C as the Ethernet PHY (physical layer) interface, and communicates data through the network port transformer LFE8505.

[0111] Among them, TR1-R4 is 49.9Ω, which is used to enhance the output signal of the two pairs of differential lines RD+, RD- and TD+, TD-. The four 75Ω resistors TR1-R0 to TR1-R3 are used to match the impedance of the twisted pair, which can maximize the output signal amplitude and facilitate long-distance transmission. The two 1000pF / 2KV capacitors TR1-C1 and TR1-C2 are used to improve EMI.

[0112] The host computer is used to display the two-way 4-20mA current setting values, as well as the collected voltage values ​​and the converted current values; at the same time, it periodically sends random data packets to the HDLC link, reads back the data sent back by the HDLC link, and compares the results.

[0113] Example 2

[0114] like Figure 6 As shown, a subway train TCMS central bureau IAI board test system and method includes the following steps:

[0115] Step 1: Connect the interface of the test board and IAI board. The test board is connected to the host computer through a network cable. Take out the original IAI plug-in EPROM, insert the test EPROM, power the power interface, power the test board and IAI board, and perform a read and write test on the 1M byte RAM space from 0x00000 to 0xFFFFF of MC68360. After completion, load the test EPROM content into RAM and run it. After IAI and the test board are initialized, the communication status light on the host computer interface flashes to indicate normal communication.

[0116] Step 2: The host computer interface sets two 4-20mA current values. The current source circuit of the test board outputs the corresponding current to drive the IAI board. The IAI board collects and converts it into voltage data and transmits it back to the host computer. The host computer displays the voltage value and converts it into current value according to the proportional value, and compares it with the set original current value to see if it is the same.

[0117] The voltage data transmitted by the IAI board back to the host computer is sent by the MC68360 to the second serial port of the Cortex-M7 processor through the serial port. After the second serial port receives the data, it is sent to the host computer through the network port.

[0118] The host computer detects the current loops in sequence. First, the first current loop is detected. When the error between the set current value and the feedback current value is within 5%, it is considered to be consistent and the output logic is "1". Otherwise, an error message is given and the output logic is "0". Secondly, the second current loop is detected. The detection method is the same as the first loop.

[0119] The upper computer interface uses two status lights 1 and 2 to feedback the two current loop detection results according to the output logic. Green represents normal and the logic is "1", and red represents error and the logic is "0".

[0120] Step 3: The host computer periodically sends 2K-byte random data packets to the Cortex-M7 processor. The first serial port of the processor communicates with IAI via the link configuration circuit via the HDLC four-level link. After the last level of the MC68360 processor receives the data packet, it returns to the first-level HDLC link and sends it to the Cortex-M7 processor via the link configuration circuit. The processor sends the data packet to the host computer. After receiving the data packet, the host computer compares it with the sent data packet to check whether it is consistent.

[0121] Among them, when the software compares the data packet received by the host computer and the data packet sent are completely consistent, the HDLC level 4 link function is normal and the output logic is "1", otherwise the host computer reports an error and outputs a logic "0";

[0122] The host computer interface uses the third status light to feedback the HDLC test results according to the output logic. Green represents normal, the logic is "1", and red represents error, the logic is "0";

[0123] Step 4: The upper computer interface uses the fourth status light to feedback whether the IAI test is normal. The judgment logic of the above steps 2 and 3 is "ANDed". Green represents normal, the logic is "1", and red represents error, the logic is "0".

[0124] Step 5: Turn off the power, unplug the test device, take out the IAI test EPROM, and insert the original EPROM.

[0125] The invention provides a subway train TCMS central bureau IAI board test system and method. The detection method is applicable to the HITACHI subway train TCMS central bureau IAI board. The invention can simulate the on-board 4-20mA train handle current signal, the current value can be freely set by a host computer, and the current value collected by the IAI can be read in real time; meanwhile, the HDLC four-level cross link communication can be tested by the host computer, and the health status of the IAI board can be monitored in real time. The method can be used for reference by other boards with MC68360 processors in the TCMS system for laboratory offline testing.

[0126] Those skilled in the art know that, in addition to realizing the system and its various devices, modules, and units provided by the present invention in a purely computer-readable program code, it is entirely possible to realize the same functions in the form of logic gates, switches, application-specific integrated circuits, programmable logic controllers, and embedded microcontrollers by logically programming the method steps. Therefore, the system and its various devices, modules, and units provided by the present invention can be considered as a hardware component, and the devices, modules, and units included therein for realizing various functions can also be regarded as structures within the hardware component; the devices, modules, and units for realizing various functions can also be regarded as both software modules for realizing the method and structures within the hardware component.

[0127] The above describes the specific embodiments of the present invention. It should be understood that the present invention is not limited to the above specific embodiments, and those skilled in the art can make various changes or modifications within the scope of the claims, which does not affect the essence of the present invention. In the absence of conflict, the embodiments of the present application and the features in the embodiments can be combined with each other arbitrarily.

Claims

1. A subway TCMS central bureau IAI test system, characterized in that: include: IAI board to be tested, test board and host computer; The test board includes a power interface, a first circuit, a second circuit, a third circuit, a fourth circuit, a fifth circuit, a test board processor, a serial port, an interface configuration circuit and a network port; The IAI board to be tested includes a power module, a conversion circuit, a first board processor, a dual-port RAM, a second board processor, a startup EPROM, an HDLC link and a link interface; One end of the power interface is connected to the power module, and the other end is connected to the third circuit, the fourth circuit and the fifth circuit inside the test board; The first circuit and the second circuit are respectively connected to the conversion circuit; One end of the first card processor is connected to the conversion circuit, and the other end is connected to the dual-port RAM; The second board processor is respectively connected to the dual-port RAM, the boot EPROM, the HDLC link, the serial port and the test board processor; One end of the link interface is connected to the HDLC link, and the other end is connected to the interface configuration circuit; The host computer is connected to the network port and is connected to a status light; the status light indicates different logical output states by displaying green or red.

2. The subway TCMS central bureau IAI test system according to claim 1, characterized in that: The test board processor includes a Cortex-M7 processor; the first board processor includes an HD64F7044 processor, and the second board processor includes an MC68360 processor; the third circuit includes 24V / 15V, which supplies 24V through the power interface, and outputs 15V that is not common to the ground and is used to power the analog circuit op amp inside the test board; the fourth circuit includes 24V / 5V, which supplies 24V through the power interface, and outputs 5V and is used to power the analog circuit chip inside the test board; the fifth circuit includes 5V / 3.3V, which outputs 3.3V from the 5V output from the fourth circuit, and is used to power the Cortex-M7 processor inside the test board, as well as the network port driver chip.

3. The subway TCMS central bureau IAI test system according to claim 2, characterized in that: The Cortex-M7 processor drives and controls two AD421BRZ chips, so that the first circuit and the second circuit form a current source circuit; the power supply module includes three groups, and each group of power supply modules corresponds to the third circuit, the fourth circuit and the fifth circuit respectively.

4. The subway TCMS central bureau IAI test system according to claim 2, characterized in that: The conversion circuit includes a first conversion circuit and a second conversion circuit, and the structures of the two conversion circuits are completely consistent; the conversion circuit converts the current of the first circuit and the second circuit into a voltage signal for collection and calculation by the HD64F7044 processor, and uses two identical preset resistors in parallel at the input end and a 4-20mA current source output by the test board to form a ring loop; the preset resistor is used as the differential input end of the two-stage operational amplifier circuit, the positive end of the first-stage operational amplifier circuit is connected to a 2.5V reference voltage for calculation, and the output voltage value of the first-stage operational amplifier is the sum of 2.5V and the negative value of the resistor voltage at both ends of the resistor; the voltage output of the first-stage operational amplifier enters the negative input end of the second-stage operational amplifier, the positive end of the second-stage operational amplifier circuit is connected to a 2.5V reference voltage for calculation, and the voltage value of the output end of the second-stage operational amplifier is the difference between 2.5V and the output value of the first-stage operational amplifier, which is simplified to the voltage value at both ends of the parallel resistor, and 4-20mA is converted into a voltage value with an amplitude range of 0-2.5V through the two-stage operational amplifier; the ratio of 4-20mA to 0-2.5V is half of the two identical preset resistor values.

5. The subway TCMS central office IAI test system according to claim 2, characterized in that: The dual-port RAM is used for data transmission between the HD64F7044 processor and the MC68360 processor; the HD64F7044 processor and the MC68360 processor have two sets of completely independent data buses, address buses, chip select lines, interrupt signals and BUSY signals. The access rights when two processors access the same address unit at the same time are determined by the arbitration mechanism of the dual-port RAM chip itself, and the arbitration results are fed back to the dual processors through corresponding tags for them to decide whether to give up the access.

6. The subway TCMS central bureau IAI test system according to claim 2, characterized in that: The HDLC link is used by the MC68360 processor for data transmission and communication between boards in the TCMS module, and all the HDLC four-level link peripherals thereon are enabled; each frame of data sent by the HDLC link includes six fields of five types, namely, a flag field, an address field, a control field, an information field, and a frame check field.

7. The subway TCMS central office IAI test system according to claim 2, characterized in that: The link interface is used for the interactive interface between the HDLC four-level link on the MC68360 chip and the TCMS module bus backplane, and for data communication with the HDLC communication board in the module.

8. The subway TCMS central office IAI test system according to claim 2, characterized in that: The startup EPROM is used to store the MC68360 running program, realize the HDLC link cross-level transmission by writing the program, read the analog-to-digital conversion value through the dual-port RAM, and burn the HEX file generated by the program into the EPROM.

9. The subway TCMS central office IAI test system according to claim 2, characterized in that: The serial port includes a first serial port and a second serial port; the first serial port is used to send and receive HDLC data converted by the HDLC protocol chip; the second serial port is used to receive two-way 4-20mA current analog-to-digital conversion values ​​sent by the MC68360 processor; The network port is connected to the Cortex-M7 processor and the computer end through the Ethernet transmission chip and the network port transformer, and is used for communication between the host computer and the processor.

10. A subway TCMS central office IAI test method, based on the subway TCMS central office IAI test system according to any one of claims 1 to 9, characterized in that: include: Step S1: Connect the test board and the interface of the IAI board to be tested, connect the IAI board to be tested to the host computer through a network cable, take out the original IAI direct-insert EPROM, insert the test EPROM, and supply power to the power interface; initialize the test board and the IAI board to be tested; Step S2: two 4-20mA current values ​​are set by the host computer, so that the current source circuit of the test board outputs the corresponding current to drive the IAI board to be tested; the IAI board collects and converts it into voltage data and transmits it back to the host computer, the host computer displays the voltage value and converts it into a current value according to the ratio value, and compares it with the set original current value to see if it is the same; Step S3: The host computer periodically sends a 2K-byte random data packet to the Cortex-M7 processor. The first serial port communicates with the IAI through the link configuration circuit for the HDLC four-level link. After the last level of the MC68360 processor receives the data packet, it returns to the first-level HDLC link along the original path and sends it to the Cortex-M7 processor through the link configuration circuit. The data packet is sent to the host computer. After the host computer receives the data packet, it compares it with the sent data packet to check whether it is consistent. Step S4: The host computer feedbacks whether the IAI test is normal according to the color of the status light, and performs "AND" on the judgment logic of step S2 and step S3; if the status light is green, it means it is normal, and the logic is "1", if the status light is red, it means it is wrong, and the logic is "0"; Step S5: Take out the IAI test EPROM, insert the original EPROM, and end the test process.

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