A positive and negative pressure load detection circuit for BMS

Abstract

The present invention discloses a positive and negative voltage load detection circuit applied to BMS, which relates to the technical field of battery management system. It includes: a clamping circuit module, a load voltage module, and a comparator module. The present invention provides a positive and negative voltage load detection circuit applied to BMS, which forms a negative feedback regulation loop by introducing a clamping circuit. Through negative feedback regulation, the value of the input voltage tends to be stable, and due to the effect of the clamping circuit, the output voltage always maintains a fixed value. The input voltage is compared with the load detection threshold voltage by the comparator module to determine the connection status of the external load, thereby realizing negative voltage load detection, and performing negative voltage detection while detecting positive voltage, realizing the design of an on-chip integrated positive and negative voltage load detection circuit, thereby saving design costs, reducing design area, and making it easier and more convenient for ordinary users to use.

Description

Technical Field

[0001] The present invention relates to the technical field of battery management systems, and in particular to a positive and negative voltage load detection circuit applied to a BMS. Background Art

[0002] At present, the Battery Management System (BMS) is a highly complex technical system that is specially designed for all-round real-time monitoring and control of battery packs. The core function of BMS is to ensure that the battery pack operates in a safe, efficient and optimal state, thereby extending the service life of the battery and ensuring safe use. Among them, load detection is one of the important functions of BMS. When the BMS is connected to a charger externally, the load detection voltage is negative. At this time, the parasitic diode in the chip will be turned on, resulting in leakage. When the leakage current is large, the chip will be damaged. Therefore, it is an important task of BMS to detect positive and negative voltages at the same time through the design of the load detection circuit.

[0003] In the prior art, the design of load detection circuits all achieves simultaneous detection of positive and negative voltages through off-chip means, so that the BMS can accurately assess the charge state of the battery pack by real-time monitoring the voltage parameters of each battery cell in the battery pack, thereby preventing damage to the battery due to overcharging or over-discharging.

[0004] However, the disadvantage of realizing the simultaneous detection of positive and negative pressures off-chip is that additional components and equipment are required for negative pressure detection, which increases the cost of the device. In addition, the off-chip design method leads to a large space occupation, which affects the compactness of the device, and requires users to have certain technical knowledge and operating experience, which limits the popularization and application of the technology. Therefore, it is a problem to be solved to save costs, reduce design area and optimize user configuration by realizing the design of positive and negative pressure load detection circuits integrated on-chip. Summary of the invention

[0005] Based on this, it is necessary to provide a positive and negative pressure load detection circuit applied to BMS to address the above technical problems.

[0006] The present invention adopts the following technical solutions:

[0007] The present invention provides a positive and negative voltage load detection circuit applied to a BMS, comprising:

[0008] Clamping circuit module, load voltage module, comparator module;

[0009] The clamping circuit module includes: a load clamping operational amplifier AMP, a capacitor C1, a third MOS tube M3, a resistor R4 and a fifth MOS tube M5;

[0010] The input end of the clamp circuit and the input end of the comparator module are connected to the output end of the load voltage module;

[0011] The positive input end of the load clamp operational amplifier AMP is connected to the gate of the third MOS tube M3 and the upper plate of the capacitor C1; the drain of the third MOS tube M3 and the lower plate of the capacitor C1 are connected to one end of the resistor R4; the other end of the resistor R4 is connected to the drain of the fifth MOS tube M5; the gate of the fifth MOS tube M5 is connected to the enable end; the source of the fifth MOS tube M5 is grounded.

[0012] Preferably, the load voltage module comprises: a load voltage port DSGD, a load voltage port VPP, a resistor R2, a resistor R3 and a second MOS tube M2;

[0013] The load voltage port DSGD is connected to one end of the resistor R2; the other end of the resistor R2 is connected to one end of the resistor R3; the other end of the resistor R3 is connected to the drain of the second MOS tube M2; the gate of the second MOS tube M2 is connected to the analog power port AVDD.

[0014] Preferably, the load voltage module further comprises: a load voltage port VPP, a resistor R1 and a first MOS tube M1;

[0015] The load voltage port VPP is connected to one end of the resistor R1 ; the other end of the resistor R1 is connected to the drain of the first MOS transistor M1 ; the gate of the first MOS transistor M1 is connected to the analog power supply AVDD.

[0016] Preferably, the comparator module comprises: a comparator COMP, a load detection output terminal LOAD_DET and a fourth MOS tube M4;

[0017] The gate of the fourth MOS tube M4 is connected to the enable terminal; the source of the fourth MOS tube M4 is connected to the positive input terminal of the comparator COMP; the output terminal of the comparator COMP is connected to the load detection output terminal LOAD_DET;

[0018] Preferably, the negative input terminal of the comparator COMP is used to store the load detection threshold voltage VTH.

[0019] Compared with the prior art, the above technical solution adopted by the present invention can achieve the following beneficial effects:

[0020] The present invention provides a positive and negative voltage load detection circuit applied to a BMS. A clamping circuit is introduced to form a negative feedback regulation loop. The negative feedback regulation makes the value of the input voltage tend to be stable. Due to the effect of the clamping circuit, the output voltage always maintains a fixed value. The input voltage is compared with the load detection threshold voltage by a comparator module to determine the connection status of the external load, thereby realizing negative voltage load detection.

[0021] Among them, when the voltage detected at the load voltage port is a negative value, the input voltage is a negative value, the negative voltage clamp operational amplifier AMP works, and the output voltage VO becomes a low potential, so that the third MOS tube M3 is turned on. As the voltage value of the load voltage port DSGD gradually decreases, the input voltage decreases, the output voltage decreases, and the voltage between the gate and the source of the third MOS tube M3 increases, so that the current flowing through it increases. The increased current generates a voltage drop in the resistor R4, so that the potential of the input voltage increases, and the output voltage increases, thereby realizing negative feedback regulation.

[0022] In addition, when the detection voltage at the load voltage input terminal DSGD is a positive voltage, the input voltage is a positive voltage, the negative voltage clamp operational amplifier AMP does not work, and the output voltage is a high level, so that the third MOS tube M3 is cut off, and the current flows from the DSGD port through the R2-R3-M2-R4-M5 circuit to the ground. The input voltage is compared with the load detection threshold voltage through the comparator module to determine the connection status of the external load, thereby realizing positive voltage load detection.

[0023] Therefore, through the positive and negative voltage load detection circuit designed by the present invention and applied to BMS, a load detection circuit design for simultaneous detection of positive and negative voltages is implemented on the chip, thereby saving design costs, reducing design area and making it easier and more convenient for ordinary users to use. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] Figure 1 A circuit diagram of a positive and negative voltage load detection circuit applied to a BMS provided by the present invention;

[0025] Figure 2 A circuit diagram of a negative voltage clamping operational amplifier AMP in a positive and negative voltage load detection circuit for BMS provided by the present invention. DETAILED DESCRIPTION

[0026] In order to make the purpose, technical solution and advantages of the present invention more clearly understood, the present invention is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not intended to limit the present invention.

[0027] In one embodiment, a positive and negative voltage load detection circuit for BMS is provided, such as Figure 1As shown, including:

[0028] 1. A positive and negative voltage load detection circuit applied to BMS, characterized by comprising:

[0029] Clamping circuit module, load voltage module, comparator module;

[0030] The clamping circuit module includes: a load clamping operational amplifier AMP, a capacitor C1, a third MOS tube M3, a resistor R4 and a fifth MOS tube M5;

[0031] The input end of the clamp circuit and the input end of the comparator module are connected to the output end of the load voltage module;

[0032] The positive input end of the load clamp operational amplifier AMP is connected to the gate of the third MOS tube M3 and the upper plate of the capacitor C1; the drain of the third MOS tube M3 and the lower plate of the capacitor C1 are connected to one end of the resistor R4; the other end of the resistor R4 is connected to the drain of the fifth MOS tube M5; the gate of the fifth MOS tube M5 is connected to the enable end; the source of the fifth MOS tube M5 is grounded.

[0033] In addition, the load voltage module includes: a load voltage port DSGD, a load voltage port VPP, a resistor R2, a resistor R3 and a second MOS tube M2;

[0034] The load voltage port DSGD is connected to one end of the resistor R2; the other end of the resistor R2 is connected to one end of the resistor R3; the other end of the resistor R3 is connected to the drain of the second MOS tube M2; the gate of the second MOS tube M2 is connected to the analog power port AVDD.

[0035] In addition, the load voltage module further includes: a load voltage port VPP, a resistor R1 and a first MOS tube M1;

[0036] The load voltage port VPP is connected to one end of the resistor R1 ; the other end of the resistor R1 is connected to the drain of the first MOS transistor M1 ; the gate of the first MOS transistor M1 is connected to the analog power supply AVDD.

[0037] In addition, the comparator module includes: a comparator COMP, a load detection output terminal LOAD_DET and a fourth MOS tube M4;

[0038] The gate of the fourth MOS tube M4 is connected to the enable terminal; the source of the fourth MOS tube M4 is connected to the positive input terminal of the comparator COMP; the output terminal of the comparator COMP is connected to the load detection output terminal LOAD_DET;

[0039] In addition, the negative input terminal of the comparator COMP is used to store the load detection threshold voltage VTH.

[0040] In addition, such as Figure 2 As shown, the negative voltage clamp operational amplifier AMP includes: a bias circuit module and an operational amplifier input pair module;

[0041] A bias circuit module, including: a seventh MOS tube M7, an eighth MOS tube M8, a ninth MOS tube M9, and a tenth MOS tube M10;

[0042] The input end of the bias circuit is connected to the drain of the ninth MOS tube M9, the gate of the ninth MOS tube M9, and the gate of the tenth MOS tube M10;

[0043] The gate of the ninth MOS tube M9 is connected to the gate of the tenth MOS tube M10; the source of the ninth MOS tube M9 is connected to the drain of the seventh MOS tube M7, the gate of the seventh MOS tube M7, and the gate of the eighth MOS tube M8;

[0044] The source of the seventh MOS tube M7 is connected to the source of the eighth MOS tube M8 and the first output end of the bias circuit; the drain of the seventh MOS tube M7 is connected to the source of the ninth MOS tube M9; the gate of the seventh MOS tube M7 is connected to the gate of the eighth MOS tube M8;

[0045] The source of the eighth MOS tube M8 is connected to the first output terminal of the bias circuit; the drain of the eighth MOS tube M8 is connected to the source of the tenth MOS tube M10; the drain of the tenth MOS tube M10 is connected to the second output terminal;

[0046] The operational amplifier input pair tube module includes: a first MOS tube M1, a second MOS tube M2, a third MOS tube M3, a fourth MOS tube M4, a fifth MOS tube M5, and a sixth MOS tube M6;

[0047] The first MOS tube M1, the second MOS tube M2, the third MOS tube M3, the fourth MOS tube M4 and the fifth MOS tube M5 are connected in series; the sixth MOS tube M6 is connected in parallel with the series structure including the first MOS tube M1, the second MOS tube M2, the third MOS tube M3, the fourth MOS tube M4 and the fifth MOS tube M5;

[0048] The source of the first MOS tube M1 is connected to the source of the sixth MOS tube M6; the drain of the first MOS tube M1 is connected to the source of the second MOS tube M2; the drain of the second MOS tube M2 is connected to the source of the third MOS tube M3; the drain of the third MOS tube M3 is connected to the source of the fourth MOS tube M4; the drain of the fourth MOS tube M4 is connected to the source of the fifth MOS tube M5; the drain of the fifth MOS tube M5 is connected to the first output end of the operational amplifier input pair module; the drain of the sixth MOS tube M6 is connected to the second output end of the operational amplifier input pair module.

[0049] In addition, the negative voltage clamp operational amplifier AMP further includes: an eleventh MOS tube M11, a twelfth MOS tube M12, a thirteenth MOS tube M13, a fourteenth MOS tube M14, a fifteenth MOS tube M15, a sixteenth MOS tube M16, a seventeenth MOS tube M17, an eighteenth MOS tube M18, a nineteenth MOS tube M19 and a twentieth MOS tube M20;

[0050] The source of the eleventh MOS tube M11 is connected to the source of the twelfth MOS tube M12, the source of the thirteenth MOS tube M13 and the source of the eighth MOS tube M8; the drain of the eleventh MOS tube M11 is connected to the source of the first MOS tube M1 and the source of the sixth MOS tube M6;

[0051] The gate of the twelfth MOS tube M12 is connected to the drain of the twelfth MOS tube M12, the gate of the thirteenth MOS tube M13 and the drain of the sixteenth MOS tube M16; the source of the twelfth MOS tube M12 is connected to the source of the thirteenth MOS tube M13; the drain of the twelfth MOS tube M12 is connected to the drain of the sixteenth MOS tube M16;

[0052] The drain of the thirteenth MOS tube M13 is connected to the source of the fourteenth MOS tube M14; the drain of the fourteenth MOS tube M14 is connected to the drain of the nineteenth MOS tube M19;

[0053] The gate of the fifteenth MOS tube M15 is connected to the second output end of the bias circuit and the gate of the sixteenth MOS tube M16; the source of the fifteenth MOS tube M15 is connected to the drain of the seventeenth MOS tube M17, the gate of the seventeenth MOS tube M17 and the gate of the eighteenth MOS tube M18;

[0054] The source of the sixteenth MOS tube M16 is connected to the drain of the eighteenth MOS tube M18 and the first output end of the operational amplifier input pair tube module; the source of the eighteenth MOS tube M18 is connected to the source of the twelfth MOS tube M12 and the source of the seventeenth MOS tube M17; the source of the nineteenth MOS tube M19 is connected to the drain of the twentieth MOS tube M20 and the second output end of the operational amplifier input pair tube module.

[0055] In addition, the negative voltage clamp operational amplifier AMP also includes a power supply voltage module:

[0056] The power supply voltage module includes: bias voltage ports, VBP0, VBP1, VBN0 and VBN1;

[0057] Input voltage port, VIP and VIN; output voltage port VOUT;

[0058] The power supply voltage port VBP0 is connected to the gate of the eleventh MOS tube M11; the power supply voltage port VBP1 is connected to the gate of the fourteenth MOS tube M14; the power supply voltage input terminal VBN1 is connected to the gate of the nineteenth MOS tube M19; the power supply voltage input terminal VBN0 is connected to the gate of the twentieth MOS tube M20;

[0059] The input voltage port VIP is connected to the gate of the first MOS tube M1, the gate of the second MOS tube M2, the gate of the third MOS tube M3, the gate of the fourth MOS tube M4 and the gate of the fifth MOS tube M5; the input voltage port VIN is connected to the gate of the sixth MOS tube M6;

[0060] The output voltage port VOUT is connected to the drain of the fourteenth MOS tube M14 and the drain of the nineteenth MOS tube M196;

[0061] In addition, the bias current input terminal IBP of the negative voltage clamp operational amplifier AMP is connected to the input terminal of the bias circuit module.

[0062] The specific detection method is: the comparator COMP is used as a load detection comparator to compare the detection voltage VI and the load detection threshold voltage VTH to determine the connection status of the external load. A clamping op amp AMP is added to the circuit to form a negative feedback loop so that when a negative voltage is detected, the VI voltage is reduced, VO can be clamped at a fixed value, and the circuit detects negative voltage normally; among them, when the detection voltage at the load voltage input terminal DSGD is a positive voltage, VI is a positive voltage, the op amp AMP does not work, and VO outputs a high level. At this time, the third MOS tube M3 is cut off, and the current flows from the DSGD port to the ground through the loop composed of R2-R3-M2-R4-M5; if the detection voltage at the load voltage input terminal DSGD is a negative voltage, VI is a negative value, and the negative voltage clamp The operational amplifier AMP works, the VO potential is pulled down, and the third MOS tube M3 is turned on. As the voltage value of the load voltage input terminal DSGD gradually decreases, VI decreases, and VO decreases. The voltage VGS of the third MOS tube M3 increases, and the current flowing through it increases. The increased current produces a voltage drop at R4, which increases the VI potential and VO increases, forming a negative feedback. At this time, there is a current regulation loop composed of VPP-R1-M1-M3-M2-R3-R2 in the circuit. Finally, the VI value tends to be stable, and VO always maintains a fixed value due to the clamping effect.

[0063] In summary, the positive and negative voltage load detection circuit provided in this embodiment introduces a negative voltage clamping operational amplifier AMP to form a negative feedback loop, reduces the input voltage VI during the negative voltage detection process, and clamps the output voltage VO at a preset fixed value, thereby realizing a load detection circuit design that can detect positive and negative voltages at the same time on the chip, thereby saving design costs, reducing design area and making it easier and more convenient for ordinary users to use.

[0064] The above embodiments only express one or several implementation modes of the present invention, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the invention patent. It should be pointed out that, for those of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present invention, and these all belong to the protection scope of the present invention. Therefore, the protection scope of the patent of the present invention shall be subject to the attached claims.

Claims

1. A positive and negative voltage load detection circuit applied to BMS, characterized in that: include: Clamping circuit module, load voltage module, comparator module; The clamping circuit module includes: a load clamping operational amplifier AMP, a capacitor C1, a third MOS tube M3, a resistor R4 and a fifth MOS tube M5; The input end of the clamp circuit and the input end of the comparator module are connected to the output end of the load voltage module; The positive input end of the load clamp operational amplifier AMP is connected to the gate of the third MOS tube M3 and the upper plate of the capacitor C1; the drain of the third MOS tube M3 and the lower plate of the capacitor C1 are connected to one end of the resistor R4; the other end of the resistor R4 is connected to the drain of the fifth MOS tube M5; the gate of the fifth MOS tube M5 is connected to the enable end; the source of the fifth MOS tube M5 is grounded.

2. A positive and negative voltage load detection circuit for BMS according to claim 1, characterized in that: The load voltage module includes: a load voltage port DSGD, a load voltage port VPP, a resistor R2, a resistor R3 and a second MOS tube M2; The load voltage port DSGD is connected to one end of the resistor R2; the other end of the resistor R2 is connected to one end of the resistor R3; the other end of the resistor R3 is connected to the drain of the second MOS tube M2; the gate of the second MOS tube M2 is connected to the analog power port AVDD.

3. A positive and negative voltage load detection circuit for BMS as claimed in claim 2, characterized in that: The load voltage module further includes: a load voltage port VPP, a resistor R1 and a first MOS tube M1; The load voltage port VPP is connected to one end of the resistor R1 ; the other end of the resistor R1 is connected to the drain of the first MOS transistor M1 ; the gate of the first MOS transistor M1 is connected to the analog power supply AVDD.

4. A positive and negative voltage load detection circuit for BMS according to claim 1, characterized in that: The comparator module comprises: a comparator COMP, a load detection output terminal LOAD_DET and a fourth MOS tube M4; The gate of the fourth MOS transistor M4 is connected to the enable terminal; the source of the fourth MOS transistor M4 is connected to the positive input terminal of the comparator COMP; the output terminal of the comparator COMP is connected to the load detection output terminal LOAD_DET.

5. A positive and negative voltage load detection circuit for BMS according to claim 1, characterized in that: The negative input terminal of the comparator COMP is used to store the load detection threshold voltage VTH.

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