A method for testing trap density of heterogeneous semiconductor devices based on threshold voltage variation

Abstract

The present invention discloses a method for testing the trap density of heterogeneous semiconductor devices based on threshold voltage changes, and relates to the field of trap testing and reliability assessment of power semiconductor devices. The method comprises: connecting the device under test to a transient threshold voltage test circuit; applying a negative gate voltage to the device during the trap filling process; applying a test current to the source and drain sections of the device during the trap test process to obtain the source-drain voltage change, which is the threshold voltage change; and simultaneously utilizing a structure function to process the threshold voltage change caused by each trap, and calculating the trap density of each trap. The present invention implements transient threshold voltage testing and trap density calculation of heterogeneous semiconductor devices through circuit design. The method can be applied to trap density testing of heterogeneous semiconductor devices from different sources and has good universality.

Description

Technical Field

[0001] The present invention relates to threshold voltage testing and trap density characterization of heterogeneous semiconductor devices, and belongs to the field of power semiconductor device testing and reliability. Background Art

[0002] GaN material has a large band gap (3.4eV), a high breakdown electric field (3.3MV / cm), and a high electron mobility (2000cm 2 Due to its characteristics such as high current density (V / s), it can be applied in high-voltage, high-temperature, and high-power applications. To meet the safety requirements of practical applications, enhancement-mode GaN-based HEMTs are typically fabricated using a p-GaN gate, based on depletion-mode devices. This allows the two-dimensional electron gas beneath the gate to be depleted at zero bias, ensuring effective device shutdown. While p-GaN-based HEMTs have a wide range of applications in power switching, their unstable threshold voltage remains a key factor hindering the reliability of p-GaN-based devices.

[0003] The gate structure of p-GaN-based HEMTs is relatively complex, and gate bias voltage can cause electron or hole traps to capture carriers, leading to threshold voltage drift. The threshold voltage variation of p-GaN-based devices under positive gate voltage has been widely reported. In reality, the threshold voltage of p-GaN-based HEMTs is relatively low and may shift under stress. A negative gate voltage is typically applied to the device to ensure complete shutdown and avoid false turn-on in switching applications. Furthermore, the threshold voltage drift of p-GaN HEMTs under gate bias has been extensively studied. Researchers typically use pulse transfer characteristics testing to characterize the static variation of the threshold voltage under different gate voltages. However, effective characterization of the transient variation of the threshold voltage after the voltage bias is removed remains lacking. Therefore, further development of testing techniques is needed to characterize the transient variation of the threshold voltage of p-GaN HEMTs under gate stress, as well as to further obtain information on the trap density that causes the threshold voltage variation.

[0004] This technology proposes a method for testing trap density in heterogeneous semiconductor devices based on threshold voltage variation. This method is applied to assess transient threshold voltage variations and calculate trap density in heterogeneous semiconductor devices after gate stress removal. It enables accurate, rapid, and non-destructive characterization of trap parameters, providing a reference for improving device gate reliability. This technology can be applied to transient threshold voltage variation and trap density testing of heterogeneous semiconductor devices from various sources, demonstrating broad applicability. Summary of the Invention

[0005] The present invention discloses a method for testing the trap density of a heterojunction semiconductor device based on the change in threshold voltage. By circuit design, the source-drain voltage Vsd of the heterojunction semiconductor device is tested to obtain the transient threshold voltage change ΔVth, and the change in threshold voltage caused by each hole trap is analyzed to calculate and obtain the trap density. The main inventive points of the present invention are: designing a test circuit for the transient threshold voltage change of a heterojunction semiconductor device, which can quickly obtain the change in the device threshold voltage caused by traps under a negative gate voltage through the source-drain voltage Vsd; and at the same time, proposing a method for calculating the trap density of a heterojunction semiconductor device based on the change in threshold voltage, providing an effective characterization technology for the trap effect and reliability assessment of heterojunction semiconductor devices.

[0006] A method for testing the trap density of a heterojunction semiconductor device based on the change in threshold voltage, comprising:

[0007] 1. Connect the device under test to a gate resistor Rg, a gate driver, a gate voltage source, and a drain current source. Among them, the gate driver is connected to the device under test through the gate resistor Rg and provides a gate drive; the gate resistor Rg is used to limit the gate current to protect the circuit, and the range of the gate resistor Rg is 1 < Rg < 50 Ω; the gate voltage source is connected to the gate driver and the device under test and provides a gate-source voltage for the device under test; the drain current source is connected to the device under test, the gate driver, and the gate voltage source and provides a source-drain current for the device under test.

[0008] 2. During the trap filling process, a gate filling voltage Vgf is provided by the gate voltage source, and the filling time is tf; where the range of the gate filling voltage Vgf is -1V ≤ Vgf ≤ -10V, and the range of the filling time tf is 10 ms ≤ tf ≤ 200 s. After the filling time tf ends, the drain current source provides a test current Isense, and the test time is tm; where the range of the test current Isense is 1 mA ≤ Isense ≤ 10 mA, and the range of the test time tm is 1 s ≤ tm ≤ 1000 s. The test current Isense flows through both ends of the source and drain of the device, and the transient source-drain voltage change Vsd of the device is collected in real time, which is the threshold voltage change ΔVth of the device under test. The acquisition accuracy of the transient source-drain voltage can reach 4 ms. Under the condition of a negative filling gate voltage, the threshold voltage shifts negatively, indicating that holes inside the device are captured by traps under a negative gate voltage.

[0009] 3. Based on the transient threshold voltage change ΔVth, a time constant spectrum is constructed using the structure function method. The number of trap peaks N is identified from the threshold voltage change, indicating that there are N hole traps inside the device under the condition of Vgf, where the range of N is 1 ≤ N ≤ 10. The N hole trap peaks are sequentially named H1, H2,... HN in ascending order of the time constant ti, where 1 ≤ i ≤ N; the time constants of the corresponding hole traps can be read from the horizontal axis of the time constant spectrum, which are t1, t2,... tN.

[0010] 4. Add the vertical axis values ​​of the time constant spectrum, swap them with the horizontal axis, and perform a differential calculation to construct the differential amplitude spectrum. The difference between the N peaks corresponding to the horizontal axis represents the threshold voltage change ΔVthi caused by the N traps H1, H2, ..., HN. The specific threshold voltage change caused by the i-th trap Hi under Vgf conditions is expressed as the absolute value of |ΔVthi|, where 0.001V≤|ΔVthi|≤1V.

[0011] 5. Calculate the trap density nti based on |ΔVthi|: (2ε|ΔVthi|) / (qd). ε is the GaN dielectric constant, q is the charge, and d is the depletion layer thickness, where d is in the range of 10nm≤d≤25nm. The trap density nti for each trap can be calculated based on the change in threshold voltage caused by N traps under Vgf voltage, |ΔVthi|, where 1E12≤nti≤1E17.

[0012] This invention proposes, for the first time, a method for testing the trap density of heterogeneous semiconductor devices based on threshold voltage variations. This method effectively captures the transient threshold voltage curve and extracts the threshold voltage variation caused by each trap, thereby effectively characterizing the trap density within the device. The invention has the beneficial effect of being simple, fast, and easy to operate. It can effectively evaluate the threshold voltage variation of heterogeneous semiconductor devices under different gate voltages, providing a simple and convenient characterization method for analyzing the trap characteristics of heterogeneous semiconductor devices. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] Figure 1 : This is a connection diagram of the test circuit involved in the present invention, in which: 1-p-GaN HEMT device, 2-gate resistor, 3-gate driver, 4-gate voltage source, 5-drain current source.

[0014] Figure 2 : The threshold voltage change curve of the device under negative gate voltage involved in the present invention.

[0015] Figure 3 : Time constant spectrum constructed based on threshold voltage variation under negative gate voltage.

[0016] Figure 4 : Differential amplitude spectrum constructed based on threshold voltage variation under negative gate voltage.

[0017] Figure 5 : Trap amplitude in p-GaN HEMT under negative gate voltage based on differential amplitude spectrum.

[0018] Figure 6 : Trap density in p-GaN HEMT under negative gate voltage based on differential amplitude spectrum. DETAILED DESCRIPTION

[0019] The following is an example of trap density testing of heterogeneous semiconductor devices based on threshold voltage variation. An EPC2010C p-GaN HEMT manufactured by EPC Corporation is selected as the device under test 1, with a maximum operating voltage of 200 V and a maximum operating current of 22 A. The method of the present invention includes the following steps:

[0020] Step 1: Connect the 1-p-GaN HEMT device to the test circuit, as shown in the following diagram: Figure 1 As shown in the figure, the 1-p-GaN HEMT device is connected to 2-gate resistor Rg, 3-gate drive, 4-gate voltage source, and 5-drain current source. Among them, 3-gate drive is connected to the 1-p-GaN HEMT through 2-gate resistor Rg and provides gate drive for the device under test. 2-gate resistor Rg is 1Ω and is used to limit the gate current. 4-gate voltage source is connected to 3-gate drive and the 1-p-GaN HEMT device and provides gate-source voltage for the device under test. 5-drain current source is connected to the 1-p-GaN HEMT device, 3-gate drive, and 4-gate voltage source and provides source-drain current for the device under test.

[0021] Step 2: During the trap filling process, the 4-gate voltage source provides a gate filling voltage Vgf of -4V, and the filling time tf is 15s. After the filling time tf ends, the 5-drain current source provides a test current Isense of 10mA during the trap test process, and the test time tm is 500s. At this time, the test current Isense flows through the source and drain of the device, and the real-time acquisition of the device's transient source-drain voltage change Vsd is the threshold voltage change ΔVth of the device under test. The acquisition accuracy of the transient source-drain voltage can reach 4ms, and the results are as follows: Figure 2 When Vgf is -4V, the threshold voltage shifts negatively, indicating that holes are trapped inside the device under negative gate voltage. The captured transient threshold voltage change ΔVth = -0.07639 is a negative value.

[0022] Step 3: Based on the transient threshold voltage change ΔVth, use the structure function method to construct the time constant spectrum as follows Figure 3 As shown in the figure, the number of trap peaks N = 3 was identified from the threshold voltage change, indicating that there are three hole traps inside the device under the condition of Vgf of -4V. The three hole trap peaks are named H1, H2, and H3 in descending order according to the time constant ti, and their time constants ti are t1 = 0.024s, t2 = 2.184s, and t3 = 137.89s, respectively.

[0023] Step 4: Figure 3 The vertical axis values ​​of the time constant spectrum shown are added and then exchanged with the horizontal axis and differential calculation is performed to construct the differential amplitude spectrum as shown in Figure 4 As shown. Among them, the difference between the three peaks corresponding to the horizontal axis is the threshold voltage change ΔVthi caused by the three hole traps H1, H2, and H3. The specific test results are expressed in the form of the absolute value of |ΔVthi| as follows Figure 5 As shown, under the condition of Vgf of -4V, the absolute value of the threshold voltage change caused by H1 trap filling |ΔVth1| is 0.0348V, the threshold voltage change caused by H2 trap filling |ΔVth2| is 0.01552V, and the threshold voltage change caused by H3 trap filling |ΔVth3| is 0.02607V.

[0024] Step 5: Calculate the trap density nti based on |ΔVthi| = (2ε|ΔVthi|) / (qd), where ε is the GaN dielectric constant, q is the charge, and d is the depletion layer thickness. The trap density can be calculated based on the threshold voltage changes caused by the three traps obtained in step 4. The results are as follows: Figure 6 shown.

Claims

1. A method for testing the trap density of heterogeneous semiconductor devices based on threshold voltage variation, characterized by: 1) Connecting the heterogeneous semiconductor device under test to a gate resistor Rg, a gate driver, a gate voltage source, and a drain current source; wherein the gate driver is connected to the heterogeneous semiconductor device under test through the gate resistor Rg and provides gate drive for the device under test; the gate resistor Rg is used to limit the gate current to protect the circuit; the gate voltage source is connected to the gate driver and the heterogeneous semiconductor device under test and provides a gate-source voltage for the heterogeneous semiconductor device under test; the drain current source is connected to the device under test, the gate driver, and the gate voltage source and provides a source-drain current for the heterogeneous semiconductor device under test; 2) During the trap filling process, a gate voltage source provides a gate filling voltage Vgf for a filling time of tf. After the filling time tf, a drain current source provides a test current Isense for a test time of tm. The test current Isense flows through the source and drain of the device, and the device's transient source-drain voltage change Vsd is collected in real time, which is the threshold voltage change ΔVth of the heterogeneous semiconductor device under test. 3) Based on the transient threshold voltage change ΔVth, a time constant spectrum is constructed using the structure function method. The number of trap peaks N is identified from the transient threshold voltage change, indicating that there are N hole traps inside the heterogeneous semiconductor device under Vgf conditions. The N hole trap peaks are named H1, H2, ...HN in order from small to large according to the time constant ti, where 1≤i≤N. The time constants of the corresponding hole traps are read from the horizontal axis of the time constant spectrum as t1, t2, ...tN. 4) Add the vertical axis values ​​of the time constant spectrum, swap them with the horizontal axis, and perform differential calculations to construct a differential amplitude spectrum, where the difference between the N peaks corresponding to the horizontal axis is the threshold voltage change ΔVthi caused by the N traps H1, H2, ...HN. The specific threshold voltage change caused by the i-th trap Hi under the Vgf condition is expressed as the absolute value of |ΔVthi|; 5) Calculate each trap density nti based on the threshold voltage change |ΔVthi| caused by N traps under Vgf voltage; Each trap density nti=(2ε|ΔVthi|) / (qd) is directly calculated based on |ΔVthi|, where ε is the GaN dielectric constant, q is the charge, and d is the depletion layer thickness.

2. The method for testing the trap density of a heterogeneous semiconductor device based on threshold voltage variation according to claim 1, wherein: In the threshold voltage transient test, the test current Isense flows through the source and drain of the device, and the range of the test current Isense is 1 mA ≤ Isense ≤ 10 mA; The threshold voltage change ΔVth of the heterogeneous semiconductor device under test is obtained by real-time acquisition of the transient source-drain voltage change Vsd of the p-GaN HEMT device, and the gate resistance Rg in the threshold voltage test circuit is in the range of 1 <Rg<50 Ω。 3. The method for testing the trap density of a heterogeneous semiconductor device based on threshold voltage variation according to claim 1, wherein: The trap filling type can be determined based on the threshold voltage change ΔVth of the device under test; where ΔVth<0 indicates a negative shift in the threshold voltage, and holes inside the heterogeneous semiconductor device under test are trapped; ΔVth>0 indicates a positive shift in the threshold voltage, and electrons inside the heterogeneous semiconductor device under test are trapped.

4. The method for testing trap density of heterogeneous semiconductor devices based on threshold voltage variation according to claim 1, wherein: The range of gate filling voltage Vgf is -1 V≤Vgf≤-10 V, the range of filling time tf is 10 ms≤tf≤200s, the range of test time tm is 1 s≤tm≤1000 s, and the acquisition accuracy of transient source-drain voltage is 4 ms.

5. The method for testing trap density of heterogeneous semiconductor devices based on threshold voltage variation according to claim 1, wherein: The structure function method is used to identify trap peaks in transient threshold voltage changes of heterogeneous semiconductor devices, where the number of trap peaks N is in the range of 1≤N≤10; the trap time constant ti can be read from the peak horizontal coordinate, where i is in the range of 1≤i≤N.

6. The method for testing trap density of heterogeneous semiconductor devices based on threshold voltage variation according to claim 1, characterized in that: Based on the difference between the peak values ​​in the differential amplitude spectrum, the transient threshold voltage change ΔVthi caused by each trap is directly read, where 0.001 V ≤ |ΔVthi| ≤ 1 V.

7. The method for testing trap density of heterogeneous semiconductor devices based on threshold voltage variation according to claim 1, wherein: The range of d is 10 nm≤d≤25 nm, and the range of trap density nti is 1E12≤nti≤1E17.

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