A CNTFET trap characterization method based on transient drain-source current response

Abstract

The present invention discloses a CNTFET trap characterization method based on transient drain-source current response, which belongs to the field of semiconductor device reliability. It includes: a gate fill voltage interval in a given trap filling phase; a test voltage condition in a given trap test phase; a test time range and accuracy of a transient current response in a given trap test phase; and a test range of a given trap energy level and time constant. A certain gate fill voltage is applied to the CNTFET to fill the hole trap, and the transient current response curve at both ends of the CNTFET drain and source under the gate and drain test voltages is collected. The time constant spectrum of the hole trap is established through Bayesian deconvolution, and the time constant parameters of the trap inside the CNTFET are extracted. The test is repeated under multiple sets of temperature conditions to obtain the change in the trap time constant, and the CNTFET trap energy level parameters are calculated using the Arrhenius formula. The method involved in this patent is simple and convenient to operate, can be applied to CNTFET devices from various sources, and can achieve accurate, non-destructive, and in-situ characterization of CNTFET trap parameters.

Description

Technical Field

[0001] The present invention relates to electrical characteristic testing and trap parameter characterization of carbon nanotube field effect transistors (CNTFETs), and belongs to the field of reliability testing of novel semiconductor devices. Background Art

[0002] Carbon nanotube electronic devices, with their advantages of low power consumption, small size, and high mobility, have great potential to break through Moore's Law. With the continuous development and maturity of carbon-based electronic technology, its practical application and industrialization are beginning to see the light of day. In particular, applications in submicron waves and high-performance thin films are expected to achieve significant progress, further addressing the application limitations of traditional semiconductor devices. The reliability of carbon-based electronic devices is a key issue driving their application development. The trap effect is a key factor affecting the reliability of carbon nanotube field-effect transistors (CNTFETs) under stress conditions such as irradiation and voltage. Compared to common interface states such as Si / SiO2 and SiC / SiO2, the interface state density of CNTFETs can be approximately one to two orders of magnitude higher. Currently, the gate structure of carbon-based devices is immature. The mismatch between the quasi-one-dimensional carbon tube channel and the three-dimensional gate dielectric lattice structure can lead to complex interface state problems, resulting in hysteresis, reduced device mobility, and unstable threshold voltage, posing serious risks to the application of carbon-based devices and integrated circuits.

[0003] Currently, the main methods for characterizing the trap effect of CNTFETs include hysteresis curve testing, pulse transfer characteristics testing, noise characteristics testing, and time domain curve testing. Among them, hysteresis curves and pulse transfer characteristics can intuitively reflect the impact of traps on the electrical characteristics of the device under test. However, detailed analysis of trap characteristics and their location distribution has not yet been achieved. Low-frequency noise testing (LFN), random telegraph noise, and 1 / f noise testing methods can be used to obtain the energy level of traps within CNTFETs. However, the corresponding noise characteristics testing makes it difficult to eliminate the errors caused by intrinsic noise, and it is also impossible to fully analyze the location and physical source of the traps. Currently, there is still a lack of accurate and non-destructive characterization methods for CNTFET trap parameters.

[0004] The technology of the present invention proposes a trap parameter testing method based on transient drain-source current response for CNTFET trap characterization. By evaluating the release of CNTFET traps after the gate fill voltage is removed, the trap time constant and energy level information are obtained, thereby achieving accurate, non-destructive, and in-situ characterization of the internal trap parameters of CNTFET, providing a basis for analyzing the CNTFET trap effect under different stress conditions. Summary of the Invention

[0005] CNTFET interface traps and gate dielectric traps can cause reliability issues such as threshold voltage drift and increased hysteresis window. Under various stresses, including electrical, thermal, and radiation stresses, the reliability issues caused by CNTFET trap effects are becoming increasingly prominent. The generation and increase of defects and traps can lead to device performance degradation and failure. Currently proposed methods, such as pulse transfer characteristics testing and noise characteristics testing, struggle to achieve accurate, non-destructive, and in-situ characterization of CNTFET trap parameters. To address this issue, we use the transient drain-source current response curve of CNTFETs under electrical bias to analyze parameters such as the time constant and energy level of CNTFET internal traps, accurately analyze the CNTFET trap filling mechanism under gate bias, and obtain accurate trap information.

[0006] The technical solution adopted by the present invention is a CNTFET trap characterization method based on transient drain-source current response. The specific implementation process is as follows:

[0007] S1. Set the constant temperature platform within the probe station to T. In this step, the T setting range is 20°C ≤ T ≤ 30°C. This allows the device under test to be evaluated for changes in drain-source current over time at room temperature. Next, place the CNTFET device under test on the constant temperature platform within the probe station. Connect the CNTFET device to the corresponding interface of the B1500 semiconductor parameter analyzer using three probes. This allows for easy and convenient trap testing of the device under test using existing test equipment, eliminating the need for a complex test platform.

[0008] S2. Place the device on a constant temperature platform at a temperature of T without power and keep it still for t d minutes, where the range of the standing time is 10 min≤t d ≤20 min, the device is in the initial state without being affected by electrical stress, and the device temperature is consistent with the set constant temperature platform temperature T.

[0009] S3. Set the test conditions of the semiconductor parameter analyzer B1500. In the trap filling stage, the gate filling voltage V is applied to the CNTFET device under test. GF To achieve carrier filling, the drain voltage is 0 V and the gate filling voltage V is applied GF The time is t f Among them, V GF The range is -25 V≤V GF ≤15 V, filling time t f The range is 10 s≤t f ≤100 s. During the trap release phase, a gate test voltage V is applied to the CNTFET device under test. GM and drain test voltage V DM ; Wherein the gate test voltage VGM The range is -7 V≤V GM ≤0 V, drain test voltage V DM The range is -1 V≤V DM ≤-0.1 V. Obtain the device drain-source current I in logarithmic form DS The change over time until the drain-source current remains stable, the test time is t m , which is the response curve corresponding to the trap release process. The logarithmic form can be set to log 10, log20, log50 or log100, and the test time t m The range is 10 s≤t m ≤1000 s, the sampling accuracy of transient curve changing with time can reach 10ms.

[0010] S4. Based on the acquired transient current response curve, use Bayesian deconvolution technology to establish the time constant spectrum and identify the trap peak. Set the Bayesian deconvolution fitting order A and the number of iterations B to complete the Bayesian deconvolution and construct the time constant spectrum. The fitting order represents the number of traps inside the device, and its range is 2≤A≤8; the number of iterations represents the data density of the time constant spectrum after the Bayesian deconvolution operation, and its range is 100≤B≤1000. GF and V DF Trap peaks are identified under test conditions, where the horizontal axis corresponding to each peak is the time constant parameter of the CNTFET trap, and the vertical axis corresponding to the peak is the relative amplitude parameter of the CNTFET trap.

[0011] S5. Determine whether the constant temperature platform temperature T is greater than or equal to 70°C at this time. If the constant temperature platform temperature T is less than 70°C, increase the platform temperature by 10°C and repeat steps 2 to 4 until the platform temperature is greater than or equal to 70°C. If the constant temperature platform temperature T is already greater than or equal to 70°C, stop the transient curve test and summarize the time constants of the traps obtained at different temperatures. After the transient curve test is stopped, the corresponding transient current curves under N temperature conditions can be obtained. If the constant temperature platform temperature T is greater than 70°C, obtain the drain-source current response curves under N = 6 temperature conditions; if the constant temperature platform temperature T is equal to 70°C, obtain the drain-source current response curves under N = 5 temperature conditions.

[0012] S6. Based on steps 1 to 5, the trap parameters of the CNTFET at 10°C intervals are obtained. Based on the time constants of the CNTFET traps at N temperature conditions, the Arrhenius formula can be used to draw the Arrhenius diagram. The horizontal axis of the Arrhenius diagram is ln(T 2t), where T is the temperature; t is the trap time constant, which ranges from 10 ms ≤ t ≤ 1000 s. The ordinate of the Arrhenius plot is 1 / kT, where k is the Boltzmann constant and T is the temperature. A linear fit is performed on the data in the Arrhenius plot, and the slope of the fit is the trap energy level, Ea, which ranges from 0.01 eV ≤ Ea ≤ 1 eV.

[0013] The present invention proposes for the first time a CNTFET trap characterization method based on transient drain-source current response. For trap parameter testing of carbon-based devices, this method can obtain the transient drain-source current response of the device under test at a certain fill voltage, thereby achieving accurate, non-destructive, and in-situ CNTFET trap parameter extraction. The beneficial effects of the present invention are: the characterization method described in the present invention is simple and fast, the test steps are easy to operate, and the test voltage conditions involved in the present invention are adjustable. It is applicable to trap testing of CNTFET devices from different sources, providing an accurate and convenient characterization method for trap testing and reliability assessment of carbon-based devices. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] Figure 1 : Schematic diagram of the device electrical testing device involved in the present invention, in which: 1-CNTFET device, 2-constant temperature platform, 3-high and low temperature probe station, 4-Keysight B1500 semiconductor parameter tester.

[0015] Figure 2 : Flowchart of device testing involved in the present invention.

[0016] Figure 3 : The device trap test timing diagram involved in the present invention.

[0017] Figure 4 : Drain-source current response curves at different temperatures.

[0018] Figure 5 : Trap time constant parameter test results.

[0019] Figure 6 : Trap energy level parameter test results. DETAILED DESCRIPTION

[0020] The present invention will be described in more detail below with reference to the accompanying drawings and specific embodiments.

[0021] Taking CNTFET device as an example, the device electrical testing device involved in the present invention is as follows: Figure 1 As shown, it includes a CNTFET device, a constant temperature platform, a high and low temperature probe station and a semiconductor parameter tester, wherein the CNTFET to be tested is a p-type bottom gate CNTFET. The test process of the method involved in the present invention is as follows Figure 2As shown, the following steps are included:

[0022] Step 1: Set the temperature T of the constant temperature platform in the high and low temperature probe station to 30°C, place the CNTFET device on the constant temperature platform in the high and low temperature probe station, and connect the CNTFET device under test to the corresponding interface of the semiconductor parameter analyzer B1500 through the three probes of the high and low temperature probe station to complete the preparation work before electrical testing.

[0023] Step 2: Leave the device alone without power for a period of time t d The device is in an initial state without being affected by electrical stress and its temperature is consistent with the set constant temperature platform temperature.

[0024] Step 3: Set the test conditions of the semiconductor parameter analyzer B1500 and set the gate fill voltage V GF Set to -16 V, drain voltage to 0 V, fill time t f After the 15 s filling phase is completed, the gate test voltage V GM and drain test voltage V DM Set to -5 V and -1 V respectively, and obtain the drain-source current I in log50 form DS The curve changes with time until the drain-source current remains stable. This curve is the response curve corresponding to the trap release process. The test time t m The test sequence is 180 s. Figure 3 As shown in the figure, the measured transient drain-source current curve is as follows Figure 4 shown.

[0025] Step 4: Based on the acquired transient current response curve, use Bayesian deconvolution technology to establish the time constant spectrum and identify the trap peak. Set the fitting order A to 3 times and the number of iterations B to 300 times. The time constant spectrum processing results are as follows: Figure 5 As shown. At V GF -5 V and V DF Three trap peaks H1, H2 and H3 were identified under -1 V test conditions, where the horizontal axis corresponding to each peak is the time constant parameter of the CNTFET trap. Under the temperature condition of 30°C, the three trap time constants are 0.7 s, 8 s and 75 s in ascending order.

[0026] Step 5: Determine whether the constant temperature platform temperature T is greater than or equal to 70°C. If the constant temperature platform temperature is less than 70°C, increase the platform temperature by 10°C and repeat steps 2 to 4. If the constant temperature platform temperature is greater than or equal to 70°C, stop the transient curve test and summarize the time constants of the traps at different temperatures. After the transient curve test is stopped, the constant temperature platform temperature T is equal to 70°C, and the transient drain-source current curves under N=5 temperature conditions are obtained, as shown in the figure. Figure 5 shown.

[0027] Step 6: Based on steps 1 to 5, the trap parameters of CNTFET are obtained under the temperature conditions of 30℃ to 70℃ with an interval of 10℃. Figure 5 The trap time constants of CNTFET under the five temperature conditions shown can be plotted using the Arrhenius formula. Figure 6 As shown, at V GF For -16V filling condition, V GF -5 V and V DF Under the -1 V test condition, the three CNTFET trap energy levels Ea can be identified from the Arrhenius plot by linear fitting, where the trap energy levels of H1, H2 and H3 are 0.190, 0.155 and 0.080 eV, respectively.

Claims

1. A CNTFET trap characterization method based on transient drain-source current response, characterized by: Step 1: Set the temperature of the constant temperature platform in the high and low temperature probe station to T; then, place the CNTFET device under test on the constant temperature platform in the high and low temperature probe station, and connect the CNTFET device to the corresponding interface of the semiconductor parameter analyzer B1500 through three probes to complete the trap test of the device under test; Step 2: Place the CNTFET device under test on a constant temperature platform at a temperature of T without power and keep it still for t d Minutes, the CNTFET device under test is in the initial state without being affected by electrical stress, and the temperature of the CNTFET device under test is consistent with the set constant temperature platform temperature T; Step 3: Set the test conditions of the semiconductor parameter analyzer B1500; in the trap filling stage, apply the gate filling voltage V to the CNTFET device under test. GF To achieve carrier filling, the drain voltage is 0 V and the gate filling voltage V is applied GF The time is t f ; In the trap release phase, a gate test voltage V is applied to the CNTFET device under test GM and drain test voltage V DM ; Obtain the device drain-source current I in logarithmic form DS The change over time until the drain-source current remains stable, the test time is t m , the corresponding curve is the response curve corresponding to the trap release process; Step 4: Based on the acquired transient current response curve, use Bayesian deconvolution technology to establish the time constant spectrum and identify the trap peak; set the Bayesian deconvolution fitting order A and the number of iterations B to complete the Bayesian deconvolution and construct the time constant spectrum; in the set V GF and V DF The trap peaks are identified under the test conditions, where the horizontal axis corresponding to each peak is the time constant parameter of the CNTFET trap, and the vertical axis corresponding to the peak is the relative amplitude parameter of the CNTFET trap; Step 5: Determine whether the constant temperature platform temperature T is greater than or equal to 70°C at this time; if the constant temperature platform temperature T is less than 70°C, increase the platform temperature by 10°C and repeat steps 2 to 4 until the platform temperature is greater than or equal to 70°C; if the constant temperature platform temperature T is already greater than or equal to 70°C, stop the transient curve test and summarize the time constants of the traps obtained at different temperatures; after the transient curve test is stopped, obtain the corresponding transient curves under N temperature conditions; Step 6: Based on steps 1 to 5, the trap parameters of the CNTFET at 10°C intervals are obtained; based on the CNTFET trap time constants at N temperature conditions, the Arrhenius diagram is drawn using the Arrhenius formula; the horizontal axis of the Arrhenius diagram is ln(T 2 t), where T is the temperature condition and t is the trap time constant; the ordinate of the Arrhenius plot is 1 / kT, where k is the Boltzmann constant; a linear fit is performed on the data in the Arrhenius plot, and its slope is the trap energy level Ea.

2. The CNTFET trap characterization method based on transient drain-source current response according to claim 1, characterized in that: In step 1, the setting range of T is 20°C ≤ T ≤ 30°C to evaluate the change of the drain-source current of the CNTFET device under test at room temperature over time.

3. The CNTFET trap characterization method based on transient drain-source current response according to claim 1, characterized in that: In step 2, the standing time t d The range is 10 min≤t d ≤20 min, and the standing time t d The device is in an unpowered state during the corresponding time.

4. The CNTFET trap characterization method based on transient drain-source current response according to claim 1, characterized in that: In step 3, the gate filling voltage V GF The range is -25 V≤V GF ≤15 V, filling time t f The range is 10 s≤t f ≤100 s; Gate test voltage V GM The range is -7 V≤V GM ≤0 V, drain test voltage V DM The range is -1 V≤V DM ≤-0.1 V.

5. The CNTFET trap characterization method based on transient drain-source current response according to claim 1, characterized in that: In step 3, the transient drain-source current is obtained in logarithmic form, where the logarithmic form is set to log10, log20, log50 or log100, and the test time t m The range is 10 s≤t m ≤1000 s, the sampling accuracy of transient curve changing with time is 10 ms.

6. The CNTFET trap characterization method based on transient drain-source current response according to claim 1, characterized in that: In step 4, the time constant spectrum is constructed using Bayesian iteration, where the fitting order represents the number of traps inside the device, and its range is 2≤A≤8; the number of iterations represents the data density of the time constant spectrum after the Bayesian deconvolution operation, and its range is 100≤B≤1000.

7. The CNTFET trap characterization method based on transient drain-source current response according to claim 1, characterized in that: In step 5, N is the number of temperature conditions. After the transient curve test stops, if the constant temperature platform temperature T is greater than 70°C, then N=6; if the constant temperature platform temperature T is equal to 70°C, then N=5.

8. The CNTFET trap characterization method based on transient drain-source current response according to claim 1, characterized in that: In step 6, the range of the trap time constant is 10 ms≤t≤1000 s, and the range of the trap energy level obtained using the Arrhenius diagram is 0.01 eV≤Ea≤1 eV.

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