Chip testing method, electronic equipment, readable storage medium and program product

Abstract

The invention relates to a chip testing method, electronic equipment, a readable storage medium and a program product. The method comprises the following steps: sending a synchronization request signal to a fault injection system and requesting to inject a fault pulse; starting to operate a fault response program, and receiving a fault pulse injected by a fault injection system in the process of operating the fault response program; wherein the operation of the fault response program comprises the following steps of: performing sequential operation on each module internally integrated with a data verification and correction function, and performing data verification on each module under the action of a fault pulse; and if the first data verification result is abnormal under the action of the fault pulse, resetting after responding to a reset signal sent by the fault injection system, sending the reset first data verification result to the fault injection system, and taking the first data verification result as an abnormal data verification result. By adopting the method, the problem that in a hardware fault injection method, the method is difficult to be used for ECC function verification under high-energy fault injection can be solved.

Description

Technical Field

[0001] The present application relates to the field of chip testing technology, and in particular to a chip testing method, electronic equipment, readable storage medium and program product. Background Art

[0002] In the field of functional safety, Error-Correcting Code (ECC) technology plays a vital role. By using ECC technology, system failures and performance degradation caused by data errors can be significantly reduced. Therefore, ECC technology is widely used in computer memory, storage devices and communication systems, and is a key technology for achieving functional safety. Specifically at the chip level, ECC technology is applied to the chip's built-in memory and CAN communication module.

[0003] Generally, the fault injection test method is used to verify the function of the chip's ECC mechanism. The fault injection test method is to inject faults into the memory or communication module with integrated ECC function in the chip, thereby causing single-bit errors or multi-bit errors. After the fault is injected, the chip reads or receives data and performs ECC data verification on the data to verify that ECC implements its single-bit error correction and multi-bit error detection functions. The hardware fault injection method (such as electromagnetic fault injection and laser fault) in the fault injection test method has high spatial accuracy and can be used for ECC functional verification.

[0004] Since there are often more than one module with integrated ECC function in the chip, usually including multiple types of memories and CAN communication modules, it is necessary to ensure that the fault injection test fully covers the functional verification of the modules with integrated ECC function in the chip. If the energy of the fault injection is low, the fault injection test may only cause a single type of bit error, or only cause bit errors in some ECC functional modules. At this time, it is difficult for the fault injection test to fully cover the functional verification of all modules with integrated ECC function in the chip. If the energy of the fault injection is high, the chip will be affected by the high-energy fault injection, unable to work normally or even crash, and difficult to use for ECC functional verification. Therefore, how to solve the problem of hardware fault injection method that is difficult to use for ECC functional verification under high-energy fault injection still needs to be considered. Summary of the invention

[0005] Based on this, it is necessary to provide a chip testing method, electronic device, readable storage medium and program product that can solve the problem of hardware fault injection method being difficult to use for ECC functional verification under high-energy fault injection in response to the above technical problems.

[0006] In a first aspect, the present application provides a chip testing method, which is applied to a chip, comprising:

[0007] In response to a start command sent by the fault injection system, sending a synchronization request signal to the fault injection system and requesting injection of a fault pulse;

[0008] If the synchronization confirmation signal sent by the fault injection system is received, the fault response program is started to run, and the fault pulse injected by the fault injection system is received during the process of starting to run the fault response program; wherein the running of the fault response program includes: sequentially operating each module with data verification and correction functions integrated therein, and performing data verification on each module under the action of the fault pulse;

[0009] After running the fault response program, the data verification result is sent to the fault injection system; wherein, if an abnormality occurs under the action of the fault pulse, the system is reset after responding to the reset signal sent by the fault injection system, and the first data verification result after the reset is sent to the fault injection system, with the first data verification result being the data verification result when the abnormality occurs.

[0010] In one embodiment, each module includes a memory and a communication module, and before sending a synchronization request signal to the fault injection system for the first time, the method further includes:

[0011] Performing a read operation on the memory, and then performing an operation of reading a receiving buffer on the communication module;

[0012] Performing data verification on the memory when performing the read operation, and performing data verification on the communication module when performing the read buffer operation, and sending the data verification results of the memory and the data verification results of the communication module to the fault injection system;

[0013] Resetting after receiving a reset signal sent by the fault injection system, wherein the reset signal is generated by the fault injection system when the data verification result represents a chip abnormality.

[0014] In one embodiment, after sending the data verification result to the fault injection system, the method further includes:

[0015] The step of responding to the start command sent by the fault injection system and sending the data verification result to the fault injection system is repeatedly performed until the number of fault pulses injected by the fault injection system reaches the target number.

[0016] In one embodiment, sending a synchronization request signal to the fault injection system includes:

[0017] Sending a synchronization request signal to the fault injection system via a first pin;

[0018] The receiving of the synchronization confirmation signal sent by the fault injection system comprises:

[0019] A synchronization confirmation signal sent by the fault injection system is received through the second pin.

[0020] In a second aspect, the present application further provides a chip testing method, which is applied to a fault injection system, and the method comprises:

[0021] Sending a start command to the chip under test, and receiving a synchronization request signal sent by the chip under test;

[0022] In response to the synchronization request signal, sending a synchronization confirmation signal to the chip under test;

[0023] In the process of the chip under test running the fault response program, injecting a fault pulse into the chip under test, wherein the running of the fault response program includes: sequentially operating each module with data verification and correction functions integrated therein, and performing data verification on each module under the action of the fault pulse;

[0024] Receive the data verification result sent by the chip under test, wherein, when the chip under test is abnormal under the action of the fault pulse, send a reset signal to the chip under test, and use the first data verification result received after the chip under test is reset as the data verification result when the chip under test is abnormal.

[0025] In one of the embodiments, before receiving the synchronization request signal sent by the chip under test for the first time, the method further includes:

[0026] Receiving a data verification result of a memory in the chip under test and a data verification result of a communication module in the chip under test;

[0027] When the data verification result of the memory or the data verification result of the communication module indicates that the chip under test is abnormal, sending a reset signal to the chip under test;

[0028] The receiving a synchronization request signal sent by the chip under test comprises:

[0029] When the data verification result of the memory and the data verification result of the communication module indicate that the chip under test is normal, a synchronization request signal sent by the chip under test is received.

[0030] In one embodiment, the method further comprises:

[0031] The steps of sending a start command to the chip under test and receiving a data verification result sent by the chip under test are repeatedly performed until the number of fault pulses injected into the chip under test reaches a target number.

[0032] In a third aspect, the present application further provides an electronic device, comprising a memory and a processor, wherein the memory stores a computer program, and when the processor executes the computer program, it implements the chip testing method provided in the first aspect or the chip testing method provided in the second aspect.

[0033] In a fourth aspect, the present application further provides a computer-readable storage medium having a computer program stored thereon, wherein when the computer program is executed by a processor, the chip testing method provided in the first aspect or the chip testing method provided in the second aspect is implemented.

[0034] In a fifth aspect, the present application also provides a computer program product, including a computer program, which, when executed by a processor, implements the chip testing method provided in the first aspect or implements the chip testing method provided in the second aspect.

[0035] The above-mentioned chip testing method, electronic device, readable storage medium and program product do not need to rely on the unique fault injection circuit or special circuit inside the chip, and the hardware fault is injected from the outside of the chip to perform ECC function verification through the fault injection system. When the chip works abnormally or even crashes and it is difficult to verify the ECC function, the chip is reset through the fault injection system, and the first data verification result after the reset is used as the data verification result when the chip is abnormal. Therefore, it can solve the problem that the chip works abnormally or even crashes under the influence of high-energy hardware fault injection and is difficult to use for ECC function verification, and realize the ECC function verification of the chip by the hardware fault injection method. In addition, the single-bit error detection, double-bit and above error detection functions of ECC and the single-bit error correction function of ECC can be verified, and the functional verification of the module with integrated ECC function in the chip can be fully covered. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] In order to more clearly illustrate the technical solutions in the embodiments of the present application or related technologies, the drawings required for use in the embodiments of the present application or related technical descriptions will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other related drawings can be obtained based on these drawings without paying creative work.

[0037] Figure 1 An application environment diagram of a chip testing method in an embodiment;

[0038] Figure 2A schematic diagram of a chip testing method according to an embodiment of the present invention;

[0039] Figure 3 is a schematic flow chart of a chip testing method in another embodiment;

[0040] Figure 4 is a schematic flow chart of a chip testing method in yet another embodiment;

[0041] Figure 5 is a structural block diagram of a chip testing device in one embodiment;

[0042] Figure 6 is a structural block diagram of a chip testing device in one embodiment;

[0043] Figure 7 FIG. 4 is a diagram showing the internal structure of an electronic device in one embodiment. DETAILED DESCRIPTION

[0044] In order to make the purpose, technical solution and advantages of the present application more clearly understood, the present application is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and are not used to limit the present application.

[0045] The chip testing method provided in the embodiment of the present application can be applied to Figure 1 In the application environment shown. Among them, the chip is set in the electronic device, and the chip is connected to the fault injection system. The fault injection system includes a fault injector, a three-axis table, a fault injection controller, a host computer, etc. The fault injector is used to inject a fault pulse into the chip. The fault injector is moved to a specified position by moving the three-axis table. The fault injection controller is used to control the fault injector to inject a fault pulse, etc. The host computer is used to control the fault injection controller.

[0046] In an exemplary embodiment, Figure 2 As shown, a chip testing method is provided, which is applied to Figure 1 The chip in FIG. 1 is taken as an example to illustrate, and the method includes the following steps 201 to 203. Among them:

[0047] Step 201 : In response to a start command sent by a fault injection system, a synchronization request signal is sent to the fault injection system and a request is made to inject a fault pulse.

[0048] The start command is sent by the fault injection system, and the sending of the start command can be initiated according to actual needs.

[0049] The synchronization request signal is used to request synchronization between the fault injection system and the chip. As the number of fault injection sequences increases, the time required for the injection process is correspondingly extended, resulting in the synchronization between the fault injection system and the chip being affected. Therefore, before performing fault pulse injection, the fault injection system and the chip need to be synchronized first.

[0050] The chip requests the fault injection system to inject a fault pulse, and correspondingly, the fault injection system injects a fault pulse into the chip at the same time or after sending the synchronization confirmation signal described below (while the chip is running the fault response program). The fault parameters of the injected fault pulse are adjustable, and different fault parameters can be set each time a fault pulse is injected. The fault parameters include fault injection power, fault injection delay, and fault injection pulse width.

[0051] Before injecting the fault pulse, the fault injection system first sets the range of fault parameters, where the range of fault injection power is 0% to 100%, corresponding to fault injection energy of different intensities. Since the fault injection process starts synchronously with the fault response program of the chip, the timing of fault injection should cover all operations of each module with integrated ECC function in the chip, and the fault injection delay range is determined according to the duration of the chip's fault response program. Since the fault injection process ends synchronously with the chip running the fault response program, the sum of the fault injection delay and the fault injection pulse width should not exceed the duration of the chip's fault response program, and the range of the fault injection pulse width is limited by the hardware injection probe (such as an electromagnetic injection probe or a laser injection probe) used by the fault injection system. Then set the fault parameters for each fault injection, randomly select within the range of the fault parameters, and perform fault injection with different fault injection powers, fault injection delays, and fault injection pulse widths.

[0052] Step 202: If a synchronization confirmation signal sent by the fault injection system is received, the fault response program is started to run, and the fault pulse injected by the fault injection system is received during the running of the fault response program. The running of the fault response program includes: sequentially operating each module with data verification and correction functions integrated therein, and performing data verification on each module under the action of the fault pulse.

[0053] The chip receives the synchronization confirmation signal sent by the fault injection system, which confirms that the fault injection system and the chip are synchronized. At this time, the chip starts to run the fault response program.

[0054] During the operation of the fault response program, the chip needs to receive the fault pulse injected by the fault injection system. The timing of fault injection should cover all operations of various modules with integrated ECC functions in the chip, such as memory erase, read, write operations and CAN module send and receive operations. It should be noted that the fault pulse is injected at a certain moment.

[0055] The running fault response program includes: under the action of the fault pulse, sequentially operating each module with an internally integrated data check and correction (Error-Correcting Code, referred to as ECC) function, and performing data check on each module.

[0056] The chip has integrated modules with data checking and correction functions, such as memory with ECC function and communication module with ECC function. The communication module is such as Controller Area Network (CAN) communication module. The memory is operated sequentially, including sequentially executing erase operation, write operation and read operation. The communication module is operated sequentially, including sequentially executing send operation and receive operation.

[0057] When data verification is performed on each module under the action of the fault pulse, specifically, data verification is performed when a module reads, for example, when the module is a memory, data verification is performed when a memory read operation is performed, and when the module is a communication module, data verification is performed when an operation of reading data in a receiving buffer is performed. After running the fault response program, the data verification result is sent to the fault injection system.

[0058] In one embodiment, when steps 201 to 203 are repeatedly executed to perform ECC data verification of the chip multiple times, the CAN communication module is configured to be in loopback self-test mode, and the CAN receiving buffer is configured to be reserved, and the CAN receiving buffer is updated only when the CAN communication module sends data. The data written to the memory and the data sent by the CAN communication module are respectively increased by 1 based on the data read by the last fault response program.

[0059] Step 203, after running the fault response program, the data verification result is sent to the fault injection system. If it is abnormal under the action of the fault pulse, it will be reset after responding to the reset signal sent by the fault injection system, and the first data verification result after the reset will be sent to the fault injection system, and the first data verification result will be the data verification result when it is abnormal.

[0060] When the energy of the fault pulse is too high (for example, the intensity is too large or the frequency is too high), the chip will be abnormal under the action of the fault pulse. At this time, the chip will not return the data verification result of the time. When the fault injection system does not receive the data verification result of the time returned by the chip, it will send a reset signal to the chip. The chip resets after responding to the reset signal sent by the fault injection system, and takes the first data verification result after the reset as the data verification result when abnormal, and sends the first data verification result to the fault injection system. The fault injection system takes the first data verification result as the data verification result when the chip is abnormal.

[0061] It should be noted that when the fault injection causes the chip to be abnormal, the chip will not change the data from the end of the fault injection to the next fault injection, and the fault injection system will not inject fault pulses again. Therefore, the memory data or communication module data read by the fault response program during the fault injection is consistent with the memory data or communication module data read by the redundant function program before the next fault injection. Therefore, the data verification result of the next redundant function program can be used to represent the data verification result of the fault injection.

[0062] In the above chip testing method, there is no need to rely on the unique fault injection circuit or special circuit inside the chip. The fault injection system is used to inject hardware faults from outside the chip to verify the ECC function. When the chip works abnormally or even crashes and is difficult to verify with the ECC function, the chip is reset through the fault injection system, and the first data verification result after the reset is used as the data verification result when the chip is abnormal. Therefore, it can solve the problem that the chip works abnormally or even crashes under the influence of high-energy hardware fault injection and is difficult to use for ECC function verification, and realize the ECC function verification of the chip by the hardware fault injection method. In addition, the single-bit error detection, double-bit and above error detection functions of ECC and the single-bit error correction function of ECC can be verified, and the functional verification of the module with integrated ECC function in the chip can be fully covered.

[0063] In an exemplary embodiment, each module includes a memory and a communication module, such as the CAN communication module mentioned above.

[0064] Before sending a synchronization request signal to the fault injection system for the first time, the chip testing method further includes:

[0065] Step 1: perform a read operation on the memory, and then perform an operation of reading a receiving buffer on the communication module. Perform data verification on the memory when performing the read operation, and perform data verification on the communication module when performing the operation of reading the buffer, and send the data verification results of the memory and the communication module to the fault injection system.

[0066] The chip runs the redundant function program before receiving the start command and running the fault response program. The chip runs the redundant program including: firstly, performing a read operation on the memory with integrated ECC function in the chip, and then performing a read operation on the CAN receiving buffer of the CAN communication module with integrated ECC function in the chip. When reading the memory data or receiving the CAN communication module data, the ECC performs ECC data verification on the data, and the read data and the data verification result are sent to the fault injection system through the communication interface.

[0067] Step 2: Reset after receiving a reset signal sent by the fault injection system, wherein the reset signal is generated by the fault injection system when the data verification result represents that the chip is abnormal.

[0068] When the data inspection result sent to the fault injection system in step 1 indicates that the chip is abnormal, the fault injection system generates a reset signal and sends the reset signal to the chip.

[0069] The chip is reset after receiving the reset signal, and then executes step 201 for the first time after being reset.

[0070] When the chip fails to work properly or even crashes, the fault response status information will be lost. Therefore, designing redundant function programs and resetting the chip in time will help improve the reliability and accuracy of the chip data verification results.

[0071] In this embodiment, through the redundant function program that is not affected by fault injection, the ECC data verification results of different ECC function modules after the chip crashes due to high-energy faults are discovered, and the single-bit error detection, double-bit and above error detection functions of ECC and the single-bit error correction function of ECC can be verified, so that the functional verification of the module with integrated ECC function in the chip can be fully covered. In addition, the purpose of resetting the chip in time is achieved, which is conducive to improving the reliability and accuracy of the chip data verification results.

[0072] In an exemplary embodiment, after step 203 sends the data verification result to the fault injection system, the chip testing method further includes:

[0073] Repeat steps 201 to 203 until the number of fault pulses injected by the fault injection system reaches the target number. The target number can be set according to actual needs. After each execution of steps 201 to 203, a chip data verification result is obtained.

[0074] In an exemplary embodiment, the step of sending a synchronization request signal to the fault injection system in step 201 includes:

[0075] Step 1: Send a synchronization request signal to the fault injection system through the first pin.

[0076] Furthermore, step 202 of receiving a synchronization confirmation signal sent by the fault injection system includes:

[0077] Step 2: receiving a synchronization confirmation signal sent by the fault injection system through the second pin.

[0078] Both the first pin and the second pin may be input / output (IO) pins.

[0079] After the redundant function program is finished running, the chip sends a synchronization request signal to the fault injection system through the first pin and requests fault injection. After receiving the synchronization request, the fault injection system returns a synchronization confirmation signal through the second pin, and waits for a delay before injecting the fault pulse this time. After receiving the returned synchronization confirmation signal, the chip runs the fault response program to ensure that this fault injection process starts synchronously with the chip's fault response program. After the fault injection is finished, the fault injection system delays for a period of time and waits for the chip to finish running the fault response program before starting the next fault injection to ensure that this fault injection process ends synchronously with the chip running the fault response program. This fine synchronization mechanism ensures the timing accuracy of the fault injection process, thereby improving the reliability and effectiveness of the chip's data verification results. The injection process includes processes such as returning a synchronization confirmation signal, delaying, injecting faults, waiting, and ending. Ensuring the timing accuracy of the fault injection process refers to ensuring the execution time and execution order of processes such as returning a synchronization confirmation signal, delaying, injecting faults, waiting, and ending.

[0080] This embodiment adopts a command-driven dual IO synchronization method to ensure that each fault injection starts and ends synchronously with the chip running the fault response program, thereby improving the reliability and effectiveness of the chip data verification result.

[0081] It should be noted that in the chip testing method provided in any of the above embodiments, when the chip to be tested is a chip with a programming control function (such as a controller chip), the chip can be directly programmed so that the chip executes the chip testing method. When the chip to be tested is a chip that does not have a programming control function, such as a memory chip or a CAN communication module chip, it is necessary to add another controller chip to solve the problem during the hardware fault injection test, program another controller chip, and realize the synchronization of the controller chip, the chip to be tested, and the fault injection system, and control the chip to be tested to perform various operations, etc. The fault injection system injects fault pulses into the chip to be tested.

[0082] In an exemplary embodiment, Figure 3 As shown, a chip testing method is provided, which is applied to Figure 1 The fault injection system in is taken as an example to illustrate, including the following steps 301 to 304.

[0083] in:

[0084] Step 301: Send a start command to the chip under test, and receive a synchronization request signal sent by the chip under test.

[0085] The start command is sent by the fault injection system, and the sending of the start command can be initiated according to actual needs.

[0086] The synchronization request signal is used to request synchronization between the fault injection system and the chip. As the number of fault injection sequences increases, the time required for the injection process is correspondingly extended, resulting in the synchronization between the fault injection system and the chip being affected. Therefore, before performing fault pulse injection, the fault injection system and the chip need to be synchronized first.

[0087] When the chip sends a synchronization request signal, the chip requests the fault injection system to inject a fault pulse. Correspondingly, the fault injection system injects a fault pulse into the chip at the same time or after sending a synchronization confirmation signal as described below. The fault parameters of the injected fault pulse are adjustable. Different fault parameters can be set each time a fault pulse is injected. The fault parameters include fault injection power, fault injection delay, and fault injection pulse width.

[0088] Step 302: In response to the synchronization request signal, a synchronization confirmation signal is sent to the chip under test.

[0089] The chip receives the synchronization confirmation signal sent by the fault injection system, which confirms that the fault injection system and the chip are synchronized. At this time, the chip starts to run the fault response program.

[0090] During the operation of the fault response program, the chip needs to receive the fault pulse injected by the fault injection system. The timing of fault injection should cover all operations of each module with integrated ECC function in the chip, such as memory erase, read, write operations and CAN module send and receive operations.

[0091] Step 303, injecting a fault pulse into the chip under test during the process of the chip under test running the fault response program, wherein the running of the fault response program includes: sequentially operating each module with integrated data verification and correction functions, and performing data verification on each module under the action of the fault pulse.

[0092] Before injecting the fault pulse, the fault injection system first sets the range of fault parameters, where the range of fault injection power is 0% to 100%, corresponding to fault injection energy of different intensities. Since the fault injection process starts synchronously with the fault response program of the chip, the timing of fault injection should cover all operations of each module with integrated ECC function in the chip, and the fault injection delay range is determined according to the duration of the chip's fault response program. Since the fault injection process ends synchronously with the chip running the fault response program, the sum of the fault injection delay and the fault injection pulse width should not exceed the duration of the chip's fault response program, and the range of the fault injection pulse width is limited by the hardware injection probe (such as an electromagnetic injection probe or a laser injection probe) used by the fault injection system. Then set the fault parameters for each fault injection, randomly select within the range of the fault parameters, and perform fault injection with different fault injection powers, fault injection delays, and fault injection pulse widths.

[0093] The running fault response program includes: under the action of the fault pulse, sequentially operating each module with an internally integrated data check and correction (Error-Correcting Code, referred to as ECC) function, and performing data check on each module.

[0094] The chip has integrated modules with data checking and correction functions, such as memory with ECC function and communication module with ECC function. The communication module is such as Controller Area Network (CAN) communication module. The memory is operated sequentially, including sequentially executing erase operation, write operation and read operation. The communication module is operated sequentially, including sequentially executing send operation and receive operation.

[0095] When data verification is performed on each module under the action of the fault pulse, specifically, data verification is performed when a module reads, for example, when the module is a memory, data verification is performed when a memory read operation is performed, and when the module is a communication module, data verification is performed when an operation of reading data in a receiving buffer is performed. After running the fault response program, the data verification result is sent to the fault injection system.

[0096] In one embodiment, when steps 201 to 203 are repeatedly executed to perform ECC data verification of the chip multiple times, the CAN communication module is configured to be in loopback self-test mode, and the CAN receiving buffer is configured to be reserved, and the CAN receiving buffer is updated only when the CAN communication module sends data. The data written to the memory and the data sent by the CAN communication module are respectively increased by 1 based on the data read by the last fault response program.

[0097] Step 304, receiving the data verification result sent by the chip under test, wherein, when the chip under test is abnormal under the action of the fault pulse, a reset signal is sent to the chip under test, and the first data verification result received after the chip under test is reset is used as the data verification result when the chip under test is abnormal.

[0098] When the energy of the fault pulse is too high (for example, the intensity is too large or the frequency is too high), the chip will be abnormal under the action of the fault pulse. At this time, the chip will not return the data verification result of the time. When the fault injection system does not receive the data verification result of the time returned by the chip, it will send a reset signal to the chip. The chip resets after responding to the reset signal sent by the fault injection system, and takes the first data verification result after the reset as the data verification result when abnormal, and sends the first data verification result to the fault injection system. The fault injection system takes the first data verification result as the data verification result when the chip is abnormal.

[0099] In the above chip testing method, there is no need to rely on the unique fault injection circuit or special circuit inside the chip. The fault injection system is used to inject hardware faults from outside the chip to verify the ECC function. When the chip works abnormally or even crashes and is difficult to verify with the ECC function, the chip is reset through the fault injection system, and the first data verification result after the reset is used as the data verification result when the chip is abnormal. Therefore, it can solve the problem that the chip works abnormally or even crashes under the influence of high-energy hardware fault injection and is difficult to use for ECC function verification, and realize the ECC function verification of the chip by the hardware fault injection method. In addition, the single-bit error detection, double-bit and above error detection functions of ECC and the single-bit error correction function of ECC can be verified, and the functional verification of the module with integrated ECC function in the chip can be fully covered.

[0100] In an exemplary embodiment, each module in the chip includes a memory and a communication module, and the communication module is, for example, the CAN communication module mentioned above.

[0101] Before receiving the synchronization request signal sent by the chip under test for the first time, the chip testing method further includes:

[0102] Step 1: receiving the data verification result of the memory in the chip under test and the data verification result of the communication module in the chip under test.

[0103] The chip runs the redundant function program before receiving the start command and running the fault response program. The chip runs the redundant program including: firstly, performing a read operation on the memory with integrated ECC function in the chip, and then performing a read operation on the CAN receiving buffer of the CAN communication module with integrated ECC function in the chip. When reading the memory data or receiving the CAN communication module data, the ECC performs ECC data verification on the data, and the read data and the data verification result are sent to the fault injection system through the communication interface.

[0104] Step 2: When the data verification result of the memory or the data verification result of the communication module indicates that the chip under test is abnormal, a reset signal is sent to the chip under test.

[0105] When any data inspection result received in step 1 indicates that the chip is abnormal, the fault injection system generates a reset signal and sends the reset signal to the chip.

[0106] When the chip fails to work properly or even crashes, the fault response status information will be lost. Therefore, designing redundant function programs and resetting the chip in time will help improve the reliability and accuracy of the chip data verification results.

[0107] Step 301 of receiving a synchronization request signal sent by the chip under test includes:

[0108] Step three: when the data verification result of the memory and the data verification result of the communication module indicate that the chip under test is normal, receiving a synchronization request signal sent by the chip under test.

[0109] That is to say, when the chip works normally after being reset, a synchronization request signal is sent to the chip.

[0110] Optionally, if the chip is still abnormal after one reset, a reset signal is sent to the chip to reset the chip for a second time. Further, if the chip is still abnormal after sending the reset signal multiple times, an alarm is issued.

[0111] In this embodiment, through the redundant function program that is not affected by fault injection, the ECC data verification results of different ECC function modules after the chip crashes due to high-energy faults are discovered, and the single-bit error detection, double-bit and above error detection functions of ECC and the single-bit error correction function of ECC can be verified, so that the functional verification of the module with integrated ECC function in the chip can be fully covered. In addition, the purpose of resetting the chip in time is achieved, which is conducive to improving the reliability and accuracy of the chip data verification results.

[0112] In an exemplary embodiment, the chip testing method further includes:

[0113] Step 1: repeatedly execute step 301 to step 304 until the number of times the fault pulse is injected into the chip under test reaches the target number.

[0114] The target number of times can be set according to actual needs. After each execution of step 301 to step 304, a chip data verification result is obtained.

[0115] In an exemplary embodiment, the chip testing method further includes:

[0116] Step 1: Mark the data verification result as an event.

[0117] Multiple data verification results may correspond to multiple events. Events can be divided into no ECC error, single-bit ECC error in memory, multi-bit ECC error in memory, single-bit ECC error in CAN module, and multi-bit ECC error in CAN module. Therefore, this embodiment can verify the single-bit error detection, double-bit and above error detection functions of ECC.

[0118] The single-bit error correction function verification of ECC cannot be directly judged by the read data of the fault injection response program of the ECC single-bit error event because the data has been corrected when it is read. The read data of the fault injection response program of the ECC single-bit error event can be subtracted from the read data of the redundant function program of the event. If the result is 1, it means that the single-bit error correction function verification of ECC has passed.

[0119] For easier understanding, see Figure 4 , the chip testing method is described in more detail below with the most detailed embodiment.

[0120] Step 401: The fault injection system and chip are initialized.

[0121] The initialization of the fault injection system includes initializing the three-axis platform, the fault injector, the fault injection controller, the host computer, the communication interface, etc. The initialization of the chip includes initializing each module in the chip, initializing each communication interface, initializing each pin (including the first pin and the second pin mentioned above), etc.

[0122] Step 402: Preparation before fault injection.

[0123] Preparations before fault injection include, for example, moving the fault injector to a specified location, setting fault parameters during fault pulse injection, and sending a start command from the fault injection system.

[0124] Step 403: The fault injection system and the chip are synchronized.

[0125] Referring to the above description, the chip sends a synchronization request signal to the fault injection system and requests a fault pulse, and the fault injection system returns a synchronization confirmation signal to the chip, thereby completing the synchronization between the fault injection system and the chip.

[0126] Step 404: The chip runs the redundant function program.

[0127] For the relevant description about the chip running the redundant function program, please refer to the above related description, which will not be repeated in this embodiment.

[0128] Step 405: The fault injection system adjusts the fault parameters during fault pulse injection.

[0129] Before the chip runs the fault response program, the fault injection system can adjust the fault parameters during fault pulse injection according to actual needs to improve the reliability of the data verification results. Fault parameters include, for example, fault injection power, fault injection delay, and fault injection pulse width.

[0130] Step 406: The chip runs a fault response program.

[0131] For the relevant description about the chip running the fault response program, please refer to the above related description, which will not be repeated in this embodiment.

[0132] Step 407: Analysis and marking of fault injection events.

[0133] The fault injection system can mark the data verification results as events. Multiple data verification results may correspond to multiple events. Events can be divided into no ECC error, single-bit ECC error in the memory, multi-bit ECC error in the memory, single-bit ECC error in the CAN module, and multi-bit ECC error in the CAN module. Therefore, this embodiment can verify the single-bit error detection, double-bit and above error detection functions of ECC.

[0134] Step 408: If the fault injection process is not completed, the process returns to step 402 to step 408 until another fault injection process is completed. In order to improve the richness, reliability and accuracy of the data verification results, steps 402 to step 408 may be executed repeatedly. The process ends when the fault injection process is completed.

[0135] When the number of injections of the fault pulses reaches the target number, it can be determined that the fault injection process is completed.

[0136] The chip testing method provided in this embodiment does not need to rely on the fault injection circuit or special circuit unique to the chip, and the hardware fault is injected from the outside of the chip to perform ECC function verification through the fault injection system. In the case where the chip works abnormally or even crashes and is difficult to verify with the ECC function, the chip is reset through the fault injection system, and the first data verification result after the reset is used as the data verification result when the chip is abnormal. Therefore, it can solve the problem that the chip works abnormally or even crashes under the influence of high-energy hardware fault injection and is difficult to use for ECC function verification, and realize the ECC function verification of the chip by the hardware fault injection method. In addition, the single-bit error detection, double-bit and above error detection functions of ECC and the single-bit error correction function of ECC can be verified, and the functional verification of the module with integrated ECC function in the chip can be fully covered.

[0137] In addition, through the redundant function program that is not affected by fault injection, the ECC data verification results of different ECC function modules after the chip crashes due to high-energy faults can be discovered, and the single-bit error detection, double-bit and above error detection functions of ECC and the single-bit error correction function of ECC can be verified, and the functional verification of the modules with integrated ECC functions in the chip can be fully covered. In addition, the purpose of resetting the chip in time is achieved, which is conducive to improving the reliability and accuracy of the chip data verification results.

[0138] It should be understood that, although the steps in the flowcharts of the embodiments described above are shown in sequence according to the instructions of the arrows, these steps are not necessarily performed in sequence according to the order indicated by the arrows. Unless there is a clear explanation in this article, the execution of these steps is not strictly limited in order, and these steps can be performed in other orders. Moreover, at least a portion of the steps in the flowcharts of the embodiments described above can include multiple steps or multiple stages, and these steps or stages are not necessarily performed at the same time, but can be performed at different times, and the execution order of these steps or stages is not necessarily performed in sequence, but can be performed in turn or alternately with other steps or at least a portion of the steps or stages in other steps.

[0139] Based on the same inventive concept, the embodiment of the present application also provides a chip testing device for implementing the chip testing method involved above. The implementation scheme for solving the problem provided by the device is similar to the implementation scheme recorded in the above method, so the specific limitations in one or more chip testing device embodiments provided below can refer to the limitations on the chip testing method above, and will not be repeated here.

[0140] In an exemplary embodiment, Figure 5 As shown, a chip testing device 50 is provided, which is applied to a chip and includes: a communication module 501 and a processing module 502. Among them:

[0141] The communication module 501 is used to respond to the start command sent by the fault injection system, send a synchronization request signal to the fault injection system and request to inject a fault pulse.

[0142] The processing module 502 is used to start running the fault response program if a synchronization confirmation signal sent by the fault injection system is received, and receive the fault pulse injected by the fault injection system during the running of the fault response program; wherein the running of the fault response program includes: sequentially operating each module with integrated data verification and correction functions, and performing data verification on each module under the action of the fault pulse.

[0143] The communication module 501 is also used to send the data verification result to the fault injection system after running the fault response program; wherein, if an abnormality occurs under the action of the fault pulse, it will reset after responding to the reset signal sent by the fault injection system, and send the first data verification result after the reset to the fault injection system, with the first data verification result being the data verification result when the abnormality occurs.

[0144] In one embodiment, each module includes a memory and a communication module, and the processing module 502 is used to perform a read operation on the memory, and then perform an operation of reading a receiving buffer on the communication module; perform data verification on the memory when performing the read operation, and perform data verification on the communication module when performing the operation of reading the buffer, and send the data verification results of the memory and the data verification results of the communication module to the fault injection system; reset after receiving a reset signal sent by the fault injection system, wherein the reset signal is generated by the fault injection system when the data verification result represents a chip abnormality.

[0145] In one embodiment, the processing module 502 is used to repeatedly execute the step of responding to the start command sent by the fault injection system and sending the data verification result to the fault injection system until the number of fault pulses injected by the fault injection system reaches the target number.

[0146] In one embodiment, the communication module 501 is used to: send a synchronization request signal to the fault injection system through a first pin; and receive a synchronization confirmation signal sent by the fault injection system through a second pin.

[0147] Each module in the chip testing device 50 can be implemented in whole or in part by software, hardware, or a combination thereof. Each module can be embedded in or independent of a processor in an electronic device in the form of hardware, or can be stored in a memory in the electronic device in the form of software, so that the processor can call and execute operations corresponding to each module.

[0148] In an exemplary embodiment, Figure 6 As shown, a chip testing device 60 is provided, which is applied to a fault injection system and includes: a communication module 601 and a processing module 602. Among them:

[0149] The communication module 601 is used to send a start command to the chip under test and receive a synchronization request signal sent by the chip under test.

[0150] The communication module 601 is further configured to respond to the synchronization request signal and send a synchronization confirmation signal to the chip under test.

[0151] The processing module 602 is used to inject a fault pulse into the chip under test when the chip under test runs a fault response program, wherein the running of the fault response program includes: sequentially operating each module with integrated data verification and correction functions, and performing data verification on each module under the action of the fault pulse.

[0152] The processing module 602 is also used to receive the data verification result sent by the chip under test, wherein, when the chip under test is abnormal under the action of the fault pulse, a reset signal is sent to the chip under test, and the first data verification result received after the chip under test is reset is used as the data verification result when the chip under test is abnormal.

[0153] In one embodiment, the communication module 601 is also used to receive data verification results of the memory in the chip under test and data verification results of the communication module in the chip under test; when the data verification results of the memory or the data verification results of the communication module indicate that the chip under test is abnormal, a reset signal is sent to the chip under test; when the data verification results of the memory and the data verification results of the communication module indicate that the chip under test is normal, a synchronization request signal sent by the chip under test is received.

[0154] In one embodiment, the processing module 602 is used to repeatedly execute the steps of sending a start command to the chip under test and receiving a data verification result sent by the chip under test until the number of fault pulses injected into the chip under test reaches a target number.

[0155] Each module in the chip testing device 60 can be implemented in whole or in part by software, hardware, or a combination thereof. Each module can be embedded in or independent of a processor in an electronic device in the form of hardware, or can be stored in a memory in an electronic device in the form of software, so that the processor can call and execute operations corresponding to each module.

[0156] In an exemplary embodiment, an electronic device is provided. The electronic device may be a server, and its internal structure diagram may be as shown in FIG. Figure 7 As shown. The electronic device includes a processor, a memory, an input / output interface (Input / Output, referred to as I / O) and a communication interface. Wherein, the processor, the memory and the input / output interface are connected through a system bus, and the communication interface is connected to the system bus through the input / output interface. Wherein, the processor of the electronic device is used to provide computing and control capabilities. The memory of the electronic device includes a non-volatile storage medium and an internal memory. The non-volatile storage medium stores an operating system, a computer program and a database. The internal memory provides an environment for the operation of the operating system and the computer program in the non-volatile storage medium. The database of the electronic device is used to store data. The input / output interface of the electronic device is used to exchange information between the processor and an external device. The communication interface of the electronic device is used to communicate with an external terminal through a network connection. When the computer program is executed by the processor, the chip testing method applied to the chip as provided in any of the above embodiments is implemented, or the chip testing method applied to the fault injection system as provided in any of the above embodiments is implemented.

[0157] Those skilled in the art will understand that Figure 7 The structure shown in the figure is merely a block diagram of a partial structure related to the scheme of the present application, and does not constitute a limitation on the electronic device to which the scheme of the present application is applied. The specific electronic device may include more or fewer components than shown in the figure, or combine certain components, or have a different arrangement of components.

[0158] In one embodiment, a computer-readable storage medium is provided, on which a computer program is stored. When the computer program is executed by a processor, the chip testing method applied to a chip as provided in any of the above embodiments is implemented, or the chip testing method applied to a fault injection system as provided in any of the above embodiments is implemented.

[0159] In one embodiment, a computer program product is provided, including a computer program, which, when executed by a processor, implements a chip testing method applied to a chip as provided in any of the above embodiments, or implements a chip testing method applied to a fault injection system as provided in any of the above embodiments.

[0160] Those of ordinary skill in the art can understand that all or part of the processes in the above-mentioned embodiment methods can be completed by instructing the relevant hardware through a computer program, and the computer program can be stored in a non-volatile computer-readable storage medium. When the computer program is executed, it can include the processes of the embodiments of the above-mentioned methods. Among them, any reference to the memory, database or other medium used in the embodiments provided in the present application can include at least one of non-volatile memory and volatile memory. Non-volatile memory can include read-only memory (ROM), magnetic tape, floppy disk, flash memory, optical memory, high-density embedded non-volatile memory, resistive random access memory (ReRAM), magnetic random access memory (MRAM), ferroelectric random access memory (FRAM), phase change memory (PCM), graphene memory, etc. Volatile memory can include random access memory (RAM) or external cache memory, etc. As an illustration and not limitation, RAM can be in various forms, such as static random access memory (SRAM) or dynamic random access memory (DRAM). The database involved in each embodiment provided in this application may include at least one of a relational database and a non-relational database. Non-relational databases may include distributed databases based on blockchains, etc., but are not limited to this. The processor involved in each embodiment provided in this application may be a general-purpose processor, a central processing unit, a graphics processor, a digital signal processor, a programmable logic device, a data processing logic device based on quantum computing, an artificial intelligence (AI) processor, etc., but are not limited to this.

[0161] The technical features of the above embodiments may be combined arbitrarily. To make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this application.

[0162] The above embodiments only express several implementation methods of the present application, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the present application. It should be pointed out that, for a person of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present application, and these all belong to the protection scope of the present application. Therefore, the protection scope of the present application shall be subject to the attached claims.

Claims

1. A chip testing method, characterized in that: Applied to a chip, the method comprises: In response to a start command sent by the fault injection system, sending a synchronization request signal to the fault injection system and requesting injection of a fault pulse; If the synchronization confirmation signal sent by the fault injection system is received, the fault response program is started to run, and the fault pulse injected by the fault injection system is received during the running of the fault response program; wherein the running of the fault response program includes: sequentially operating each module with data verification and correction functions integrated therein, and performing data verification on each module under the action of the fault pulse; After running the fault response program, the data verification result is sent to the fault injection system; wherein, if an abnormality occurs under the action of the fault pulse, the system is reset after responding to the reset signal sent by the fault injection system, and the first data verification result after the reset is sent to the fault injection system, with the first data verification result being the data verification result when the abnormality occurs.

2. The method according to claim 1, characterized in that Each module includes a memory and a communication module. Before sending a synchronization request signal to the fault injection system for the first time, the method further includes: Performing a read operation on the memory, and then performing an operation of reading a receiving buffer on the communication module; Performing data verification on the memory when performing the read operation, and performing data verification on the communication module when performing the read buffer operation, and sending the data verification results of the memory and the data verification results of the communication module to the fault injection system; Resetting after receiving a reset signal sent by the fault injection system, wherein the reset signal is generated by the fault injection system when the data verification result represents a chip abnormality.

3. The method according to claim 1, characterized in that After sending the data verification result to the fault injection system, the method further includes: The step of responding to the start command sent by the fault injection system and sending the data verification result to the fault injection system is repeatedly performed until the number of fault pulses injected by the fault injection system reaches the target number.

4. The method according to any one of claims 1 to 3, characterized in that: The sending of a synchronization request signal to the fault injection system comprises: Sending a synchronization request signal to the fault injection system via a first pin; The receiving of the synchronization confirmation signal sent by the fault injection system comprises: A synchronization confirmation signal sent by the fault injection system is received through the second pin.

5. A chip testing method, characterized in that: Applied to a fault injection system, the method comprises: Sending a start command to the chip under test, and receiving a synchronization request signal sent by the chip under test; In response to the synchronization request signal, sending a synchronization confirmation signal to the chip under test; In the process of the chip under test running the fault response program, injecting a fault pulse into the chip under test, wherein the running of the fault response program includes: sequentially operating each module with data verification and correction functions integrated therein, and performing data verification on each module under the action of the fault pulse; Receive the data verification result sent by the chip under test, wherein, when the chip under test is abnormal under the action of the fault pulse, send a reset signal to the chip under test, and use the first data verification result received after the chip under test is reset as the data verification result when the chip under test is abnormal.

6. The method according to claim 5, characterized in that Before receiving the synchronization request signal sent by the chip under test for the first time, the method further includes: Receiving a data verification result of a memory in the chip under test and a data verification result of a communication module in the chip under test; When the data verification result of the memory or the data verification result of the communication module indicates that the chip under test is abnormal, sending a reset signal to the chip under test; The receiving a synchronization request signal sent by the chip under test comprises: When the data verification result of the memory and the data verification result of the communication module indicate that the chip under test is normal, a synchronization request signal sent by the chip under test is received.

7. The method according to claim 5, characterized in that The method further comprises: The steps of sending a start command to the chip under test and receiving a data verification result sent by the chip under test are repeatedly performed until the number of fault pulses injected into the chip under test reaches a target number.

8. An electronic device comprising a memory and a processor, wherein the memory stores a computer program, wherein: When the processor executes the computer program, the processor implements the steps of the method according to any one of claims 1 to 4, or implements the steps of the method according to any one of claims 5 to 7.

9. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the computer program implements the steps of the method according to any one of claims 1 to 4, or implements the steps of the method according to any one of claims 5 to 7.

10. A computer program product, comprising a computer program, characterized in that When the computer program is executed by a processor, the computer program implements the steps of the method according to any one of claims 1 to 4, or implements the steps of the method according to any one of claims 5 to 7.

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