Command management method, storage control chip and flash memory device

Abstract

The embodiment of the invention relates to the field of storage device application, and discloses a command management method, a storage control chip and a flash memory device, and the flash memory device comprises a host data path and a garbage collection data path. Determining a first command execution time for executing a plurality of host data processing commands on the host data path and a second command execution time for executing a plurality of garbage collection commands on the garbage collection data path in each time slice; according to the size relation between the first command execution time and the second command execution time, the number of the host data processing commands and the number of the garbage collection commands issued and executed in the next time slice are adjusted till the flash memory device enters a stable state. The utilization rate of the overall data path is improved, and the overall performance of the flash memory device is improved.

Description

Technical Field

[0001] The present application relates to the application field of storage devices, and in particular to a command management method, a storage control chip and a flash memory device. Background Art

[0002] Flash memory devices, such as solid state drives (SSDs), are storage devices that use semiconductor flash memory (NAND Flash) as a medium. Flash memory devices include a host data path, which is used to implement data exchange between the host and the flash memory.

[0003] Currently, a high-speed cache memory is added inside a flash memory device to allocate cache resources to a host data path for use, thereby increasing the speed at which the host data path processes data.

[0004] In the process of implementing the present application, the inventors found that there are at least the following problems in the prior art: after the flash memory device starts garbage collection, the garbage collection process needs to perform a garbage collection write operation to provide necessary storage space for the host data write, and the host write operation will not be performed until enough space is released by garbage collection. Although the existence of the cache speeds up the transmission speed of part of the data in the host data path, the space release limitation in the garbage collection process still restricts the overall performance of the host data path and cannot improve the overall performance of the flash memory device. Summary of the invention

[0005] The embodiment of the present application provides a command management method to adjust the command allocation of the host data path and the garbage collection data path in real time, improve the utilization rate of the overall data path, and enhance the overall performance of the flash memory device.

[0006] The embodiments of the present application provide the following technical solutions:

[0007] In a first aspect, an embodiment of the present application provides a command management method, the command management method is applied to a flash memory device, the flash memory device includes a host data path and a garbage collection data path, the command management method includes:

[0008] After the flash memory device starts garbage collection, determining a first command execution time and a second command execution time in each time slice, wherein the first command execution time is the time for executing a plurality of host data processing commands on the host data path, and the second command execution time is the time for executing a plurality of garbage collection commands on the garbage collection data path;

[0009] When the flash memory device has not entered a stable state, the number of host data processing commands and garbage collection commands issued and executed in the next time slice is adjusted according to the relationship between the first command execution time and the second command execution time until the flash memory device enters a stable state.

[0010] In some embodiments, the flash memory device includes a cache, a memory, and a flash memory;

[0011] The host data path includes a data path between the host and the cache or a data path between the host and the memory, and the garbage collection data path includes a data path between the flash memory and the cache or a data path between the flash memory and the memory;

[0012] Alternatively, the host data path includes a data path between the host and the cache or a data path between the cache and the memory, and the garbage collection data path includes a data path between the flash memory and the cache or a data path between the cache and the memory.

[0013] In some embodiments, the host data processing command includes a host data write command, and the garbage collection command includes a garbage collection write command or a garbage collection read command;

[0014] The host data path includes a host write path, and the garbage collection data path includes a garbage collection write path or a garbage collection read path. The host write path is used to execute host data write commands, the garbage collection write path is used to execute garbage collection write commands, and the garbage collection read path is used to execute garbage collection read commands.

[0015] In some embodiments, the flash memory device includes a front-end module, and before determining the first command execution time and the second command execution time in each time slice, the method further includes:

[0016] Calculate the write amplification factor and use it as the ratio of the number of garbage collection write commands and host data write commands issued in each time slice;

[0017] Determine a first quantity of host data write commands and a second quantity of garbage collection write commands issued in each time slice according to the quantity ratio and the preset unit quantity;

[0018] In each time slice, a first number of host data write commands and a second number of garbage collection write commands are sent to the front-end module.

[0019] In some embodiments, the host write path, the garbage collection write path, and the garbage collection read path each correspond to a command submission queue and a command completion queue;

[0020] Determining the first command execution time and the second command execution time within each time slice includes:

[0021] Record the starting timestamp of each host data write command, garbage collection write command or garbage collection read command submitted to the corresponding command submission queue;

[0022] In a first time slice, executing a plurality of host data write commands, garbage collection write commands, and garbage collection read commands;

[0023] Record the end timestamp of each host data write command, garbage collection write command or garbage collection read command when it is submitted to the corresponding command completion queue after execution;

[0024] Based on the end timestamp and the start timestamp, the execution time of each host data write command, garbage collection write command or garbage collection read command is calculated;

[0025] Adding the execution time of each host data write command executed in the first time slice, and using the result as the first command execution time;

[0026] The execution time of each garbage collection write command and garbage collection read command executed in the first time slice is added together, and the obtained result is used as the second command execution time.

[0027] In some embodiments, the flash memory device includes a cache, a memory and a flash memory, the host data write command includes a host cache write command or a host memory write command, the garbage collection write command includes a garbage collection cache write command or a garbage collection memory write command, and the garbage collection read command includes a garbage collection cache read command or a garbage collection memory read command.

[0028] In some embodiments, adjusting the number of host data processing commands and garbage collection commands issued and executed in the next time slice according to the relationship between the first command execution time and the second command execution time includes:

[0029] After the issuance of the plurality of host data write commands, garbage collection write commands and garbage collection read commands executed in the first time slice is completed, the plurality of host data write commands, garbage collection write commands and garbage collection read commands executed in the second time slice are issued;

[0030] Calculating a minimum command execution time within the first time slice, wherein the minimum command execution time is a minimum value between the first command execution time and the second command execution time;

[0031] When the minimum command execution time is the first command execution time, the number of host cache write commands, garbage collection memory write commands, and garbage collection memory read commands issued in the third time slice is reduced, and the number of host memory write commands, garbage collection cache write commands, and garbage collection cache read commands issued in the third time slice is increased;

[0032] When the minimum command execution time is the second command execution time, the number of host cache write commands, garbage collection memory write commands, and garbage collection memory read commands issued in the third time slice is increased, and the number of host memory write commands, garbage collection cache write commands, and garbage collection cache read commands issued in the third time slice is reduced;

[0033] The sum of the number of host cache write commands and the number of host memory write commands is the first number, and the sum of the number of garbage collection memory write commands and the number of garbage collection cache write commands is the second number.

[0034] In some embodiments, adjusting the number of host data processing commands and garbage collection commands issued and executed in the next time slice according to the relationship between the first command execution time and the second command execution time also includes:

[0035] In the third time slice, execute a plurality of host data write commands, garbage collection write commands and garbage collection read commands, and use the third time slice as the first time slice of a new round, and determine the first command execution time and the second command execution time of the first time slice of the new round;

[0036] After the issuance of the plurality of host data write commands, garbage collection write commands and garbage collection read commands executed in the third time slice is completed, according to the number of host cache write commands, host memory write commands, garbage collection cache read commands, garbage collection memory read commands, garbage collection memory write commands and garbage collection cache write commands issued in the third time slice, a new round of plurality of host cache write commands, host memory write commands, garbage collection cache read commands, garbage collection memory read commands, garbage collection memory write commands and garbage collection cache write commands executed in the second time slice is issued;

[0037] According to the relationship between the first command execution time and the second command execution time of the first time slice of the new round, adjust the number of host cache write commands, host memory write commands, garbage collection cache read commands, garbage collection memory read commands, garbage collection memory write commands, and garbage collection cache write commands issued and executed in the third time slice of the new round until the flash memory device enters a stable state.

[0038] In some embodiments, the method further comprises:

[0039] When the difference between the minimum command execution times of each two consecutive rounds is less than a preset time threshold, or when the number of host cache write commands, host memory write commands, garbage collection cache write commands, garbage collection memory write commands, garbage collection cache read commands or garbage collection memory read commands is zero in any time slice of any round, it is determined that the flash memory device enters a stable state, wherein the time slice includes a first time slice, a second time slice or a third time slice.

[0040] In some embodiments, the host data processing command further includes a host data read command, the host data path further includes a host read path, the host read path is used to execute the host data read command, and the host read path corresponds to a command submission queue;

[0041] The method also includes:

[0042] Setting different priorities for the host data read command, the host data write command, the garbage collection write command and the garbage collection read command, and controlling the priority of the host data read command to be the highest priority;

[0043] After the host data read command is submitted to the corresponding command submission queue, the processing of low-priority host data write commands, garbage collection write commands and garbage collection read commands is interrupted, and the host data read command is issued and executed.

[0044] In a second aspect, an embodiment of the present application provides a storage control chip, including:

[0045] at least one processor; and,

[0046] a memory communicatively connected to at least one processor; wherein,

[0047] The memory stores instructions that can be executed by at least one processor, and the instructions are executed by the at least one processor to enable the at least one processor to perform the command management method according to the first aspect.

[0048] In a third aspect, an embodiment of the present application provides a flash memory device, including:

[0049] The storage control chip of the second aspect;

[0050] At least one flash memory is communicatively connected to the storage control chip.

[0051] In a fourth aspect, an embodiment of the present application further provides a non-volatile computer-readable storage medium, which stores computer-executable instructions. When the computer-executable instructions are executed by a processor, the processor executes the command management method of the first aspect.

[0052] In a fifth aspect, an embodiment of the present application provides a computer program product, which includes instructions or programs. When the instructions or programs are executed by a flash memory device, the flash memory device executes the computer program of the command management method of the first aspect above.

[0053] The beneficial effect of the embodiments of the present application is as follows: different from the prior art, the embodiments of the present application provide a command management method, which is applied to a flash memory device, and the flash memory device includes a host data path and a garbage collection data path. The command management method includes: after the flash memory device starts garbage collection, determining the first command execution time and the second command execution time in each time slice, wherein the first command execution time is the time for executing several host data processing commands on the host data path, and the second command execution time is the time for executing several garbage collection commands on the garbage collection data path; when the flash memory device has not entered a stable state, adjusting the number of host data processing commands and garbage collection commands issued and executed in the next time slice according to the relationship between the first command execution time and the second command execution time, until the flash memory device enters a stable state.

[0054] After garbage collection is started on the flash memory device, the first command execution time of executing several host data processing commands on the host data path and the second command execution time of executing several garbage collection commands on the garbage collection data path in each time slice are determined. When the flash memory device has not entered a stable state, the number of host data processing commands and garbage collection commands issued and executed in the next time slice is adjusted according to the relationship between the first command execution time and the second command execution time until the flash memory device enters a stable state. The present application can adjust the command allocation of the host data path and the garbage collection data path in real time to achieve optimal utilization of data path resources under different states, thereby improving the utilization rate of the overall data path and enhancing the overall performance of the flash memory device. BRIEF DESCRIPTION OF THE DRAWINGS

[0055] One or more embodiments are exemplarily described by pictures in the corresponding drawings, and these exemplified descriptions do not constitute limitations on the embodiments. Elements with the same reference numerals in the drawings represent similar elements, and unless otherwise stated, the figures in the drawings do not constitute proportional limitations.

[0056] Figure 1 is a structural schematic diagram of a flash memory device provided in an embodiment of the present application;

[0057] Figure 2 is a schematic diagram of the structure of another flash memory device provided in an embodiment of the present application;

[0058] Figure 3 It is a flowchart of a command management method provided by an embodiment of the present application;

[0059] Figure 4 It is a detailed flowchart of a command management method provided in an embodiment of the present application;

[0060] Figure 5is a schematic diagram of the structure of a storage control chip provided in an embodiment of the present application;

[0061] Figure 6 It is a structural schematic diagram of another flash memory device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0062] In order to make the purpose, technical solutions and advantages of the present application more clearly understood, the present application is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and are not intended to limit the present application. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in the field without making creative work are within the scope of protection of the present application.

[0063] It should be noted that, if there is no conflict, the various features in the embodiments of the present application can be combined with each other, all within the scope of protection of the present application. In addition, although the functional module division is performed in the device schematic diagram and the logical order is shown in the flow chart, in some cases, the steps shown or described can be performed in a sequence different from the module division in the device or the flow chart. Furthermore, the words "first", "second", "third", etc. used in this application do not limit the data and execution order, but only distinguish the same items or similar items with basically the same functions and effects.

[0064] The technical solution of this application is described in detail below with reference to the accompanying drawings:

[0065] Flash memory devices, such as solid state drives (SSDs), are storage devices that use semiconductor flash memory (NAND Flash) as a medium. Flash memory devices include a host data path, which is used to implement data exchange between the host and the flash memory.

[0066] Currently, cache memory is added inside the flash memory device to allocate cache resources to the host data path to increase the speed at which the host data path processes data. However, the cache is usually integrated inside the main control of the flash memory device. Due to cost pressure, the storage space of the cache is usually not very large, and the flash memory device still uses memory to store part of the host data.

[0067] See also Figure 1 , Figure 1 is a structural schematic diagram of a flash memory device provided in an embodiment of the present application;

[0068] like Figure 1As shown, the flash memory device 100 includes a cache 101, a memory 102 and a flash memory 103. There is no exchange path (swap path) between the cache 101 and the memory 102. The flash memory device 100 uses the cache 101 and the memory 102 to store host data at the same time. Among them, the storage space of the cache 101 is smaller than the storage space of the memory 102. The speed of storing data in the cache 101 is faster than the speed of storing data in the memory 102. The cache 101 includes but is not limited to high-speed caches such as cache memory, and the memory 102 includes but is not limited to dynamic random access memories such as double data rate synchronous dynamic random access memory (DDR SDRAM).

[0069] At this time, the host data sent by the host 200 will be first stored in the cache 101 or the memory 102, and then written to the flash memory 103. After the flash memory device starts garbage collection (GC), the garbage collection read operation reads the data from the flash memory 103 to the cache 101 or the memory 102, and the garbage collection write operation rewrites the data to a new data block in the flash memory 103. In this case, the host data path includes the data path between the host 200 and the cache 101 or the data path between the host 200 and the memory 102, and the garbage collection data path includes the data path between the flash memory 103 and the cache 101 or the data path between the flash memory 103 and the memory 102.

[0070] See also Figure 2 , Figure 2 is a schematic diagram of the structure of another flash memory device provided in an embodiment of the present application;

[0071] like Figure 2 As shown, the flash memory device 100 includes a cache 101, a memory 102 and a flash memory 103. There is a swap path (swap path) between the cache 101 and the memory 102. The flash memory device 100 uses the cache 101 to store host data and realizes the swap function of the memory 102 at the same time, thereby completing the unified access to the cache 101 and the memory 102. Among them, the storage space of the cache 101 is smaller than the storage space of the memory 102, and the speed of storing data in the cache 101 is faster than the speed of storing data in the memory 102. The cache 101 includes but is not limited to high-speed caches such as cache memory (Cache Memory), and the memory 102 includes but is not limited to dynamic random access memories such as double data rate synchronous dynamic random access memory (Double Data Rate Synchronous Dynamic Random-Access Memory, DDR SDRAM).

[0072] At this time, the host data sent by the host 200 will first be stored in the cache 101. When the data written to the cache 101 is greater than the preset capacity threshold, the flash memory device 100 will swap part of the old data in the cache 101 to the memory 102. When it is necessary to write the data in the memory 102 to the flash memory 103, the path type is selected according to the data demand (i.e., writing the data to the flash memory 103 through the cache 101 or the memory 102). Usually, the data is first cached to the cache 101, and then the flushing action is performed to write the data from the cache 101 to the flash memory 103. After the flash memory device starts garbage collection, the garbage collection read operation first reads data from the flash memory 103 to the cache 101. When the data written to the cache 101 is greater than the preset capacity threshold, the flash memory device 100 swaps part of the old data in the cache 101 to the memory 102, and the garbage collection write operation rewrites the data from the cache 101 to the new data block in the flash memory 103, or caches the data from the memory 102 to the cache 101, and then writes the data from the cache 101 to the new data block in the flash memory 103. Among them, the preset capacity threshold can be set by those skilled in the art according to the capacity of the storage space of the cache 101, and is not limited here.

[0073] In this case, the host data path includes a data path between the host 200 and the cache 101 or a data path between the cache 101 and the memory 102 , and the garbage collection data path includes a data path between the flash memory 103 and the cache 101 or a data path between the cache 101 and the memory 102 .

[0074] It can be seen that Figure 1 and Figure 2 They are all optimized for the host data path, allocating cache resources to the host data path. After the flash device starts garbage collection, the garbage collection process needs to perform garbage collection write operations to provide the necessary storage space for the host data write. The host write operation will only be performed after garbage collection releases enough space.

[0075] For example, when the ratio of garbage collection write operations to host write operations is 3:1, three garbage collection write operations must be performed before each host write operation. Figure 1 In the case where there is no exchange path between the cache 101 and the memory 102, if the execution ratio of garbage collection write operations to host write operations is strictly controlled to be 3:1, the host data will enter the cache and also enter the memory. However, in fact, even if the host data enters the cache and improves the storage speed to some extent, the space release limitation in the garbage collection process still restricts the overall performance of the host data path and cannot improve the overall performance of the flash memory device.

[0076] for Figure 2In the case where there is an exchange path between the cache 101 and the memory 102, if the execution ratio of the garbage collection write operation and the host write operation is strictly controlled to be 3:1, the host data will enter the cache 101 and also enter the memory 102. However, in fact, even if the host data enters the cache 101 and improves the storage speed, the space release limitation in the garbage collection process still restricts the overall performance of the host data path. The utilization rate of the overall data path is low, and the overall performance of the flash memory device cannot be improved.

[0077] Although all host data will enter the cache and it seems that all paths are accelerated, in actual applications, the bandwidth of the memory is the bottleneck that determines the overall data path. All data enters the cache and is synchronously exchanged to the memory due to storage space constraints, which also occupies the memory bandwidth. In addition, due to the mutual constraints of data, the data in the cache cannot be fully utilized. There is also a low utilization rate of the overall data path, which cannot improve the overall performance of the flash memory device.

[0078] Based on this, an embodiment of the present application provides a command management method. When the flash memory device has not entered a stable state, the method adjusts the number of host data processing commands and garbage collection commands issued and executed in the next time slice according to the relationship between the first command execution time of executing several host data processing commands on the host data path and the second command execution time of executing several garbage collection commands on the garbage collection data path in each time slice, thereby adjusting the command allocation of the host data path and the garbage collection data path in real time, improving the utilization rate of the overall data path, and enhancing the overall performance of the flash memory device.

[0079] See also Figure 3 , Figure 3 It is a flowchart of a command management method provided by an embodiment of the present application;

[0080] The command management method is applied to a flash memory device, and specifically, to at least one processor of the flash memory device.

[0081] In an embodiment of the present application, the flash memory device includes a host data path and a garbage collection data path, wherein the host data path is used to implement data exchange between the host and the flash memory, and the garbage collection data path is used to implement data migration and recycling operations between different storage blocks in the flash memory.

[0082] In the embodiment of the present application, the flash memory device includes a cache, a memory and a flash memory, wherein the storage space of the cache is smaller than the storage space of the memory, and the speed of storing data in the cache is faster than the speed of storing data in the memory. The cache includes but is not limited to high-speed caches such as cache memory, and the memory includes but is not limited to dynamic random access memories such as double data rate synchronous dynamic random access memory (DDR SDRAM). The specific connection method between the cache and the memory is as follows: Figure 1 or Figure 2 shown.

[0083] In some embodiments, when the cache and memory are used as Figure 1 In the connection mode shown, that is, when there is no exchange path between the cache and the memory, the host data path includes the data path between the host and the cache or the data path between the host and the memory, and the garbage collection data path includes the data path between the flash memory and the cache or the data path between the flash memory and the memory.

[0084] In some embodiments, when the cache and memory are used as Figure 2 In the connection mode shown, that is, when there is an exchange path between the cache and the memory, the host data path includes the data path between the host and the cache or the data path between the cache and the memory, and the garbage collection data path includes the data path between the flash memory and the cache or the data path between the cache and the memory.

[0085] like Figure 3 As shown, the command management method includes:

[0086] Step S301: after the flash memory device starts garbage collection, determining the first command execution time and the second command execution time in each time slice;

[0087] Among them, the first command execution time is the time for executing several host data processing commands on the host data path, and the second command execution time is the time for executing several garbage collection commands on the garbage collection data path. The host data processing command is an operation instruction inside the flash memory device for realizing data interaction between the host and the flash memory, and the garbage collection command is an operation instruction inside the flash memory device for managing and optimizing the storage space of the flash memory.

[0088] Specifically, after the flash memory device starts garbage collection, a host data path and a garbage collection data path exist simultaneously inside the flash memory device, and the first command execution time of executing a plurality of host data processing commands on the host data path and the second command execution time of executing a plurality of garbage collection commands on the garbage collection data path are determined within each time slice. The size of each time slice is the same, and the size of the time slice can be set by those skilled in the art according to the time when the flash memory device executes the host data processing command or the garbage collection command, and is not limited here.

[0089] In an embodiment of the present application, the host data processing command includes a host data write command, and the garbage collection command includes a garbage collection write command or a garbage collection read command. Among them, the host data write command is a command initiated from within the flash memory device, which is used to instruct the flash memory device to first store the host data sent by the host to the cache or memory, and then write the host data from the cache or memory to the flash memory, the garbage collection read command is used to instruct the flash memory device to read valid data from the old data block in the flash memory to the cache or memory during the garbage collection process, and the garbage collection write command is used to instruct the flash memory device to execute the garbage collection read command to store the valid data stored in the cache or memory, and re-store it to the new data block in the flash memory.

[0090] In an embodiment of the present application, the host data path includes a host write path, and the garbage collection data path includes a garbage collection write path or a garbage collection read path. The host write path is used to execute a host data write command, the garbage collection write path is used to execute a garbage collection write command, and the garbage collection read path is used to execute a garbage collection read command.

[0091] In some embodiments, when the cache and memory are used as Figure 1 In the connection mode shown, that is, when there is no exchange path between the cache and the memory, the host write path includes the data path between the host and the cache or the data path between the host and the memory, the garbage collection write path includes the data path between the flash memory and the cache or the data path between the flash memory and the memory, and the garbage collection read path includes the data path between the flash memory and the cache or the data path between the flash memory and the memory.

[0092] In some embodiments, when the cache and memory are used as Figure 2 In the connection mode shown, that is, when there is an exchange path between the cache and the memory, the host write path includes the data path between the host and the cache or the data path between the cache and the memory, the garbage collection write path includes the data path between the flash memory and the cache or the data path between the cache and the memory, and the garbage collection read path includes the data path between the flash memory and the cache or the data path between the cache and the memory.

[0093] In an embodiment of the present application, a flash memory device includes a front-end module and a flash translation layer (FTL), the flash translation layer is used to send host data write commands, garbage collection write commands and garbage collection read commands to the front-end module, and the front-end module is used to receive and execute host data write commands, garbage collection write commands and garbage collection read commands. Before determining the first command execution time and the second command execution time in each time slice, the command management method also includes: determining the first number of host data write commands and the second number of garbage collection write commands issued in each time slice according to the write amplification factor, specifically including steps S1-step S3:

[0094] Step S1: Calculate the write amplification factor, and use the write amplification factor as the ratio of the number of garbage collection write commands and host data write commands issued in each time slice;

[0095] The write amplification factor is the ratio of the amount of data written to the flash memory to the amount of data written by the host to the flash memory device. For example, when the write amplification factor is 3:1, the ratio of the number of garbage collection write commands and host data write commands issued in each time slice is 3:1.

[0096] Step S2: determining a first quantity of host data write commands and a second quantity of garbage collection write commands issued in each time slice according to the quantity ratio and the preset unit quantity;

[0097] The preset unit quantity is a reference value of the number of write commands issued in each time slice, and is used to calculate the first quantity and the second quantity issued in each time slice in combination with the quantity ratio. The first quantity is the number of host data write commands issued in one time slice, and the second quantity is the number of garbage collection write commands issued in one time slice. The size of the preset unit quantity can be set by those skilled in the art according to the size of the cache or memory, and is not limited here.

[0098] Specifically, when the ratio of the number of garbage collection write commands and host data write commands issued in each time slice is a:b, the first number of host data write commands issued in each time slice is determined to be b*preset unit number, and the second number of garbage collection write commands issued in each time slice is determined to be a*preset unit number.

[0099] For example: the ratio of the number of garbage collection write commands and host data write commands issued in each time slice is 3:1, and the preset unit number is 100. Then the first number of host data write commands issued in each time slice is 100*1=100, and the second number of garbage collection write commands issued in each time slice is 100*3=300.

[0100] Step S3: In each time slice, a first number of host data write commands and a second number of garbage collection write commands are sent to the front-end module.

[0101] Specifically, the flash translation layer sends a first number of host data write commands and a second number of garbage collection write commands to the front-end module in each time slice.

[0102] In an embodiment of the present application, the host write path, the garbage collection write path, and the garbage collection read path each correspond to a command submission queue and a command completion queue. The command submission queue is used to store commands to be executed, and the command completion queue is used to store and record commands that have been executed.

[0103] In the embodiment of the present application, the time slice includes a first time slice, and the flash memory device executes a plurality of host data write commands and garbage collection commands within the first time slice, and calculates the first command execution time of executing these host data write commands and the second command execution time of executing these garbage collection commands. Step S301 specifically includes steps S311 to S316:

[0104] Step S311: recording the start timestamp of each host data write command, garbage collection write command or garbage collection read command submitted to the corresponding command submission queue;

[0105] The start timestamp is used to record the time when each host data write command, garbage collection write command or garbage collection read command is submitted to the corresponding command submission queue.

[0106] In an embodiment of the present application, the host data write command includes a host cache write command or a host memory write command, the garbage collection write command includes a garbage collection cache write command or a garbage collection memory write command, and the garbage collection read command includes a garbage collection cache read command or a garbage collection memory read command. The host cache write command and the garbage collection cache write command are used to store the corresponding data in the cache, the host memory write command and the garbage collection memory write command are used to store the corresponding data in the memory, the garbage collection cache read command is used to read the data in the flash memory into the cache, and the garbage collection memory read command is used to read the data in the flash memory into the memory.

[0107] In some embodiments, each host data write command, garbage collection write command, and garbage collection read command corresponds to a command type identifier to distinguish the command type of each host data write command, garbage collection write command, and garbage collection read command, wherein the command type of the host data write command is a host cache write command or a host memory write command, the command type of the garbage collection write command is a garbage collection cache write command or a garbage collection memory write command, and the command type of the garbage collection read command is a garbage collection cache read command or a garbage collection memory read command.

[0108] Step S312: executing a plurality of host data write commands, garbage collection write commands and garbage collection read commands within the first time slice;

[0109] Specifically, in the first time slice, a host cache write command, a host memory write command, a garbage collection cache write command, a garbage collection memory write command, a garbage collection cache read command, and a garbage collection memory read command are executed.

[0110] In the embodiment of the present application, when step S312 is executed for the first time, host cache write commands, host memory write commands, garbage collection cache write commands, garbage collection memory write commands, garbage collection cache read commands, and garbage collection memory read commands are issued according to the initial issued quantity, and each subsequent execution of step S312 is based on the number of host cache write commands, the number of host memory write commands, the number of garbage collection cache write commands, the number of garbage collection memory write commands, the number of garbage collection cache read commands, and the number of garbage collection memory read commands adjusted in step S302, and these commands are issued and executed until the flash memory device enters a stable state. The initial issued quantity can be set by a person skilled in the art according to the size of the cache or memory, and is not limited here.

[0111] It can be understood that the number of host data write commands and the number of garbage collection commands executed in each time slice remain unchanged, and what changes are the number of host cache write commands, the number of host memory write commands, the number of garbage collection cache write commands, the number of garbage collection memory write commands, the number of garbage collection cache read commands or the number of garbage collection memory read commands.

[0112] Step S313: Record the end timestamp of each host data write command, garbage collection write command or garbage collection read command when it is submitted to the corresponding command completion queue after execution is completed;

[0113] The end timestamp is used to record the time when the executed host data write command, garbage collection write command or garbage collection read command is submitted to the corresponding command completion queue.

[0114] Step S314: Calculate the execution time of each host data write command, garbage collection write command or garbage collection read command based on the end timestamp and the start timestamp;

[0115] Specifically, the execution time of each host data write command, garbage collection write command, or garbage collection read command is the time difference between the end timestamp and the start timestamp.

[0116] Step S315: adding the execution time of each host data write command executed in the first time slice, and taking the result as the first command execution time;

[0117] Specifically, the first command execution time is the sum of the execution time of each host cache write command and the execution time of each host memory write command executed in the first time slice.

[0118] Step S316: Add the execution time of each garbage collection write command and garbage collection read command executed in the first time slice, and use the obtained result as the second command execution time.

[0119] Specifically, the second command execution time is the sum of the execution time of each garbage collection cache write command, the execution time of each garbage collection memory write command, the execution time of each garbage collection cache read command and the execution time of each garbage collection memory read command executed within the first time slice.

[0120] In an embodiment of the present application, the second command execution time is the sum of the execution time of the garbage collection write command and the execution time of the garbage collection read command. Combined with step S302, which adjusts the number of each type of host data write commands and the number of each type of garbage collection commands issued based on the second command execution time, the present application only needs to issue the first number of host data write commands and the second number of garbage collection write commands in each time slice, and there is no need to specifically determine the number of garbage collection read commands issued in each time slice.

[0121] Step S302: When the flash memory device has not entered a stable state, the number of host data processing commands and garbage collection commands issued and executed in the next time slice is adjusted according to the relationship between the first command execution time and the second command execution time until the flash memory device enters a stable state.

[0122] The stable state includes a state in which the number of each type of host data write commands executed on the host data path of the flash memory device changes less than a preset number threshold within a number of consecutive time slices, or the number of each type of garbage collection commands executed on the garbage collection data path changes less than a preset number threshold. The preset number threshold can be set by those skilled in the art according to the size of the cache or memory, and is not limited here.

[0123] Specifically, determine whether the flash memory device has entered a stable state. If the flash memory device has entered a stable state, end the process; if the flash memory device has not entered a stable state, adjust the number of host cache write commands, the number of host memory write commands, the number of garbage collection cache write commands, the number of garbage collection memory write commands, the number of garbage collection cache read commands, and the number of garbage collection memory read commands issued and executed in the next time slice according to the relationship between the execution time of the first command and the execution time of the second command, until the flash memory device enters a stable state.

[0124] In an embodiment of the present application, the time slice also includes a second time slice or a third time slice. The flash memory device executes a number of host data write commands and garbage collection commands in the second time slice. The difference from the first time slice is that the flash memory device does not need to calculate the first command execution time and the second command execution time in the second time slice. The flash memory device determines the number of each type of host data write commands and the number of each type of garbage collection commands issued and executed in the third time slice based on the relationship between the first command execution time and the second command execution time in the first time slice. The flash memory device executes a number of host data write commands and garbage collection commands in the third time slice based on the adjusted number of each type of host data write commands and the number of each type of garbage collection commands. Step S302 specifically includes steps S321-S324:

[0125] Step S321: after the issuance of several host data write commands, garbage collection write commands and garbage collection read commands executed in the first time slice is completed, the issuance of several host data write commands, garbage collection write commands and garbage collection read commands executed in the second time slice is completed;

[0126] Specifically, after several host cache write commands, host memory write commands, garbage collection cache write commands, garbage collection memory write commands, garbage collection cache read commands, and garbage collection memory read commands executed in the first time slice are issued, several host data write commands, garbage collection write commands, and garbage collection read commands executed in the second time slice are issued.

[0127] In an embodiment of the present application, when step S321 is executed for the first time, host cache write commands, host memory write commands, garbage collection cache write commands, garbage collection memory write commands, garbage collection cache read commands, and garbage collection memory read commands are issued according to the initial issued quantity, and each subsequent execution of step S321 is similar to step S312, and these commands are issued and executed according to the number of host cache write commands, the number of host memory write commands, the number of garbage collection cache write commands, the number of garbage collection memory write commands, the number of garbage collection cache read commands, and the number of garbage collection memory read commands adjusted in step S302 until the flash memory device enters a stable state.

[0128] Step S322: Calculate the minimum command execution time within the first time slice;

[0129] The minimum command execution time is the minimum value between the first command execution time and the second command execution time.

[0130] Step S323: when the minimum command execution time is the first command execution time, reduce the number of host cache write commands, garbage collection memory write commands, and garbage collection memory read commands issued in the third time slice, and increase the number of host memory write commands, garbage collection cache write commands, and garbage collection cache read commands issued in the third time slice;

[0131] The sum of the number of host cache write commands and the number of host memory write commands is the first number, and the sum of the number of garbage collection memory write commands and the number of garbage collection cache write commands is the second number. Reducing the number of issued host cache write commands, the number of garbage collection memory write commands, and the number of garbage collection memory read commands, and increasing the number of issued host memory write commands, the number of garbage collection cache write commands, and the number of garbage collection cache read commands within the third time slice can be set by those skilled in the art according to the first command execution time and the second command execution time, and is not limited here.

[0132] Specifically, when the minimum command execution time is the first command execution time, the execution speed of the host data write command is better than the execution speed of the garbage collection command. Since the ratio of the number of garbage collection write commands and host data write commands issued in each time slice remains unchanged, the execution speed of the garbage collection command is improved by reducing the number of host cache write commands, the number of garbage collection memory write commands, and the number of garbage collection memory read commands issued in the third time slice, and increasing the number of host memory write commands, the number of garbage collection cache write commands, and the number of garbage collection cache read commands issued in the third time slice, thereby improving the utilization rate of the entire data path.

[0133] Step S324: When the minimum command execution time is the second command execution time, increase the number of host cache write commands, garbage collection memory write commands, and garbage collection memory read commands issued in the third time slice, and reduce the number of host memory write commands, garbage collection cache write commands, and garbage collection cache read commands issued in the third time slice.

[0134] The sum of the number of host cache write commands and the number of host memory write commands is the first number, and the sum of the number of garbage collection memory write commands and the number of garbage collection cache write commands is the second number. Increasing the number of issued host cache write commands, the number of garbage collection memory write commands, and the number of garbage collection memory read commands, and reducing the number of issued host memory write commands, the number of garbage collection cache write commands, and the number of garbage collection cache read commands within the third time slice can be set by those skilled in the art according to the first command execution time and the second command execution time, and is not limited here.

[0135] Specifically, when the minimum command execution time is the second command execution time, the execution speed of the host data write command is lower than the execution speed of the garbage collection command. Since the ratio of the number of garbage collection write commands and host data write commands issued in each time slice remains unchanged, the execution speed of the host data write command is improved by increasing the number of host cache write commands, the number of garbage collection memory write commands, and the number of garbage collection memory read commands issued in the third time slice and reducing the number of host memory write commands, the number of garbage collection cache write commands, and the number of garbage collection cache read commands issued in the third time slice, thereby improving the utilization rate of the entire data path.

[0136] In the embodiment of the present application, step S302 also includes steps S325-S327:

[0137] Step S325: executing a plurality of host data write commands, garbage collection write commands and garbage collection read commands within the third time slice, and using the third time slice as the first time slice of a new round, and determining the first command execution time and the second command execution time of the first time slice of the new round;

[0138] Specifically, the third time slice is used as the first time slice of a new round, and step S301 is executed again.

[0139] Step S326: after the issuance of a number of host data write commands, garbage collection write commands and garbage collection read commands executed in the third time slice, a number of host cache write commands, host memory write commands, garbage collection cache read commands, garbage collection memory read commands, garbage collection memory write commands and garbage collection cache write commands executed in a new round in the second time slice are issued according to the number of host cache write commands, the number of host memory write commands, the number of garbage collection cache read commands, the number of garbage collection memory write commands and the number of garbage collection cache write commands issued in the third time slice;

[0140] Specifically, after the third time slice is used as the first time slice of a new round in step S325, step S321 is re-executed.

[0141] Step S327: According to the relationship between the first command execution time and the second command execution time of the first time slice of the new round, adjust the number of host cache write commands, the number of host memory write commands, the number of garbage collection cache read commands, the number of garbage collection memory read commands, the number of garbage collection memory write commands, and the number of garbage collection cache write commands issued and executed in the third time slice of the new round until the flash memory device enters a stable state.

[0142] Specifically, after the third time slice is used as the first time slice of a new round in step S325, steps S322 to S324 are re-executed to adjust the number of host cache write commands, host memory write commands, garbage collection cache read commands, garbage collection memory read commands, garbage collection memory write commands, and garbage collection cache write commands issued and executed in the third time slice of the new round. Steps S301 to S302 are repeatedly executed until after any execution of step S301, when it is determined whether the flash memory device has entered a stable state, it is determined that the flash memory device has entered a stable state, and the process ends.

[0143] In an embodiment of the present application, the step of determining whether the flash memory device has entered a stable state includes: determining whether the difference between the minimum command execution time of each two consecutive rounds is less than a preset time threshold, or whether the number of host cache write commands, host memory write commands, garbage collection cache write commands, garbage collection memory write commands, garbage collection cache read commands, or garbage collection memory read commands in any time slice of any round is zero. The time slice includes a first time slice, a second time slice, or a third time slice.

[0144] Specifically, the minimum command execution time of each round is recorded by an array. When the difference between the minimum command execution time of two consecutive rounds in the preset number of rounds is less than the preset time threshold, that is, the fluctuation of the minimum command execution time of multiple rounds is within a small range, it is determined that the flash memory device has entered a stable state. Alternatively, when the number of any command of the host cache write command, host memory write command, garbage collection cache write command, garbage collection memory write command, garbage collection cache read command or garbage collection memory read command is reduced to zero in any time slice of any round, there is no room for adjusting the number of commands at this time, and it is determined that the flash memory device has entered a stable state. Among them, the preset number of rounds is the minimum number of rounds for executing steps S301 and S302 when the flash memory device enters a stable state, and the preset time threshold is the maximum value of the difference between the minimum command execution time of two consecutive rounds when the flash memory device enters a stable state. The preset number of rounds and the preset time threshold can be set by those skilled in the art according to the first command execution time and the second command execution time, and are not limited here.

[0145] When the difference between the minimum command execution times of two consecutive rounds is less than a preset time threshold, or when the number of host cache write commands, host memory write commands, garbage collection cache write commands, garbage collection memory write commands, garbage collection cache read commands or garbage collection memory read commands is zero in any time slice of any round, it is determined that the flash memory device has entered a stable state.

[0146] For example, all host data write commands issued in any time slice of any round are host memory write commands, that is, the number of host cache write commands is zero. This is the slowest execution of host data write commands, and there is no room for adjustment, which means that the flash memory device enters a stable state.

[0147] When the difference between the minimum command execution times of two consecutive rounds is greater than or equal to a preset time threshold, and the number of each of the host cache write commands, host memory write commands, garbage collection cache write commands, garbage collection memory write commands, garbage collection cache read commands, and garbage collection memory read commands in any time slice of each round is not zero, it is determined that the flash memory device has not entered a stable state.

[0148] See also Figure 4 , Figure 4 It is a detailed flowchart of a command management method provided in an embodiment of the present application;

[0149] like Figure 4 As shown in the figure, the detailed process of the command management method includes:

[0150] Step S401: Determine whether the flash memory device starts garbage collection;

[0151] Specifically, if the flash memory device starts garbage collection, the process proceeds to step S402; if the flash memory device does not start garbage collection, the process ends.

[0152] Step S402: determining a first number of host data write commands and a second number of garbage collection write commands issued in each time slice according to the write amplification factor;

[0153] Specifically, the write amplification coefficient is calculated and used as the ratio of the number of garbage collection write commands and host data write commands issued in each time slice. When the ratio of the number of garbage collection write commands and host data write commands issued in each time slice is a:b, the first number of host data write commands issued in each time slice is determined to be b*preset unit number, and the second number of garbage collection write commands issued in each time slice is determined to be a*preset unit number.

[0154] Step S403: Initialize three time slice data command management bodies;

[0155] Specifically, the three time slice data command management bodies include a first time slice data command management body, a second time slice data command management body, and a third time slice data command management body. The first time slice data command management body is used to schedule and execute a number of host data write commands and garbage collection commands within a first time slice, and calculate the first command execution time of executing these host data write commands and the second command execution time of executing these garbage collection commands.

[0156] The second time slice data command management body is used to schedule the execution of a number of host data write commands and garbage collection commands in the second time slice, and determine the number of each type of host data write commands and the number of each type of garbage collection commands issued and executed in the third time slice according to the relationship between the first command execution time and the second command execution time in the first time slice in the second time slice. The third time slice data command management body is used to schedule the execution of a number of host data write commands and garbage collection commands in the third time slice according to the adjusted number of each type of host data write commands and the number of each type of garbage collection commands.

[0157] Step S404: determining the first command execution time and the second command execution time within the current time slice;

[0158] Specifically, within the first time slice, several host cache write commands, host memory write commands, garbage collection cache write commands, garbage collection memory write commands, garbage collection cache read commands, and garbage collection memory read commands are executed, and the first command execution time and the second command execution time within the first time slice are determined.

[0159] Alternatively, after executing step S410 or step S411, the third time slice is used as the first time slice of a new round, and according to the number of host cache write commands, the number of host memory write commands, the number of garbage collection cache write commands, the number of garbage collection memory write commands, the number of garbage collection cache read commands, and the number of garbage collection memory read commands adjusted in step S410 or step S411, these commands are issued and executed, and the first command execution time and the second command execution time in the first time slice of the new round are determined. The specific implementation of this step is similar to the specific implementation of step S301, and will not be repeated here.

[0160] Step S405: determining whether the flash memory device enters a stable state;

[0161] Specifically, it is determined whether the difference between the minimum command execution time of each two consecutive rounds is less than a preset time threshold, or whether the number of host cache write commands, host memory write commands, garbage collection cache write commands, garbage collection memory write commands, garbage collection cache read commands, or garbage collection memory read commands in any time slice of any round is zero. The time slice includes a first time slice, a second time slice, or a third time slice.

[0162] If the difference between the minimum command execution time of each two consecutive rounds is less than the preset time threshold, or if the number of host cache write commands, host memory write commands, garbage collection cache write commands, garbage collection memory write commands, garbage collection cache read commands or garbage collection memory read commands is zero in any time slice of any round, it is determined that the flash memory device has entered a stable state and the process ends.

[0163] If the difference between the minimum command execution time of each consecutive round is greater than or equal to the preset time threshold, and the number of each type of command among the host cache write command, host memory write command, garbage collection cache write command, garbage collection memory write command, garbage collection cache read command, and garbage collection memory read command in any time slice of each round is not zero, it is determined that the flash memory device has not entered a stable state, and the process goes to step S406.

[0164] Step S406: determining whether a number of host data write commands, garbage collection write commands and garbage collection read commands executed in the first time slice have been issued;

[0165] Specifically, if several host data write commands, garbage collection write commands and garbage collection read commands executed in the first time slice have been issued, enter step S407; if several host data write commands, garbage collection write commands and garbage collection read commands executed in the first time slice have not been issued, return to step S404.

[0166] Step S407: issuing a number of host data write commands, garbage collection write commands and garbage collection read commands executed in the second time slice;

[0167] Specifically, when step S407 is executed for the first time, a number of host data write commands, garbage collection write commands, and garbage collection read commands executed in the second time slice are issued according to the initial issued quantity. Each subsequent execution of step S407 is based on the number of host cache write commands, the number of host memory write commands, the number of garbage collection cache write commands, the number of garbage collection memory write commands, the number of garbage collection cache read commands, and the number of garbage collection memory read commands adjusted in step S410 or step S411, and these commands are issued and executed.

[0168] Step S408: Calculate the minimum command execution time within the first time slice;

[0169] The minimum command execution time is the minimum value between the first command execution time and the second command execution time.

[0170] Step S409: determining whether the minimum command execution time is the first command execution time;

[0171] Specifically, if the minimum command execution time is the first command execution time, the process proceeds to step S410 ; if the minimum command execution time is not the first command execution time, that is, the minimum command execution time is the second command execution time, the process proceeds to step S411 .

[0172] Step S410: reducing the number of host cache write commands, garbage collection memory write commands, and garbage collection memory read commands issued in the third time slice, and increasing the number of host memory write commands, garbage collection cache write commands, and garbage collection cache read commands issued in the third time slice;

[0173] Specifically, the specific implementation of this step is the same as the specific implementation of step S323, which will not be repeated here.

[0174] Step S411: Increase the number of host cache write commands, garbage collection memory write commands, and garbage collection memory read commands issued in the third time slice, and reduce the number of host memory write commands, garbage collection cache write commands, and garbage collection cache read commands issued in the third time slice.

[0175] Specifically, the specific implementation of this step is the same as the specific implementation of step S324, which will not be repeated here.

[0176] Further, after executing step S411, return to step S404, use the third time slice as the first time slice of a new round, and repeat steps S404-S411 until it is determined in any round of step S405 that the flash memory device enters a stable state, and the process ends.

[0177] In an embodiment of the present application, by executing several host data write commands and garbage collection commands within a first time slice, and calculating the first command execution time of executing these host data write commands and the second command execution time of executing these garbage collection commands, the number of each type of host data write commands and the number of each type of garbage collection commands issued and executed in a third time slice are determined in a second time slice according to the relationship between the first command execution time and the second command execution time in the first time slice, and the host data write commands and the garbage collection commands are executed in the third time slice according to the adjusted number of each type of host data write commands and the number of each type of garbage collection commands. The present application can improve the smoothness and controllability of the command quantity adjustment of the host data path and the garbage collection data path, reduce data fluctuations, and improve the stability of the flash memory device.

[0178] In an embodiment of the present application, when the flash memory device has not entered a stable state, according to the relationship between the first command execution time and the second command execution time in the first time slice, the number of host cache write commands, the number of host memory write commands, the number of garbage collection cache write commands, the number of garbage collection memory write commands, the number of garbage collection cache read commands, and the number of garbage collection memory read commands issued and executed in the third time slice are adjusted until the flash memory device enters a stable state. The present application can ignore the underlying implementation and only obtain the optimal command quantity scheduling method based on upper-layer feedback, and is applicable to various types of caches.

[0179] In some embodiments, the host data processing command also includes a host data read command, which is a command initiated from within the flash memory device and is used to instruct the flash memory device to read data from the flash memory into a cache or memory, and then send the data from the cache or memory to the host. The host data read command includes a host cache read command and a host memory read command. The host cache read command is used to instruct the flash memory device to read data from the flash memory into a cache, and the host memory read command is used to instruct the flash memory device to read data from the flash memory into a memory. The host data path also includes a host read path, which is used to execute the host data read command.

[0180] In some embodiments, when the cache and memory are used as Figure 1 In the connection mode shown, that is, when there is no exchange path between the cache and the memory, the host read path includes the data path between the host and the cache or the data path between the host and the memory. At this time, the data types in the cache include: data corresponding to the host cache write command, data corresponding to the host cache read command, data corresponding to the garbage collection cache write command, and data corresponding to the garbage collection cache read command, and the data types in the memory include: data corresponding to the host memory write command, data corresponding to the host memory read command, data corresponding to the garbage collection memory write command, and data corresponding to the garbage collection memory read command.

[0181] In some embodiments, when the cache and memory are used as Figure 2 In the connection mode shown, when there is a switching path between the cache and the memory, the host read path includes the data path between the host and the cache or the data path between the cache and the memory. At this time, since there is a switching path between the cache and the memory, by configuring the data priority, the data types in the cache can still include: data corresponding to the host cache write command, data corresponding to the host cache read command, data corresponding to the garbage collection cache write command, and data corresponding to the garbage collection cache read command, and the data types in the memory include: data corresponding to the host memory write command, data corresponding to the host memory read command, data corresponding to the garbage collection memory write command, and data corresponding to the garbage collection memory read command.

[0182] In some embodiments, the host read path corresponds to a command submission queue. The command management method further includes: setting different priorities for the host data read command, the host data write command, the garbage collection write command and the garbage collection read command, and controlling the priority of the host data read command to be the highest priority; after the host data read command is submitted to the corresponding command submission queue, interrupting the processing of the low-priority host data write command, the garbage collection write command and the garbage collection read command, and issuing and executing the host data read command.

[0183] Specifically, for the data types in the cache and the data types in the memory, different data types determine the priority and processing method of the data. By controlling the priority of the host data read command to be the highest priority, the host cache read command or the host memory read command is preferentially issued and executed, and the command allocation of the host write path and the garbage collection data path will not affect the host data read command. Moreover, due to the fast reading speed, the host data read command will not occupy a large amount of cache or memory when executed. Only steps S301 and S302 are executed for the host data write command and the garbage collection command to adjust the number of issued and executed host cache write commands, the number of host memory write commands, the number of garbage collection cache write commands, the number of garbage collection memory write commands, the number of garbage collection cache read commands, and the number of garbage collection memory read commands, so as to adjust the cache occupancy of the data corresponding to the host cache write command, the data corresponding to the garbage collection cache write command, and the data corresponding to the garbage collection cache read command, and adjust the memory occupancy of the data corresponding to the host memory write command, the data corresponding to the garbage collection memory write command, and the data corresponding to the garbage collection memory read command, thereby achieving optimal utilization of data path resources under different states, improving the utilization rate of the overall data path, and improving the overall performance of the flash memory device.

[0184] In an embodiment of the present application, a command management method is provided, which is applied to a flash memory device, and the flash memory device includes a host data path and a garbage collection data path. The command management method includes: after the flash memory device starts garbage collection, determining a first command execution time and a second command execution time in each time slice, wherein the first command execution time is the time for executing several host data processing commands on the host data path, and the second command execution time is the time for executing several garbage collection commands on the garbage collection data path; when the flash memory device has not entered a stable state, adjusting the number of host data processing commands and garbage collection commands issued and executed in the next time slice according to the relationship between the first command execution time and the second command execution time until the flash memory device enters a stable state.

[0185] After garbage collection is started on the flash memory device, the first command execution time of executing several host data processing commands on the host data path and the second command execution time of executing several garbage collection commands on the garbage collection data path in each time slice are determined. When the flash memory device has not entered a stable state, the number of host data processing commands and garbage collection commands issued and executed in the next time slice is adjusted according to the relationship between the first command execution time and the second command execution time until the flash memory device enters a stable state. The present application can adjust the command allocation of the host data path and the garbage collection data path in real time to achieve optimal utilization of data path resources under different states, thereby improving the utilization rate of the overall data path and enhancing the overall performance of the flash memory device.

[0186] See also Figure 5 , Figure 5 is a schematic diagram of the structure of a storage control chip provided in an embodiment of the present application;

[0187] like Figure 5 As shown, the storage control chip 104 includes one or more processors 141 and a memory 142. Among them, Figure 5 A processor 141 is taken as an example.

[0188] The processor 141 and the memory 142 may be connected via a bus or other means. Figure 5 The example of connecting through bus is taken in the following.

[0189] The processor 141 is used to provide computing and control capabilities to control the flash memory device 100 to perform corresponding tasks, for example, to control the flash memory device 100 to execute the command management method in any of the above method embodiments, the command management method is applied to the flash memory device, the flash memory device includes a host data path and a garbage collection data path, the command management method includes: after the flash memory device starts garbage collection, determine the first command execution time and the second command execution time in each time slice, wherein the first command execution time is the time for executing several host data processing commands on the host data path, and the second command execution time is the time for executing several garbage collection commands on the garbage collection data path; when the flash memory device has not entered a stable state, according to the relationship between the first command execution time and the second command execution time, adjust the number of host data processing commands and garbage collection commands issued and executed in the next time slice until the flash memory device enters a stable state.

[0190] After garbage collection is started on the flash memory device, the first command execution time of executing several host data processing commands on the host data path and the second command execution time of executing several garbage collection commands on the garbage collection data path in each time slice are determined. When the flash memory device has not entered a stable state, the number of host data processing commands and garbage collection commands issued and executed in the next time slice is adjusted according to the relationship between the first command execution time and the second command execution time until the flash memory device enters a stable state. The present application can adjust the command allocation of the host data path and the garbage collection data path in real time to achieve optimal utilization of data path resources under different states, thereby improving the utilization rate of the overall data path and enhancing the overall performance of the flash memory device.

[0191] The processor 141 may be a general-purpose processor, including a central processing unit (CPU), a network processor (NP), a hardware chip or any combination thereof; it may also be a digital signal processor (DSP), an application specific integrated circuit (ASIC), a programmable logic device (PLD) or a combination thereof. The above-mentioned PLD may be a complex programmable logic device (CPLD), a field programmable gate array (FPGA), a generic array logic (GAL) or any combination thereof.

[0192] The memory 142, as a non-transitory computer-readable storage medium, can be used to store non-transitory software programs, non-transitory computer executable programs and modules, such as program instructions / modules corresponding to the command management method in the embodiment of the present application. The processor 141 can implement the command management method in any of the above method embodiments by running the non-transitory software programs, instructions and modules stored in the memory 142. Specifically, the memory 142 may include a volatile memory (VM), such as a random access memory (RAM); the memory 142 may also include a non-volatile memory (NVM), such as a read-only memory (ROM), a flash memory (Flash Memory), a hard disk (HDD) or a solid-state drive (SSD) or other non-transitory solid-state storage device; the memory 142 may also include a combination of the above types of memories.

[0193] The memory 142 may include a high-speed random access memory, and may also include a non-volatile memory, such as at least one disk storage device, a flash memory device, or other non-volatile solid-state storage device. In some embodiments, the memory 142 may optionally include a memory remotely arranged relative to the processor 141, and these remote memories may be connected to the processor 141 via a network. Examples of the above-mentioned network include, but are not limited to, the Internet, an intranet, a local area network, a mobile communication network, and combinations thereof.

[0194] One or more modules are stored in the memory 142, and when executed by one or more processors 141, execute the command management method in any of the above method embodiments, for example, execute the command management method described above. Figure 3 The steps shown.

[0195] See also Figure 6 , Figure 6 is a structural schematic diagram of another flash memory device provided in an embodiment of the present application;

[0196] like Figure 6 As shown, the flash memory device 100 includes a storage control chip 104 and at least one flash memory 103. The flash memory 103 is connected to the storage control chip 104 for communication. Figure 6 A flash memory 103 is taken as an example.

[0197] The storage control chip 104 is used to execute the command management method in any of the above embodiments, and the command management method is applied to a flash memory device, and the flash memory device includes a host data path and a garbage collection data path. The command management method includes: after the flash memory device starts garbage collection, determining the first command execution time and the second command execution time in each time slice, wherein the first command execution time is the time for executing several host data processing commands on the host data path, and the second command execution time is the time for executing several garbage collection commands on the garbage collection data path; when the flash memory device has not entered a stable state, adjusting the number of host data processing commands and garbage collection commands issued and executed in the next time slice according to the relationship between the first command execution time and the second command execution time until the flash memory device enters a stable state.

[0198] The flash memory 103 is communicatively connected to the storage control chip 104 and is used for storing data.

[0199] In an embodiment of the present application, a flash memory device includes a storage control chip, and the storage control chip is used to execute the command management method in any of the above embodiments. The present application can adjust the command allocation of the host data path and the garbage collection data path in real time to achieve optimal utilization of data path resources under different states, thereby improving the utilization rate of the overall data path and enhancing the overall performance of the flash memory device.

[0200] An embodiment of the present application also provides a non-volatile computer storage medium, which stores computer executable instructions, and the computer executable instructions are executed by one or more processors. For example, the one or more processors can execute the command management method in any of the above method embodiments, for example, execute the various steps described above.

[0201] The above-described device or equipment embodiments are merely illustrative, wherein the unit modules described as separate components may or may not be physically separated, and the components displayed as module units may or may not be physical units, that is, they may be located in one place, or may be distributed on multiple network module units. Some or all of the modules may be selected according to actual needs to achieve the purpose of the present embodiment.

[0202] Through the description of the above implementation methods, those skilled in the art can clearly understand that each implementation method can be implemented by means of software plus a general hardware platform, and of course, by hardware. Based on this understanding, the above technical solution can be essentially or in other words, the part that contributes to the relevant technology can be embodied in the form of a software product, and the computer software product can be stored in a computer-readable storage medium, such as ROM / RAM, a disk, an optical disk, etc., including a number of instructions for a computer device (which can be a personal computer, a server, or a network device, etc.) to execute various embodiments or certain parts of the embodiments.

[0203] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present application, rather than to limit them. Under the concept of the present application, the technical features in the above embodiments or different embodiments can also be combined, the steps can be implemented in any order, and there are many other changes in different aspects of the present application as above, which are not provided in detail for the sake of simplicity. Although the present application has been described in detail with reference to the aforementioned embodiments, a person of ordinary skill in the art should understand that the technical solutions described in the aforementioned embodiments can still be modified, or some of the technical features can be replaced by equivalents. These modifications or replacements do not deviate the essence of the corresponding technical solutions from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A command management method, characterized in that: Applied to a flash memory device, the flash memory device includes a host data path and a garbage collection data path, the method includes: After the flash memory device starts garbage collection, determining a first command execution time and a second command execution time in each time slice, wherein the first command execution time is the time for executing a plurality of host data processing commands on the host data path, and the second command execution time is the time for executing a plurality of garbage collection commands on the garbage collection data path; When the flash memory device has not entered a stable state, the number of host data processing commands and garbage collection commands issued and executed in the next time slice is adjusted according to the relationship between the execution time of the first command and the execution time of the second command until the flash memory device enters a stable state.

2. The method according to claim 1, characterized in that The flash memory device includes a cache, a memory and a flash memory; The host data path includes a data path between the host and the cache or a data path between the host and the memory, and the garbage collection data path includes a data path between the flash memory and the cache or a data path between the flash memory and the memory; Alternatively, the host data path includes a data path between the host and the cache or a data path between the cache and the memory, and the garbage collection data path includes a data path between the flash memory and the cache or a data path between the cache and the memory.

3. The method according to claim 1, characterized in that The host data processing command includes a host data write command, and the garbage collection command includes a garbage collection write command or a garbage collection read command; The host data path includes a host write path, and the garbage collection data path includes a garbage collection write path or a garbage collection read path. The host write path is used to execute host data write commands, the garbage collection write path is used to execute garbage collection write commands, and the garbage collection read path is used to execute garbage collection read commands.

4. The method according to claim 3, characterized in that The flash memory device includes a front-end module. Before determining the first command execution time and the second command execution time in each time slice, the method further includes: Calculate a write amplification factor, and use the write amplification factor as the ratio of the number of garbage collection write commands and host data write commands issued in each time slice; Determining a first quantity of host data write commands and a second quantity of garbage collection write commands issued in each time slice according to the quantity ratio and a preset unit quantity; In each time slice, a first number of host data write commands and a second number of garbage collection write commands are sent to the front-end module.

5. The method according to claim 3, characterized in that: The host write path, the garbage collection write path, and the garbage collection read path each correspond to a command submission queue and a command completion queue; The determining of the first command execution time and the second command execution time in each time slice includes: Recording a start timestamp when each of the host data write commands, the garbage collection write commands, or the garbage collection read commands is submitted to a corresponding command submission queue; In a first time slice, executing a plurality of the host data write commands, the garbage collection write commands and the garbage collection read commands; Recording the end timestamp of each host data write command, garbage collection write command or garbage collection read command when it is submitted to the corresponding command completion queue after execution is completed; Calculating the execution time of each of the host data write command, the garbage collection write command, or the garbage collection read command based on the end timestamp and the start timestamp; Adding the execution time of each host data write command executed in the first time slice, and using the result as the first command execution time; The execution time of each garbage collection write command and garbage collection read command executed in the first time slice is added together, and the obtained result is used as the second command execution time.

6. The method according to claim 5, characterized in that The flash memory device includes a cache, a memory and a flash memory, the host data write command includes a host cache write command or a host memory write command, the garbage collection write command includes a garbage collection cache write command or a garbage collection memory write command, and the garbage collection read command includes a garbage collection cache read command or a garbage collection memory read command.

7. The method according to claim 6, characterized in that The adjusting, according to the relationship between the first command execution time and the second command execution time, the number of host data processing commands and garbage collection commands issued and executed in the next time slice includes: After the issuance of the plurality of host data write commands, the garbage collection write commands and the garbage collection read commands executed in the first time slice is completed, issuing the plurality of host data write commands, the garbage collection write commands and the garbage collection read commands executed in the second time slice; Calculating a minimum command execution time within a first time slice, wherein the minimum command execution time is a minimum value between the first command execution time and the second command execution time; When the minimum command execution time is the first command execution time, the number of host cache write commands, garbage collection memory write commands, and garbage collection memory read commands issued in the third time slice is reduced, and the number of host memory write commands, garbage collection cache write commands, and garbage collection cache read commands issued in the third time slice is increased; When the minimum command execution time is the second command execution time, the number of host cache write commands, garbage collection memory write commands, and garbage collection memory read commands issued in the third time slice is increased, and the number of host memory write commands, garbage collection cache write commands, and garbage collection cache read commands issued in the third time slice is reduced; The sum of the host cache write commands and the host memory write commands is a first quantity, and the sum of the garbage collection memory write commands and the garbage collection cache write commands is a second quantity.

8. The method according to claim 7, characterized in that The adjusting the number of host data processing commands and garbage collection commands issued and executed in the next time slice according to the relationship between the execution time of the first command and the execution time of the second command also includes: In a third time slice, execute a plurality of the host data write commands, the garbage collection write commands, and the garbage collection read commands, and use the third time slice as a first time slice of a new round, and determine a first command execution time and a second command execution time of the first time slice of the new round; After the issuance of the plurality of host data write commands, the garbage collection write commands and the garbage collection read commands executed in the third time slice is completed, issuing a new round of plurality of host cache write commands, host memory write commands, garbage collection cache read commands, garbage collection memory read commands, garbage collection memory write commands and garbage collection cache write commands executed in the second time slice according to the number of host cache write commands, host memory write commands, garbage collection cache read commands, garbage collection memory read commands, garbage collection memory write commands and garbage collection cache write commands issued in the third time slice; According to the relationship between the first command execution time and the second command execution time of the first time slice of the new round, adjust the number of host cache write commands, host memory write commands, garbage collection cache read commands, garbage collection memory read commands, garbage collection memory write commands, and garbage collection cache write commands issued and executed in the third time slice of the new round until the flash memory device enters a stable state.

9. The method according to claim 7 or 8, characterized in that: The method further comprises: When the difference between the minimum command execution times of each two consecutive rounds is less than a preset time threshold, or when the number of host cache write commands, host memory write commands, garbage collection cache write commands, garbage collection memory write commands, garbage collection cache read commands or garbage collection memory read commands is zero in any time slice of any round, it is determined that the flash memory device enters a stable state, wherein the time slice includes a first time slice, a second time slice or a third time slice.

10. The method according to any one of claims 3 to 8, characterized in that: The host data processing command further includes a host data read command, the host data path further includes a host read path, the host read path is used to execute the host data read command, and the host read path corresponds to a command submission queue; The method further comprises: Setting different priorities for the host data read command, the host data write command, the garbage collection write command and the garbage collection read command, and controlling the priority of the host data read command to be the highest priority; After the host data read command is submitted to the corresponding command submission queue, the processing of low-priority host data write commands, garbage collection write commands and garbage collection read commands is interrupted, and the host data read command is issued and executed.

11. A storage control chip, characterized in that: include: at least one processor; as well as, a memory communicatively connected to the at least one processor; wherein, The memory stores instructions that can be executed by the at least one processor, and the instructions are executed by the at least one processor so that the at least one processor can execute the command management method according to any one of claims 1 to 10.

12. A flash memory device, characterized in that: include: The storage control chip as claimed in claim 11; At least one flash memory is communicatively connected to the storage control chip.

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