Command management methods, storage controller chips, and flash memory devices

Abstract

This application relates to the field of storage device applications and discloses a command management method, a storage control chip, and a flash memory device. The flash memory device includes a host data path and a garbage collection data path. After the flash memory device starts garbage collection, the method determines the first command execution time for executing several host data processing commands on the host data path and the second command execution time for executing several garbage collection commands on the garbage collection data path within each time slice. When the flash memory device has not entered a stable state, the method adjusts the number of host data processing commands and garbage collection commands issued and executed in the next time slice according to the relationship between the first command execution time and the second command execution time, until the flash memory device enters a stable state. This application can adjust the command allocation of the host data path and the garbage collection data path in real time, improve the overall data path utilization, and enhance the overall performance of the flash memory device.

Description

Technical Field

[0001] This application relates to the field of storage device applications, and in particular to a command management method, a storage control chip, and a flash memory device. Background Technology

[0002] Flash memory devices, such as solid-state drives (SSDs), are storage devices that use semiconductor flash memory (NAND flash) as their medium. Flash memory devices include a host data path, which enables data exchange between the host and the flash memory.

[0003] Currently, by adding cache memory inside the flash memory device, cache resources are allocated to the host data path to improve the speed at which the host data path processes data.

[0004] In developing this application, the inventors discovered at least the following problems in the prior art: After the flash memory device initiates garbage collection, the garbage collection process requires performing garbage collection write operations to provide the necessary storage space for host data writing. Host write operations are only performed after sufficient space has been released by garbage collection. Although the existence of cache speeds up the transmission of some data in the host data path, the space release limitations during garbage collection still constrain the overall performance of the host data path and cannot improve the overall performance of the flash memory device. Summary of the Invention

[0005] This application provides a command management method to adjust the command allocation of the host data path and the garbage collection data path in real time, thereby improving the overall data path utilization and enhancing the overall performance of the flash memory device.

[0006] The embodiments of this application provide the following technical solutions:

[0007] In a first aspect, embodiments of this application provide a command management method applied to a flash memory device, the flash memory device including a host data path and a garbage collection data path, the command management method comprising:

[0008] After the flash memory device initiates garbage collection, the first command execution time and the second command execution time within each time slice are determined. The first command execution time is the time for executing several host data processing commands on the host data path, and the second command execution time is the time for executing several garbage collection commands on the garbage collection data path.

[0009] While the flash memory device is not in a stable state, the number of host data processing commands and garbage collection commands to be issued and executed in the next time slice is adjusted according to the relationship between the execution time of the first command and the execution time of the second command, until the flash memory device enters a stable state.

[0010] In some embodiments, a flash memory device includes a cache, memory, and flash memory;

[0011] Host data paths include data paths between the host and cache or between the host and memory; garbage collection data paths include data paths between flash memory and cache or between flash memory and memory.

[0012] Alternatively, the host data path includes the data path between the host and the cache or the data path between the cache and memory, and the garbage collection data path includes the data path between flash memory and the cache or the data path between the cache and memory.

[0013] In some embodiments, host data processing commands include host data write commands, and garbage collection commands include garbage collection write commands or garbage collection read commands.

[0014] The host data path includes the host write path, and the garbage collection data path includes the garbage collection write path or the garbage collection read path. The host write path is used to execute host data write commands, the garbage collection write path is used to execute garbage collection write commands, and the garbage collection read path is used to execute garbage collection read commands.

[0015] In some embodiments, the flash memory device includes a front-end module, and the method further includes, before determining the first command execution time and the second command execution time within each time slice:

[0016] Calculate the write amplification factor and use it as the ratio of the number of garbage collection write commands and host data write commands issued in each time slice;

[0017] Based on the quantity ratio and the preset unit quantity, determine the first quantity of host data write commands and the second quantity of garbage collection write commands issued in each time slice;

[0018] At each time slice, a first number of host data write commands and a second number of garbage collection write commands are sent to the front-end module.

[0019] In some embodiments, the host write path, the garbage collection write path, and the garbage collection read path each correspond to a command submission queue and a command completion queue;

[0020] Determine the execution time of the first command and the execution time of the second command within each time slice, including:

[0021] Record the start timestamp of each host data write command, garbage collection write command, or garbage collection read command when it is submitted to the corresponding command submission queue;

[0022] Within the first time slice, several host data write commands, garbage collection write commands, and garbage collection read commands are executed;

[0023] Record the end timestamp of each host data write command, garbage collection write command, or garbage collection read command when it is submitted to the corresponding command completion queue after execution;

[0024] Based on the end timestamp and the start timestamp, calculate the execution time of each host data write command, garbage collection write command, or garbage collection read command;

[0025] The execution times of each host data write command executed within the first time slice are added together, and the result is used as the execution time of the first command.

[0026] The execution times of each garbage collection write command and garbage collection read command executed within the first time slice are added together, and the result is used as the execution time of the second command.

[0027] In some embodiments, the flash memory device includes a cache, memory, and flash memory; host data write commands include host cache write commands or host memory write commands; garbage collection write commands include garbage collection cache write commands or garbage collection memory write commands; and garbage collection read commands include garbage collection cache read commands or garbage collection memory read commands.

[0028] In some embodiments, adjusting the number of host data processing commands and garbage collection commands to be issued and executed in the next time slice based on the relationship between the execution time of the first command and the execution time of the second command includes:

[0029] After the first time slice has completed issuing several host data write commands, garbage collection write commands, and garbage collection read commands, the second time slice will issue several host data write commands, garbage collection write commands, and garbage collection read commands.

[0030] Calculate the minimum command execution time within the first time slice, where the minimum command execution time is the minimum of the first command execution time and the second command execution time;

[0031] When the minimum command execution time is the same as the first command execution time, reduce the number of host cache write commands, garbage collection memory write commands, and garbage collection memory read commands issued in the third time slice, and increase the number of host memory write commands, garbage collection cache write commands, and garbage collection cache read commands issued in the third time slice;

[0032] When the minimum command execution time is the second command execution time, increase the number of host cache write commands, garbage collection memory write commands, and garbage collection memory read commands issued in the third time slice, and decrease the number of host memory write commands, garbage collection cache write commands, and garbage collection cache read commands issued in the third time slice;

[0033] The first number is the sum of the number of host cache write commands and the number of host memory write commands, and the second number is the sum of the number of garbage collection memory write commands and the number of garbage collection cache write commands.

[0034] In some embodiments, adjusting the number of host data processing commands and garbage collection commands to be issued and executed in the next time slice based on the relationship between the execution time of the first command and the execution time of the second command further includes:

[0035] Within the third time slice, several host data write commands, garbage collection write commands, and garbage collection read commands are executed, and the third time slice is used as the first time slice of the new round. The execution time of the first command and the execution time of the second command in the first time slice of the new round are determined.

[0036] After the execution of several host data write commands, garbage collection write commands, and garbage collection read commands in the third time slice is completed, a new round of several host cache write commands, host memory write commands, garbage collection cache read commands, garbage collection memory read commands, garbage collection memory write commands, and garbage collection cache write commands in the second time slice is issued according to the number of host cache write commands, host memory write commands, garbage collection cache read commands, garbage collection memory read commands, garbage collection memory write commands, and garbage collection cache write commands executed in the third time slice.

[0037] Based on the relationship between the execution time of the first command and the execution time of the second command in the first time slice of the new round, adjust the number of host cache write commands, host memory write commands, garbage collection cache read commands, garbage collection memory read commands, garbage collection memory write commands, and garbage collection cache write commands issued and executed in the third time slice of the new round until the flash memory device enters a stable state.

[0038] In some embodiments, the method further includes:

[0039] The flash memory device is determined to have entered a stable state when the difference between the minimum command execution times of two consecutive rounds is less than a preset time threshold, or when the number of host cache write commands, host memory write commands, garbage collection cache write commands, garbage collection memory write commands, garbage collection cache read commands, or garbage collection memory read commands is zero in any time slice of any round. The time slice includes a first time slice, a second time slice, or a third time slice.

[0040] In some embodiments, the host data processing command further includes a host data read command, and the host data path further includes a host read path. The host read path is used to execute the host data read command, and the host read path corresponds to a command submission queue.

[0041] The method also includes:

[0042] Set different priorities for host data read commands, host data write commands, garbage collection write commands, and garbage collection read commands, and control the priority of host data read commands to be the highest.

[0043] After a host data read command is submitted to the corresponding command submission queue, the low-priority host data write command, garbage collection write command, and garbage collection read command are interrupted, and the host data read command is issued and executed.

[0044] Secondly, embodiments of this application provide a storage control chip, comprising:

[0045] At least one processor; and,

[0046] A memory that is communicatively connected to at least one processor; wherein,

[0047] The memory stores instructions that can be executed by at least one processor, such that the instructions are executed by at least one processor to enable the at least one processor to perform the command management method as described in the first aspect.

[0048] Thirdly, embodiments of this application provide a flash memory device, including:

[0049] Such as the storage control chip in the second aspect;

[0050] At least one flash memory is connected in communication with the storage controller chip.

[0051] Fourthly, embodiments of this application also provide a non-volatile computer-readable storage medium storing computer-executable instructions, which, when executed by a processor, cause the processor to execute the command management method as described in the first aspect.

[0052] Fifthly, embodiments of this application provide a computer program product, which includes instructions or programs that, when executed by a flash memory device, cause the flash memory device to execute the command management method described in the first aspect.

[0053] The beneficial effects of this application embodiment are as follows: Unlike the prior art, this application embodiment provides a command management method applied to a flash memory device, which includes a host data path and a garbage collection data path. The command management method includes: after the flash memory device initiates garbage collection, determining a first command execution time and a second command execution time within each time slice, wherein the first command execution time is the time for executing several host data processing commands on the host data path, and the second command execution time is the time for executing several garbage collection commands on the garbage collection data path; when the flash memory device has not entered a stable state, adjusting the number of host data processing commands and garbage collection commands issued and executed in the next time slice according to the relationship between the first command execution time and the second command execution time, until the flash memory device enters a stable state.

[0054] By determining the execution time of the first command for executing several host data processing commands on the host data path and the execution time of the second command for executing several garbage collection commands on the garbage collection data path within each time slice after the flash memory device initiates garbage collection, and adjusting the number of host data processing commands and garbage collection commands issued and executed in the next time slice based on the relationship between the first and second command execution times before the flash memory device enters a stable state, this application can adjust the command allocation of the host data path and garbage collection data path in real time, achieving optimal utilization of data path resources under different states, thereby improving the overall data path utilization rate and enhancing the overall performance of the flash memory device. Attached Figure Description

[0055] One or more embodiments are illustrated by way of example with reference numerals in the accompanying drawings. These illustrations do not constitute a limitation on the embodiments. Elements with the same reference numerals in the drawings are denoted as similar elements. Unless otherwise stated, the figures in the drawings are not to be limited by scale.

[0056] Figure 1 This is a schematic diagram of the structure of a flash memory device provided in an embodiment of this application;

[0057] Figure 2 This is a schematic diagram of another flash memory device provided in an embodiment of this application;

[0058] Figure 3 This is a flowchart illustrating a command management method provided in an embodiment of this application;

[0059] Figure 4 This is a detailed flowchart illustrating a command management method provided in an embodiment of this application;

[0060] Figure 5This is a schematic diagram of the structure of a storage control chip provided in an embodiment of this application;

[0061] Figure 6 This is a schematic diagram of the structure of another flash memory device provided in the embodiments of this application. Detailed Implementation

[0062] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the scope of this application. All other embodiments obtained by those skilled in the art based on the embodiments in this application without inventive effort are within the scope of protection of this application.

[0063] It should be noted that, unless there is a conflict, the various features in the embodiments of this application can be combined with each other, all of which are within the protection scope of this application. Furthermore, although functional modules are divided in the device schematic diagram and a logical order is shown in the flowchart, in some cases, the steps shown or described can be executed in a different order than the module division in the device or the order in the flowchart. Moreover, the terms "first," "second," and "third" used in this application do not limit the data or execution order, but only distinguish identical or similar items with essentially the same function and effect.

[0064] The technical solution of this application will be described in detail below with reference to the accompanying drawings:

[0065] Flash memory devices, such as solid-state drives (SSDs), are storage devices that use semiconductor flash memory (NAND flash) as their medium. Flash memory devices include a host data path, which enables data exchange between the host and the flash memory.

[0066] Currently, adding cache memory inside flash memory devices allocates cache resources to the host data path to improve the speed of data processing. However, since the cache is usually integrated inside the controller of the flash memory device, the storage space of the cache is usually not very large due to cost constraints, and the flash memory device still uses main memory to store part of the host data.

[0067] Please see Figure 1 , Figure 1 This is a schematic diagram of the structure of a flash memory device provided in an embodiment of this application;

[0068] like Figure 1As shown, the flash memory device 100 includes a cache 101, memory 102, and flash memory 103. There is no swap path between the cache 101 and memory 102. The flash memory device 100 uses both the cache 101 and memory 102 to store host data. The storage space of the cache 101 is smaller than that of the memory 102. The data storage speed of the cache 101 is faster than that of the memory 102. The cache 101 includes, but is not limited to, high-speed caches such as cache memory. The memory 102 includes, but is not limited to, dynamic random access memory such as double data rate synchronous dynamic random access memory (DDR SDRAM).

[0069] At this time, the host data sent by host 200 is first stored in cache 101 or memory 102, and then written to flash memory 103. After the flash memory device initiates garbage collection (GC), garbage collection read operations read data from flash memory 103 into cache 101 or memory 102, and garbage collection write operations rewrite data into new data blocks in flash memory 103. In this case, the host data path includes the data path between host 200 and cache 101 or the data path between host 200 and memory 102, and the garbage collection data path includes the data path between flash memory 103 and cache 101 or the data path between flash memory 103 and memory 102.

[0070] Please see Figure 2 , Figure 2 This is a schematic diagram of another flash memory device provided in an embodiment of this application;

[0071] like Figure 2 As shown, the flash memory device 100 includes a cache 101, memory 102, and flash memory 103. A swap path exists between the cache 101 and memory 102. The flash memory device 100 uses the cache 101 to store host data and simultaneously performs swapping functionality with the memory 102, thereby achieving unified access to both the cache 101 and memory 102. The storage space of the cache 101 is smaller than that of the memory 102, and the data storage speed of the cache 101 is faster than that of the memory 102. The cache 101 includes, but is not limited to, high-speed caches such as cache memory, and the memory 102 includes, but is not limited to, dynamic random access memory such as double data rate synchronous dynamic random access memory (DDR SDRAM).

[0072] At this time, the host data sent by host 200 is first stored in cache 101. When the data written to cache 101 exceeds a preset capacity threshold, flash memory device 100 swaps some of the old data in cache 101 to memory 102. When it is necessary to write data from memory 102 to flash memory 103, the path type is selected according to the data demand (i.e., writing data to flash memory 103 via cache 101 or memory 102). Usually, the data is first cached in cache 101, and then a flush operation is performed to write the data from cache 101 to flash memory 103. After the flash memory device initiates garbage collection, the garbage collection read operation first reads data from flash memory 103 into cache 101. When the data written to cache 101 exceeds a preset capacity threshold, the flash memory device 100 swaps a portion of the old data in cache 101 to memory 102. The garbage collection write operation then rewrites the data from cache 101 into a new data block in flash memory 103, or caches the data from memory 102 into cache 101, and then writes the data from cache 101 into a new data block in flash memory 103. The preset capacity threshold can be set by those skilled in the art based on the storage capacity of cache 101, and is not limited here.

[0073] In this case, the host data path includes the data path between the host 200 and the cache 101 or the data path between the cache 101 and the memory 102, and the garbage collection data path includes the data path between the flash memory 103 and the cache 101 or the data path between the cache 101 and the memory 102.

[0074] It can be seen that, Figure 1 and Figure 2 Both methods optimize the host data path by allocating cache resources to it. When garbage collection is initiated on the flash memory device, the garbage collection process requires garbage collection write operations to provide the necessary storage space for host data writing. Only after sufficient space has been freed up by garbage collection will host write operations be performed.

[0075] For example, when the ratio of garbage collection write operations to host write operations is 3:1, three garbage collection write operations must be performed before each host write operation. In this case, for... Figure 1 In the case shown where there is no exchange path between cache 101 and memory 102, if the execution ratio of garbage collection write operations to host write operations is strictly controlled at 3:1, host data will enter both cache and memory. However, even if host data enters the cache and improves storage speed to some extent, the space release limit during garbage collection still restricts the overall performance of the host data path and cannot improve the overall performance of the flash memory device.

[0076] for Figure 2In the case shown, there is an exchange path between cache 101 and memory 102. If the execution ratio of garbage collection write operations to host write operations is strictly controlled at 3:1, host data will enter both cache 101 and memory 102. However, even if host data enters cache 101 and storage speed is improved, the space release limit during garbage collection still restricts the overall performance of the host data path. The overall data path utilization is low, and the overall performance of the flash memory device cannot be improved.

[0077] Although host data enters the cache, seemingly accelerating all pathways, in practice, memory bandwidth is the bottleneck determining the overall data pathway. All data enters the cache and is then synchronously swapped into memory due to storage space constraints, also consuming memory bandwidth. Moreover, due to the mutual constraints between data, the data in the cache cannot be fully utilized, resulting in low utilization of the overall data pathway and failing to improve the overall performance of the flash memory device.

[0078] Based on this, this application provides a command management method. When the flash memory device has not entered a stable state, the method adjusts the number of host data processing commands and garbage collection commands issued and executed in the next time slice according to the relationship between the execution time of the first command of several host data processing commands executed on the host data path and the execution time of the second command of several garbage collection commands executed on the garbage collection data path within each time slice. This allows for real-time adjustment of the command allocation on the host data path and the garbage collection data path, improving the overall data path utilization and enhancing the overall performance of the flash memory device.

[0079] Please see Figure 3 , Figure 3 This is a flowchart illustrating a command management method provided in an embodiment of this application;

[0080] This command management method is applied to flash memory devices, specifically to at least one processor in the flash memory device.

[0081] In this embodiment, the flash memory device includes a host data path and a garbage collection data path. The host data path is used to realize data exchange between the host and the flash memory, while the garbage collection data path is used to realize data migration and recycling operations between different storage blocks within the flash memory.

[0082] In this embodiment, the flash memory device includes a cache, main memory, and flash memory. The cache has a smaller storage space than the main memory, and the cache stores data faster than the main memory. The cache includes, but is not limited to, high-speed caches such as cache memory. The main memory includes, but is not limited to, dynamic random access memory such as double data rate synchronous dynamic random access memory (DDR SDRAM). The specific connection method between the cache and the main memory is as follows: Figure 1 or Figure 2 As shown.

[0083] In some embodiments, when cache and memory employ, as Figure 1 The connection method shown refers to the situation where there is no exchange path between the cache and memory. The host data path includes the data path between the host and the cache or the data path between the host and memory. The garbage collection data path includes the data path between flash memory and the cache or the data path between flash memory and memory.

[0084] In some embodiments, when cache and memory employ, as Figure 2 The connection method shown, i.e., when there is an exchange path between the cache and memory, includes the data path between the host and the cache or the data path between the cache and memory, and the garbage collection data path includes the data path between the flash memory and the cache or the data path between the cache and memory.

[0085] like Figure 3 As shown, the command management method includes:

[0086] Step S301: After the flash memory device starts garbage collection, determine the first command execution time and the second command execution time within each time slice;

[0087] The first command execution time is the time for executing several host data processing commands on the host data path, and the second command execution time is the time for executing several garbage collection commands on the garbage collection data path. The host data processing command is the operation instruction inside the flash memory device that enables data interaction between the host and the flash memory, and the garbage collection command is the operation instruction inside the flash memory device used to manage and optimize the storage space of the flash memory.

[0088] Specifically, after the flash memory device initiates garbage collection, both a host data path and a garbage collection data path exist simultaneously within the flash memory device. Within each time slice, the execution time of the first command (containing several host data processing commands) on the host data path and the execution time of the second command (containing several garbage collection commands) on the garbage collection data path are determined. Each time slice has the same size, which can be set by those skilled in the art based on the execution time of the host data processing commands or garbage collection commands by the flash memory device; no restrictions are imposed here.

[0089] In this embodiment, the host data processing command includes a host data write command, and the garbage collection command includes a garbage collection write command or a garbage collection read command. The host data write command is an internal command initiated by the flash memory device, instructing the flash memory device to first store the host data sent by the host in a cache or memory, and then write the host data from the cache or memory to the flash memory. The garbage collection read command instructs the flash memory device to read valid data from older data blocks in the flash memory into the cache or memory during garbage collection. The garbage collection write command instructs the flash memory device to re-store the valid data stored in the cache or memory after executing the garbage collection read command into a new data block in the flash memory.

[0090] In this embodiment, the host data path includes a host write path, and the garbage collection data path includes a garbage collection write path or a garbage collection read path. The host write path is used to execute host data write commands, the garbage collection write path is used to execute garbage collection write commands, and the garbage collection read path is used to execute garbage collection read commands.

[0091] In some embodiments, when cache and memory employ, as Figure 1 The connection method shown, i.e. there is no exchange path between the cache and memory, the host write path includes the data path between the host and the cache or the data path between the host and memory, the garbage collection write path includes the data path between the flash memory and the cache or the data path between the flash memory and memory, and the garbage collection read path includes the data path between the flash memory and the cache or the data path between the flash memory and memory.

[0092] In some embodiments, when cache and memory employ, as Figure 2 The connection method shown, i.e., when there is an exchange path between the cache and memory, includes the host write path, which includes the data path between the host and the cache or the data path between the cache and memory; the garbage collection write path includes the data path between the flash memory and the cache or the data path between the cache and memory; and the garbage collection read path includes the data path between the flash memory and the cache or the data path between the cache and memory.

[0093] In this embodiment, the flash memory device includes a front-end module and a flash translation layer (FTL). The flash translation layer is used to issue host data write commands, garbage collection write commands, and garbage collection read commands to the front-end module. The front-end module is used to receive and execute the host data write commands, garbage collection write commands, and garbage collection read commands. Before determining the first command execution time and the second command execution time within each time slice, the command management method further includes: determining the first number of host data write commands and the second number of garbage collection write commands issued in each time slice based on the write amplification factor, specifically including steps S1-S3:

[0094] Step S1: Calculate the write amplification factor and use it as the ratio of the number of garbage collection write commands and host data write commands issued in each time slice;

[0095] The write amplification factor is the ratio of the amount of data written to the flash memory to the amount of data written by the host to the flash memory device. For example, when the write amplification factor is 3:1, the ratio of garbage collection write commands to host data write commands issued in each time slice is 3:1.

[0096] Step S2: Based on the quantity ratio and the preset unit quantity, determine the first quantity of host data write commands and the second quantity of garbage collection write commands issued in each time slice;

[0097] The preset unit quantity is a baseline value for the number of write commands issued in each time slice, used to calculate the first and second quantities issued in each time slice based on the quantity ratio. The first quantity is the number of host data write commands issued in one time slice, and the second quantity is the number of garbage collection write commands issued in one time slice. The size of the preset unit quantity can be set by those skilled in the art based on the size of the cache or memory, and is not limited here.

[0098] Specifically, when the ratio of garbage collection write commands to host data write commands issued in each time slice is a:b, the first number of host data write commands issued in each time slice is determined to be b * preset unit number, and the second number of garbage collection write commands issued in each time slice is determined to be a * preset unit number.

[0099] For example, if the ratio of garbage collection write commands to host data write commands issued in each time slice is 3:1, and the preset unit quantity is 100, then the first quantity of host data write commands issued in each time slice is 100*1=100, and the second quantity of garbage collection write commands issued in each time slice is 100*3=300.

[0100] Step S3: In each time slice, send the first number of host data write commands and the second number of garbage collection write commands to the front-end module.

[0101] Specifically, the flash memory conversion layer sends a first number of host data write commands and a second number of garbage collection write commands to the front-end module in each time slice.

[0102] In this embodiment, the host write path, the garbage collection write path, and the garbage collection read path each correspond to a command submission queue and a command completion queue. The command submission queue is used to store commands to be executed, and the command completion queue is used to store and record commands that have been executed.

[0103] In this embodiment, the time slice includes a first time slice. Within the first time slice, the flash memory device executes several host data write commands and garbage collection commands, and calculates the execution time of the first command executing these host data write commands and the execution time of the second command executing these garbage collection commands. Step S301 specifically includes steps S311-S316:

[0104] Step S311: Record the start timestamp of each host data write command, garbage collection write command, or garbage collection read command when it is submitted to the corresponding command submission queue;

[0105] The start timestamp is used to record the time when each host data write command, garbage collection write command, or garbage collection read command is submitted to the corresponding command submission queue.

[0106] In this embodiment, the host data write command includes a host cache write command or a host memory write command; the garbage collection write command includes a garbage collection cache write command or a garbage collection memory write command; and the garbage collection read command includes a garbage collection cache read command or a garbage collection memory read command. The host cache write command and the garbage collection cache write command are used to store the corresponding data in the cache; the host memory write command and the garbage collection memory write command are used to store the corresponding data in memory; the garbage collection cache read command is used to read data from the flash memory into the cache; and the garbage collection memory read command is used to read data from the flash memory into memory.

[0107] In some embodiments, each host data write command, garbage collection write command, and garbage collection read command corresponds to a command type identifier to distinguish the command type of each host data write command, garbage collection write command, and garbage collection read command. The command type of the host data write command is either a host cache write command or a host memory write command, the command type of the garbage collection write command is either a garbage collection cache write command or a garbage collection memory write command, and the command type of the garbage collection read command is either a garbage collection cache read command or a garbage collection memory read command.

[0108] Step S312: Within the first time slice, execute several host data write commands, garbage collection write commands, and garbage collection read commands;

[0109] Specifically, within the first time slice, the following commands are executed: host cache write command, host memory write command, garbage collection cache write command, garbage collection memory write command, garbage collection cache read command, and garbage collection memory read command.

[0110] In this embodiment, during the first execution of step S312, host cache write commands, host memory write commands, garbage collection cache write commands, garbage collection memory write commands, garbage collection cache read commands, and garbage collection memory read commands are issued according to the initial issuance quantity. Subsequently, each time step S312 is executed, these commands are issued and executed according to the adjusted quantity of host cache write commands, host memory write commands, garbage collection cache write commands, garbage collection memory write commands, garbage collection cache read commands, and garbage collection memory read commands in step S302, until the flash memory device reaches a stable state. The initial issuance quantity can be set by those skilled in the art based on the size of the cache or memory, and is not limited here.

[0111] It is understandable that the number of host data write commands and the number of garbage collection commands executed in each time slice remain unchanged. What changes are the number of host cache write commands, the number of host memory write commands, the number of garbage collection cache write commands, the number of garbage collection memory write commands, the number of garbage collection cache read commands, or the number of garbage collection memory read commands.

[0112] Step S313: Record the end timestamp when each host data write command, garbage collection write command, or garbage collection read command is submitted to the corresponding command completion queue after execution;

[0113] The end timestamp is used to record the time when a completed host data write command, garbage collection write command, or garbage collection read command is submitted to the corresponding command completion queue.

[0114] Step S314: Based on the end timestamp and the start timestamp, calculate the execution time of each host data write command, garbage collection write command, or garbage collection read command;

[0115] Specifically, the execution time of each host data write command, garbage collection write command, or garbage collection read command is the difference between the end timestamp and the start timestamp.

[0116] Step S315: Add up the execution times of each host data write command executed within the first time slice, and use the result as the execution time of the first command;

[0117] Specifically, the execution time of the first command is the sum of the execution time of each host cache write command executed within the first time slice and the execution time of each host memory write command.

[0118] Step S316: Add the execution time of each garbage collection write command and garbage collection read command executed within the first time slice, and use the result as the execution time of the second command.

[0119] Specifically, the execution time of the second command is the sum of the execution time of each garbage collection cache write command, each garbage collection memory write command, each garbage collection cache read command, and each garbage collection memory read command executed within the first time slice.

[0120] In this embodiment, the second command execution time is the sum of the execution time of the garbage collection write command and the execution time of the garbage collection read command. Combined with step S302, which adjusts the number of host data write commands of each type and the number of garbage collection commands of each type based on the second command execution time, this application only needs to issue a first number of host data write commands and a second number of garbage collection write commands in each time slice, without needing to specifically determine the number of garbage collection read commands issued in each time slice.

[0121] Step S302: When the flash memory device has not entered a stable state, adjust the number of host data processing commands and garbage collection commands to be issued and executed in the next time slice according to the relationship between the execution time of the first command and the execution time of the second command, until the flash memory device enters a stable state.

[0122] The stable state includes the state where, over several consecutive time slices, the change in the number of each type of host data write commands executed on the host data path is less than a preset threshold, or the change in the number of each type of garbage collection commands executed on the garbage collection data path is less than a preset threshold. The preset threshold can be set by those skilled in the art based on the size of the cache or memory, and is not limited here.

[0123] Specifically, the process determines whether the flash memory device has entered a stable state. If the flash memory device has entered a stable state, the process ends. If the flash memory device has not entered a stable state, the number of host cache write commands, host memory write commands, garbage collection cache write commands, garbage collection memory write commands, garbage collection cache read commands, and garbage collection memory read commands issued and executed in the next time slice are adjusted according to the relationship between the execution time of the first command and the execution time of the second command, until the flash memory device enters a stable state.

[0124] In this embodiment, the time slice further includes a second time slice or a third time slice. The flash memory device executes several host data write commands and garbage collection commands within the second time slice. The difference from the first time slice is that the flash memory device does not need to calculate the execution time of the first command and the execution time of the second command within the second time slice. Instead, the flash memory device determines the number of each type of host data write command and the number of each type of garbage collection command to be issued and executed in the third time slice based on the relationship between the execution times of the first and second commands in the first time slice. Within the third time slice, the flash memory device executes several host data write commands and garbage collection commands based on the adjusted number of each type of host data write command and the number of each type of garbage collection command. Step S302 specifically includes steps S321-S324:

[0125] Step S321: After the first time slice has completed issuing several host data write commands, garbage collection write commands, and garbage collection read commands, issue several host data write commands, garbage collection write commands, and garbage collection read commands to be executed in the second time slice.

[0126] Specifically, after the first time slice has completed issuing several host cache write commands, host memory write commands, garbage collection cache write commands, garbage collection memory write commands, garbage collection cache read commands, and garbage collection memory read commands, several host data write commands, garbage collection write commands, and garbage collection read commands to be executed in the second time slice are issued.

[0127] In this embodiment of the application, when step S321 is executed for the first time, host cache write commands, host memory write commands, garbage collection cache write commands, garbage collection memory write commands, garbage collection cache read commands, and garbage collection memory read commands are issued according to the initial issuance quantity. Subsequently, each time step S321 is executed, similar to step S312, these commands are also issued and executed according to the adjusted quantity of host cache write commands, host memory write commands, garbage collection cache write commands, garbage collection memory write commands, garbage collection cache read commands, and garbage collection memory read commands in step S302, until the flash memory device enters a stable state.

[0128] Step S322: Calculate the minimum command execution time within the first time slice;

[0129] The minimum command execution time is the minimum of the first command execution time and the second command execution time.

[0130] Step S323: When the minimum command execution time is the first command execution time, reduce the number of host cache write commands, garbage collection memory write commands, and garbage collection memory read commands issued in the third time slice, and increase the number of host memory write commands, garbage collection cache write commands, and garbage collection cache read commands issued in the third time slice;

[0131] The first quantity is the sum of the number of host cache write commands and the number of host memory write commands, and the second quantity is the sum of the number of garbage collection memory write commands and the number of garbage collection cache write commands. Within the third time slice, reducing the number of host cache write commands, garbage collection memory write commands, and garbage collection memory read commands, and increasing the number of host memory write commands, garbage collection cache write commands, and garbage collection cache read commands can be set by those skilled in the art based on the execution times of the first and second commands, and is not limited here.

[0132] Specifically, when the minimum command execution time is the same as the first command execution time, the execution speed of host data write commands is faster than that of garbage collection commands. Since the ratio of garbage collection write commands to host data write commands issued in each time slice remains unchanged, by reducing the number of host cache write commands, garbage collection memory write commands, and garbage collection memory read commands issued in the third time slice, and increasing the number of host memory write commands, garbage collection cache write commands, and garbage collection cache read commands issued in the third time slice, the execution speed of garbage collection commands is improved, thereby improving the utilization rate of the entire data path.

[0133] Step S324: When the minimum command execution time is the second command execution time, increase the number of host cache write commands, garbage collection memory write commands, and garbage collection memory read commands issued in the third time slice, and decrease the number of host memory write commands, garbage collection cache write commands, and garbage collection cache read commands issued in the third time slice.

[0134] The first quantity is the sum of the number of host cache write commands and the number of host memory write commands, and the second quantity is the sum of the number of garbage collection memory write commands and the number of garbage collection cache write commands. The number of host cache write commands, garbage collection memory write commands, and garbage collection memory read commands issued during the third time slice can be increased, and the number of host memory write commands, garbage collection cache write commands, and garbage collection cache read commands issued can be decreased. This can be set by those skilled in the art based on the execution times of the first and second commands, and is not limited here.

[0135] Specifically, when the minimum command execution time is the second command execution time, the execution speed of host data write commands is lower than that of garbage collection commands. Since the ratio of garbage collection write commands to host data write commands issued in each time slice remains unchanged, by increasing the number of host cache write commands, garbage collection memory write commands, and garbage collection memory read commands issued in the third time slice, and decreasing the number of host memory write commands, garbage collection cache write commands, and garbage collection cache read commands issued in the third time slice, the execution speed of host data write commands is improved, thereby improving the utilization rate of the entire data path.

[0136] In this embodiment of the application, step S302 further includes steps S325-S327:

[0137] Step S325: Within the third time slice, execute several host data write commands, garbage collection write commands, and garbage collection read commands, and use the third time slice as the first time slice of the new round, and determine the first command execution time and the second command execution time of the first time slice of the new round;

[0138] Specifically, the third time slice is used as the first time slice of the new round, and step S301 is executed again.

[0139] Step S326: After the execution of several host data write commands, garbage collection write commands, and garbage collection read commands in the third time slice is completed, according to the number of host cache write commands, host memory write commands, garbage collection cache read commands, garbage collection memory write commands, and garbage collection cache write commands issued in the third time slice, a new round of several host cache write commands, host memory write commands, garbage collection cache read commands, garbage collection memory read commands, garbage collection memory write commands, and garbage collection cache write commands executed in the second time slice is issued.

[0140] Specifically, after setting the third time slice as the first time slice of the new round in step S325, step S321 is executed again.

[0141] Step S327: Based on the relationship between the execution time of the first command and the execution time of the second command in the new round of the first time slice, adjust the number of host cache write commands, host memory write commands, garbage collection cache read commands, garbage collection memory read commands, garbage collection memory write commands, and garbage collection cache write commands issued and executed in the new round of the third time slice until the flash memory device enters a stable state.

[0142] Specifically, after setting the third time slice as the first time slice in step S325, steps S322-S324 are re-executed to adjust the number of host cache write commands, host memory write commands, garbage collection cache read commands, garbage collection memory read commands, garbage collection memory write commands, and garbage collection cache write commands issued and executed in the new third time slice. Steps S301-S302 are repeated until, after completing step S301 in any iteration, it is determined whether the flash memory device has entered a stable state. If so, the process ends.

[0143] In this embodiment, the step of determining whether the flash memory device has entered a stable state includes: determining whether the difference between the minimum command execution times of two consecutive rounds is less than a preset time threshold, or whether the number of host cache write commands, host memory write commands, garbage collection cache write commands, garbage collection memory write commands, garbage collection cache read commands, or garbage collection memory read commands within any time slice of any round is zero. The time slice includes a first time slice, a second time slice, or a third time slice.

[0144] Specifically, the minimum command execution time for each round is recorded using an array. When the difference between the minimum command execution times of any two consecutive rounds within a preset number of rounds is less than a preset time threshold, indicating that the fluctuations in the minimum command execution times across multiple rounds are within a small range, the flash memory device is determined to have entered a stable state. Alternatively, when the number of any one of the following commands—host cache write commands, host memory write commands, garbage collection cache write commands, garbage collection memory write commands, garbage collection cache read commands, or garbage collection memory read commands—decreases to zero within any time slice of any round, indicating that there is no room for adjustment in the command count, the flash memory device is determined to have entered a stable state. Here, the preset number of rounds is the minimum number of rounds required to execute steps S301 and S302 when the flash memory device enters a stable state, and the preset time threshold is the maximum value of the difference between the minimum command execution times of two consecutive rounds when the flash memory device enters a stable state. The preset number of rounds and the preset time threshold can be set by those skilled in the art based on the first command execution time and the second command execution time, and are not limited here.

[0145] The flash memory device is determined to have entered a stable state when the difference between the minimum command execution times of two consecutive rounds is less than a preset time threshold, or when the number of host cache write commands, host memory write commands, garbage collection cache write commands, garbage collection memory write commands, garbage collection cache read commands, or garbage collection memory read commands is zero in any time slice of any round.

[0146] For example, if all host data write commands issued in any time slice of any round are host memory write commands, that is, the number of host cache write commands is zero, this is the slowest execution of host data write commands, there is no room for adjustment, which means that the flash memory device has entered a stable state.

[0147] If the difference between the minimum command execution times of two consecutive rounds is greater than or equal to a preset time threshold, and the number of each type of command (host cache write command, host memory write command, garbage collection cache write command, garbage collection memory write command, garbage collection cache read command, and garbage collection memory read command) is not zero in any time slice of each round, then the flash memory device is determined to have not entered a stable state.

[0148] Please see Figure 4 , Figure 4 This is a detailed flowchart illustrating a command management method provided in an embodiment of this application;

[0149] like Figure 4 As shown, the detailed process of this command management method includes:

[0150] Step S401: Determine whether the flash memory device has started garbage collection;

[0151] Specifically, if the flash memory device starts garbage collection, proceed to step S402; if the flash memory device does not start garbage collection, end the process.

[0152] Step S402: Based on the write amplification factor, determine the first number of host data write commands and the second number of garbage collection write commands issued in each time slice;

[0153] Specifically, the write amplification factor is calculated and used as the ratio of the number of garbage collection write commands and host data write commands issued in each time slice. When the ratio of the number of garbage collection write commands and host data write commands issued in each time slice is a:b, the first number of host data write commands issued in each time slice is determined to be b * preset unit number, and the second number of garbage collection write commands issued in each time slice is determined to be a * preset unit number.

[0154] Step S403: Initialize the three time-slice data command management bodies;

[0155] Specifically, the three time-slice data command management entities include a first time-slice data command management entity, a second time-slice data command management entity, and a third time-slice data command management entity. The first time-slice data command management entity is used to schedule the execution of several host data write commands and garbage collection commands within the first time slice, and to calculate the execution time of the first command for executing these host data write commands and the execution time of the second command for executing these garbage collection commands.

[0156] The second time-slice data command management unit is used to schedule and execute several host data write commands and garbage collection commands within the second time slice. It also determines the number of each type of host data write command and the number of each type of garbage collection command to be issued and executed in the third time slice based on the relationship between the execution times of the first and second commands in the first time slice. The third time-slice data command management unit is used to schedule and execute several host data write commands and garbage collection commands within the third time slice based on the adjusted number of each type of host data write command and the number of each type of garbage collection command.

[0157] Step S404: Determine the execution time of the first command and the execution time of the second command within the current time slice;

[0158] Specifically, within the first time slice, several host cache write commands, host memory write commands, garbage collection cache write commands, garbage collection memory write commands, garbage collection cache read commands, and garbage collection memory read commands are executed, and the execution time of the first command and the execution time of the second command within the first time slice are determined.

[0159] Alternatively, after completing step S410 or S411, the third time slice is used as the first time slice of a new round. Based on the number of host cache write commands, host memory write commands, garbage collection cache write commands, garbage collection memory write commands, garbage collection cache read commands, and garbage collection memory read commands adjusted in step S410 or S411, these commands are issued and executed, and the execution times of the first and second commands within the new round's first time slice are determined. The specific implementation of this step is similar to that of step S301 and will not be repeated here.

[0160] Step S405: Determine whether the flash memory device has entered a stable state;

[0161] Specifically, it is determined whether the difference between the minimum command execution times of two consecutive rounds is less than a preset time threshold, or whether the number of host cache write commands, host memory write commands, garbage collection cache write commands, garbage collection memory write commands, garbage collection cache read commands, or garbage collection memory read commands within any time slice of any round is zero. Here, a time slice includes a first time slice, a second time slice, or a third time slice.

[0162] If the difference between the minimum command execution times of two consecutive rounds is less than the preset time threshold, or if the number of host cache write commands, host memory write commands, garbage collection cache write commands, garbage collection memory write commands, garbage collection cache read commands, or garbage collection memory read commands is zero in any time slice of any round, then the flash memory device is determined to have entered a stable state and the process ends.

[0163] If the difference between the minimum command execution times of two consecutive rounds is greater than or equal to the preset time threshold, and the number of each type of command in any time slice of each round, including host cache write command, host memory write command, garbage collection cache write command, garbage collection memory write command, garbage collection cache read command, and garbage collection memory read command, is not zero, then it is determined that the flash memory device has not entered a stable state, and proceed to step S406.

[0164] Step S406: Determine whether the several host data write commands, garbage collection write commands and garbage collection read commands executed within the chip in the first time have been issued;

[0165] Specifically, if the host data write command, garbage collection write command and garbage collection read command executed within the first time slice have been issued, then proceed to step S407; if the host data write command, garbage collection write command and garbage collection read command executed within the first time slice have not been issued, then return to step S404.

[0166] Step S407: Issue several host data write commands, garbage collection write commands, and garbage collection read commands to be executed within the second time slice;

[0167] Specifically, during the first execution of step S407, several host data write commands, garbage collection write commands, and garbage collection read commands are issued according to the initial issuance quantity for execution within the second time slice. Subsequently, during each execution of step S407, these commands are issued and executed according to the adjusted quantities of host cache write commands, host memory write commands, garbage collection cache write commands, garbage collection memory write commands, garbage collection cache read commands, and garbage collection memory read commands from step S410 or S411.

[0168] Step S408: Calculate the minimum command execution time within the first time slice;

[0169] The minimum command execution time is the minimum of the first command execution time and the second command execution time.

[0170] Step S409: Determine whether the execution time of the minimum command is the execution time of the first command;

[0171] Specifically, if the minimum command execution time is the same as the first command execution time, proceed to step S410; if the minimum command execution time is not the same as the first command execution time, i.e., the minimum command execution time is the same as the second command execution time, proceed to step S411.

[0172] Step S410: Reduce the number of host cache write commands, garbage collection memory write commands, and garbage collection memory read commands issued within the third time slice, and increase the number of host memory write commands, garbage collection cache write commands, and garbage collection cache read commands issued within the third time slice;

[0173] Specifically, the implementation method of this step is the same as that of step S323, and will not be repeated here.

[0174] Step S411: Increase the number of host cache write commands, garbage collection memory write commands, and garbage collection memory read commands issued within the third time slice, and decrease the number of host memory write commands, garbage collection cache write commands, and garbage collection cache read commands issued within the third time slice.

[0175] Specifically, the implementation method of this step is the same as that of step S324, and will not be repeated here.

[0176] Further, after completing step S411, return to step S404, take the third time slice as the first time slice of the new round, and repeat steps S404-S411 until it is determined that the flash memory device has entered a stable state in step S405 of any round, and end the process.

[0177] In this embodiment, by executing several host data write commands and garbage collection commands within a first time slice, and calculating the execution time of the first command for executing these host data write commands and the execution time of the second command for executing these garbage collection commands, the number of each type of host data write command and the number of each type of garbage collection command to be issued and executed in the third time slice are determined based on the relationship between the execution time of the first command and the execution time of the second command in the first time slice within the second time slice. Within the third time slice, host data write commands and garbage collection commands are executed based on the adjusted number of each type of host data write command and the number of each type of garbage collection command. This application can improve the smoothness and controllability of the command quantity adjustment of the host data path and the garbage collection data path, reduce data fluctuations, and improve the stability of the flash memory device.

[0178] In this embodiment, when the flash memory device has not entered a stable state, the number of host cache write commands, host memory write commands, garbage collection cache write commands, garbage collection memory write commands, garbage collection cache read commands, and garbage collection memory read commands issued and executed in the third time slice are adjusted according to the relationship between the execution time of the first command and the execution time of the second command in the first time slice until the flash memory device enters a stable state. This application can ignore the underlying implementation and obtain the optimal command quantity scheduling method only based on the feedback from the upper layer, and is applicable to various types of caches.

[0179] In some embodiments, the host data processing commands further include host data read commands, which are commands initiated internally by the flash memory device to instruct the flash memory device to read data from the flash memory into a cache or memory, and then send the data from the cache or memory to the host. Host data read commands include host cache read commands and host memory read commands. The host cache read command instructs the flash memory device to read data from the flash memory into a cache, and the host memory read command instructs the flash memory device to read data from the flash memory into memory. The host data path also includes a host read path, which is used to execute the host data read commands.

[0180] In some embodiments, when cache and memory employ, as Figure 1 The connection method shown illustrates a scenario where there is no data exchange path between the cache and memory. In this case, the host read path includes either a data path between the host and the cache or a data path between the host and memory. The data types in the cache include: data corresponding to host cache write commands, data corresponding to host cache read commands, data corresponding to garbage collection cache write commands, and data corresponding to garbage collection cache read commands. The data types in memory include: data corresponding to host memory write commands, data corresponding to host memory read commands, data corresponding to garbage collection memory write commands, and data corresponding to garbage collection memory read commands.

[0181] In some embodiments, when cache and memory employ, as Figure 2 The connection method shown, where there is an exchange path between the cache and memory, includes either a data path between the host and the cache or a data path between the cache and memory. In this case, because there is an exchange path between the cache and memory, by configuring data priorities, the data types in the cache can still include: data corresponding to host cache write commands, data corresponding to host cache read commands, data corresponding to garbage collection cache write commands, and data corresponding to garbage collection cache read commands. The data types in memory can also include: data corresponding to host memory write commands, data corresponding to host memory read commands, data corresponding to garbage collection memory write commands, and data corresponding to garbage collection memory read commands.

[0182] In some embodiments, the host read path corresponds to a command submission queue. The command management method further includes: setting different priorities for host data read commands, host data write commands, garbage collection write commands, and garbage collection read commands, and controlling the priority of host data read commands to be the highest priority; after a host data read command is submitted to the corresponding command submission queue, interrupting the processing of low-priority host data write commands, garbage collection write commands, and garbage collection read commands, and issuing and executing host data read commands.

[0183] Specifically, for data types in the cache and data types in memory, different data types determine the data priority and processing method. By controlling the priority of host data read commands to the highest priority, host cache read commands or host memory read commands are issued and executed first. The command allocation of the host write path and garbage collection data path will not affect the host data read commands. Moreover, due to the fast reading speed, the execution of host data read commands will not occupy a large amount of cache or memory. Steps S301 and S302 are only executed for host data write commands and garbage collection commands to adjust the number of host cache write commands, host memory write commands, garbage collection cache write commands, garbage collection memory write commands, garbage collection cache read commands, and garbage collection memory read commands issued and executed. This adjusts the cache usage of the data corresponding to the host cache write commands, the data corresponding to the garbage collection cache write commands, and the data corresponding to the garbage collection cache read commands, as well as the memory usage of the data corresponding to the host memory write commands, the data corresponding to the garbage collection memory write commands, and the data corresponding to the garbage collection memory read commands. This achieves optimal utilization of data path resources under different states, improves the overall data path utilization rate, and enhances the overall performance of the flash memory device.

[0184] In this embodiment, a command management method is provided, which is applied to a flash memory device. The flash memory device includes a host data path and a garbage collection data path. The command management method includes: after the flash memory device starts garbage collection, determining a first command execution time and a second command execution time within each time slice, wherein the first command execution time is the time for executing a number of host data processing commands on the host data path, and the second command execution time is the time for executing a number of garbage collection commands on the garbage collection data path; when the flash memory device has not entered a stable state, adjusting the number of host data processing commands and garbage collection commands issued and executed in the next time slice according to the relationship between the first command execution time and the second command execution time, until the flash memory device enters a stable state.

[0185] By determining the execution time of the first command for executing several host data processing commands on the host data path and the execution time of the second command for executing several garbage collection commands on the garbage collection data path within each time slice after the flash memory device initiates garbage collection, and adjusting the number of host data processing commands and garbage collection commands issued and executed in the next time slice based on the relationship between the first and second command execution times before the flash memory device enters a stable state, this application can adjust the command allocation of the host data path and garbage collection data path in real time, achieving optimal utilization of data path resources under different states, thereby improving the overall data path utilization rate and enhancing the overall performance of the flash memory device.

[0186] Please see Figure 5 , Figure 5 This is a schematic diagram of the structure of a storage control chip provided in an embodiment of this application;

[0187] like Figure 5 As shown, the storage control chip 104 includes one or more processors 141 and a memory 142. Wherein, Figure 5 Take a processor 141 as an example.

[0188] Processor 141 and memory 142 can be connected via a bus or other means. Figure 5 Taking the example of a connection between China and Israel via a bus.

[0189] Processor 141 is configured to provide computing and control capabilities to control flash memory device 100 to perform corresponding tasks, such as controlling flash memory device 100 to execute the command management method in any of the above method embodiments. The command management method is applied to the flash memory device, which includes a host data path and a garbage collection data path. The command management method includes: after the flash memory device starts garbage collection, determining a first command execution time and a second command execution time within each time slice, wherein the first command execution time is the time for executing a number of host data processing commands on the host data path, and the second command execution time is the time for executing a number of garbage collection commands on the garbage collection data path; when the flash memory device has not entered a stable state, adjusting the number of host data processing commands and garbage collection commands issued and executed in the next time slice according to the relationship between the first command execution time and the second command execution time, until the flash memory device enters a stable state.

[0190] By determining the execution time of the first command for executing several host data processing commands on the host data path and the execution time of the second command for executing several garbage collection commands on the garbage collection data path within each time slice after the flash memory device initiates garbage collection, and adjusting the number of host data processing commands and garbage collection commands issued and executed in the next time slice based on the relationship between the first and second command execution times before the flash memory device enters a stable state, this application can adjust the command allocation of the host data path and garbage collection data path in real time, achieving optimal utilization of data path resources under different states, thereby improving the overall data path utilization rate and enhancing the overall performance of the flash memory device.

[0191] Processor 141 can be a general-purpose processor, including a central processing unit (CPU), a network processor (NP), a hardware chip, or any combination thereof; it can also be a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a programmable logic device (PLD), or a combination thereof. The aforementioned PLD can be a complex programmable logic device (CPLD), a field-programmable gate array (FPGA), a generic array logic (GAL), or any combination thereof.

[0192] Memory 142, as a non-transitory computer-readable storage medium, can be used to store non-transitory software programs, non-transitory computer-executable programs, and modules, such as program instructions / modules corresponding to the command management method in the embodiments of this application. Processor 141 can implement the command management method in any of the above method embodiments by running the non-transitory software programs, instructions, and modules stored in memory 142. Specifically, memory 142 may include volatile memory (VM), such as random access memory (RAM); memory 142 may also include non-volatile memory (NVM), such as read-only memory (ROM), flash memory, hard disk drive (HDD), solid-state drive (SSD), or other non-transitory solid-state storage devices; memory 142 may also include combinations of the above types of memory.

[0193] Memory 142 may include high-speed random access memory, and may also include non-volatile memory, such as at least one disk storage device, flash memory device, or other non-volatile solid-state storage device. In some embodiments, memory 142 may optionally include memory remotely located relative to processor 141, and such remote memory may be connected to processor 141 via a network. Examples of such networks include, but are not limited to, the Internet, intranets, local area networks, mobile communication networks, and combinations thereof.

[0194] One or more modules are stored in memory 142. When executed by one or more processors 141, they execute the command management method in any of the above method embodiments, for example, executing the methods described above. Figure 3 The steps shown.

[0195] Please see Figure 6 , Figure 6 This is a schematic diagram of the structure of another flash memory device provided in the embodiments of this application;

[0196] like Figure 6 As shown, the flash memory device 100 includes a storage controller chip 104 and at least one flash memory 103. The flash memory 103 is communicatively connected to the storage controller chip 104. Figure 6 Take a flash memory 103 as an example.

[0197] The storage control chip 104 is used to execute the command management method in any of the above embodiments. The command management method is applied to a flash memory device, which includes a host data path and a garbage collection data path. The command management method includes: after the flash memory device starts garbage collection, determining a first command execution time and a second command execution time in each time slice, wherein the first command execution time is the time for executing a number of host data processing commands on the host data path, and the second command execution time is the time for executing a number of garbage collection commands on the garbage collection data path; when the flash memory device has not entered a stable state, adjusting the number of host data processing commands and garbage collection commands issued and executed in the next time slice according to the relationship between the first command execution time and the second command execution time, until the flash memory device enters a stable state.

[0198] Flash memory 103 communicates with storage control chip 104 and is used to store data.

[0199] In this application embodiment, the flash memory device includes a storage control chip, which is used to execute the command management method in any of the above embodiments. This application can adjust the command allocation of the host data path and the garbage collection data path in real time, realize the optimal utilization of data path resources under different states, thereby improving the overall data path utilization rate and enhancing the overall performance of the flash memory device.

[0200] This application also provides a non-volatile computer storage medium storing computer-executable instructions that are executed by one or more processors. For example, the one or more processors can execute the command management method in any of the above method embodiments, such as performing the steps described above.

[0201] The apparatus or device embodiments described above are merely illustrative. The unit modules described as separate components may or may not be physically separate, and the components shown as module units may or may not be physical units; that is, they may be located in one place or distributed across multiple network module units. Some or all of the modules can be selected to achieve the purpose of this embodiment according to actual needs.

[0202] Through the above description of the embodiments, those skilled in the art can clearly understand that each embodiment can be implemented using software plus a general-purpose hardware platform, or of course, using hardware. Based on this understanding, the above technical solutions, in essence or the parts that contribute to the related technology, can be embodied in the form of a software product. This computer software product can be stored in a computer-readable storage medium, such as ROM / RAM, magnetic disk, optical disk, etc., including several instructions for a computer device (which may be a personal computer, server, or network device, etc.) to execute the various embodiments or some parts of the embodiments.

[0203] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this application, and not to limit them; under the concept of this application, the technical features of the above embodiments or different embodiments can also be combined, the steps can be implemented in any order, and there are many other variations of different aspects of this application as described above. For the sake of brevity, they are not provided in detail; although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the foregoing embodiments, or make equivalent substitutions for some of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this application.

Claims

1. A command management method, characterized in that, Applied to a flash memory device, the flash memory device including a host data path and a garbage collection data path, the method includes: After the flash memory device initiates garbage collection, the first command execution time and the second command execution time within each time slice are determined, wherein the first command execution time is the time for executing a number of host data processing commands on the host data path, and the second command execution time is the time for executing a number of garbage collection commands on the garbage collection data path. While the flash memory device is not in a stable state, the number of host data processing commands and garbage collection commands to be issued and executed in the next time slice is adjusted according to the relationship between the execution time of the first command and the execution time of the second command, until the flash memory device enters a stable state; The stable state includes the state in which the number of each type of host data write command executed on the host data path of the flash memory device changes less than a preset number threshold within a number of consecutive time slices, or the number of each type of garbage collection command executed on the garbage collection data path changes less than a preset number threshold. The step of adjusting the number of host data processing commands and garbage collection commands issued and executed in the next time slice based on the relationship between the execution time of the first command and the execution time of the second command includes: Calculate the minimum command execution time within the first time slice, wherein the minimum command execution time is the minimum value between the first command execution time and the second command execution time; When the minimum command execution time is the same as the first command execution time, the number of host cache write commands, garbage collection memory write commands, and garbage collection memory read commands issued in the third time slice is reduced, and the number of host memory write commands, garbage collection cache write commands, and garbage collection cache read commands issued in the third time slice is increased. When the minimum command execution time is the same as the second command execution time, the number of host cache write commands, garbage collection memory write commands, and garbage collection memory read commands issued in the third time slice is increased, and the number of host memory write commands, garbage collection cache write commands, and garbage collection cache read commands issued in the third time slice is decreased.

2. The method according to claim 1, characterized in that, The flash memory device includes cache, memory, and flash storage; The host data path includes a data path between the host and the cache or a data path between the host and memory; the garbage collection data path includes a data path between flash memory and the cache or a data path between flash memory and memory. Alternatively, the host data path may include a data path between the host and the cache or a data path between the cache and memory, and the garbage collection data path may include a data path between flash memory and the cache or a data path between the cache and memory.

3. The method according to claim 1, characterized in that, The host data processing commands include host data write commands, and the garbage collection commands include garbage collection write commands or garbage collection read commands; The host data path includes a host write path, and the garbage collection data path includes a garbage collection write path or a garbage collection read path. The host write path is used to execute host data write commands, the garbage collection write path is used to execute garbage collection write commands, and the garbage collection read path is used to execute garbage collection read commands.

4. The method according to claim 3, characterized in that, The flash memory device includes a front-end module, and before determining the first command execution time and the second command execution time within each time slice, the method further includes: Calculate the write amplification factor and use the write amplification factor as the ratio of the number of garbage collection write commands and host data write commands issued in each time slice; Based on the aforementioned quantity ratio and the preset unit quantity, determine the first quantity of host data write commands and the second quantity of garbage collection write commands issued for each time slice; In each time slice, a first number of host data write commands and a second number of garbage collection write commands are sent to the front-end module.

5. The method according to claim 3, characterized in that, The host write path, the garbage collection write path, and the garbage collection read path each correspond to a command submission queue and a command completion queue; Determining the first command execution time and the second command execution time within each time slice includes: Record the start timestamp of each host data write command, garbage collection write command, or garbage collection read command when it is submitted to the corresponding command submission queue; Within the first time slice, several host data write commands, garbage collection write commands, and garbage collection read commands are executed. Record the end timestamp of each host data write command, garbage collection write command, or garbage collection read command when it is submitted to the corresponding command completion queue after execution; Based on the end timestamp and the start timestamp, calculate the execution time of each host data write command, garbage collection write command, or garbage collection read command; The execution times of each host data write command executed within the first time slice are added together, and the result is used as the execution time of the first command. The execution times of each garbage collection write command and garbage collection read command executed within the first time slice are added together, and the result is used as the execution time of the second command.

6. The method according to claim 5, characterized in that, The flash memory device includes a cache, memory, and flash memory. The host data write command includes a host cache write command or a host memory write command. The garbage collection write command includes a garbage collection cache write command or a garbage collection memory write command. The garbage collection read command includes a garbage collection cache read command or a garbage collection memory read command.

7. The method according to claim 6, characterized in that, The sum of the number of host cache write commands and the number of host memory write commands is a first quantity, and the sum of the number of garbage collection memory write commands and the number of garbage collection cache write commands is a second quantity; Before calculating the minimum command execution time within the first time slice, adjusting the number of host data processing commands and garbage collection commands to be issued and executed in the next time slice based on the relationship between the first command execution time and the second command execution time includes: After the execution of several host data write commands, garbage collection write commands, and garbage collection read commands within the first time slice is completed, several host data write commands, garbage collection write commands, and garbage collection read commands to be executed within the second time slice are issued.

8. The method according to claim 7, characterized in that, The step of adjusting the number of host data processing commands and garbage collection commands to be issued and executed in the next time slice based on the relationship between the execution times of the first command and the second command further includes: Within the third time slice, several host data write commands, garbage collection write commands, and garbage collection read commands are executed, and the third time slice is used as the first time slice of a new round. The first command execution time and the second command execution time of the new round of the first time slice are determined. After the execution of several host data write commands, garbage collection write commands, and garbage collection read commands within the third time slice is completed, a new round of several host cache write commands, host memory write commands, garbage collection cache read commands, garbage collection memory read commands, garbage collection memory write commands, and garbage collection cache write commands within the second time slice is issued according to the number of host cache write commands, host memory write commands, garbage collection cache read commands, garbage collection memory read commands, garbage collection memory write commands, and garbage collection cache write commands executed within the third time slice. Based on the relationship between the execution time of the first command and the execution time of the second command in the first time slice of the new round, the number of host cache write commands, host memory write commands, garbage collection cache read commands, garbage collection memory read commands, garbage collection memory write commands, and garbage collection cache write commands issued and executed in the third time slice of the new round is adjusted until the flash memory device enters a stable state.

9. The method according to claim 7 or 8, characterized in that, The method further includes: The flash memory device is determined to have entered a stable state when the difference between the minimum command execution times of two consecutive rounds is less than a preset time threshold, or when the number of host cache write commands, host memory write commands, garbage collection cache write commands, garbage collection memory write commands, garbage collection cache read commands, or garbage collection memory read commands is zero in any time slice of any round. The time slice includes a first time slice, a second time slice, or a third time slice.

10. The method according to any one of claims 3-8, characterized in that, The host data processing command also includes a host data read command, and the host data path also includes a host read path. The host read path is used to execute the host data read command, and the host read path corresponds to a command submission queue. The method further includes: Different priorities are set for the host data read command, the host data write command, the garbage collection write command, and the garbage collection read command, and the priority of the host data read command is controlled to be the highest. After the host data read command is submitted to the corresponding command submission queue, the processing of low-priority host data write commands, garbage collection write commands, and garbage collection read commands is interrupted, and the host data read command is issued and executed.

11. A storage control chip, characterized in that, include: At least one processor; as well as, A memory communicatively connected to the at least one processor; wherein, The memory stores instructions that can be executed by the at least one processor, which, when executed by the at least one processor, enables the at least one processor to perform the command management method as described in any one of claims 1-10.

12. A flash memory device, characterized in that, include: The storage control chip as described in claim 11; At least one flash memory is communicatively connected to the storage control chip.

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