Task sending method and device and task execution method and device

Abstract

The invention provides a task sending method and device and a task execution method and device, relates to the field of computers, and solves the problem that the time delay of a processor running program is relatively large. According to the specific scheme, multiple tasks and task issuing modes are obtained; and if the task issuing mode is non-list issuing and the sending task descriptor satisfies a memory barrier-free condition, sending the sending task descriptor to the hardware circuit, the sending task descriptor being used for indicating processing information of at least one task in the plurality of tasks, and the memory barrier-free condition being used for indicating a data volume that can be processed by the processor core in one period. Therefore, the time consumption caused by executing the memory barrier operation can be reduced, and the time delay when the processor runs the program is reduced.

Description

Technical Field

[0001] The present application relates to the field of computers, and in particular to a task sending method, a task execution method and a device. Background Art

[0002] When the processor runs a program, the order in which the program instructions are processed is inconsistent with the order in which the program instructions are written, resulting in out-of-order memory access. For example, after multi-threaded execution optimization, the program will cause out-of-order memory access. For another example, when multiple processor cores run a program, it will also cause out-of-order memory access.

[0003] In order to avoid out-of-order memory access, memory barrier technology can be used to make multiple processor cores access memory in the order in which the program code is written. However, since memory barrier operations are time-consuming, the processor's program execution delay is increased. Summary of the invention

[0004] The present application provides a task sending method, a task execution method and a device, which solve the problem of large delay in processor running program.

[0005] In a first aspect, the present application provides a task sending method, which includes: obtaining multiple tasks and a task sending method; if the task sending method is non-list sending, and the sending task descriptor satisfies a memory barrier-free condition, sending the sending task descriptor to a hardware circuit, the sending task descriptor is used to indicate processing information of at least one task among multiple tasks, and the memory barrier-free condition is used to indicate the amount of data that the processor core can process within one cycle.

[0006] Therefore, if the task is sent in a non-list manner and the sending task descriptor meets the memory barrier-free condition, the processor core can process the sending task descriptor within one cycle. That is, the instructions corresponding to the task in the sending task descriptor will be sent in order, and the processor core will not have disorderly memory access. Therefore, it can choose not to perform the memory barrier operation and directly send the sending task descriptor to the hardware circuit. Compared with adding a memory barrier operation in the task sending process to ensure orderly memory access, the sending process of the sending task descriptor of the present application can choose not to perform the memory barrier operation, which can reduce the time consumption caused by the memory barrier operation and reduce the delay when the processor runs the program.

[0007] In a possible design, the memory barrier-free condition is that the amount of data sent in the task descriptor satisfies the amount of data that can be processed by the processor core in one cycle.

[0008] In a possible design, the memory barrier-free condition is that the amount of data in the task descriptor sent is less than or equal to a threshold, and the threshold is the amount of data that can be processed by the processor core in one cycle.

[0009] In a possible design, if the task delivery mode is non-list delivery and the sending task descriptor satisfies the memory barrier-free condition, sending the sending task descriptor to the hardware circuit includes:

[0010] If the task delivery mode is non-list delivery, and the data amount of the sending task descriptor is less than or equal to the threshold, the memory barrier is not executed, and the sending task descriptor is sent to the hardware circuit. The threshold is the amount of data that the processor core can process in one cycle.

[0011] In a possible design, the sending task descriptor includes a control field and multiple hash fields, the hash field is used to store the address of the task, and the amount of data in the sending task descriptor is determined by the number of hash fields.

[0012] In this design, the amount of data in the sending task descriptor can be controlled by setting the number of hash domain segments to ensure that the sending task descriptor meets the memory barrier-free condition. Therefore, it is possible to choose not to perform the memory barrier operation and directly send the sending task descriptor to the hardware circuit, thereby reducing the time consumption caused by the memory barrier operation and reducing the latency when the processor runs the program.

[0013] In a possible design, the control domain segment also includes indication information, where the indication information is used to indicate whether the task has been executed.

[0014] In this design, the hardware circuit that receives the sending task descriptor can determine whether the task has been executed based on the indication information, thereby ensuring the consistency of the data in the sending task descriptor.

[0015] In one possible design, the method also includes: the method also includes: if the task is sent in a non-list manner and the sending task descriptor does not meet the memory barrier-free condition, a memory barrier operation is performed and a doorbell information is sent to the hardware circuit, the memory barrier operation is used to control the execution order of instructions corresponding to the task, and the doorbell information is used to indicate reading the sending task descriptor from the memory.

[0016] In this design, when the sending task descriptor does not meet the memory barrier-free condition, a memory barrier operation needs to be performed after the sending task descriptor is sent to the hardware circuit to ensure orderly memory access.

[0017] In one possible design, the send task descriptor is stored in memory.

[0018] In this design, when the sending task descriptor meets the memory barrier-free condition, you can choose not to perform the memory barrier operation and directly store the sending task descriptor into the memory, which can reduce the time consumed by performing the memory barrier operation.

[0019] In a possible design, if the task is sent in a non-list manner and the sending task descriptor does not meet the memory barrier-free condition, the sending task descriptor is stored in the memory and a memory barrier operation is performed.

[0020] In this design, when the sending task descriptor does not meet the memory barrier-free condition, a memory barrier operation needs to be performed after the sending task descriptor is sent to the memory to ensure orderly memory access.

[0021] In a possible design, if the task is sent in a list-based manner, a memory barrier operation is performed and a doorbell message is sent to the hardware circuit.

[0022] In a possible design, if the task is sent in a list-based manner, a memory barrier operation is performed and the sending task descriptor is stored in the memory.

[0023] In a second aspect, the present application provides a task execution method, the method comprising: receiving a sending task descriptor; if the cache does not overflow, sending the sending task descriptor to the cache and generating a first doorbell information, the first doorbell information being used to notify the hardware circuit to read the sending task descriptor from the cache; based on the first doorbell information, reading the sending task descriptor from the cache and executing the task of the sending task descriptor.

[0024] Therefore, in the task execution method provided in the embodiment of the present application, when the cache does not overflow, the sending task descriptor is sent to the cache, and the hardware circuit reads the sending task descriptor from the cache, which can improve the processing speed of the hardware circuit.

[0025] In one possible design, the method also includes: if the cache overflows, discarding the sending task descriptor and generating a second doorbell information, the second doorbell information is used to notify the hardware circuit to read the sending task descriptor from the memory; based on the second doorbell information, reading the sending task descriptor from the memory and executing the task of the sending task descriptor.

[0026] In this design, if the cache overflows, the hardware circuit can read the sending task descriptor from the memory based on the second doorbell information, thereby also realizing the execution of the task in the sending task descriptor.

[0027] In one possible design, the sending task descriptor includes a control field segment, the control field segment includes indication information, and the indication information is used to indicate whether the task is executed. The method also includes: if the indication information in the sending task descriptor indicates that the task has not been executed, executing the task of the sending task descriptor; if the indication information indicates that the task has been executed, scheduling the task queue of the sending task descriptor to the end of the queue pair.

[0028] In this design, the hardware circuit can determine whether the task in the sending task descriptor has been executed by judging the indication information in the sending task descriptor. If the task has not been executed, the task in the sending task descriptor can be directly executed. If the task has been executed, the task can be re-executed after waiting for a period of time.

[0029] In the third aspect, the present application provides a task sending device, which includes: a communication module, used to obtain multiple tasks and task sending methods; a processing module, used to determine that the task sending method is non-list sending, and the sending task descriptor satisfies the memory barrier-free condition, the communication module is also used to send the sending task descriptor to the hardware circuit, the sending task descriptor is used to indicate the processing information of at least one task among multiple tasks, and the memory barrier-free condition is used to indicate the amount of data that the processor core can process within one cycle.

[0030] The beneficial effects of the third aspect can refer to the description of the first aspect.

[0031] In a possible design, the memory barrier-free condition is that the amount of data sent in the task descriptor satisfies the amount of data that can be processed by the processor core in one cycle.

[0032] In a possible design, the sending task descriptor includes a control field and multiple hash fields, the hash field is used to store the address of the task, and the amount of data in the sending task descriptor is determined by the number of hash fields.

[0033] In a possible design, the control domain segment also includes indication information, where the indication information is used to indicate whether the task has been executed.

[0034] In a possible design, the communication module is specifically used for: if the task is sent in a non-list manner and the sending task descriptor does not meet the memory barrier-free condition, performing a memory barrier operation and sending doorbell information to the hardware circuit, the memory barrier operation is used to control the execution order of instructions corresponding to the task, and the doorbell information is used to indicate reading the sending task descriptor from the memory.

[0035] In a possible design, the communication module is specifically used to: if the task is sent in a non-list manner and the sending task descriptor meets the memory barrier-free condition, store the sending task descriptor in the memory.

[0036] In a possible design, the communication module is specifically used to: if the task is sent in a non-list manner and the sending task descriptor does not meet the memory barrier-free condition, store the sending task descriptor in the memory and perform a memory barrier operation.

[0037] In a fourth aspect, the present application provides a task execution device, comprising: a receiving module, a sending module and an execution module. The receiving module is used to receive a sending task descriptor. The sending module is used to send the sending task descriptor to the cache and generate a first doorbell information if the cache does not overflow, and the first doorbell information is used to notify the hardware circuit to read the sending task descriptor from the cache. The execution module is used to read the sending task descriptor from the cache based on the first doorbell information and execute the task of the sending task descriptor.

[0038] The beneficial effects of the fourth aspect can refer to the description of the second aspect.

[0039] In a possible design, the sending module is further used to discard the sending task descriptor and generate a second doorbell information if the buffer overflows, and the second doorbell information is used to notify the hardware circuit to read the sending task descriptor from the memory. The execution module is also used to read the sending task descriptor from the memory based on the second doorbell information and execute the task of the sending task descriptor.

[0040] In a possible design, the sending task descriptor includes a control field segment, the control field segment includes indication information, the indication information is used to indicate whether the task is executed, and the execution module is further used to: if the indication information in the sending task descriptor indicates that the task is not executed, execute the task of the sending task descriptor. If the indication information indicates that the task has been executed, schedule the task queue of the sending task descriptor to the end of the queue pair.

[0041] In a fifth aspect, the present application provides a chip, comprising: a processor and a power supply circuit; wherein the power supply circuit is used to supply power to the processor; and the processor is used to implement the method of the first aspect.

[0042] In a sixth aspect, the present application provides a computer device, comprising a processor and a memory, wherein the memory is used to store a set of computer instructions; when the processor executes the set of computer instructions, it is used to execute the method of the first aspect or the second aspect.

[0043] In a seventh aspect, the present application provides a computer-readable storage medium, comprising computer instructions, which, when executed on an electronic device, enables the electronic device to execute a task sending method or a task execution method in any of the above aspects and any possible implementation methods.

[0044] In an eighth aspect, the present application provides a computer program product, which, when executed on a computer or a processor, enables the computer or the processor to execute a task sending method or a task execution method in any of the above aspects and any possible implementation methods.

[0045] It can be understood that any of the task sending devices, task execution devices, chips, computer devices, computer-readable storage media or computer program products provided above can be applied to the corresponding methods provided above. Therefore, the beneficial effects that can be achieved can refer to the beneficial effects in the corresponding methods and will not be repeated here.

[0046] These and other aspects of the present application will become more apparent from the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0047] Figure 1 A schematic diagram of sending a task descriptor provided by this application;

[0048] Figure 2 A schematic diagram of a computer system provided for this application;

[0049] Figure 3 A schematic diagram of the operation flow of a WQE and direct WQE provided for this application;

[0050] Figure 4 A time-consuming distribution diagram of operations of a processor core provided by the present application;

[0051] Figure 5 A flowchart of a task sending method provided by this application;

[0052] Figure 6 A schematic diagram of a sending task descriptor that satisfies the memory barrier-free condition provided by the present application;

[0053] Figure 7 A flowchart of a task execution method provided for this application;

[0054] Figure 8 A flowchart of accessing a processor core and a hardware circuit provided by the present application;

[0055] Fig. 9 A comparison chart of the speed of processing instructions for executing or not executing a memory barrier operation provided by the present application;

[0056] Fig.10 A time comparison diagram of instructions for executing a memory barrier operation provided by this application;

[0057] Fig.11 A schematic diagram of the composition of a task sending device provided in this application;

[0058] Fig.12 A schematic diagram of the composition of a task sending device provided in this application. DETAILED DESCRIPTION

[0059] For ease of understanding, some examples of concepts related to this application are provided for reference, as shown below:

[0060] Send queue work queue element (SQE), also known as send task descriptor, such as Figure 1 As shown, the sending task descriptor may include a control section, an extended section, and multiple hash sections (segment sections, SGE). Figure 1 , N hash fields are shown, namely SGE_1 to SGE_N. For example, the space size of the control field and the extension field is 16 bytes (byte, B), and the space size of one hash field is also 16B.

[0061] Direct WQE technology sends work queue elements (WQE) issued by software to registers of hardware circuits to reduce the operation of the hardware circuit to read WQEs.

[0062] SQE Ownership is a technology that prevents configuration and reading between software and hardware from being out of sync. This technology includes the SQE check bit (owner bit), and the hardware circuit checks the SQE check bit according to certain rules to determine whether the SQE is valid.

[0063] A memory barrier operation is an operation performed based on a memory barrier instruction, which ensures that the hardware circuit first executes all memory access instructions before the memory barrier instruction, and then executes the memory access instructions after the memory barrier instruction, without affecting the execution order of other instructions on the hardware circuit.

[0064] A queue is a linear list with the characteristics of first-in-first-out, with insertion at one end and deletion at the other end. Optionally, new tasks are pushed into the queue at the rear, and the tasks at the front are popped out each time.

[0065] The technical solution in this application will be described below in conjunction with the drawings in this application.

[0066] For ease of understanding, the task sending device for executing the task sending method provided by the present application and the task executing device for implementing the task executing method are first introduced below. Among them, the task sending device can be a terminal device, such as a mobile phone terminal, a tablet computer, a laptop computer, an augmented reality device (augmented reality, AR), a virtual reality device (virtual reality, VR) and a vehicle-mounted terminal, etc., and can also be a server, etc. In addition, the task executing device can also be a terminal device, such as a mobile phone terminal, a tablet computer, a laptop computer, AR, VR and a vehicle-mounted terminal, etc. The task sending device or the task executing device can be configured with an input / output (input / output, I / O) interface for data interaction with an external device. For example, a user can submit a task request to the input / output interface through an external device. The task request in this application may include: the processor core reads data in the terminal device or writes data to the terminal device, etc.

[0067] In some embodiments, the task sending device implementing the task sending method and the task executing device implementing the task executing method provided by the present application may be a computer system. Figure 2 As shown, Figure 2A schematic diagram of the structure of a computer system provided for the present application. The computer system 20 may include a processor 21, a hardware circuit 22 and a memory 23. Among them, the processor 21 may include multiple processor cores, and the processor core may be a central processing unit (CPU) core or a graphic processing unit (GPU) core, which is not specifically limited in the present application. The processor core can be used to perform the memory barrier operation in the present application. The hardware circuit 22 includes a circuit composed of various unit module circuits, wherein the drive interface of the hardware circuit 22 may include: peripheral component interconnect express (PCIE), serial attached small computer system interface (SAS) and serial integrated device circuit (SATA). The hardware circuit 22 can be used to execute the task in the sending task descriptor. The memory 23 may be a synchronous dynamic random access memory (DRAM) or a double data rate synchronous dynamic random access memory (DDR SDRAM), which may be referred to as DDR, which is not specifically limited in the present application. The memory 23 may be used to store data and instructions.

[0068] At present, when issuing tasks, the processor core submits a task request (work request) to the send queue (SQ) of the hardware circuit through the driver interface to form an SQE stored in the send queue, and generates doorbell (db) information to notify the hardware circuit to execute the task.

[0069] Optionally, the processor core needs to perform data memory barrier (DMB) isolation when writing the send task descriptor and updating the doorbell information, or when writing the send task descriptor and updating the direct WQE. Through data memory barrier isolation, it can be ensured that when the hardware circuit reads the send task descriptor, the WQE has been written into the data consistency node.

[0070] like Figure 3 As shown, Figure 3 (a) in FIG. 1 shows a schematic diagram of the operation flow of WQE. Figure 3 (b) in FIG. 1 shows a schematic diagram of the operation flow of directWQE. Figure 3 As shown in (a) in the figure, the operation process of WQE includes three steps, namely: Step 1: The processor core stores WQE in the off-chip DDR. Step 2: The processor core sends db information to the hardware circuit. Step 3: The hardware circuit reads WQE from DDR. Figure 3 As shown in (b) of FIG. 1 , the operation flow of direct WQE includes five steps, namely: Step 1: The processor core stores SQE in the off-chip DDR. Step 2: The processor core sends SQE to the hardware circuit through the direct WQE path. Step 3: The hardware circuit stores SQE in the cache (on-chip). Step 4: The hardware circuit sends db information. Step 5: The hardware circuit reads SQE from the cache.

[0071] Among them, Figure 3 As shown in (a) in , if the processor core sends db information, or the processor core cannot guarantee 64B aggregate write, the hardware circuit reads WQE from DDR after obtaining db information. At this time, it is necessary to add memory barrier operations in steps 1 and 2. In addition, Figure 3 As shown in (b) in the figure, if the processor core issues SQE through the direct WQE path and the processor core can guarantee 64B aggregate write, but the cache overflows and the SQE is discarded, the hardware circuit generates db information and also reads SQE from DDR. At this time, it is also necessary to add memory barrier operations in steps 1 and 2.

[0072] like Figure 4 As shown, Figure 4 This is a time-consuming distribution diagram of the operation of a processor core provided by the present application. Figure 4 The time consumption diagram of five instructions is shown in FIG. 5 , which include: queue pair (QP) initialization instruction, generate send task descriptor instruction, memory barrier instruction, send to bus instruction and send to hardware circuit instruction. Figure 4 It can be seen that memory barrier instructions account for about one-third of the time consumption. Therefore, how to reduce the time consumption of instructions and reduce the latency of the processor running the program is an urgent problem to be solved.

[0073] Therefore, the present application provides a task sending method, in which if the task is sent in a non-list manner and the sending task descriptor satisfies the memory barrier-free condition, the processor core can process the sending task descriptor within one cycle. That is, the instructions corresponding to the task in the sending task descriptor will be sent in order, and the processor core will not have disorderly memory access, so it can choose not to perform the memory barrier operation and directly send the sending task descriptor to the hardware circuit. Compared with the prior art, which adds a memory barrier operation during the task sending process to ensure orderly memory access, the sending process of the sending task descriptor of the present application can choose not to perform the memory barrier operation, which can reduce the time consumption caused by the memory barrier operation and reduce the delay when the processor runs the program.

[0074] Applied to the terminal device mentioned above, the task sending method provided by the present application is introduced below. The task sending method can be executed by the processor core, such as Figure 5 As shown, Figure 5 A flowchart of a task sending method provided in the present application, the task sending method includes the following process.

[0075] 501. Get multiple tasks and task delivery methods.

[0076] The task in this application is a work request issued by the application. The task may include any one of reading data from the local memory, storing data in the local memory, storing data in the remote memory, and reading data from the remote memory. If the computational complexity of the task is large, the processor core may divide the task into multiple subtasks and send the subtasks to the hardware circuit respectively. After the hardware circuit calculates the subtask, it obtains the calculation result of the subtask, and sends the calculation result of the subtask back to the processor core, which summarizes the calculation result of the subtask to obtain the calculation result of the task.

[0077] Among them, the task delivery method can include list delivery (work request list, wr_list) and non-list delivery. Non-list delivery can also be called single task delivery. The instructions of a single task will not have out-of-order memory access during delivery. List delivery can also be called multiple task delivery. The instructions of multiple tasks may have out-of-order memory access during delivery.

[0078] When an application sends multiple tasks, a memory barrier operation needs to be performed to avoid out-of-order memory access. In an example, the application sends tasks A and B. Task A writes data a to the memory, and task B reads data b from the memory. After the memory barrier operation is performed, all write operations before the memory barrier operation must be written to the memory first, and read operations after the memory barrier operation can obtain the results of the write operation.

[0079] 502. If the task delivery mode is non-list delivery and the sending task descriptor satisfies the memory barrier-free condition, the sending task descriptor is sent to the hardware circuit.

[0080] The processor core obtains a work queue element (WQE) based on the task, and the WQE is stored in a work queue (WQ). The WQE may include the starting address of the task, the address length, and the identifier of the destination host. In an example, the WQE may be: sending 10 bytes of data with a starting address of 0x10000000 in the memory to the host identified as 2. A pair of WQs can be understood as a queue pair (queue pair, QP), and a QP may include a send queue (send queue, SQ) and a receive queue (receive queue, RQ), where SQ is used to store send tasks and RQ is used to store receive tasks.

[0081] The sending task descriptor can be understood as a "task description". The sending task descriptor can include a control field and multiple hash fields. The hash fields are used to store the address of the task. The data volume of the sending task descriptor is determined by the number of hash fields. The more hash fields there are, the larger the data volume of the sending task descriptor.

[0082] The processor core can generate a sending task descriptor based on WQE. The content of WQE is stored in the hash field, and the address information of the task includes the starting address, address length and the identifier of the destination host. Therefore, each hash field (scatter / gather element, SGE) in the sending task descriptor can point to a continuous memory area, and multiple hash fields can represent multiple discrete continuous memory areas.

[0083] The control domain segment also includes indication information, which is used to indicate whether the task has been executed.

[0084] The indication information may be an owner bit. In one implementation, if the indication information is 1, it indicates that the task has not been executed. If the indication information is 0, it indicates that the task has been executed, that is, the memory space storing the task can be overwritten. In another implementation, if the indication information is 1, it indicates that the task has been executed. If the indication information is 0, it indicates that the task has not been executed.

[0085] Among them, the sending queue can be in the form of a linked list, and the processor core can update the indication information based on the information of the sending queue. The information of the sending queue may include a pointer to the sending queue (sq_producer_idx) and a depth of the sending queue (sq_shift), wherein the depth of the sending queue is a power of 2. The information of the sending queue can ensure that the indication information sent by the sending queue in each round has been updated. In one implementation, the processor core configuration rule is: owner = ~((qpc.sq_producer_idx>>qpc.sq_shift)&0x1), that is, the indication information is a value calculated based on the information of the sending queue and then inverted after taking 1 bit value. In an example, if the depth of the sending queue is 16, then sq_shift = 4, and when the indication information is sent in the first round, that is, when sq_shift is in the range of 0 to 15, the indication information is 1. When the indication information is sent in the second round, that is, when sq_shift is in the range of 16 to 31, the indication information is 0.

[0086] In addition, the sending task descriptor may further include an extension field segment, and the extension field segment may include a starting address, address length, and verification information of the extended operation.

[0087] The memory barrier-free condition is that the amount of data in the task descriptor sent meets the amount of data that the processor core can process in one cycle. For example, the memory barrier-free condition is that the amount of data in the task descriptor sent is less than or equal to a threshold, and the threshold is the amount of data that the processor core can process in one cycle.

[0088] In one example, the threshold may be 64B. Since both the control field and the extension field are 16B, when the number of hash fields is less than or equal to 2, the data volume of the sending task descriptor is less than or equal to the threshold. That is, the sending task descriptor includes one control field, one extension field and two hash fields, or the sending task descriptor includes one control field, one extension field and one hash field. Figure 6 As shown, Figure 6 A schematic diagram of a sending task descriptor that satisfies the memory barrier-free condition provided by this application. Figure 6 The sending task descriptor shown in (a) includes a control field segment, an extension field segment and two hash fields (SGE_1 and SGE_2). Figure 6 The sending task descriptor shown in (b) includes a control field segment, an extension field segment and a hash field segment (SGE_1).

[0089] Therefore, when the task is sent in a non-list manner and the sending task descriptor meets the memory barrier-free condition, it is possible to choose not to perform the memory barrier operation and directly send the sending task descriptor to the hardware circuit. Since the memory barrier operation is not performed, the delay when the processor core runs the program can be reduced.

[0090] Optionally, after step 501, the method may further include: if the task is sent in a non-list manner and the sending of the task descriptor does not meet the memory barrier-free condition, executing a memory barrier operation and sending doorbell information to the hardware circuit, the memory barrier operation is used to control the execution order of instructions corresponding to the task, and the doorbell information is used to indicate reading the sending task descriptor from the memory.

[0091] The memory barrier condition is not met when the amount of data in the sending task descriptor is greater than the threshold. In order to avoid out-of-order memory access, when the memory barrier-free condition is not met, the processor core performs a memory barrier operation to ensure orderly memory access. The processor core also sends doorbell information to the hardware circuit. The doorbell information is a fast notification type short message. After the hardware circuit receives the doorbell information, it can read the sending task descriptor from the memory based on the doorbell information.

[0092] Optionally, after step 501, the method may further include: if the task is sent in a list manner, executing a memory barrier operation and sending doorbell information to the hardware circuit.

[0093] Exemplarily, when the memory barrier-free condition is not met, in order to ensure orderly access to memory, the processor core performs a memory barrier operation and sends doorbell information to the hardware circuit. After the hardware circuit receives the doorbell information, it can read the sending task descriptor from the memory based on the doorbell information to execute the task in the sending task descriptor.

[0094] Optionally, after step 501, the method may further include: storing the sending task descriptor in a memory.

[0095] In order to ensure that the hardware circuit can read the WQE, the processor core will also store the sending task descriptor in the memory. Therefore, when the cache of the hardware circuit overflows, the hardware circuit can also read the sending task descriptor from the memory to execute the task in the sending task descriptor.

[0096] It can be understood that the present application does not limit the order in which the processor core sends the sending task descriptor to the hardware circuit and the memory respectively. The processor core can send the sending task descriptor to the hardware circuit and the memory at the same time, or send the sending task descriptor to the hardware circuit first, or send the sending task descriptor to the memory first.

[0097] Optionally, if the task is not sent in a list and the sending task descriptor does not meet the memory barrier condition, the sending task descriptor is stored in the memory and a memory barrier operation is performed. If the task is sent in a list, the sending task descriptor is stored in the memory and a memory barrier operation is performed.

[0098] Among them, when the memory barrier-free condition is not met, in order to avoid out-of-order memory access, it is necessary to perform a memory barrier operation after storing the sending task descriptor in the memory to control the execution order of the instructions corresponding to the task and ensure orderly memory access.

[0099] Optionally, if the task is sent in a list-based manner, the processor core performs a memory barrier operation and sends the doorbell information to the hardware circuit.

[0100] Exemplarily, when the memory barrier operation conditions are not met, the processor core performs the memory barrier operation and only sends the doorbell information to the hardware circuit. After the hardware circuit receives the doorbell information, it can read the sending task descriptor from the memory based on the doorbell information.

[0101] Applied to the terminal device shown above, the task execution method provided by the embodiment of the present application is introduced below. Figure 7 As shown, Figure 7 A flowchart of a task execution method provided in an embodiment of the present application, the task execution method includes the following process.

[0102] 701. The hardware circuit receives and sends a task descriptor.

[0103] 702. If the cache does not overflow, the hardware circuit sends the sending task descriptor to the cache and generates first doorbell information, where the first doorbell information is used to notify the hardware circuit to read the sending task descriptor from the cache.

[0104] Exemplarily, the cache may be a high-speed cache (cache), which may temporarily store the sending task descriptor. The access speed of the cache is higher than that of the memory, and the hardware circuit may increase the processing speed by reading data from the cache.

[0105] Exemplarily, after the sending task descriptor is written into the configuration space of the hardware circuit, the hardware circuit will determine whether a buffer overflow scenario occurs. If the buffer does not overflow, the hardware circuit sends the sending task descriptor to the buffer.

[0106] 703. The hardware circuit reads a sending task descriptor from a cache based on the first doorbell information and executes a task of sending the task descriptor.

[0107] Exemplarily, the hardware circuit may read the starting address in the sending task descriptor, obtain the physical address of the memory space corresponding to the starting address by looking up a table, and access the memory space.

[0108] Optionally, after step 701, the method may further include: if the cache overflows, the hardware circuit discards the sending task descriptor and generates a second doorbell message, the second doorbell message is used to notify the hardware circuit to read the task sending descriptor from the memory. The hardware circuit reads the sending task descriptor from the memory based on the second doorbell message and executes the task of sending the task descriptor.

[0109] Exemplarily, in the case of a cache overflow, the hardware circuit discards the sending task descriptor, thereby reading the sending task descriptor from the memory based on the second doorbell information. The hardware circuit can also read the starting address in the sending task descriptor, obtain the physical address of the memory space corresponding to the starting address by looking up the table, and access the memory space.

[0110] Optionally, the sending task descriptor includes a control field segment, the control field segment includes indication information, and the indication information is used to indicate whether the task has been executed. The method further includes: if the indication information in the sending task descriptor indicates that the task has not been executed, the hardware circuit executes the task of the sending task descriptor. If the indication information in the sending task descriptor indicates that the task has been executed, the task queue of the sending task descriptor is scheduled to the end of the queue pair.

[0111] Exemplarily, after the hardware circuit reads the WQE corresponding to the hash field in the sending task descriptor, it determines whether the owner bit of the control field of the sending task descriptor is updated to indicate that the task has not been executed. If the owner bit indicates that the task has not been executed, the WQE is directly executed. If the owner bit indicates that the task has been executed, it can be re-executed after waiting for a period of time according to the scheduling rules. The embodiments of the present application do not limit the scheduling rules. In one example, the task queue of the sending task descriptor can be scheduled to the end of the queue pair for re-execution. In another example, an accelerated backoff algorithm can be used to wait for a period of time before re-executing the task in the sending task descriptor.

[0112] In summary, the flowchart of accessing the processor core and hardware circuit is as follows: Figure 8 The flow chart may include steps (1) to (9).

[0113] Step (1): The processor core generates and sends a task descriptor based on the task. For details, please refer to the implementation method of step 502.

[0114] Step (2), the processor core determines whether the memory barrier-free condition is met, wherein the memory barrier-free condition is met when the amount of data of the task descriptor sent meets the amount of data that the processor core can process within one cycle; if the memory barrier-free condition is not met, step (3) is executed; if the memory barrier-free condition is met, step (4) is executed.

[0115] Step (3), sending the task descriptor to the hardware circuit and memory and performing the memory barrier operation.

[0116] Step (4), sending the task descriptor to the hardware circuit.

[0117] Step (5), after the hardware circuit receives the task descriptor, it determines whether the cache overflows. If the cache overflows, it executes step (6); if the cache does not overflow, it executes step (9).

[0118] Step (6), the hardware circuit reads the sending task descriptor from the memory according to the doorbell information.

[0119] Step (7), the hardware circuit determines whether the task has been executed based on the indication information in the sent task descriptor. If the indication information indicates that the task has been executed, execute step (8); if the indication information indicates that the task has not been executed, execute step (9).

[0120] Step (8), schedule the task queue that sends the task descriptor to the end of the queue pair, and then execute step (6).

[0121] Step (9), the hardware circuit executes the task in the sending task descriptor.

[0122] Based on the above task sending method and task execution method, a rate graph of processing instructions for executing memory barrier operations can be obtained, such as Fig. 9 and Fig.10 As shown. Among them, Fig. 9 The figure shows the rate of processing instructions that execute memory barrier operations and the rate of processing instructions that do not execute memory barrier operations when the task is issued in a non-list manner. Fig.10 The figure shows the time taken to execute the memory barrier operation and the time taken to execute the instruction without the memory barrier operation in the latency scenario. Fig. 9 It can be seen that the processing rate of instructions that perform memory barrier operations is about 11.5Mpps, while the processing rate of instructions that do not perform memory barrier operations is about 13.3Mpps, which greatly improves the processing rate of instructions. Fig.10 It can be seen that the instruction time for executing the memory barrier operation is about 92ns, and the instruction time for not executing the memory barrier operation is about 80ns, which reduces the instruction time consumption.

[0123] The present application also provides a chip, which includes a processor and a power supply circuit, wherein the power supply circuit is used to supply power to the processor, and the processor is used to implement a task sending method or a task execution method.

[0124] The present application also provides a computer device, which includes a processor and a memory, the memory is used to store instructions, and the processor obtains instructions to execute a task sending method or a task execution method.

[0125] It is understandable that, in order to implement the above functions, the computer device includes hardware and / or software modules corresponding to the execution of each function. In combination with the algorithm steps of each example described in the embodiments disclosed herein, the present application can be implemented in the form of hardware or a combination of hardware and computer software. Whether a function is executed in the form of hardware or computer software driving hardware depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application in combination with the embodiments, but such implementation should not be considered to be beyond the scope of the present application.

[0126] In this embodiment, the computer device can be divided into functional modules according to the above method example. For example, each functional module can be divided according to each function, or two or more functions can be integrated into one processing module. The above integrated module can be implemented in the form of hardware. It should be noted that the division of modules in this embodiment is schematic and is only a logical function division. There may be other division methods in actual implementation.

[0127] In the case of dividing each functional module into corresponding functional modules, Fig.11 A possible schematic diagram of the task sending device 1100 involved in the above embodiment is shown. Fig.11 As shown, the task sending device 1100 may include: a communication module 1101 and a processing module 1102 .

[0128] The communication module 1101 is used to obtain multiple tasks and task delivery methods. Specifically, the communication module 1101 can be used to support the task sending device 1100 to execute the above step 501, etc., and / or other processes of the technology described in this article.

[0129] The processing module 1102 is used to determine that the task delivery method is non-list delivery, and the sending task descriptor meets the memory barrier-free condition.

[0130] The communication module 1101 is also used to send the task descriptor to the hardware circuit. Specifically, the communication module 1101 can be used to support the task sending device 1100 to perform the above step 502, etc., and / or be used for other processes of the technology described herein.

[0131] It should be noted that all relevant contents of each step involved in the above method embodiment can be referred to the functional description of the corresponding functional module and will not be repeated here.

[0132] The task sending device 1100 provided in this embodiment is used to execute the above-mentioned task sending method, and thus can achieve the same effect as the above-mentioned implementation method.

[0133] Among them, the processing module can be a processor or a controller. It can implement or execute various exemplary logic boxes, modules and circuits described in conjunction with the disclosure of this application. The processor can also be a combination that implements computing functions, such as a combination of one or more microprocessors, a combination of digital signal processing (DSP) and a microprocessor, etc. The storage module can be a memory. The communication module can specifically be a device that interacts with other electronic devices, such as a radio frequency circuit, a Bluetooth chip, a Wi-Fi chip, etc.

[0134] In the case of dividing each functional module into corresponding functional modules, Fig.12 A possible schematic diagram of the task execution device 1200 involved in the above embodiment is shown. Fig.12 As shown, the task execution device 1200 may include: a receiving module 1201 , a sending module 1202 and an execution module 1203 .

[0135] The receiving module 1201 may be used to support the task execution device 1200 in executing the above-mentioned step 701, etc., and / or other processes of the technology described herein.

[0136] The sending module 1202 may be used to support the task execution device 1200 to execute the above-mentioned step 702, etc., and / or other processes of the technology described herein.

[0137] The execution module 1203 may be used to support the task execution device 1200 to execute the above-mentioned step 703 and / or other processes of the technology described herein.

[0138] It should be noted that all relevant contents of each step involved in the above method embodiment can be referred to the functional description of the corresponding functional module and will not be repeated here.

[0139] An embodiment of the present application also provides a computer storage medium, which stores computer instructions. When the computer instructions are executed on an electronic device, the electronic device executes the above-mentioned related method steps to implement the task sending method or task execution method in the above-mentioned embodiment.

[0140] An embodiment of the present application further provides a computer program product. When the computer program product is run on a computer, the computer is caused to execute the above-mentioned related steps to implement the task sending method or task execution method performed by the electronic device in the above-mentioned embodiment.

[0141] In addition, an embodiment of the present application also provides a device, which may specifically be a chip, component or module, and the device may include a connected processor and memory; wherein the memory is used to store computer execution instructions, and when the device is running, the processor may execute the computer execution instructions stored in the memory so that the chip executes the task sending method or task execution method performed by the electronic device in the above-mentioned method embodiments.

[0142] Among them, the task sending device, computer storage medium, computer program product or chip provided in this embodiment are all used to execute the corresponding methods provided above. Therefore, the beneficial effects that can be achieved can refer to the beneficial effects in the corresponding methods provided above, and will not be repeated here.

[0143] Through the description of the above implementation methods, technical personnel in the relevant field can understand that for the convenience and simplicity of description, only the division of the above-mentioned functional modules is used as an example. In actual applications, the above-mentioned functions can be assigned to different functional modules as needed, that is, the internal structure of the device can be divided into different functional modules to complete all or part of the functions described above.

[0144] In the description of this application, unless otherwise specified, " / " means or, for example, A / B can mean A or B; "and / or" in this article is only a description of the association relationship of associated objects, indicating that there can be three relationships, for example, A and / or B can mean: A exists alone, A and B exist at the same time, and B exists alone. In addition, in the description of this application, "multiple" means two or more than two.

[0145] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of this embodiment, unless otherwise specified, "plurality" means two or more.

[0146] In the several embodiments provided in the present application, it should be understood that the disclosed devices and methods can be implemented in other ways. For example, the device embodiments described above are only schematic. For example, the division of the modules or units is only a logical function division. There may be other division methods in actual implementation, such as multiple units or components can be combined or integrated into another device, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some interfaces, indirect coupling or communication connection of devices or units, which can be electrical, mechanical or other forms.

[0147] The units described as separate components may or may not be physically separated, and the components shown as units may be one physical unit or multiple physical units, that is, they may be located in one place or distributed in multiple different places. Some or all of the units may be selected according to actual needs to achieve the purpose of the present embodiment.

[0148] In addition, each functional unit in each embodiment of the present application may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit. The above-mentioned integrated unit may be implemented in the form of hardware or in the form of software functional units.

[0149] If the integrated unit is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a readable storage medium. Based on this understanding, the technical solution of the present application is essentially or the part that contributes to the prior art or all or part of the technical solution can be embodied in the form of a software product, which is stored in a storage medium and includes several instructions to enable a device (which can be a single-chip microcomputer, chip, etc.) or a processor (processor) to execute all or part of the steps of the method described in each embodiment of the present application. The aforementioned storage medium includes: U disk, mobile hard disk, read only memory (ROM), random access memory (RAM), disk or optical disk and other media that can store program code.

[0150] The above contents are only specific implementation methods of the present application, but the protection scope of the present application is not limited thereto. Any technician familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed in the present application, which should be included in the protection scope of the present application. Therefore, the protection scope of the present application should be based on the protection scope of the claims.

Claims

1. A task sending method, characterized in that: The method comprises: Get multiple tasks and task delivery methods; If the task sending method is non-list sending and the sending task descriptor meets the memory barrier-free condition, the sending task descriptor is sent to the hardware circuit, and the sending task descriptor is used to indicate the processing information of at least one task among the multiple tasks, and the memory barrier-free condition is used to indicate the amount of data that the processor core can process within one cycle.

2. The method according to claim 1, characterized in that The sending task descriptor includes a control field and multiple hash fields, the hash fields are used to store the address of the task, and the data volume of the sending task descriptor is determined by the number of the hash fields.

3. The method according to claim 2, characterized in that The control domain segment also includes indication information, and the indication information is used to indicate whether the task has been executed.

4. The method according to any one of claims 1 to 3, characterized in that: The method further comprises: If the task is sent in a non-list manner and the sending task descriptor does not meet the memory barrier-free condition, a memory barrier operation is performed and a doorbell message is sent to the hardware circuit. The memory barrier operation is used to control the execution order of the instructions corresponding to the task, and the doorbell message is used to indicate reading the sending task descriptor from the memory.

5. The method according to any one of claims 1 to 4, characterized in that: The method further comprises: The sending task descriptor is stored in a memory.

6. A task execution method, characterized in that: The method comprises: Receive send task descriptor; If the cache does not overflow, sending the sending task descriptor to the cache and generating first doorbell information, wherein the first doorbell information is used to notify the hardware circuit to read the sending task descriptor from the cache; The sending task descriptor is read from the buffer based on the first doorbell information and the task of the sending task descriptor is executed.

7. The method according to claim 6, characterized in that The method further comprises: If the buffer overflows, discard the sending task descriptor and generate second doorbell information, wherein the second doorbell information is used to notify the hardware circuit to read the sending task descriptor from the memory; The sending task descriptor is read from the memory based on the second doorbell information and a task of the sending task descriptor is executed.

8. The method according to claim 7, characterized in that The sending task descriptor includes a control field segment, the control field segment includes indication information, and the indication information is used to indicate whether the task is executed. The method further includes: If the indication information in the sending task descriptor indicates that the task has not been executed, executing the task of the sending task descriptor; If the indication information indicates that the task has been executed, the task queue for sending the task descriptor is scheduled to the end of the queue pair.

9. A task sending device, characterized in that: The task sending device comprises: Communication module, used to obtain multiple tasks and task delivery methods; A processing module, used for determining that the task delivery mode is non-list delivery and the sending task descriptor satisfies the memory barrier-free condition; The communication module is also used to send the sending task descriptor to the hardware circuit, wherein the sending task descriptor is used to indicate processing information of at least one task among the multiple tasks, and the memory barrier-free condition is used to indicate the amount of data that can be processed by the processor core within one cycle.

10. The device according to claim 9, characterized in that The sending task descriptor includes a control field and multiple hash fields, the hash fields are used to store the address of the task, and the data volume of the sending task descriptor is determined by the number of the hash fields.

11. The device according to claim 9, characterized in that The control domain segment also includes indication information, and the indication information is used to indicate whether the task has been executed.

12. The device according to any one of claims 9 to 11, characterized in that: The communication module is specifically used for: If the task is sent in a non-list manner and the sending task descriptor does not meet the memory barrier-free condition, a memory barrier operation is performed and a doorbell message is sent to the hardware circuit. The memory barrier operation is used to control the execution order of the instructions corresponding to the task, and the doorbell message is used to indicate reading the sending task descriptor from the memory.

13. The device according to any one of claims 9 to 12, characterized in that: The communication module is specifically used for: The sending task descriptor is stored in a memory.

14. A task execution device, characterized in that: The task execution device comprises: A receiving module, used for receiving and sending a task descriptor; A sending module, configured to send the sending task descriptor to the cache and generate first doorbell information if the cache does not overflow, wherein the first doorbell information is used to notify a hardware circuit to read the sending task descriptor from the cache; An execution module is used to read the sending task descriptor from the cache based on the first doorbell information and execute the task of the sending task descriptor.

15. The device according to claim 14, characterized in that The sending module is further used to discard the sending task descriptor and generate second doorbell information if the buffer overflows, and the second doorbell information is used to notify the hardware circuit to read the sending task descriptor from the memory; The execution module is further configured to read the sending task descriptor from the memory based on the second doorbell information and execute the task of the sending task descriptor.

16. The device according to claim 15, characterized in that The sending task descriptor includes a control field segment, the control field segment includes indication information, the indication information is used to indicate whether the task is executed, and the execution module is further used to: If the indication information in the sending task descriptor indicates that the task has not been executed, executing the task of the sending task descriptor; If the indication information indicates that the task has been executed, the task queue for sending the task descriptor is scheduled to the end of the queue pair.

17. A chip, characterized in that: The chip includes: a processor and a power supply circuit; wherein the power supply circuit is used to supply power to the processor; and the processor is used to implement the method of any one of claims 1 to 5 or any one of claims 6 to 8.

18. A computer device, characterized in that: The computer device includes a processor and a memory, wherein the memory is used to store a set of computer instructions; when the processor executes the set of computer instructions, it is used to execute the method described in any one of claims 1 to 5 or any one of claims 6 to 8.

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