Data error correction method, storage medium and integrated chip based on BCH coding

Abstract

The present invention discloses a data error correction method, storage medium, and integrated chip based on BCH coding, relating to the field of chip design and application technology. The data error correction method based on BCH coding comprises: obtaining target data obtained by BCH coding, determining each syndrome corresponding to the target vector based on the target vector of the target data and a preset check matrix; if a syndrome indicating a data error exists among the determined syndromes, generating an error equation based on each syndrome; constructing a target number of check equations based on the coefficients of the error equations, grouping the constructed check equations, and solving each group of check equations using the same set of summation modules to obtain error position data; and correcting the target data based on the error position data to obtain an error correction result. Application of the solution provided by the embodiments of the present invention can reduce the resources occupied by implementing the error correction function.

Description

Technical Field

[0001] The present invention relates to the field of chip design and application technology, and in particular to a data error correction method, storage medium and integrated chip based on BCH coding. Background Art

[0002] When decoding BCH (Bose-Chaudhuri-Hocquenghem) encoded data, error correction requires the most computational effort compared to simple error detection, especially when transmitting a large number of data bits. Existing technologies often rely on designing numerous complex circuits to complete calculations within a single clock cycle, or inserting registers to form a pipeline. While this can reduce path latency, it doesn't actually reduce the circuit area.

[0003] Furthermore, in actual chip applications, not every data transmission will experience errors. For example, in the early stages of a flash memory device's life, the probability of errors is very low. Error detection must be used during every data transmission, while error correction is only activated after an error is detected. However, error correction circuitry is significantly more complex than error detection. Existing technologies require BCH circuitry to implement error correction, which occupies a significant chip area and inefficiently utilizes resources. Summary of the Invention

[0004] The present invention aims to solve at least one of the technical problems in the related art to a certain extent. To this end, one object of the present invention is to provide a data error correction method, storage medium and integrated chip based on BCH coding to reduce the resources occupied by the error correction function.

[0005] According to a first aspect of an embodiment of the present invention, a data error correction method based on BCH coding is provided, the method comprising:

[0006] Obtain target data obtained by BCH encoding, and determine syndromes corresponding to the target vector based on a target vector of the target data and a preset check matrix; wherein the target vector is obtained by concatenating the target data and check bit data corresponding to the target data;

[0007] If there is a syndrome indicating data error among the determined syndromes, an error equation is generated according to the syndromes;

[0008] Constructing a target number of check equations based on coefficients of the error equation, where the target number is consistent with the number of bits of the target vector;

[0009] The constructed verification equations are grouped and each group of verification equations is solved using the same set of summing modules to obtain error position data; wherein each summing module in the same set of summing modules includes a modular multiplier and a modular adder;

[0010] The target data is corrected according to the error position data to obtain an error correction result.

[0011] According to a second aspect of an embodiment of the present invention, a computer-readable storage medium is provided, on which a computer program is stored. When the computer program is executed by a processor, the data error correction method based on BCH coding is implemented.

[0012] According to a third aspect of an embodiment of the present invention, an integrated chip is provided, comprising: a memory and a processor; a computer program is stored on the memory, and when the computer program is executed by the processor, the above-mentioned data error correction method based on BCH coding is implemented.

[0013] In the solution provided by an embodiment of the present invention, each syndrome corresponding to the target vector is determined based on the target vector of the target data and a preset check matrix. The syndrome can be used to determine whether a data error exists. If so, the syndrome is used to generate an error equation, and then a check equation is constructed based on the error equation to obtain error position data, thereby determining the error position and performing error correction.

[0014] In the process of solving the check equations, the check equations are grouped and solved by reusing the same set of summing modules. In this way, there is no need to design a separate summing module and corresponding circuit for each check equation. By reusing the modular multipliers and modular adders in the summing modules, the area of the BCH error correction circuit can be greatly reduced, thereby improving resource utilization efficiency.

[0015] And if no error is detected, the calculation based on the syndrome can give data in a shorter time. If error correction is required, the correct result can also be given within fewer clock cycles.

[0016] Additional aspects and advantages of the present invention will be set forth in part in the description which follows and, in part, will be obvious from the description which follows, or may be learned through practice of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Figure 1 1 is a flow chart of a data error correction method based on BCH coding provided by an embodiment of the present invention;

[0018] Figure 2 This is a schematic diagram of a first circuit structure provided by an embodiment of the present invention;

[0019] Figure 3 This is a schematic diagram of a second circuit structure provided by an embodiment of the present invention;

[0020] Figure 4 This is a schematic diagram of a third circuit structure provided by an embodiment of the present invention;

[0021] Figure 5 is a state transition diagram of a state machine provided by an embodiment of the present invention;

[0022] Figure 6 This is a schematic diagram of a fourth circuit structure provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0023] The following describes embodiments of the present invention in detail, examples of which are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are intended to be used to explain the present invention, and are not to be construed as limiting the present invention.

[0024] The following describes a data error correction method, storage medium, and integrated chip based on BCH coding according to embodiments of the present invention with reference to the accompanying drawings.

[0025] In one embodiment of the present invention, see Figure 1 , provides a data error correction method based on BCH coding, including the following steps S101-S105.

[0026] S101: Obtain target data obtained by BCH encoding, and determine syndromes corresponding to the target vector according to a target vector of the target data and a preset check matrix.

[0027] The target vector is obtained by concatenating the target data and the check bit data corresponding to the target data.

[0028] S102: If there is a syndrome indicating data error among the determined syndromes, an error equation is generated according to the syndromes.

[0029] S103: Constructing a target number of check equations based on the coefficients of the error equation, where the target number is consistent with the number of bits of the target vector.

[0030] S104: Grouping the constructed verification equations, and solving each group of verification equations using the same set of summation modules to obtain error position data.

[0031] Each summing module in the same group of summing modules includes a modular multiplier and a modular adder.

[0032] S105: Correct the target data according to the error position data to obtain an error correction result.

[0033] The target data and check digits need to be generated using a BCH code encoding module. The implementation method of generating target data and check digits by BCH encoding is an existing method in the prior art and will not be described in detail here.

[0034] Assume that the number of bits of the target data is n bits, the number of parity bits is r bits, and they are spliced together to generate a target vector of n + r bits. Correspondingly, there are also n + r parity equations.

[0035] This application can use shortened or unshortened BCH codes. Assume the total codeword length N, the maximum number of bits that can be corrected t, the number of parity bits r, and the number of data bits to be decoded n, where n <= N - r. When n < N - r, it is a shortened BCH code. In this case, it can be padded with 0s at the high positions to make it N - r bits and the above error correction method can be implemented.

[0036] As Figure 2 shown in the circuit structure diagram, data_dcd_i represents the target data, and parity_dcd_i represents the parity bit data; the target vector is input into the syndrome generation module to obtain t syndromes S1, S3,... S 2t-1 .

[0037] If the values of all syndromes are 0, it means there is no error. The state machine outputs a high-level signal at the dcd_done pin and outputs the error correction result including the decoded data data_dcd_o and the parity bit data parity_dcd_o. Among them, data_dcd_o = data_dcd_i and parity_dcd_o = parity_dcd_i.

[0038] If the calculated syndromes are not all 0, it means there are data errors and error correction is required.

[0039] In one embodiment, the following formula can be used to determine each syndrome:

[0040]

[0041] Among them, S represents each syndrome; d represents the target vector; represents the parity check matrix;

[0042] The parity check matrix is:

[0043]

[0044] Among them, H represents the parity check matrix; represents the elements in, m is a preset parameter; t represents the number of syndromes; n represents the number of bits of the target data; r represents the number of bits of the parity bit data.

[0045] GF (Galois Field) is a set containing a finite number of elements, and these elements are closed under addition and multiplication operations. Specifically, is a finite field, and the elements are polynomials in this set. The results of addition and multiplication operations in this set are also in this set.

[0046] Specifically, in the H matrix, any It can be represented as an m-dimensional vector, where i can be any integer from 0 to (2t-1)(n+r-1). Replace each element of H with its corresponding The m-dimensional vector on the field and expressed in column form can obtain the transposed matrix of the binary check matrix, which has a total of mt columns, n+r rows, and each column is a column vector.

[0047] Then the syndrome is equal to the target vector d multiplied by the transpose of the check matrix H: The obtained S is a vector of mt dimensions, consisting of t syndromes: S=[S1, S3, ... S 2t-1 ], where each syndrome is An m-dimensional vector over the field.

[0048] According to the above principle, the column vectors composed of the column elements in the transposed matrix of the check matrix can be determined; for each column vector, a syndrome element is determined according to the column vector and the target vector; and each syndrome is generated based on the determined syndrome element.

[0049] Furthermore, different column vectors can be stored in different branches of the parallel circuit. The hardware can be used as follows Figure 3 The circuit structure shown calculates the syndrome S. Modular addition of binary elements is essentially an exclusive-OR operation. A0, A1, A2, ..., and A(mt-1) are column vectors consisting of the elements in the 1st, 2nd, 3rd, ... columns of the transposed parity check matrix, respectively. This allows for parallel computation of these column vectors.

[0050] Multiply the input n+r-bit vector d and the corresponding elements in A0 one by one, and then perform bit-wise XOR. This is equivalent to using {data_dcd_i, parity_dcd_i} in the figure and A[0] to perform the operation. The result is the lowest-order element S[0] of the syndrome. Similarly, according to this method, the target vector and A1 are subjected to the above operation to obtain S[1]. Similar calculations are performed on S[2], S[3]... until S[mt-1]. The target vector and A2 are subjected to the above operation to obtain S[2]. There are a total of mt such circuits, corresponding to a set of syndromes S with an output of mt bits.

[0051] Specifically, the error equation can be generated according to the following formula :

[0052]

[0053] in, 、 、 、……、 are the coefficients of the error equation, and v represents the number of error correction bits. The coefficients of the error equation are determined according to the syndromes.

[0054] Among them, for domain, the maximum correctable number of bits t is ( ) / 2 is a positive number rounded down, v<=t.

[0055] like Figure 2 As shown, the syndrome generation module gives the syndrome to the error equation generation module, and the error equation generation module calculates the error equation The coefficients of .

[0056] The error equation generation module only involves modular multiplication and modular addition operations. This part of the circuit is all combinational logic, which can calculate the coefficients within one clock cycle and send them to the front search module. And since the column vector is based on Figure 3 The circuits can be calculated separately and simultaneously without going through any sequential circuits, so they can be completed within one clock cycle, greatly saving decoding time.

[0057] The relationship between and the syndrome S is given by the following Newton identity:

[0058]

[0059]

[0060] The Qian search module applies Peterson decoding theory and constructs n+r check equations according to the coefficients of the error equation, corresponding to the n+r bits of decoded data and check bit data that need to be corrected.

[0061] After the check equations are grouped, each group of check equations is input into the same set of summation modules checksum_0, checksum_1, checksum_2, ..., checksum_u-1 for solution, reducing the area of the BCH error correction circuit through multiplexing.

[0062] During the operation of the money search module, the state machine controls the operation state and controls the high level signal output by the dcd_done pin after the operation is completed.

[0063] In the solution provided by an embodiment of the present invention, each syndrome corresponding to the target vector is determined based on the target vector of the target data and a preset check matrix. The syndrome can be used to determine whether a data error exists. If so, the syndrome is used to generate an error equation, and then a check equation is constructed based on the error equation to obtain error position data, thereby determining the error position and performing error correction.

[0064] In the process of solving the check equations, the check equations are grouped and solved by reusing the same set of summing modules. In this way, there is no need to design a separate summing module and corresponding circuit for each check equation. By reusing the modular multipliers and modular adders in the summing modules, the area of the BCH error correction circuit can be greatly reduced, thereby improving resource utilization efficiency.

[0065] And if no error is detected, the calculation based on the syndrome can give data in a shorter time. If error correction is required, the correct result can also be given within fewer clock cycles.

[0066] The following describes the calculation process using the calibration equation.

[0067] In one embodiment, among the target number of verification equations, the i-th verification equation is constructed as:

[0068]

[0069] in, 、 、 、……、 is the coefficient of the error equation, v represents the number of error correction bits; express Chinese elements.

[0070] For any bit i, the corresponding check equation is the sum of multiple additions, that is, the checksum. If the value of the checksum is It is 0, indicating that the Ni-th bit is wrong, N represents the code length, otherwise it is 1.

[0071] Each check equation requires v modular multiplications and modular additions. When the number of bits n+r requiring error correction is relatively large, the computational effort is also considerable. If implemented entirely using combinational logic, the circuit size occupied would be relatively large. Therefore, the solution provided in the embodiments of the present invention groups the check equations, reuses modular multipliers and modular adders, performs one calculation per clock cycle, and completes the calculation of all check equations over several clock cycles. This significantly reduces the number of modular multipliers and modular adders, thereby reducing circuit size and area. Although this adds several clock cycles, as mentioned above, in most practical applications, error correction is not required; only error detection is required. Error detection can be completed within a single clock cycle using the syndrome generation module described above, so the performance loss is minimal.

[0072] like Figure 2 As shown in , checksum_0, checksum_1, checksum_2, ..., checksum_u-1 are a group of summation modules, which contain a total of u summation modules. Figure 4 As shown, each checksum module includes a modular multiplier and a modular adder, and the modular adder is represented by the symbol "+".

[0073] In addition, each summing module may also include a register;

[0074] For each summing module, a target calibration equation to be solved is selected from each set of calibration equations by a first selection signal; the target calibration equation is solved using the summing module in the following manner:

[0075] For the nth modular multiplication calculation included in the target verification equation, the modular multiplier included in the summation module is used to obtain an intermediate calculation result, and the intermediate calculation result is subjected to modular addition calculation with the modular addition calculation result stored in the register to obtain the nth modular addition calculation result, and the modular addition calculation result stored in the register is updated using the nth modular addition calculation result;

[0076] After completing all modular multiplication calculations contained in the target verification equation, the solution result of the target verification equation is obtained from the register, that is, Figure 4 in error_map.

[0077] exist Figure 4In [1], group_select indicates the first selection signal used to select a group of checksum equations as the target checksum equations for calculation. Each time a group of u checksum equations is selected, different summation modules determine the target checksum equation based on the order in which the checksum equations are arranged. For example, for the summation module checksum_0, the first checksum equation in each group of u checksum equations is selected as the target checksum equation; for the summation module checksum_1, the second checksum equation in each group of u checksum equations is selected as the target checksum equation, and so on.

[0078] According to the above method, starting from n=1, after the result of the nth operation is stored in the register, if there is an n+1th modular multiplication calculation, the intermediate result of the n+1th modular multiplication calculation is obtained, and then the modular addition calculation is performed with the previous calculation result in the register to overwrite the calculation result previously stored in the register. And so on. After all modular multiplication calculations are completed, the register contains the sum of all modular multiplication calculation results.

[0079] The specific value of u is adjusted based on the size of the check equation grouping. For example, if four check equations are grouped together, u can be set to four summation modules. This allows flexible configuration of the number of modular multipliers and modular adders and the number of clock cycles based on the actual application scenario during chip design, allowing the optimal solution to be selected while balancing area and performance.

[0080] Assume that n+r check equations are divided into w groups, each group contains u equations. The first calculation is for the first u equations, the second calculation is for the u+1th to 2uth equations, and so on.

[0081] exist Figure 4 In the example, after the group_select signal selects the group of the check equation, the ckst signal is used to select a modular multiplication calculation in the check equation.

[0082] For example, select α(i) and transmit it to the error equation generation module 1 is sent to the modular multiplier, the result is XORed with the result of the previous modular multiplication, and then stored in the register, and then α (2i) and 2. Perform modular multiplication, XOR the result of modular multiplication with the result stored in the register and store it in the register, continue to overwrite the previous XOR calculation result until α (vi) and The modular multiplication of v is performed, and the modular multiplication result is XORed with the XOR result in the register to obtain a solution to the verification equation.

[0083] Figure 4 α(i), α(2i)…α(vi) are equivalent to the above-mentioned ith verification equation 、 、…… σ1, σ2, ... σv are equivalent to 、 、 、……、 .

[0084] The group_select signal is then used to select the target calibration equation for the next set of calibration equations. The elements of the next target calibration equation are α(i+u), α(2(i+u)), and so on. The calculation method is similar to the above α(i), α(2i), and so on. This continues until the last set of target calibration equations is calculated.

[0085] Repeat this process v times to complete the calculation of a verification equation.

[0086] Each summation module repeats the above process for a total of w times, and finally obtains the error_map containing the error position, that is, the error position data.

[0087] Because of the w groups, the Qian search module requires vw clock cycles to complete a search for an error location, where v is the number of error correction bits. For example, correcting two bits in four groups requires 2*4=8 clock cycles, and the number of modular multipliers and modular adders required is only 1 / 8 the original number, significantly optimizing the Qian search module's circuit area. This method allows for the freedom to choose different grouping methods based on actual needs. For example, if performance requirements are high and there are many check equations, the number of u groups can be increased, reducing the number of groups. This allows multiple check equations to be solved simultaneously within the same clock cycle, reducing the number of clock cycles required for calculation. Alternatively, if area requirements are high, the number of modular multipliers and modular adders can be reduced by increasing the number of groups.

[0088] It can be seen from the above embodiment that the n+r check equations respectively correspond to the n+r bit positions that need to be corrected.

[0089] In this way, for each bit, the value of the check equation can be obtained, so that the sequence of n+r bit positions forms a corresponding checksum sequence, where the position where 0 is located represents the error position.

[0090] In this case, a checksum sequence representing the error position in the error position data may be obtained; an inverted result of the checksum sequence is XORed with the target data to obtain an error correction result.

[0091] That is, the checksum sequence is first inverted, that is, 0 at any position is replaced by 1, and 1 is replaced by 0. The inverted result is XORed with the target data to obtain the error-corrected data.

[0092] The following instructions Figure 5 The embodiment shown illustrates the control process of the state machine in the aforementioned embodiment.

[0093] A state machine is used to control the calculation process of the money search module and output the signal dcd_done indicating that decoding is completed.

[0094] First, the state machine generates a flag signal error_flag based on the syndrome S given by the syndrome generation module. If all of the syndrome S is equal to 0, it means no error is detected, and error_flag = 0; otherwise, error_flag = 1.

[0095] The number of states of the state machine is equal to the number w of grouped check equations. Among the w states, different states represent different groups of check equations selected from the w groups of check equations. In Figure 5 it, the ckst signal is used to control how many times the modular multiplication operation is being performed in each summation module in the current group, and it automatically increments by 1 every cycle.

[0096] Taking w = 4 as an example, its state transition diagram is as Figure 5 shown. When error_flag is equal to 0, no error correction is required and the state machine does not make any jumps. If error_flag is not equal to 0, ckst starts counting, and the money search module starts calculating the first group of check equations. When ckst reaches the number v of modular multiplications in the check equation, ckst < v does not hold. At this time, when the conditions ckst = v and error_flag = 1 are satisfied, the state machine jumps from Group1 (idle, idle state) to Group2, calculates the second group of check equations, and at the same time the money search module starts calculating the second group of check equations. This process continues in sequence. In Group2, Group3, and Group4, ckst < v means that not all the modular multiplications have been performed, and when ckst = v, it jumps to the next state.

[0097] Until the calculation of the last group is completed, the state machine returns to the initial Group1 state, and at the same time outputs the fsm_done signal indicating that the calculation is completed.

[0098] The output of the signal dcd_done indicating that decoding is completed can be implemented via the following logic circuit, as Figure 6 .

[0099] When the signal dcd_en indicating the start of decoding is 1, if the flag signal error_flag generated based on the syndrome s[0]... s[mt - 1] is equal to 0, that is, there is no error, then dcd_done directly outputs 1, indicating that decoding is completed. If error_flag is not equal to 0, then after the money search module finishes the calculation and fsm_done outputs​In one embodiment of the present invention, a computer-readable storage medium is provided, on which a computer program is stored. When the computer program is executed by a processor, the data error correction method based on BCH coding described above is implemented.

[0101] In one embodiment of the present invention, an integrated chip is provided. A circuit is integrated on the chip, and the circuit is used to execute any of the aforementioned BCH coding-based data error correction methods.

[0102] The BCH circuits designed in the aforementioned embodiments are suitable for use in high-bandwidth, multi-bit error correction, and small-area semiconductor chips, especially in embedded system MCUs that have relatively high requirements for information reliability.

[0103] It should be noted that the logic and / or steps represented in the flowcharts or otherwise described herein, for example, can be considered as a sequenced list of executable instructions for implementing the logical functions, and can be embodied in any computer-readable medium for use by, or in conjunction with, an instruction execution system, apparatus, or device (e.g., a computer-based system, a system including a processor, or other system that can fetch and execute instructions from an instruction execution system, apparatus, or device). For purposes of this specification, a "computer-readable medium" can be any device that can contain, store, communicate, propagate, or transport a program for use by, or in conjunction with, an instruction execution system, apparatus, or device. More specific examples (non-exhaustive list) of computer-readable media include the following: an electrical connection with one or more wires (electronic device), a portable computer disk cartridge (magnetic device), random access memory (RAM), read-only memory (ROM), erasable and programmable read-only memory (EPROM or flash memory), fiber optic devices, and a portable compact disc read-only memory (CDROM). Furthermore, the computer-readable medium may even be paper or other suitable medium on which the program is printed, since the program may be obtained electronically, for example, by optically scanning the paper or other medium and then editing, interpreting or processing it in another suitable manner if necessary, and then storing it in a computer memory.

[0104] It should be understood that various components of the present invention may be implemented using hardware, software, firmware, or a combination thereof. In the above-described embodiments, multiple steps or methods may be implemented using software or firmware stored in a memory and executed by a suitable instruction execution system. For example, if implemented using hardware, as in another embodiment, any one of the following technologies known in the art or a combination thereof may be used: a discrete logic circuit having logic gate circuits for implementing logic functions on data signals, an application-specific integrated circuit having suitable combinational logic gate circuits, a programmable gate array (PGA), a field-programmable gate array (FPGA), etc.

[0105] Throughout this specification, reference to terms such as "one embodiment," "some embodiments," "examples," "specific examples," or "some examples" means that a specific feature, structure, material, or characteristic described in conjunction with that embodiment or example is included in at least one embodiment or example of the present invention. In this specification, schematic representations of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples.

[0106] In the description of the present invention, it should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", "clockwise", "counterclockwise", "axial", "radial", "circumferential" and the like to indicate orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as limiting the present invention.

[0107] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of the technical features being referred to. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one such feature. In the description of the present invention, "plurality" means at least two, such as two, three, etc., unless otherwise specifically defined.

[0108] In the present invention, unless otherwise specified or limited, the terms "installed," "connected," "connect," "fixed," etc. should be understood in a broad sense. For example, they can refer to fixed connection, detachable connection, or integration; mechanical connection, electrical connection; direct connection, or indirect connection through an intermediate medium; internal communication between two components, or interaction between two components, unless otherwise specified. Those skilled in the art will understand the specific meanings of the above terms in the present invention based on specific circumstances.

[0109] In the present invention, unless otherwise expressly specified or limited, when a first feature is "above" or "below" a second feature, it may mean that the first and second features are in direct contact, or that the first and second features are in indirect contact through an intermediary. Furthermore, when a first feature is "above," "above," or "above" a second feature, it may mean that the first feature is directly above or diagonally above the second feature, or simply means that the first feature is at a higher level than the second feature. When a first feature is "below," "below," or "below" a second feature, it may mean that the first feature is directly below or diagonally below the second feature, or simply means that the first feature is at a lower level than the second feature.

[0110] Although the embodiments of the present invention have been shown and described above, it will be understood that the above embodiments are exemplary and are not to be construed as limitations on the present invention. A person skilled in the art may change, modify, replace and modify the above embodiments within the scope of the present invention.

Claims

1. A data error correction method based on BCH coding, characterized in that: The method comprises: Obtain target data obtained by BCH encoding, and determine syndromes corresponding to the target vector based on a target vector of the target data and a preset check matrix; wherein the target vector is obtained by concatenating the target data and check bit data corresponding to the target data; If there is a syndrome indicating data error among the determined syndromes, an error equation is generated according to the syndromes; Constructing a target number of check equations based on coefficients of the error equation, where the target number is consistent with the number of bits of the target vector; The constructed verification equations are grouped and each group of verification equations is solved using the same set of reusable summing modules to obtain error position data; wherein each summing module in the same set of summing modules includes a modular multiplier and a modular adder; Correct the target data according to the error position data to obtain an error correction result; Wherein, each summing module further comprises a register; For the reusable summation module, a set of target calibration equations to be solved is selected from the plurality of calibration equations through a first selection signal; The target verification equation is solved using the summation module in the following manner: For the nth modular multiplication calculation included in the target verification equation, an intermediate calculation result is obtained using the modular multiplier included in the summation module, and the intermediate calculation result is subjected to modular addition calculation with the modular addition calculation result stored in the register to obtain an nth modular addition operation result, and the nth modular addition calculation result is used to update the modular addition calculation result stored in the register; After completing all modular multiplication calculations included in the target verification equation, obtaining a solution result of solving the target verification equation from a register; The method further comprises: Use the money search module to construct each group of verification equations; The state machine is used to control the calculation process of the money search module and output the decoding completion signal; The number of states of the state machine is equal to the number of groups of verification equations. Different states indicate that different groups of verification equations are selected. The method further comprises: If the values of the syndromes are all 0, the state machine outputs a decoding completion signal and outputs the error correction result within one clock cycle.

2. The method according to claim 1, characterized in that The determining, based on the target vector of the target data and a preset check matrix, syndromes corresponding to the target vector includes: Determine each syndrome according to the following formula: Wherein, S represents each syndrome; d represents the target vector; represents the check matrix; The check matrix is: Where H represents the check matrix; express In the element, m is a preset parameter; t represents the number of syndromes; n represents the number of bits of the target data; and r represents the number of bits of the check bit data.

3. The method according to claim 2, characterized in that Determine the syndromes as follows: Determine a column vector composed of column elements in a transposed matrix of the check matrix; For each column vector, determining a syndrome element according to the column vector and the target vector; Syndromes are generated based on the determined syndrome elements.

4. The method according to claim 3, characterized in that Different column vectors are stored in different branches of the parallel circuit.

5. The method according to claim 1, wherein The error equation is generated as follows: : in, ...、 are the coefficients of the error equation, and v represents the number of error correction bits; the coefficients of the error equation are determined according to each syndrome.

6. The method according to claim 5, characterized in that Among the target number of verification equations, the i-th verification equation is constructed as: in, ...、 is the coefficient of the error equation, v represents the number of error correction bits; express Chinese elements.

7. The method according to claim 1, characterized in that Correcting the target data according to the error position data to obtain an error correction result includes: obtaining a checksum sequence representing an error position in the error position data; An XOR calculation is performed on the inverted result of the checksum sequence and the target data to obtain an error correction result.

8. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the data error correction method based on BCH coding according to any one of claims 1 to 7 is implemented.

9. An integrated chip, characterized in that: A circuit is integrated on the chip, and the circuit is used to execute the data error correction method based on BCH coding according to any one of claims 1 to 7.

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