Processing method, chip, device, system, electronic equipment and storage medium
By setting the cache area in the processor and updating the label signal, determining the type and order of access requests, it solves the problem of read-write access conflicts that may occur in the recovery state of the processor, ensuring data accuracy and improving program execution accuracy sex.
Patent Information
- Application Number
- CN202411243693.7
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-09-05
- Publication Date
- 2025-02-18
AI Technical Summary
After the processor returns to the working state of the previous period, there may be a read-write-retrieval conflict, causing the processor to read incorrect data and execute the wrong program.
By setting a cache area in the processor, the first annotation signal and the second annotation signal are updated to determine the type of access requests, and the order of read requests and write requests is determined according to the update order of these signals to avoid read-after writing Inspect conflicts.
Ensure that the data read by the processor is accurate, solves the problem of read-after-write memory access conflicts, and improves the accuracy of the processor executing programs.
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Figure CN119473707A_ABST
Abstract
Description
Technical Field
[0001] The present application relates to the field of processor technology, and more specifically, to a fault handling method, a chip, a fault handling device, a fault-tolerant system, an electronic device, and a computer-readable storage medium. Background Art
[0002] In the related art, a checkpoint backup and recovery mechanism based on a processor pipeline memory stack can enable the processor to quickly recover to the working state of the previous time period in a short period of time.
[0003] However, after the processor is restored to the working state of the previous time period, a read-after-write memory access conflict may occur, which may cause the processor to read wrong data in the memory, thereby causing the processor to execute an incorrect program. Summary of the invention
[0004] Embodiments of the present application provide a fault handling method, a chip, a fault handling device, a fault-tolerant system, an electronic device, and a computer-readable storage medium.
[0005] In a fault handling method provided by an embodiment of the present application, the processor is provided with a corresponding cache area, and when the processor reads data from the memory, the cache area is configured to update a first marking signal, and when the processor writes data to the memory, the cache area is configured to update a second marking signal. The method includes: at a first moment of switching from a first time period to a second time period, obtaining a first access request executed by the processor on the memory in the first time period, the processor is in a first state in the first time period, and the processor is in a second state in the second time period, and the second state is different from the first state; determining a read request executed by the first access request according to the first marking signal, determining a write request executed by the first access request according to the second marking signal, and determining a sequence of executing the read request and the write request by the first access request according to an update sequence of the first marking signal and the second marking signal; in a case where the first access request executes the read request first and then executes the write request, reading first data, the first data being the first data read by the processor in the first time period, so that the processor executes the read request of the first access request again, the first data being the data read by the processor in the first time period.
[0006] In this way, by setting the cache area, the read request and the write request executed by the processor in the first time period can be obtained, and then it can be determined whether the processor has a read-after-write memory access conflict. In the case where it is determined that the risk of the processor having a read-after-write memory access conflict is high, the processor can read the first data, and the first data is set to be the first data read by the processor in the first time period, ensuring that the data read by the processor is accurate, solving the technical problem of the read-after-write memory access conflict occurring in the processor, and improving the accuracy of the processor executing the program.
[0007] In some embodiments, after obtaining the first access request, the method includes: obtaining a second access request, the second access request being the first access request executed by the processor on the memory within the second time period; when the first access request is to execute a read request first and then a write request, and the second access request is a read request, reading the first data so that the processor executes the read request of the first access request again.
[0008] In this way, when it is determined that the processor has a high risk of a read-after-write memory access conflict and the first access request executed by the processor is a read request, the processor can read the first data to ensure that the data read by the processor is accurate.
[0009] In some embodiments, the method includes executing the second access request if the first access request does not include a read request or a write request.
[0010] In this way, when it is determined that the processor does not have the risk of read-after-write memory access conflict, or the risk of read-after-write memory access conflict is low, the processor can access the memory normally, thereby improving the access efficiency of the processor.
[0011] In some embodiments, the method includes: executing the second access request when the first access request is to execute a write request first and then a read request.
[0012] In this way, when it is determined that the processor does not have the risk of read-after-write memory access conflict, or the risk of read-after-write memory access conflict is low, the processor can access the memory normally, thereby improving the access efficiency of the processor.
[0013] In some embodiments, the method includes: executing the second access request if the second access request is not a read request.
[0014] In this way, when it is determined that there is no risk of the processor reading erroneous data, the processor can access the memory normally, thereby improving the access efficiency of the processor.
[0015] In some embodiments, when the processor reads data from the memory, the cache area is configured to update first cache data, where the first cache data is determined by data read by the processor from the memory, and the reading of the first data includes: at the first moment, reading the first cache data to read the first data.
[0016] In this way, the data read from the memory by the processor in the first period of time can be obtained by setting the cache area.
[0017] In some embodiments, after obtaining the first access request, the method includes: obtaining a second access request, the second access request being the first access request executed by the processor on the memory within the second time period; when the first access request is to execute a read request first and then a write request, and the second access request is a read request, obtaining a first address and a second address, the first address being the address for reading data by the first access request, and the second address being the address for reading data by the second access request; when the first address is consistent with the second address, reading the first data so that the processor executes the read request of the first access request again.
[0018] In this way, when it is determined that the first address is consistent with the second address, reading the first data can enable the processor to read correct data.
[0019] In some embodiments, the method includes: executing the second access request when the first address is inconsistent with the second address.
[0020] In this way, when it is determined that the read address of the second access request has not been executed before the processor executes the recovery mechanism, the processor can access the memory normally, thereby improving the access efficiency of the processor.
[0021] In certain embodiments, when the processor reads data from the memory, the processor is provided with a corresponding cache area, and the cache area is configured to update a first cache address, where the first cache address is determined based on the address at which the processor reads data from the memory, and obtaining the first address includes: at the first moment, reading the first cache address to read the first address.
[0022] In this way, the address at which the processor reads data from the memory during the first period of time can be obtained by setting the cache area.
[0023] In certain embodiments, when the processor writes data to the memory, the cache area is configured to update second cache data and a second cache address, wherein the second cache data is determined based on the data written by the processor to the memory, and the second cache address is determined based on the address written by the processor to the memory.
[0024] In this way, by setting the cache area, the data written by the processor to the memory during the second period and the address of the written data can be obtained.
[0025] In some embodiments, the cache area includes a first sub-cache area and a second sub-cache area, the first sub-cache area is configured to update the first cache data and the first cache address, or update the second cache data and the second cache address. The second sub-cache area is configured to update the first cache data and the first cache address, or update the second cache data and the second cache address.
[0026] In some embodiments, the cache area updates the first cache address or the second cache address, including: when the processor reads data from the memory, compressing the address of the data read to obtain a first update address, so that the first update address is updated to the first cache address, and the number of bits of the first update address is smaller than the number of bits of the first cache address; or when the processor writes data to the memory, compressing the address of the data written to obtain a second update address, so that the second update address is updated to the second cache address, and the number of bits of the second update address is smaller than the number of bits of the second cache address.
[0027] In this way, the cache area can save storage space and improve work efficiency.
[0028] In some embodiments, compressing the address for data reading to obtain a first update address, or compressing the address for data writing to obtain a second update address includes: performing bit truncation processing on the address for data reading to obtain the first update address, or performing bit truncation processing on the address for data writing to obtain the second update address.
[0029] In this way, by performing bit truncation processing on the address for reading data or the address for writing data, the cache area can save storage space and improve work efficiency.
[0030] In some embodiments, compressing the address for data reading to obtain a first update address, or compressing the address for data writing to obtain a second update address includes: determining the first update address based on a specific mapping relationship and the address for data reading, or determining the second update address based on a specific mapping relationship and the address for data writing.
[0031] In this way, by performing address mapping on the address for reading data or the address for writing data, the cache area can save storage space and improve work efficiency.
[0032] In some embodiments, compressing the address of data reading to obtain a first update address, or compressing the address of data writing to obtain a second update address includes: processing the address of data reading by a sampling encoding method to determine the first update address, or processing the address of data reading by a sampling encoding method to determine the second update address.
[0033] In this way, by performing address encoding on the address for reading data or the address for writing data, the cache area can save storage space and improve work efficiency.
[0034] In some embodiments, the first state is a fault state of the processor, and the second state is a normal state of the processor.
[0035] In this way, the fault handling method of the embodiment of the present application can be used in the fault recovery mechanism executed by the processor to ensure that the processor can read the correct data before modification in the memory when re-executing the program after the pipeline recovery error.
[0036] An embodiment of the present application provides a chip, the chip includes a processor, and the processor is used to execute the fault handling method of the above embodiment.
[0037] In some embodiments, the processor is correspondingly provided with a cache area and a memory. When the processor reads data from the memory, the cache area is configured to update a first marking signal, a first cache address, and a first cache data, wherein the first cache address is determined according to an address from which the processor reads data from the memory, and the first cache data is determined by data from which the processor reads data from the memory; when the processor writes data to the memory, the cache area is configured to update a second marking signal, a second cache address, and a second cache data, wherein the second cache address is determined according to an address from which the processor writes data to the memory, and the second cache data is determined by data from which the processor writes data to the memory.
[0038] The embodiment of the present application provides a fault handling device, including an acquisition module and a reading module. The acquisition module is configured to acquire a first access request executed by the processor to the memory in the first time period at the first moment of switching from the first time period to the second time period, the processor is in a first state in the first time period, and the processor is in a second state in the second time period, and the second state is different from the first state. The acquisition module is also configured to determine the read request executed by the first access request according to the first marking signal, determine the write request executed by the first access request according to the second marking signal, and determine the order of the first access request to execute the read request and the write request according to the update order of the first marking signal and the second marking signal. The reading module is configured to read the first data in the case where the first access request includes a read request and a write request, so that the processor executes the first access request again, and the first data is the data read by the processor in the first time period.
[0039] In some embodiments, the acquisition module is further configured to acquire a second access request, where the second access request is the first access request executed by the processor on the memory within the second time period, and the reading module is further configured to read the first data when the first access request is a read request followed by a write request, and the second access request is a read request.
[0040] In some embodiments, the acquisition module is configured to acquire a second access request, where the second access request is the first access request executed by the processor to the memory within the second time period. The acquisition module is configured to acquire a first address and a second address when the first access request is to execute a read request first and then a write request, and the second access request is a read request, where the first address is an address for reading data with the first access request, and the second address is an address for reading data with the second access request. The reading module is configured to read the first data when the first address is consistent with the second address.
[0041] An embodiment of the present application provides a fault-tolerant system, comprising a fault handling device, a fault detection device and a fault recovery device of the above-mentioned embodiment, wherein the fault detection device is configured to determine that the processor is in a first state, and the fault recovery device is configured to determine that the processor switches from the first state to a second state.
[0042] An embodiment of the present application further provides an electronic device, which includes the fault-tolerant system of the above embodiment.
[0043] The embodiment of the present application further provides a computer-readable storage medium, wherein the computer-readable storage medium stores a computer program. When the computer program is executed by one or more processors, the processing method of the above embodiment is implemented.
[0044] The embodiment of the present application provides a fault handling method of a processor, a processor, a fault handling device, a fault-tolerant system, an electronic device, and a computer-readable storage medium. The processor is correspondingly provided with a cache area. When the processor reads data from the memory, the cache area is configured to update the first marking signal. When the processor writes data to the memory, the cache area is configured to update the second marking signal. The fault handling method includes: at the first moment of switching from the first time period to the second time period, obtaining the first access request executed by the processor to the memory in the first time period, the processor is in the first state in the first time period, and the processor is in the second state in the second time period, and the second state is different from the first state; determining the read request executed by the first access request according to the first marking signal; determining the write request executed by the first access request according to the second marking signal; determining the order of executing the read request and the write request of the first access request according to the update order of the first marking signal and the second marking signal; in the case where the first access request executes the read request first and then executes the write request, reading the first data, the first data is the first data read by the processor in the first time period, so that the processor executes the read request of the first access request again, and the first data is the data read by the processor in the first time period.
[0045] In this way, by setting the cache area, the read request and the write request executed by the processor in the first time period can be obtained, and then it can be determined whether the processor has a read-after-write memory access conflict. In the case where it is determined that the risk of the processor having a read-after-write memory access conflict is high, the processor can read the first data, and the first data is set to be the first data read by the processor in the first time period, ensuring that the data read by the processor is accurate, solving the technical problem of the read-after-write memory access conflict occurring in the processor, and improving the accuracy of the processor executing the program.
[0046] Additional aspects and advantages of the present application will be given in part in the description below, and in part will become apparent from the description below, or will be learned through the practice of the present application. BRIEF DESCRIPTION OF THE DRAWINGS
[0047] The above and / or additional aspects and advantages of the present application will become apparent and easily understood from the description of the embodiments in conjunction with the following drawings, in which:
[0048] Figure 1 It is a flowchart of a fault handling method of the first implementation mode of the present application;
[0049] Figure 2is a schematic diagram of a fault handling device and a fault-tolerant system according to an embodiment of the present application;
[0050] Figure 3 It is the first timing diagram of a pipeline processor in the related technical field;
[0051] Figure 4 is a second timing diagram of a pipeline processor in the related technical field;
[0052] Figure 5 is a schematic diagram of a cache area in an embodiment of the present application;
[0053] Figure 6 It is a flowchart of a fault handling method according to a second embodiment of the present application;
[0054] Figure 7 It is a flowchart of the fault handling method of the third embodiment of the present application. DETAILED DESCRIPTION
[0055] The embodiments of the present application are described in detail below, and the embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present application, and cannot be understood as limiting the present application.
[0056] In the related art, a checkpoint backup and recovery mechanism based on a processor pipeline memory stack can enable the processor to quickly recover to the working state of the previous time period in a short period of time.
[0057] However, after the processor is restored to the working state of the previous time period, a read-after-write memory access conflict may occur, which may cause the processor to read wrong data in the memory, thereby causing the processor to execute an incorrect program.
[0058] Reference Figure 1 , the present application embodiment provides a processor fault handling method, including:
[0059] 01: at a first moment when switching from the first time period to the second time period, obtaining a first access request executed by the processor on the memory in the first time period, the processor is in a first state in the first time period, and the processor is in a second state in the second time period, and the second state is different from the first state;
[0060] 02: determining a read request executed by the first access request according to the first marking signal, determining a write request executed by the first access request according to the second marking signal, and determining a sequence in which the read request and the write request are executed by the first access request according to an update sequence of the first marking signal and the second marking signal;
[0061] 03: When the first access request executes a read request first and then executes a write request, read the first data so that the processor executes the read request of the first access request again, and the first data is the data read by the processor in the first time period.
[0062] The embodiment of the present application also provides a chip, and the fault handling method of the embodiment of the present application can be implemented by the chip of the embodiment of the present application. The chip includes a processor, and the processor can obtain a first access request executed by the processor to the memory within a first time period, and when the first access request includes a read request and a write request, read the first data so that the processor executes the read request of the first access request again.
[0063] Reference Figure 2 The embodiment of the present application also provides a fault handling device 30, and the fault handling method of the embodiment of the present application can be implemented by the fault handling device 30 of the embodiment of the present application. Specifically, the fault handling device 30 includes an acquisition module 31 and a reading module 32. The acquisition module 31 can acquire the first access request executed by the processor 10 on the memory 20 in the first time period at the first moment of switching from the first time period to the second time period. The reading module 32 can read the first data when the first access request includes a read request and a write request. The acquisition module 32 can also determine the read request executed by the first access request according to the first marking signal, determine the write request executed by the first access request according to the second marking signal, and determine the order in which the first access request executes the read request and the write request according to the update order of the first marking signal and the second marking signal.
[0064] The embodiment of the present application also provides a fault-tolerant system. Specifically, the fault-tolerant system includes a fault handling device 30, a fault detection device 40 and a fault recovery device 50 of the embodiment of the present application, wherein the fault detection device 40 can determine that the processor 10 is in the first state, and the fault recovery device 50 can determine that the processor 10 switches from the first state to the second state.
[0065] After the fault detection device 40 determines that the processor 10 is in the first state, the fault recovery device 50 may execute a recovery mechanism of the processor 10. When the fault recovery device 50 determines that the processor 10 switches from the first state to the second state, the fault processing device 30 may obtain a first access request executed by the processor 10 on the memory 20 within the first time period, and read the first data when the first access request includes a read request and a write request.
[0066] Specifically, refer to Figure 3, clk_i can be set to the working cycle of processor 10, signal check_error can be set to the state detection signal of processor 10, and signal check_error_dd can be set to the state recovery signal of processor 10. retire_pc can be set to the retirement instruction of processor 10, and state can be set to the state of checkpoint backup. retire_pc_ff3 can be set to the retirement instruction after the execution recovery mechanism of processor 10, and state_ff3 can be set to the state of checkpoint backup after the execution recovery mechanism of processor 10.
[0067] The time when the signal check_error is pulled high can be set to time t1. When the signal check_error is at a rising edge, it is detected that the state of the processor 10 is in the first state, and before time t1, the processor 10 is in the second state. The time when the signal check_error_dd is at a rising edge can be set to time t2. When check_error_dd is at a rising edge, the processor 10 executes a recovery mechanism, and the processor 10 recovers to the second state before time t1.
[0068] At time t2, when check_error_dd is at a rising edge, the processor 10 executes a recovery mechanism, the state of the processor 10 is restored to the state at time t1, and the access request executed on the memory 20 between time t1 and time t2 is obtained. If the processor 10 writes erroneous data to the memory 20 between time t1 and time t2, the processor 10 may read the erroneous data after executing the recovery mechanism, resulting in a read-after-write memory access conflict.
[0069] Time t1 is after the third cycle, and due to the delay caused by the two-level synchronization of the signal check_error, time t2 is after the fifth cycle signal. At time t2, the processor 10 should recover to the state s1 after the retirement of the pc1 instruction and then re-execute the instruction pc2. Due to the delay of the signal check_error_dd, the processor 10 starts to execute the recovery mechanism after the fifth cycle, that is, recover to the state s1 of state_ff3 and then re-execute the retire_pc_ff3 instruction pc2.
[0070] Further, Figure 4For example, the instruction at pc2 can be used to read the data at address A of the memory 20, and the initial value at address A is old. The instruction at pc3 is to write to address A of the memory 20, and the value written is new. After the pc2 instruction is executed and submitted, if a fault occurs during the execution of the pc3 instruction by the processor 10, when the fault recovery module detects a soft error and sends a recovery signal, the processor 10 has already submitted the instruction pc3. Therefore, when the processor 10 jumps to the instruction pc2 after reset and re-executes, the data at address A in the memory 20 has been updated to new. When the A address is read again, the value read is no longer the data old during normal execution, but the new written in the last write operation, resulting in a read-after-write memory access conflict, which causes errors in subsequent program execution.
[0071] In step 01, time t2 can be set as the first time, time t1 to time t2 can be set as the first time period, and the time period after time t2 can be set as the second time period. The access request executed by the processor 10 to the memory 20 between time t1 and time t2 can be set as the first access request, that is, instruction pc2 and instruction pc3 can be the first access request.
[0072] In step 02, the processor 10 reads the cache area at time t2, and determines whether the first access request includes a read request according to the first marking signal, and determines whether the first access request includes a write request according to the second marking signal.
[0073] In step 03, due to the execution characteristics of the four-stage pipeline of the sequential processor 10, when executing a memory access instruction, it must wait for an external response signal before continuing to execute the next instruction. Therefore, at most only one write request will be initiated within the synchronization time of the fault detection signal of the processor 10, that is, instruction pc2 and instruction pc3 include at most one write request. If the processor 10 executes access requests to read data and write data to the memory 20 between time t1 and time t2, it can be considered that instruction pc2 executes a write request and instruction pc3 executes a read request, or instruction pc3 executes a write request and instruction pc2 executes a read request.
[0074] If instruction pc2 executes a write request and instruction pc3 executes a read request, since instruction pc2 is initiated before time t1, the write request executed by instruction pc2 is less likely to cause erroneous data to be written into memory 20, and the read request executed by instruction pc3 will not read erroneous data in memory 20. At this time, it can be considered that the risk of processor 10 having a read-after-write memory access conflict is low.
[0075] If instruction pc3 executes a write request and instruction pc2 executes a read request, since instruction pc3 is initiated after time t1, the write request executed by instruction pc3 may cause erroneous data to be written into memory 20, which in turn causes the processor 10 to re-execute instruction pc2 and the read request to read erroneous data in memory 20. At this time, it can be considered that the processor 10 has a high risk of read-after-write memory access conflict, and the first data can be read at this time.
[0076] The first data can be set as the data read from the memory 20 by the processor 10 between time t1 and time t2, and the first data can be set as the data read from the memory 20 by the instruction pc2. The processor 10 can read the first data, that is, the processor 10 re-executes the instruction pc2, implements the recovery mechanism of the processor 10, and ensures that the data read by the processor 10 is accurate, not erroneous data.
[0077] It can be understood that when it is determined that the processor 10 has a high risk of a read-after-write memory access conflict, the processor 10 can read the first data to ensure that the data read by the processor 10 is accurate, thereby solving the technical problem of the read-after-write memory access conflict occurring in the processor 10 and improving the accuracy of the processor 10 in executing the program.
[0078] In some implementations, the first data is the first data read by the processor 10 within a first time period.
[0079] Specifically, the first data can be set as the first data read from the memory 20 by the processor 10 between time t1 and time t2, which can ensure that the first data is submitted based on the submission initiated before time t1, thereby ensuring the accuracy of the first data.
[0080] In this way, the first data is set as the first data read by the processor 10 within the first time period, which can ensure the accuracy of the first data and further ensure that the data read by the processor 10 is accurate.
[0081] In some embodiments, the first state is a fault state of the processor 10 , and the second state is a normal state of the processor 10 .
[0082] Specifically, time t1 may be set as the time when a fault of the processor 10 is detected, and time t2 may be set as the time when the processor 10 executes a fault recovery mechanism.
[0083] In this way, the fault handling method of the embodiment of the present application can be used in the fault recovery mechanism executed by the processor 10 to ensure that the processor 10 can read the correct data before modification in the memory 20 when re-executing the program after the pipeline recovery error.
[0084] Reference Figure 5In some embodiments, the processor 10 is provided with a corresponding cache area. When the processor 10 reads data from the memory 20, the cache area is configured to update the first marking signal. When the processor 10 writes data to the memory 20, the cache area is configured to update the second marking signal.
[0085] In some embodiments, at a first moment, the processor 10 may obtain a first marking signal and a second marking signal, and determine whether the first access request includes a read request according to the first marking signal, and determine whether the first access request includes a write request according to the second marking signal.
[0086] In some embodiments, the fault handling device 30 may receive a first marking signal and a second marking signal, and determine whether the first access request includes a read request according to the first marking signal, and determine whether the first access request includes a write request according to the second marking signal.
[0087] Specifically, by setting a cache area, the cache area can record the access request initiated by the processor 10 to the memory 20, while ensuring that the normal access of the processor 10 to the memory 20 is not affected. When the processor 10 is working, the processor 10 will send an access request to the cache area while initiating an access request to the memory 20.
[0088] The cache area may be provided with a corresponding read / write flag to indicate whether the access request is a read request or a write request. The first marking signal may indicate that the access request is a read request, and the first marking signal will be updated when the processor 10 reads data from the memory 20. The second marking signal may indicate that the access request is a write request, and the second marking signal will be updated when the processor 10 writes data to the memory 20.
[0089] The processor 10 reads the cache area at time t2, and determines whether the first access request includes a read request according to the first marking signal, and determines whether the first access request includes a write request according to the second marking signal.
[0090] In this way, by setting the cache area, the read request and the write request executed by the processor 10 in the first time period can be obtained.
[0091] Further, in some implementations, obtaining the first access request includes: determining a sequence in which the first access request executes a read request and a write request according to an update sequence of the first marking signal and the second marking signal.
[0092] In some implementations, the processor 10 may determine the order in which the first access request executes the read request and the write request according to the update order of the first marking signal and the second marking signal.
[0093] In some implementations, the fault handling device 30 may determine the order in which the first access request executes the read request and the write request according to the update order of the first marking signal and the second marking signal.
[0094] Specifically, an instruction sequence flag may be set in the cache area, and the update sequence of the first marking signal and the second marking signal may be determined according to the instruction sequence flag, thereby determining the sequence in which the first access request executes the read request and the write request.
[0095] For example, according to the type of access request, the first marking signal corresponding to the read request can be set to 0, and the second marking signal corresponding to the write request can be set to 1. According to the update order of the instructions, the instruction sequence flag of the access request most recently loaded into the cache is set to 0, and the instruction sequence flag of the access request previously loaded into the cache is set to 1.
[0096] The instruction sequence flag works in combination with the first marking signal and the second marking signal so that the processor 10 determines whether there is a risk of a read-after-write conflict at time t2 when the recovery mechanism is executed. When the XOR operation of the marking signal and the instruction sequence flag is 1, it indicates that there is a risk of a read-after-write conflict, that is, when the marking signal and the instruction sequence flag must satisfy 01, 10, it indicates that there is a risk of a read-after-write conflict.
[0097] When the processor 10 initiates an access request to the memory 20, it also sends an access request to the cache. Each time an access request is loaded into the cache, the instruction sequence flag of the previous access request is set to 1, and the instruction sequence flag of the updated access request is set to 0, indicating that it is a request for this round of update. At the same time, according to the request type, the read and write flag is set, set to 0 for read requests and to 1 for write requests.
[0098] After executing the recovery mechanism, the processor 10 determines whether the read-write flag and the instruction sequence flag in the cache area constitute read-after-write. If the XOR of the read-write flag and the instruction sequence flag sequence is 1, it indicates that read-after-write is constituted, otherwise it does not constitute read-after-write. In the cache area, the read-write flag and the instruction sequence flag can both be set to one byte to save storage space in the cache area.
[0099] In this way, according to the update sequence of the first marking signal and the second marking signal, it can be quickly determined whether the processor 10 has a risk of read-after-write memory access conflict, thereby improving the operating efficiency of the processor 10.
[0100] In some embodiments, when the processor 10 reads data from the memory 20, the cache area is configured to update the first cache data, and the first cache data is determined by the data read by the processor 10 from the memory 20. Reading the first data includes: at a first moment, reading the first cache data to read the first data.
[0101] In some embodiments, when the processor 10 reads data from the memory 20, the cache area is configured to update first cache data, where the first cache data is determined by data read by the processor 10 from the memory 20, and reading the first data includes: reading the first cache data at a first moment to read the first data.
[0102] In some embodiments, the fault handling device 30 can be configured to update the first cache data in the cache area when the processor 10 reads data from the memory 20. The first cache data is determined by the data read by the processor 10 from the memory 20. Reading the first data includes: reading the first cache data at a first moment to read the first data.
[0103] Specifically, the cache area is provided with a corresponding data storage space Buffer1 to store the first cache data. When the processor 10 initiates an access request to the memory 20, it also sends an access request to the cache area. Each time a read request is loaded into the cache area, the read data corresponding to the read request is also loaded into the data storage space Buffer1 to update the first cache data.
[0104] The first data can be set as the data read from the memory 20 by the processor 10 between time t1 and time t2. The data read from the memory 20 by the processor 10 between time t1 and time t2 are simultaneously loaded into the data storage space Buffer1, so that the processor 10 can read the first data from the data storage space Buffer1 at time t2.
[0105] In this way, by setting the cache area, the data read by the processor 10 from the memory 20 during the first period of time can be obtained.
[0106] Reference Figure 6 In some embodiments, step 01: after obtaining a first access request, the method includes: obtaining a second access request, the second access request being the first access request executed by the processor 10 on the memory 20 within a second time period; when the first access request is to execute a read request first and then a write request, and the second access request is a read request, reading the first data so that the processor 10 executes the read request of the first access request again.
[0107] In some embodiments, the processor 10 can obtain a second access request, which is the first access request executed by the processor 10 on the memory 20 within the second time period; when the first access request is to execute a read request first and then a write request, and the second access request is a read request, the first data is read so that the processor 10 executes the read request of the first access request again.
[0108] In some embodiments, the fault handling device 30 can obtain a second access request, which is the first access request executed by the processor 10 on the memory 20 within the second time period; when the first access request is to execute a read request first and then a write request, and the second access request is a read request, the first data is read to enable the processor 10 to execute the read request of the first access request again.
[0109] Specifically, time t2 can be set as the first time, and the period after time t2 can be set as the second period. The second access request can be the first access request executed by the processor 10 in the period after time t2, that is, the first access request after the processor 10 executes the recovery mechanism.
[0110] If the processor 10 executes a read request, the processor 10 may read erroneous data from the memory 20, that is, after time t2, the processor 10 re-executes instruction pc2 as a read request. At this time, the processor 10 can read the first data, that is, the processor 10 re-executes instruction pc2, implements the recovery mechanism of the processor 10, and ensures that the data read by the processor 10 is accurate, not erroneous data.
[0111] In this way, when it is determined that the processor 10 has a high risk of a read-after-write memory access conflict and the first access request executed by the processor 10 is a read request, the processor 10 can read the first data to ensure that the data read by the processor 10 is accurate.
[0112] Reference Figure 6 In some embodiments, the method includes: executing the second access request if the first access request does not include a read request or a write request.
[0113] In some embodiments, the processor 10 may execute the second access request when the first access request does not include a read request or a write request.
[0114] In some embodiments, the fault handling device 30 may execute the second access request when the first access request does not include a read request or a write request.
[0115] Specifically, if the access request executed by the processor 10 on the memory 20 between time t1 and time t2 does not include reading data or writing data, it can be considered that instruction pc2 executes a read request and instruction pc3 executes a read request, or instruction pc2 executes a write request and instruction pc3 executes a write request.
[0116] If instruction pc2 executes a read request and instruction pc3 executes a read request, the processor 10 does not execute a write request to the memory 20, and there is no risk of a read-after-write memory access conflict. If instruction pc2 executes a read request and instruction pc3 executes a write request, the processor 10 does not execute a read request to the memory 20, and there is no risk of a read-after-write memory access conflict.
[0117] In this way, when it is determined that the processor 10 does not have the risk of a read-after-write memory access conflict, or the risk of a read-after-write memory access conflict is low, the processor 10 can access the memory 20 normally, thereby improving the access efficiency of the processor 10.
[0118] Reference Figure 6 In some embodiments, the method includes: executing the second access request when the first access request is to execute a write request first and then a read request.
[0119] In some embodiments, the processor 10 may execute the second access request when the first access request is to execute a write request first and then a read request.
[0120] In some embodiments, the fault handling device 30 executes the second access request when the first access request is to execute a write request first and then a read request.
[0121] Specifically, if the processor 10 executes access requests to read and write data on the memory 20 between time t1 and time t2, it can be considered that instruction pc2 executes a write request and instruction pc3 executes a read request, or instruction pc3 executes a write request and instruction pc2 executes a read request.
[0122] If instruction pc2 executes a write request and instruction pc3 executes a read request, since instruction pc2 is initiated before time t1, the write request executed by instruction pc2 is less likely to cause erroneous data to be written into memory 20, and the read request executed by instruction pc3 will not read erroneous data in memory 20. At this time, it can be considered that the risk of processor 10 having a read-after-write memory access conflict is low, and processor 10 can access memory 20 normally after time t2, that is, execute the second access request.
[0123] In this way, when it is determined that the processor 10 does not have the risk of a read-after-write memory access conflict, or the risk of a read-after-write memory access conflict is low, the processor 10 can access the memory 20 normally, thereby improving the access efficiency of the processor 10.
[0124] Reference Figure 6 In some embodiments, the method includes: executing the second access request if the second access request is not a read request.
[0125] In some implementations, the processor 10 may execute the second access request when the second access request is not a read request.
[0126] In some implementations, the fault handling device 30 executes the second access request when the second access request is not a read request.
[0127] Specifically, if the processor 10 does not execute a read request, that is, after time t2, the processor 10 re-executes instruction pc2 which is not a read request, the processor 10 re-executes instruction pc2 to implement the recovery mechanism of the processor 10, and the processor 10 will not read the erroneous data in the memory 20.
[0128] In this way, when it is determined that the processor 10 does not have the risk of reading erroneous data, the processor 10 can normally access the memory 20, thereby improving the access efficiency of the processor 10.
[0129] In certain embodiments, when the processor 10 reads data from the memory 20, the processor 10 is provided with a corresponding cache area, and the cache area is configured to update a first cache address, where the first cache address is determined based on the address at which the processor 10 reads data from the memory 20, and obtaining the first address includes: at a first moment, reading the first cache address to read the first address.
[0130] In some implementations, the processor 10 may read the first cache address at a first moment to read the first address.
[0131] In some implementations, the fault handling device 30 may read the first cache address at the first moment to read the first address.
[0132] Specifically, the cache area is provided with a corresponding storage space Buffer1 to store the first cache address. When the processor 10 initiates an access request to the memory 20, it also sends an access request to the cache area. Each time a read request is loaded into the cache area, the read address corresponding to the read request is also loaded into the storage space Buffer1 to update the first cache address.
[0133] The first address can be set as the address at which the processor 10 reads data from the memory 20 between time t1 and time t2. The address at which the processor 10 reads data from the memory 20 between time t1 and time t2 is simultaneously loaded into the storage space Buffer1, so that the processor 10 can read the first address from the storage space Buffer1 at time t2.
[0134] In this way, by setting the cache area, the address at which the processor 10 reads data from the memory 20 within the first period of time can be obtained.
[0135] Reference Figure 7 In some embodiments, step 01: after obtaining the first access request, the method includes: obtaining a second access request, the second access request being the first access request executed by the processor 10 on the memory 20 within the second time period; when the first access request is to execute a read request first and then a write request, and the second access request is a read request, obtaining a first address and a second address, the first address being the address for reading data in the first access request, and the second address being the address for reading data in the second access request; when the first address is consistent with the second address, reading the first data so that the processor 10 executes the read request of the first access request again.
[0136] In some embodiments, the processor 10 can obtain a first address and a second address when the first access request is to execute a read request first and then a write request, and the second access request is a read request, the first address being the address for reading data in the first access request, and the second address being the address for reading data in the second access request; when the first address is consistent with the second address, the first data is read so that the processor 10 executes the read request of the first access request again.
[0137] In certain embodiments, the fault handling device 30 can obtain a first address and a second address when the first access request is to execute a read request first and then a write request, and the second access request is a read request, the first address being the address for reading data in the first access request, and the second address being the address for reading data in the second access request; when the first address is consistent with the second address, the first data is read so that the processor 10 executes the read request of the first access request again.
[0138] Specifically, the time t2 can be set as the first time, and the time period after the time t2 can be set as the second time period. The second access request can be the first access request executed by the processor 10 in the time period after the time t2, that is, the first access request after the processor 10 executes the recovery mechanism. The second address can be set as the access address of the first access request after the processor 10 executes the recovery mechanism.
[0139] When the first address is consistent with the second address, that is, the address of the second access request to read the data is consistent with the address of the first access request to read the data, it can be determined that the read address of the second access request was executed before the processor 10 executed the recovery mechanism. At this time, the first data can be read, so that the processor 10 reads the correct data.
[0140] In this way, when it is determined that the first address is consistent with the second address, reading the first data can enable the processor 10 to read the correct data.
[0141] In some implementations, the method includes executing the second access request if the first address is inconsistent with the second address.
[0142] In some implementations, the processor 10 may execute the second access request when the first address is inconsistent with the second address.
[0143] In some implementations, the fault handling device 30 may execute the second access request when the first address is inconsistent with the second address.
[0144] Specifically, when the first address is inconsistent with the second address, that is, the address of the second access request to read data is inconsistent with the address of the first access request to read data, it can be determined that the read address of the second access request has not been executed before the processor 10 executes the recovery mechanism. At this time, the processor 10 can access the memory 20 normally, the processor 10 will not read erroneous data, and the access efficiency of the processor 10 can also be improved.
[0145] In this way, when it is determined that the read address of the second access request has not been executed before the processor 10 executes the recovery mechanism, the processor 10 can access the memory 20 normally, thereby improving the access efficiency of the processor 10.
[0146] In some embodiments, when the processor 10 writes data to the memory 20, the cache area is configured to update the second cache data and the second cache address, the second cache data is determined based on the data written by the processor 10 to the memory 20, and the second cache address is determined based on the address at which the processor 10 writes data to the memory 20.
[0147] Specifically, the cache area is provided with a corresponding address storage space Buffer2 to store the second cache address. When the processor 10 initiates an access request to the memory 20, it also sends an access request to the cache area. Each time a write request is loaded into the cache area, the write address corresponding to the write request is also loaded into the address storage space Buffer2 to update the second cache address.
[0148] The second address can be set as the address at which the processor 10 writes data to the memory 20 between time t1 and time t2. The address at which the processor 10 writes data to the memory 20 between time t1 and time t2 is simultaneously loaded into the address storage space Buffer2, so that the processor 10 can write to the second address from the address storage space Buffer2 at time t2.
[0149] The cache area is provided with a corresponding data space Buffer2 to store the second cache data. When the processor 10 initiates an access request to the memory 20, it also sends an access request to the cache area. Each time a write request is loaded into the cache area, the write data corresponding to the write request is also loaded into the data space Buffer2 to update the second cache data.
[0150] The second data can be set as the data written by the processor 10 to the memory 20 between time t1 and time t2. The data written by the processor 10 to the memory 20 between time t1 and time t2 are simultaneously loaded into the data space Buffer2, so that the processor 10 can write the second data from the data space Buffer2 at time t2.
[0151] In this way, by setting the cache area, the data written by the processor 10 to the memory 20 during the second period and the address of the written data can be obtained.
[0152] In some embodiments, the cache area includes a first sub-cache area and a second sub-cache area, the first sub-cache area is configured to update the first cache data and the first cache address, or update the second cache data and the second cache address, and the second sub-cache area is configured to update the first cache data and the first cache address, or update the second cache data and the second cache address.
[0153] Specifically, the first sub-buffer area may be set as a storage space Buffer1, and the second sub-buffer area may be set as a storage space Buffer2.
[0154] The storage space Buffer1 can store the first cache data and the first cache address, and can also store the second cache data and the second cache address. The storage space Buffer1 is not limited to storing the data and address of a single operation. Similarly, the storage space Buffer2 can store the first cache data and the first cache address, and can also store the second cache data and the second cache address. The storage space Buffer2 is not limited to the data and address of a single operation.
[0155] When the processor reads data from the memory, the storage space Buffer1 and the storage space Buffer2 can both store the corresponding first cache data and the first cache address. When the processor writes data to the memory, the storage space Buffer1 and the storage space Buffer2 can both store the corresponding second cache data and the second cache address.
[0156] In this way, the first sub-cache area and the second sub-cache area are not limited to storing data and addresses of one operation alone, thereby improving the flexibility of the cache area in updating stored data.
[0157] In some embodiments, the cache area updates the first cache address or the second cache address, including: when the processor 10 reads data from the memory 20, compressing the address of the data read to obtain a first update address, so that the first update address is updated to the first cache address, and the number of bits of the first update address is smaller than the number of bits of the first cache address, or when the processor 10 writes data to the memory 20, compressing the address of the data write to obtain a second update address, so that the second update address is updated to the second cache address, and the number of bits of the second update address is smaller than the number of bits of the second cache address.
[0158] Specifically, when the cache area updates the read address and the write address, the obtained read address and the write address may be preprocessed to obtain an update address with a smaller number of bits, and the corresponding update address is loaded into the cache area.
[0159] In this way, the cache area can save storage space and improve work efficiency.
[0160] In some embodiments, compressing the address for data reading to obtain a first update address, or compressing the address for data writing to obtain a second update address includes: performing bit truncation processing on the address for data reading to obtain the first update address, or performing bit truncation processing on the address for data writing to obtain the second update address.
[0161] Specifically, a bit truncation process may be performed on the data reading address or the data writing address to obtain an update address with a smaller bit number.
[0162] For example, the address of the memory 20 may have 8 digits, and the effective address of the processor 10 for executing an access request to the memory 20 is 6 digits, and the data read address and the data write address can be determined based on the 6-bit effective address. The data read address or the data write address can be bit truncated to retain the 6-bit effective address, thereby saving storage space in the cache area.
[0163] In this way, by performing bit truncation processing on the address for reading data or the address for writing data, the cache area can save storage space and improve work efficiency.
[0164] In some embodiments, compressing the address for data reading to obtain a first update address, or compressing the address for data writing to obtain a second update address includes: determining the first update address based on a specific mapping relationship and the address for data reading, or determining the second update address based on a specific mapping relationship and the address for data writing.
[0165] Specifically, the address mapping technology is used to map the truncated address to a smaller address space, making full use of locality and reducing the demand for memory 20. For example, the address of memory 20 can have 8 digits, which can be mapped to a 6-digit address space based on the corresponding mapping relationship, saving storage space in the cache area.
[0166] In this way, by performing address mapping on the address for reading data or the address for writing data, the cache area can save storage space and improve work efficiency.
[0167] In some embodiments, compressing the address of data read to obtain a first update address, or compressing the address of data write to obtain a second update address includes: processing the address of data read by a sampling encoding method to determine the first update address, or processing the address of data read by a sampling encoding method to determine the second update address.
[0168] Specifically, the address encoding technology is used to map the truncated address to a smaller address space, making full use of locality and reducing the demand for the memory 20. For example, the address of the memory 20 adopts an octal encoding method, and the address of the memory 20 has a total of 8 digits. The octal encoding method can be converted into a hexadecimal encoding, so that the number of digits of the update address is 4 digits, saving the storage space of the cache area.
[0169] In this way, by performing address encoding on the address for reading data or the address for writing data, the cache area can save storage space and improve work efficiency.
[0170] An embodiment of the present application further provides an electronic device, which includes the fault-tolerant system of the above embodiment.
[0171] The embodiment of the present application further provides a computer-readable storage medium, which stores a computer program. When the computer program is executed by one or more processors 10, the processing method of the above embodiment is implemented.
[0172] In the description of this specification, the description with reference to the terms "one embodiment", "some embodiments", "illustrative embodiments", "examples", "specific examples" or "some examples" means that the specific features, deconstructions, materials or characteristics described in conjunction with the embodiments or examples are included in at least one embodiment or example of the present application. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. In addition, those skilled in the art may combine and combine different embodiments or examples described in this specification and the features of different embodiments or examples without contradiction.
[0173] In addition, the term "connection" should be understood in a broad sense, for example, it can include fixed connection, detachable connection, or integral connection; it can include direct connection, indirect connection through an intermediate medium, and internal communication between two elements. For ordinary technicians in this field, the specific meanings of the above terms in this application can be understood according to specific circumstances.
[0174] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first" and "second" may explicitly or implicitly include at least one of the features. In the description of this application, the meaning of "plurality" is at least two, such as two, three, etc., unless otherwise clearly and specifically defined.
[0175] Any process or method description in a flowchart or otherwise described herein may be understood to represent a module, fragment or portion of code that includes one or more executable instructions for implementing the steps of a specific logical function or process, and the scope of the preferred embodiments of the present application includes alternative implementations in which functions may not be performed in the order shown or discussed, including performing functions in a substantially simultaneous manner or in reverse order depending on the functions involved, which should be understood by technicians in the technical field to which the embodiments of the present application belong.
[0176] Although the embodiments of the present application have been shown and described above, it can be understood that the above embodiments are exemplary and cannot be understood as limitations on the present application. Ordinary technicians in this field can change, modify, replace and modify the above embodiments within the scope of the present application.
Claims
1. A method for handling a processor failure, characterized in that: The processor is correspondingly provided with a cache area. When the processor reads data from the memory, the cache area is configured to update a first marking signal. When the processor writes data to the memory, the cache area is configured to update a second marking signal. The method includes: At a first moment when switching from a first time period to a second time period, obtaining a first access request executed by the processor on the memory in the first time period, the processor being in a first state in the first time period, and the processor being in a second state in the second time period, the second state being different from the first state; Determine a read request executed by the first access request according to the first marking signal, determine a write request executed by the first access request according to the second marking signal, and determine a sequence in which the first access request executes the read request and the write request according to an update sequence of the first marking signal and the second marking signal; In the case where the first access request executes a read request first and then a write request, first data is read, where the first data is the first data read by the processor within the first time period, so that the processor executes the read request of the first access request again, where the first data is the data read by the processor within the first time period.
2. The processor fault handling method according to claim 1, characterized in that: In the case where the processor reads data from the memory, the cache area is configured to update first cache data, where the first cache data is determined by data read by the processor from the memory, and the reading of the first data includes: At the first moment, the first cache data is read to read the first data.
3. The processor fault handling method according to claim 1, characterized in that: After obtaining the first access request, the method includes: Obtaining a second access request, where the second access request is a first access request executed by the processor on the memory within the second time period; When the first access request is to execute a read request first and then a write request, and the second access request is a read request, the first data is read so that the processor executes the read request of the first access request again.
4. The processor fault handling method according to claim 3, characterized in that: The method comprises: In a case where the first access request does not include a read request or a write request, the second access request is executed.
5. The processor fault handling method according to claim 3, characterized in that: The method comprises: In a case where the first access request is to execute a write request first and then a read request, the second access request is executed.
6. The processor fault handling method according to claim 3, characterized in that: The method comprises: If the second access request is not a read request, the second access request is executed.
7. The processor fault handling method according to claim 1, characterized in that: After obtaining the first access request, the method includes: Obtaining a second access request, where the second access request is a first access request executed by the processor on the memory within the second time period; When the first access request is to execute a read request first and then a write request, and the second access request is a read request, obtaining a first address and a second address, wherein the first address is an address for reading data by the first access request, and the second address is an address for reading data by the second access request; When the first address is consistent with the second address, the first data is read so that the processor executes the read request of the first access request again.
8. The processor fault handling method according to claim 7, characterized in that: The method comprises: When the first address is inconsistent with the second address, the second access request is executed.
9. The processor fault handling method according to claim 7, characterized in that: In the case where the processor reads data from the memory, the processor is correspondingly provided with a cache area, and the cache area is configured to update a first cache address, where the first cache address is determined according to an address at which the processor reads data from the memory, and obtaining the first address includes: At the first moment, the first cache address is read to read the first address.
10. The processor fault handling method according to claim 9, characterized in that: When the processor writes data to the memory, the cache area is configured to update second cache data and a second cache address, the second cache data is determined based on the data written by the processor to the memory, and the second cache address is determined based on the address written by the processor to the memory.
11. The processor fault handling method according to claim 10, characterized in that: The cache area includes a first sub-cache area and a second sub-cache area, the first sub-cache area is configured to update the first cache data and the first cache address, or update the second cache data and the second cache address; The second sub-cache area is configured to update the first cache data and the first cache address, or to update the second cache data and the second cache address.
12. The processor fault handling method according to claim 1, characterized in that: The first state is a fault state of the processor, and the second state is a normal state of the processor.
13. A chip, characterized in that: The chip includes a processor, and the processor is used to execute the fault handling method according to any one of claims 1-12 during operation.
14. The chip according to claim 13, characterized in that: The processor is correspondingly provided with a cache area and a memory. When the processor reads data from the memory, the cache area is configured to update a first marking signal, a first cache address and first cache data, wherein the first cache address is determined according to an address from which the processor reads data from the memory, and the first cache data is determined by data from which the processor reads data from the memory; when the processor writes data to the memory, the cache area is configured to update a second marking signal, a second cache address and second cache data, wherein the second cache address is determined according to an address from which the processor writes data to the memory, and the second cache data is determined by data from which the processor writes data to the memory.
15. A processor fault handling device, characterized in that: The processor is correspondingly provided with a cache area, and when the processor reads data from the memory, the cache area is configured to update the first marking signal, and when the processor writes data to the memory, the cache area is configured to update the second marking signal, and the device includes: an acquisition module, configured to acquire, at a first moment when switching from a first time period to a second time period, a first access request executed by the processor on the memory in the first time period, the processor being in a first state in the first time period, and the processor being in a second state in the second time period, the second state being different from the first state; The acquisition module is further configured to determine a read request executed by the first access request according to the first marking signal, determine a write request executed by the first access request according to the second marking signal, and determine a sequence of executing the read request and the write request by the first access request according to an update sequence of the first marking signal and the second marking signal; The reading module is configured to read first data when the first access request includes a read request and a write request, so that the processor executes the first access request again, and the first data is data read by the processor within the first time period.
16. The fault handling device according to claim 15, characterized in that: The acquisition module is also configured to acquire a second access request, which is the first access request executed by the processor on the memory within the second time period. The reading module is also configured to read the first data when the first access request is to execute a read request first and then a write request, and the second access request is a read request.
17. The fault handling device according to claim 15, characterized in that: The acquisition module is configured to acquire a second access request, where the second access request is the first access request executed by the processor to the memory within the second time period. The acquisition module is configured to acquire a first address and a second address when the first access request executes a read request first and then a write request, and the second access request is a read request, where the first address is an address for reading data by the first access request, and the second address is an address for reading data by the second access request. The reading module is configured to read the first data when the first address is consistent with the second address.
18. A processor fault-tolerant system, characterized in that: The system includes a fault handling device, a fault detection device and a fault recovery device as described in any one of claims 15 to 17, wherein the fault detection device is configured to determine that the processor is in a first state, and the fault recovery device is configured to determine that the processor switches from the first state to a second state.
19. An electronic device, characterized in that: The electronic device comprises the fault-tolerant system of claim 18.
20. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores a computer program, and when the computer program is executed by one or more processors, the processing method according to any one of claims 1 to 12 is implemented.