Accelerating memory training through in-band configuration register update mode

Abstract

The configuration register update mode may be implemented as a register word update (RWUPD) mode for a register clock driver (RCD), or a mode register update (MRUPD) mode for a dynamic random access memory (DRAM) device. In an update mode, a memory device (RCD or DRAM) may perform configuration on any number of configuration registers with in-band register writes. In-band register writes may be used to configure decision feedback equalization (DFE) settings, as well as other configuration settings for non-DFE configurations of memory device interfaces.

Description

Technical Field

[0001] The description relates generally to computer memory, and more particularly to memory interface training. Background Art

[0002] Programming the RCD prior to command bus / address (CA) bus and data (DQ) bus training is performed using a sideband bus (e.g., system management bus (SMBus)). The sideband bus operates at a very low speed (approximately megahertz (MHz)) relative to the CA bus and DQ bus (approximately gigahertz (GHz)). Using the sideband bus for training can result in significant delays in training.

[0003] The Registered Clock Driver (RCD) defines in-band training that can be used for training options for decision feedback equalization (DFE) configuration. RCD in-band training defines entry into Register Word Update (RWUPD) mode. In RWUPD mode, the RCD can receive configuration updates until there is a trigger to exit update mode. Since RWUPD mode is limited to DFE configuration, its training scope is limited.

[0004] It should also be understood that configuration updates of dynamic random access memory (DRAM) devices may be performed via mode register (MR) writes. The DRAM device performs a write in response to a mode register write (MRW) command sent to the DRAM device. The memory controller traditionally requires training the CA bus before commands such as MRW can be reliably sent to the DRAM device. BRIEF DESCRIPTION OF THE DRAWINGS

[0005] The following description includes a discussion of the diagrams with illustrations given by examples of implementations. The accompanying drawings should be understood by way of example and not limitation. As used herein, reference to one or more examples should be understood to describe a specific feature, structure or characteristic included in at least one implementation of the present invention. Phrases such as "in one example" or "in an alternative example" that appear herein provide examples of implementations of the present invention and do not necessarily all refer to the same implementation. However, they are not necessarily mutually exclusive.

[0006] Figure 1 is a block diagram of an example of a system having a memory module.

[0007] Figure 2 is a block diagram of an example of a memory module with an RCD having an in-band configuration mode.

[0008] Figure 3 is a block diagram of an example of a memory module with a memory device having an in-band configuration mode.

[0009] Figure 4 is an example of a table for RWUPD mode.

[0010] Figure 5 is an example of a table for MRUPD mode.

[0011] Figure 6 is an example of a table for MRUPD mode that also uses M3C.

[0012] Figure 7 is a flow chart for an example of a RWUPD process.

[0013] Figure 8 is a flow chart of an example for the MRUPD process.

[0014] Fig. 9 is a state diagram of an example of MRUPD.

[0015] Fig.10 is a block diagram of an example of a memory subsystem that can implement an in-band configuration mode.

[0016] Fig.11 is a block diagram of an example of a computing system that can implement an in-band configuration mode.

[0017] Fig.12 is a block diagram of an example of a multi-node network that can implement in-band configuration mode.

[0018] What follows is a description of specific details and implementations, including a non-limiting description of the accompanying drawings, which may depict some or all examples, as well as other potential implementations. DETAILED DESCRIPTION

[0019] As described herein, a configuration register update mode may be implemented as a register word update (RWUPD) mode for a registered clock driver (RCD) or a mode register update (MRUPD) mode for a dynamic random access memory (DRAM) device. In update mode, a memory device (RCD or DRAM) may utilize in-band register writes to perform configuration of any number of configuration registers. In-band register writes may be used to configure decision feedback equalization (DFE) settings, as well as other configuration settings for non-DFE configuration of a memory device interface.

[0020] As described in this article, in-band communication can be used to train any DRAM register or RCD register before the chip select (CS) is trained. In one concept, there is an extension / enhancement of register word update (RWUPD). RWUPD has been limited to device command / address training mode (DCATM) and DFE, and can be extended to the update of any register or any register word. Therefore, the system can update the register word configuration through the RWUPD mode. Extending RWUPD to the update of other registers avoids the use of SMBus, thereby increasing the speed of training and setup. In another concept, there is a mode register update (MRUPD). MRUPD extends the idea of ​​using in-band communication for register updates. The use of MRUPD can replace MPC. When the bus is not fully trained, the system can use in-band communication for training.

[0021] Figure 1 1 is a block diagram of an example of a system having memory modules. System 100 includes a socket 110 coupled to a DIMM 120. Socket 110 represents a CPU socket, which may include a CPU 112 and a memory controller 114. DIMM 120 includes a plurality of DRAM devices.

[0022] System 100 illustrates an example of a system having memory devices that share a control bus or command bus (command / address (C / A) bus 126[0] for one channel and C / A bus 126[1] for another channel) and a data bus (data bus 116[0] for one channel and data bus 116[1] for another channel). The memory devices are represented as DRAM (dynamic random access memory) devices. Each channel has N DRAM devices, one channel has DRAM 132[1:N] (collectively referred to as DRAM devices 132), and the other channel has DRAM 134[1:N] (collectively referred to as DRAM devices 134), where N can be any integer. In one example, in addition to the data devices, N also includes one or more (error checking and correction, ECC) DRAM devices. Each DRAM device 132 and each DRAM device 134 can represent a memory chip having a command bus interface to a memory controller 114, where the interface can be through RCD 122.

[0023] In one example, two separate channels share the C / A bus 124 connection between the memory controller 114 and the RCD 122. In one example, separate channels will have separate C / A buses. DRAM devices can be accessed individually through device specific commands and can be accessed in parallel through parallel commands.

[0024] The registering clock driver (RCD) 122 (which may also be referred to as a registered clock driver) represents the controller of the dual inline memory module (DIMM) 120. In one example, the RCD 122 receives information from the memory controller 114 and buffers the signals to the various DRAM devices. By buffering the incoming command signals from the memory controller 114, the controller only sees the load of the RCD 122 on the command / address (CA bus 124) and can then control the timing and send signals to the DRAM devices.

[0025] In one example, RCD 122 controls command signals to DRAM device 132 via CA bus 126[0] and controls signals to DRAM device 134 via CA bus 126[1]. In one example, RCD 122 has independent command ports for separate channels. In one example, DIMM 120 includes data buffers for buffering data bus signals between DRAM devices of DIMM 120 and memory controller 114.

[0026] Data bus 116[0] provides a data bus for DRAM device 132, which is buffered by data buffers (DB) 142[1:N] (collectively referred to as DB 142). Data bus 116[1] provides a data bus for DRAM device 134, which is buffered by data buffers (DB) 144[1:N] (collectively referred to as DB 144). System 100 shows a one-to-one relationship between data buffers and DRAM devices. In one example, the number of data buffers is less than the number of DRAM devices, where the DRAM devices share data buffers.

[0027] CA bus 126[0] and CA bus 126[1] (collectively referred to as CA bus 126) are typically single-sided or unidirectional buses for transmitting command and address information from memory controller 114 to DRAM devices. Therefore, CA bus 126 can be a multi-drop bus. Data bus 116[0] and data bus 116[1] (collectively referred to as data bus 116) are traditionally bidirectional point-to-point buses.

[0028] In one example, the memory controller 114 includes one or more sideband bus connections connected to other devices in the system 100. The sideband bus refers to a bus other than the CA bus 124 and the data bus 116. As shown, the memory controller 114 has a system management bus (SMBus, shown as "SMB" in the system 100 for simplicity) to connect to the RCD 122. In one example, the memory controller 114 has an SMBus connection or other sideband bus (SBB) to connect to the DRAM device. In one example, the SBB connection represents a memory module management control (M3C) bus. Both the SMBus and SBB connections represent sideband bus communications in the system 100.

[0029] The sideband bus enables the memory controller 114 to provide commands to the device over a connection other than the CA bus. Communications on the sideband bus are not in-band because the commands are not received on the CA bus. In one example, communications on the sideband bus enable the memory controller 114 to send a command to trigger the device to enter a pre-training update mode, which uses in-band communications to perform configuration updates.

[0030] In one example, the system 100 supports a RWUPD mode to configure the RCD interface to the CA bus 124. In one example, the system 100 supports an MRUPD mode to configure a DRAM device. The configuration of the DRAM device may include configuration of a data bus interface, configuration of a CA bus interface, or configuration of both a CA bus interface and a data bus interface. With the update mode, the system 100 supports writing configuration parameters in-band before training a chip select (CS).

[0031] In one example, utilizing the update mode, the system 100 can speed up back and front training for all parameter sweeps. With the increase of in-band commands to perform configuration, the system 100 can reduce the use of the sideband bus. Since the speed difference between in-band communication and out-of-band communication (e.g., sideband bus usage) is significant, where in-band communication can be several orders of magnitude faster, using in-band communication for configuration updates can improve system boot time.

[0032] The CA bus 124 provides a link to the memory controller 114 to provide command and address information to identify the command to be executed and the address for executing the command. It will be appreciated that the command bus interface (e.g., CA bus 124) can be trained to recognize the preferred settings to ensure that the commands are properly received at the RCD 122. Training can include iterating through different configuration settings to determine the settings with the best performance, which can vary from system to system.

[0033] With the introduction of double data rate (DDR) mode for the command bus, the command bus interface may include a decision feedback equalization (DFE) with multiple taps (e.g., 2 or 4 taps) to ensure a correct data eye on the CA signal line. DFE refers to a non-linear equalization circuit that uses information about previously received bits to determine the bit currently being received and processed. Other configuration settings may include reference voltage settings, current settings, and other configuration settings. Training setting parameters to ensure correct communication on the command bus.

[0034] In one example, when the system 100 supports the MRUPD mode, the update mode can reduce or eliminate the need to configure the multi-purpose command (MPC command). In one implementation, the system 100 can replace the MPC command, replace the chip select voltage reference (voltage reference for chip select, VrefCS) command, and replace the command / address voltage reference (voltage reference for command / address, VrefCA) command. Full use of the MRUPD mode for all training can achieve the removal of the MPC encoding opcode table. Alternatively, the system can limit the opcode to a few commands. Both removing and reducing the MPC opcode can save hardware logic within the DRAM device.

[0035] MRUPD mode and RWUPD mode can enable configuration of all possible training modes. In one example, enabling configuration for all training modes includes the following: triggering the device to enter update mode (e.g., an SMBus command that triggers a RWUPD entry (RWUPDE), or an M3C command that triggers an MRUPD entry (MRUPDE)), issuing a configuration write operation using two commands, including one command for the register address and the other command for the configuration data value. The register write operation is an in-band command, which speeds up the configuration setup.

[0036] As an alternative to using the M3C command to trigger MRUPDE, in one example, the DRAM device can default to MRUPD mode after power-up. The system can use the RWUPD Exit (RWUPDX) command for RCD or the MRUPD Exit (MRUPDX) command for DRAM to trigger the end of update mode. The exit command can terminate the update cycle that issued the configuration register write.

[0037] The above can be applied to the CA bus in double data rate DDR mode. If the DRAM defaults to MRUPD mode / state immediately after power-up, the system can perform MRUPD before chip select training mode (CSTM) and before command / address training mode (CATM). Such operations can set the termination and Vref values ​​through in-band commands instead of using sideband communication. Although MRUPD can replace MPC with single-cycle commands, it can require a multi-cycle chip select feature.

[0038] Figure 2 is a block diagram of an example of a memory module with an RCD having an in-band configuration mode. System 200 illustrates a system according to an example of system 100 .

[0039] The system 200 includes a dual in-line memory module (DIMM) 210, which represents a memory module having a module controller. An RCD 220 represents a module controller. The RCD 220 is connected to a host (not specifically shown) via a CA bus 224. The RCD 220 has an interface to the CA bus 224, which can be configured by setting values ​​of a register 222.

[0040] Registers 222 may include, but are not limited to, DFE settings and termination settings. Each register may include one or more configuration settings. Registers 222 specifically illustrate DFE to indicate configuration settings of the DFE of the CA bus 224, VREF to indicate Vref configuration settings, and CA to indicate other settings (e.g., termination settings or other configurations for the CA bus 224).

[0041] RCD 220 may be connected to DRAM device 232 via CA bus 244[0] and to DRAM device 234 via CA bus 244[1]. In one example, the configuration of register 222 is applied to the interface of CA bus 224, and the DRAM devices will have a different configuration for CA bus interconnection than RCD 220.

[0042] The RWUPD mode for RCD 220 can be extended to enable system 200 to complete CSTM in RWUPD, applying in-band communication to set the configuration. In one example, RCD 220 enters RWUPD using SMBus communication and exits RWUPD in response to CS assertion. In one example, when RCD 220 is in RWUPD, system 200 has a setup / configuration qualifier. The qualifier can be, for example, a chip select (e.g., DCS0 / 1), where the assertion of the chip select can determine which channel is configured. In one example, each training mode can indicate which qualifier is used for a specific training. The training mode qualifier can be opposite to the RWUpdate qualifier.

[0043] In one example, the host can send a register address (e.g., a RW address) and an opcode for a RWUPD operation and use the RWUPD qualifier to internally loop update the operation (e.g., to utilize hardware acceleration). In one example, the system 200 triggers the RCD 220 to exit RWUPD by writing to an RCD register (RW32) or via an SMBus command. In one example, the register 222 can include a RW32 RCD register.

[0044] RWUPD can be enhanced to all training steps (not just DFE). In one example, RWUPD enhancements can include modifications to reduce significant training time (for both front and back sides) and logic in RCD.

[0045] In one example, RWUPD entry occurs when the RCD is in training mode and DCS1_[B:A]_n is asserted. The RWUPD operation involves the memory controller sending a DCS1_[B:A]_n assertion pair. On the first assertion, the device samples the target RW address on {DCA[6:0]_[B:A], DPAR_[B:A]}. On the second assertion, the device samples the value to be written to the target RW. RWUPD exit can involve writing a register word, such as writing a 1 to RW32[7], which can trigger the RCD to exit the RWUPD branch and return to the starting training mode state.

[0046] Figure 3 is a block diagram of an example of a memory module with a memory device having an in-band configuration mode. System 300 illustrates a system according to the example of system 100 or the example of system 200 .

[0047] The system 300 includes a dual in-line memory module (DIMM) 310, which represents a memory module having a module controller. RCD 320 represents a module controller. RCD 320 is connected to a host (not specifically shown). RCD 320 can be connected to DRAM device 332 via CA bus 344[0] and to DRAM device 334 via CA bus 344[1].

[0048] In one example, DRAM device 332 includes register 336, and DRAM device 334 includes register 338. In one example, the configuration of register 336 applies to the interface of DRAM device 332 to CA bus 344[0]. In one example, the configuration of register 338 applies to the interface of DRAM device 334 to CA bus 344[1].

[0049] Registers 336 and 338 may include, but are not limited to, DFE settings and termination settings. Registers 336 and 338 specifically illustrate DFE to represent a DFE configuration register for storing one or more configuration settings of the DFE for the CA bus, VREF to represent a Vref configuration setting, and CA to represent other settings (e.g., termination settings or other configurations for the CA bus). In one example, MRUPD may be applied to all configuration settings for the CA bus in a DRAM device. MRUPD may provide a training mode for all configuration register training for the CA bus.

[0050] The system 300 enables a DRAM mode register update (MRUPD) mode. In one example, the MRUPD mode has an MRUPD entry (MRUPDE) and an MRUPD exit (MRUPDX). In one example, MRUPD is applied to double data rate version 6 (DDR6). In one example, MRUPD is used in conjunction with a memory module management control (M3C) bus. The application of the MRUPD mode can replace the MPC command, the VrefCA command, and the VrefCS command. Without these commands, the MPC opcode table is not required. Removal of the table saves logic in the DRAM and allows access to the mode register at any time without being restricted by any settings.

[0051] In one example, MRUPD in DRAM provides an update mode for DRAM to use for all training steps. Using the proposed MRUPD, to scan any parameters, the system does not need to access through the SMBus, which is much slower than in-band commands. Performing training through in-band access can speed up back-end training steps, such as CSTM, CATM, and DFE training algorithms, and improve system boot time.

[0052] In one example, the in-band register write is a mode register write (MRW) based on a command on the command bus prior to executing a command / address training mode (CATM). In one example, the system 300 provides a first multi-purpose command (MPC) to enter MRUPD mode. A second MPC can trigger an exit from MRUPD mode.

[0053] Figure 4 is an example of a table for RWUPD mode. Table 400 shows various opcodes. Table 400 includes the opcode bits (OP[0:7]) as a setting column. The definition column describes the setting, and the encoding column provides detailed information for the setting.

[0054] The opcode for configuring whether DCS0 is included in the exclusive OR operation (XOR) can be set to OP0=0 to exclude DCS0 (default setting), or to OP0=1 to include DCS0. The opcode for configuring whether DCS1 is included in the XOR can be set to OP1=0 to exclude DCS1 (default setting), or to OP1=1 to include DCS1. The opcode for configuring the control signal selection can be set to OP2=0 to select DCS0 (default setting), or to OP2=1 to select DCS1.

[0055] In one example, there is a register word (RW) in-band update feature, where enablement is controlled by OP6, when OP6=0, the RWUPD feature is not enabled, which is the default setting, and when OP6=1, the RWUPD feature is enabled. In one example, exit from RWUPD can be controlled by OP7, when OP7=0, causing no action to be taken, leaving the system in RWUPD, and when OP7=1, causing exit from the RWUPD state (default setting).

[0056] Using Table 400, the following comments can be added to describe the opcode definition:

[0057] NOTE A: DCS0 line – DCS1 will be the qualifier if RWUPD is enabled. DCS1 will not participate in the XOR.

[0058] Note B: DCS1 Line – If RWUPD is enabled, then DCS0 will be the qualifier. DCS0 will not participate in the XOR.

[0059] Note C: The user can use RWUPD to change the RWUPD DCS qualifier using the previous DCS qualifier in a single register setting.

[0060] Separate RWUPD from other training modes to allow it to be used for other purposes. RW7E can define a new mode and leave RW32 as is.

[0061] Descriptions related to RWUPD refer specifically to configuration of RCD settings. Descriptions related to MRUPD refer specifically to configuration of DRAM settings. The concept of in-band communication for setting configuration applies to both RWUPD and MRUPD.

[0062] There are different options available for the application of MRUPD.

[0063] Option 1 applies to M3C and MRUPD. Under such an architecture, using M3C can reduce training time. The system can use M3C communication to trigger MRUPDE and MRUPDX. The system can use MRUPD to configure all DRAM mode registers, where CS can be a qualifier for MRUPD (for example, use CS1 as a qualifier to train CS0, and use CS0 as a qualifier to train CS1). The system can enter CSTM training using multi-cycle CS for MRUPD and exit with double CS. In Option 1, the system can switch to another CS and change the value using MRUPD. The system can then exit using the M3C command. With this architecture, M3C can be used for initialization, such as termination, device ID, etc.

[0064] The flow of Option 1 can be described based on the example of process 800. Advantages of Option 1 include: 1) configuration is significantly faster than SMBus training, even when MRUPD is a dual command (one for address and one for data); 2) elimination of VrefCA and VrefCS MPC encoding and commands; 3) potential removal of MPC commands and opcode tables; and 4) enabling MRUPD mode entry by default at DRAM power-up, which can avoid M3C commands.

[0065] Figure 5 is an example of a mode table for MRUPD. Table 500 describes the application of Option 2 for an implementation of MRUPD. Table 500 includes the functionality of initialization and training modes based on OP[7:0]. The data columns describe the different modes. The selected mode is shown, while other modes are ignored.

[0066] The operation code "0000 0000" indicates an exit from the CS training mode (CSTM).

[0067] The operation code "0000 0001" indicates entry into CSTM.

[0068] The operation code "0000 1010" indicates an exit from per device addressability (PDA) enumeration programming mode.

[0069] The operation code "0000 1011" indicates entering the PDA enumeration programming mode.

[0070] The operation code "0000 1100" indicates a manual error checking and scrub (ECS) operation.

[0071] In one example, Option 2 applies MPC and M3C (without MRUPD). With this architecture, additional opcodes can provide additional functionality. The timing of the command / address signal line (QCA) and chip select signal line (QCS) can be controlled by a continuous time linear equalizer (CTLE) and a DFE 1-tap, which can involve hundreds of register accesses to set the configuration.

[0072] The M3C bus speed can be a controlling factor in training the CA and CS signals. In one example, the system encodes the MPC opcode to allow for DFE tap setting programming. There can be two settings for gain and two settings for CTLE. Using MPC will consume command bandwidth while also reducing the burden on M3C. Compared to replacing VrefCA, VrefCS, and MPC in option 1, this architecture keeps VrefCA, VrefCS, and MPC as is. Built-in DRAM logic can be used to reduce logic to perform automatic scanning and compare to the pattern internally. Using option 2, M3C can be used for initialization settings (e.g., termination, device ID, etc.), as well as debugging and verification. Some MPC commands can be avoided in advance using debugging and verification.

[0073] In one example, Option 2 may include a new MPC opcode. An 'x' indicates a variable, and thus, an opcode with an 'x' may indicate a range.

[0074] The opcode "0000 1101" may be MRUpdate mode entry (MRUPDE) (default).

[0075] The opcode "0000 1110" may be MRUpdate mode exit (MRUPDX).

[0076] The opcode “101x xxxx” may indicate an MPC opcode for DFE tap setting.

[0077] The opcode "1100 0xxx" can be used for the mode register.

[0078] The opcode “1100 10xx” can be used for DFE CTLE setting.

[0079] The opcode “1100 11xx” can be used for DFE gain setting.

[0080] As will be appreciated, the use of so many opcodes can significantly reduce the number of opcodes available for MPC commands.

[0081] In one example, there are in-band register writes based on commands on a command bus, as described, without using a sideband bus. Thus, the register writes may be RW writes, without using the SMBus. The register writes may be mode register writes without using a sideband bus. In one example, there may be in-band register writes combined with using the SMBus, as described. The register writes may be mode register writes combined with using a sideband bus.

[0082] Figure 6 is an example of a table for MRUPD modes that also uses M3C. Table 600 describes the application of Option 3 for the implementation of MRUPD. Table 600 includes the functions of initialization and training modes based on OP[7:0]. The data columns describe the different modes. Selected modes are shown, while other modes are omitted.

[0083] The operation code "0000 0000" indicates an exit from the CS training mode (CSTM).

[0084] The operation code "0000 0001" indicates entry into CSTM.

[0085] Operation code "0000 1010" indicates an exit from Per Device Addressability (PDA) enumeration programming mode.

[0086] The operation code "0000 1011" indicates entering the PDA enumeration programming mode.

[0087] In one example, the opcodes "0000 1010" and "0000 1011" may be removed because they are not needed.

[0088] The operation code "0000 1100" indicates a manual error checking and cleaning (ECS) operation.

[0089] Operation codes “0000 1101” to “0001 1110” indicate operation codes reserved for future use (RFU).

[0090] Option 3 applies to MPC, M3C, and MRUPD. In such an architecture, MPC can be used to enter and exit MRUPD. The system can use MRUPD to scan the DRAM mode register (MR). M3C can be used for initialization (e.g., termination, device ID, etc.), as well as for debugging and verification.

[0091] In one example, option 3 may utilize opcodes “0001 1111” to “0110xxxx” for MRUPD / M3C command (CMD) operations.

[0092] The operation code “0001 1111” can trigger the application of VrefCA, VrefCS and internal resistors (RTT), including CA signal resistor (RTT_CA), chip select signal resistor (RTT_CS) and clock signal resistor (RTT_CK).

[0093] The opcode "0010 0xxx" can be a group A RTT_CK signal, setting the termination to 'xxx'.

[0094] The opcode "0010 1xxx" can be a Group B RTT_CK signal, setting the termination to 'xxx'.

[0095] The opcode "0011 0xxx" can be a Group A RTT_CS signal, setting the termination to 'xxx'.

[0096] The opcode "0011 1xxx" can be a Group B RTT_CS signal, setting the termination to 'xxx'.

[0097] The opcode "0100 0xxx" can be a Group A RTT_CA signal, setting the termination to 'xxx'.

[0098] The opcode "0100 1xxx" can be a Group B RTT_CA signal, setting the termination to 'xxx'.

[0099] The operation code '0101 0xxx' may be used to set the data strobe (DQS) parking termination DQS_RTT_PARK to 'xxx'.

[0100] The opcode "0101 1xxx" may be used to set the other park termination RTT_PARK to 'xxx'.

[0101] The opcode "0110xxxx" may be used to indicate a PDA enumeration ID (set the value to 'xxxx').

[0102] The opcode "0111xxxx" may be used to instruct the PDA to select an ID (set the value to 'xxxx').

[0103] The opcode “1000xxxx” can be used to configure the delay locked loop timing (tDLLK) and the time required between column-to-column commands (tCCD_L) (set the value to “xxxx”).

[0104] Other opcode encodings may be reserved.

[0105] Figure 7 7 is a flow chart of an example for a RWUPD process. Process 700 represents a process flow for in-band RCD configuration. In one example, at 702, a memory controller is to write a configuration to the RCD. At 704, the controller may determine whether the command interface is trained.

[0106] If the interface has been trained, then at the YES branch 706, the system may configure the RCD using a conventional RW write command at 708. If the interface has not been trained, then at the NO branch 706, the RCD may receive a command to trigger a register word update (RWUPD) mode at 710. For example, the system may use one or more SMBus commands to trigger entry into RWUPD.

[0107] At 712, the RCD enters RWUPD and receives an in-band command to write the Vref configuration, termination configuration, or DFE configuration, or a combination of these configurations, at 714. The controller can send all RWUPD settings and the RCD writes them to the registers.

[0108] At 716, the system can identify the configuration address identifier, such as using a RWUPD1 command. At 718, the system can identify the configuration data, such as using a RWUPD2 command. The system can continue to update the configuration settings until a RWUPD exit command. Therefore, if there is no RWUPD exit, then at 720 the "NO" branch, the configuration update can continue at 716.

[0109] In response to RWUPD exit, at 720 "Yes" (YES) branch, RCD can exit RWUPD at 722 and wait for the next configuration write event. At 708, after configuring using a conventional RW write command, at 722, the system can also exit configuration mode and wait for the next configuration write event.

[0110] Figure 8 8 is a flow chart of an example of an MRUPD process. Process 800 represents a process flow for in-band DRAM configuration. In one example, at 802, a memory controller is to write a configuration to a DRAM. At 804, the controller may determine whether the command interface of the DRAM is trained.

[0111] If the interface has been trained, then at the YES branch at 806, the system may configure the DRAM using a normal mode register write (MRW) command at 808. If the interface has not been trained, then at the NO branch at 806, the RCD may receive a command at 810 to trigger a mode register update (MRUPD) mode.

[0112] The device enters MRUPD at 812 and receives an in-band command to write the Vref configuration, the termination configuration, or the DFE configuration, or a combination of these configurations at 814. The controller can send all the MRUPD settings and the DRAM writes them to the registers.

[0113] The system may identify the configuration address identifier at 816, such as using the MRUPD1 command. The system may identify the configuration data at 818, such as using the MRUPD2 command. The system may continue to update the configuration settings until the MRUPD exit command. Therefore, if there is no MRUPD exit, then at 820 the "NO" branch, the configuration update may continue at 816.

[0114] In response to the MRUPD exit, at 820, the YES branch, the DRAM can exit MRUPD at 822 and wait for the next configuration write event. At 808, after configuring using a conventional RW write command, the system can also exit configuration mode at 822 and wait for the next configuration write event.

[0115] Fig. 9 900 is a state diagram of an example of MRUPD. System 900 represents various states in an example MRUPD flow. In one example, in response to a power-on reset, the memory enters state MRUPD idle 902, in which the memory can perform in-band training using MRUPD, but is idle because it currently has no operations to perform.

[0116] In one example, as an alternative to entering MRUPD IDLE on power-on reset, during debug, commands on the M3C bus (which may be a subset of I3C BASIC)

[0117] In one example, by a multi-cycle chip select (CS) assertion, the memory can move to the state MRUPDADDR 904. In response to the CS assertion, the selected memory device can check the MRUPD address for configuration update. By another CS assertion (which can also be a multi-cycle assertion), the memory moves to the state MRUPD DATA 906, where the memory device obtains data to be written to the address of the previous state.

[0118] In one example, the mode register update written may be an update to disable MRUPD mode. In response to such an update, the memory may enter state MRUPD EXIT 908 and exit from MRUPD mode.

[0119] In one example, MRUPD Idle 902 and MRUPD Data 906 may represent states for a general mode register update. Such a general update is not necessarily associated with enabling training mode. For example, the update may be used for Vref configuration. If Vref is out of range, in one example, the system may recover using the M3C bus.

[0120] In one example, the MRUPD data 906 can trigger CSTM entry 910 using a mode register configuration write to enable CSTM. In one example, upon CS assertion with all CA pins set high (e.g., set to a high logic state), the memory enters state CSTM 912 to perform chip select training. In one example, during CS training, the CA pins can remain high. In one example, during CSTM, no commands are supported. Alternatively, the DRAM device can be prohibited from decoding any commands.

[0121] In one example, in response to CS assertion with all CA pins driven low, the memory may move to state CSTM EXIT 914. In response to exiting CSTM mode, the memory may return to state MRUPD IDLE 902.

[0122] In one example, the MRUPD data 906 can trigger CATM entry 920 using a mode register configuration write to enable CATM. In one example, using a CS assertion (e.g., CA code or CATM command) with the appropriate CA mode on the CA pin, the memory enters state CATM 922 to perform CA bus training. In one example, during CA bus training, the CA pin can be held at the CA code that triggers entry into CATM.

[0123] In one example, in response to a multi-cycle CS assertion with all CA pins driven high, the memory can move to state CATM EXIT 924. In response to exiting CATM mode, the memory can return to state MRUPD IDLE 902.

[0124] Fig.10 1 is a block diagram of an example of a memory subsystem in which an in-band configuration mode can be implemented. System 1000 includes a processor in a computing device and elements of a memory subsystem. System 1000 represents a system having a memory subsystem according to the example of system 100 or the example of system 200 or the example of system 300.

[0125] In one example, system 1000 includes RCD 1072 in memory module 1070. RCD 1072 may have its configuration programmed using in-band register writes according to any description herein. Memory device 1040 may represent a DRAM device, which may have its configuration programmed using in-band register writes according to any description herein.

[0126] Processor 1010 represents a processing unit of a computing platform, which can execute an operating system (OS) and applications, which can be collectively referred to as a host or user of a memory. The OS and applications perform operations that result in memory access. Processor 1010 may include one or more separate processors. Each separate processor may include a single processing unit, a multi-core processing unit, or a combination. The processing unit may be a main processor (e.g., a CPU (central processing unit)), a peripheral processor (e.g., a GPU (graphics processing unit)), or a combination. Memory access may also be initiated by devices such as a network controller or a hard disk controller. In some systems, such a device may be integrated with a processor, or attached to a processor via a bus (e.g., PCI express), or a combination. System 1000 may be implemented as a SOC (system on chip), or may be implemented using independent components.

[0127] References to memory devices may apply to different memory types. Memory devices generally refer to volatile memory technologies. Volatile memory is memory whose state (and therefore the data stored thereon) is uncertain if the power to the device is interrupted. Non-volatile memory refers to memory whose state is determined even if the power to the device is interrupted. Dynamic volatile memory requires refreshing the data stored in the device to maintain the state. An example of dynamic volatile memory includes DRAM (dynamic random access memory) or some variants, such as synchronous DRAM (SDRAM). The memory subsystem described herein can be compatible with a variety of memory technologies, such as DDR4 (Double Data Rate Version 4, JESD79-4, originally released by JEDEC (Joint Electron Device Engineering Council, now JEDEC Solid State Technology Association) in September 2012), LPDDR4 (Low Power DDR Version 4, JESD209-4, originally released by JEDEC in August 2014), WIO2 (Wide I / O 2 (WideIO2), JESD229-2, originally released by JEDEC in August 2014), HBM (High Bandwidth Memory DRAM, JESD235A, originally released by JEDEC in November 2015), DDR5 (DDR Revision 5, originally released by JEDEC in July 2020), LPDDR5 (LPDDR Revision 5, JESD209-5, originally released by JEDEC in February 2019), HBM2 (HBM Revision 2, JESD235C, originally released by JEDEC in January 2020), HBM3 (HBM Revision 3, JESD238, originally released by JEDEC in January 2022), DDR6 (DDR Revision 6, under discussion), GDDR7 (Graphics DDR Revision 7, under discussion), or other or combinations of memory technologies, and technologies based on derivatives or extensions of such specifications.

[0128] Memory controller 1020 represents one or more memory controller circuits or devices for system 1000. In one example, memory controller 1020 is located on the same semiconductor substrate as processor 1010. Memory controller 1020 represents control logic that generates memory access commands in response to operations performed by processor 1010. Memory controller 1020 accesses one or more memory devices 1040. Memory device 1040 can be a DRAM device according to any of the above. In one example, memory device 1040 is organized and managed as different channels, wherein each channel is coupled to a bus and signal lines, which are coupled to multiple memory devices in parallel. Each channel is independently operable. Therefore, each channel is independently accessed and controlled, and the timing, data transmission, command and address exchange, and other operations for each channel are separated. Coupling can refer to electrical coupling, communication coupling, physical coupling, or a combination of these. Physical coupling can include direct contact. Electrical coupling includes interfaces or interconnections that allow current to flow between components, or allow components to be notified with signals, or both. A communicative coupling includes a connection (including wired or wireless) that enables the components to exchange data.

[0129] In one example, the settings for each channel are controlled by separate mode registers or other register settings. In one example, each memory controller 1020 manages a separate memory channel, although the system 1000 can be configured to have multiple channels managed by a single controller, or to have multiple controllers on a single channel. In one example, the memory controller 1020 is part of the host processor 1010, such as logic implemented on the same die or in the same package space as the processor.

[0130] The memory controller 1020 includes an I / O interface logic 1022 to couple to a memory bus, such as a memory channel as referred to above. The I / O interface logic 1022 (and the I / O interface logic 1042 of the memory device 1040) may include pins, pads, connectors, signal lines, traces, or wires, or other hardware for connecting devices, or a combination of these. The I / O interface logic 1022 may include a hardware interface. As shown, the I / O interface logic 1022 includes at least a driver / transceiver for a signal line. Typically, the lines within the integrated circuit interface are coupled to pads, pins, or connectors to engage with signal lines or traces or other lines between devices. The I / O interface logic 1022 may include a driver, a receiver, a transceiver, or a terminal, or other circuit systems or combinations of circuit systems to exchange signals on signal lines between devices. Signal exchange includes at least one of sending or receiving. Although I / O 1022 from memory controller 1020 is shown coupled to I / O 1042 of memory device 1040, it is understood that in implementations of system 1000 where groups of memory devices 1040 are accessed in parallel, multiple memory devices may include I / O interfaces to the same interface of memory controller 1020. In implementations of system 1000 that include one or more memory modules 1070, I / O 1042 may include interface hardware for the memory modules in addition to interface hardware on the memory devices themselves. Other memory controllers 1020 will include separate interfaces to other memory devices 1040.

[0131] The bus between the memory controller 1020 and the memory device 1040 can be implemented as a plurality of signal lines that couple the memory controller 1020 to the memory device 1040. The bus can typically include at least a clock (CLK) 1032, a command / address (CMD) 1034, a data (DQ) 1036, and zero or more other signal lines 1038. In one example, the bus or connection between the memory controller 1020 and the memory can be referred to as a memory bus. In one example, the memory bus is a multi-drop bus. The signal line for CMD can be referred to as a "C / A bus" (or an ADD / CMD bus, or some other name indicating the transmission of command (C or CMD) and address (A or ADD) information), and the signal line for writing and reading DQ can be referred to as a "data bus". In one example, independent channels have different clock signals, C / A buses, data buses, and other signal lines. Therefore, the system 1000 can be considered to have multiple "buses", that is, independent interface paths can be considered as separate buses. It is understood that, in addition to the lines clearly shown, the bus may include at least one of a gate command line, an alarm line, an auxiliary line, or other signal lines, or a combination thereof. It is also understood that serial bus technology can be used for the connection between the memory controller 1020 and the memory device 1040. An example of serial bus technology is to encode and transmit high-speed data with an embedded clock in each direction by a single differential signal. In one example, CMD 1034 represents a signal line shared in parallel with multiple memory devices. In one example, multiple memory devices share the encoding command signal line of CMD 1034, and each memory device has a separate chip select (CS_n) signal line to select each memory device.

[0132] It should be understood that in the example of system 1000, the bus between the memory controller 1020 and the memory device 1040 includes an auxiliary command bus CMD 1034 and an auxiliary bus DQ 1036 for carrying write and read data. In one example, the data bus may include a bidirectional line for reading data and for writing / command data. In another example, the auxiliary bus DQ 1036 may include a unidirectional write signal line for writing and data from the host to the memory, and may include a unidirectional line for reading data from the memory to the host. Depending on the selected memory technology and system design, other signals 1038 may accompany the bus or sub-bus, such as a strobe line DQS. Based on the design of the system 1000, or if the design supports multiple implementations, the data bus may have more or less bandwidth for each memory device 1040 based on the implementation. For example, the data bus may support memory devices with x4 interfaces, x8 interfaces, x16 interfaces, or other interfaces. The convention "xW" represents the number of signal lines that exchange data with the memory controller 1020, where W is an integer that refers to the size of the interface of the memory device 1040 or the width of the interface. The interface size of the memory device is a controlling factor for how many memory devices can be used simultaneously or coupled in parallel to the same signal line per channel in the system 1000. In one example, a high bandwidth memory device, a wide interface device, or a stacked memory configuration, or a combination thereof, can enable a wider interface, such as a x128 interface, a x256 interface, a x512 interface, a x1024 interface, or other data bus interface widths.

[0133] In one example, the memory device 1040 and the memory controller 1020 exchange data through the data bus in a sequence of bursts or continuous data transfers. The burst corresponds to the number of transfer cycles, which is related to the bus frequency. In one example, the transfer cycle can be the entire clock cycle of the transfer that occurs on the same clock or selection signal edge (e.g., on the rising edge). In one example, each clock cycle (referring to the cycle of the system clock) is divided into a plurality of unit intervals (UI), wherein each UI is a transfer cycle. For example, double data rate transfer is triggered on two edges (e.g., rising and falling edges) of the clock signal. The burst can be continuously configured for the number of UIs, which can be a configuration stored in a register, or triggered instantly. For example, a sequence of eight continuous transfer cycles can be regarded as a burst length of eight (BL8), and each memory device 1040 can transfer data on each UI. Therefore, an x8 memory device operating on BL8 can transfer 64 bits of data (8 data signal lines multiplied by 8 data bits transmitted by each line in the burst). It can be understood that this simple example is only an illustration and is not a limitation.

[0134] Memory devices 1040 represent memory resources for system 1000. In one example, each memory device 1040 is a separate memory die. In one example, each memory device 1040 can be coupled to multiple (e.g., 2) channels of each device or die. Each memory device 1040 includes I / O interface logic 1042, which has a bandwidth determined by the implementation of the device (e.g., x16 or x8 or some other interface bandwidth). I / O interface logic 1042 enables the memory device to be coupled to memory controller 1020. I / O interface logic 1042 may include a hardware interface and may be consistent with I / O 1022 of the memory controller, but at the memory device end. In one example, multiple memory devices 1040 are connected in parallel to the same command and data bus. In another example, multiple memory devices 1040 are connected in parallel to the same command bus and to different data buses. For example, system 1000 may be configured with multiple parallel coupled memory devices 1040, each memory device responds to commands, and accesses memory resources 1060 inside each memory device. For a write operation, a single memory device 1040 may write a portion of an overall data word, and for a read operation, a single memory device 1040 may obtain a portion of an overall data word. The remaining bits of the word will be provided or received in parallel by other memory devices.

[0135] In one example, the memory device 1040 is directly disposed on a motherboard or host system platform of a computing device (e.g., a PCB (printed circuit board) or substrate on which the processor 1010 is disposed). In one example, the memory device 1040 may be organized into a memory module 1070. In one example, the memory module 1070 represents a dual in-line memory module (DIMM). In one example, the memory module 1070 represents other organizations of multiple memory devices to share at least a portion of the access or control circuit system, which may be a circuit, a separate device, or a separate board separate from the host system platform. The memory module 1070 may include multiple memory devices 1040, and the memory module may include support for multiple separate channels of the included memory devices disposed thereon. In another example, the memory device 1040 may be incorporated into the same package as the memory controller 1020, for example, by technologies such as multi-chip modules (MCM), package-on-package, through silicon vias (TSV), or other technologies or combinations. Similarly, in one example, multiple memory devices 1040 can be incorporated into a memory module 1070, which itself can be incorporated into the same package as the memory controller 1020. It can be appreciated that for these and other implementations, the memory controller 1020 can be part of the host processor 1010.

[0136] Each memory device 1040 includes one or more memory arrays 1060. The memory array 1060 represents an addressable memory location or storage location of data. Typically, the memory array 1060 is managed as a data row, and access is controlled via word lines (rows) and bit lines (individual bits within a row). The memory array 1060 can be organized into separate memory channels, memory ranks, and memory banks. A channel can refer to an independent control path to a storage location within a memory device 1040. A storage rank can refer to a common location across multiple memory devices in parallel (e.g., the same row address within different devices). A storage bank can refer to a sub-array of memory locations within a memory device 1040. In one example, a storage bank of a memory is divided into sub-storage banks, wherein the sub-storage banks have at least a portion of a shared circuit system (e.g., a driver, a signal line, a control logic), thereby allowing separate addressing and access. It can be understood that channels, storage ranks, storage banks, sub-storage banks, storage bank groups, or other organizations of memory locations, and combinations of these organizations can overlap when applied to physical resources. For example, the same physical memory location as a specific memory bank can be accessed through a specific channel, and the specific memory bank can also belong to a memory rank. Therefore, the organization of memory resources is to be understood in an inclusive rather than exclusive manner.

[0137] In one example, the memory device 1040 includes one or more registers 1044. Register 1044 represents one or more storage devices or storage locations that provide configuration or settings for the operation of the memory device. In one example, register 1044 can provide a storage location for the memory device 1040 to store data for access by the memory controller 1020 as part of a control or management operation. In one example, register 1044 includes one or more mode registers. In one example, register 1044 includes one or more multi-purpose registers. The location configuration within register 1044 can configure the memory device 1040 to operate in different "modes", where command information can trigger different operations within the memory device 1040 based on the mode. In addition or as an alternative, different modes can also trigger different operations from address information or other signal lines depending on the mode. The settings of register 1044 can indicate the configuration of I / O settings (e.g., timing, termination or ODT (on-die termination) 1046, driver configuration, or other I / O settings).

[0138] In one example, the memory device 1040 includes an ODT 1046 as part of the interface hardware associated with the I / O 1042. The ODT 1046 can be configured as described above and provides impedance settings for the interface to be applied to a specified signal line. In one example, the ODT 1046 is applied to the DQ signal line. In one example, the ODT 1046 is applied to the command signal line. In one example, the ODT 1046 is applied to the address signal line. In one example, the ODT 1046 can be applied to any combination of the foregoing. The ODT setting can be changed based on whether the memory device is a selected target or a non-target device for the access operation. The ODT 1046 setting can affect the timing and reflection of the signaling on the terminated line. Careful control of the ODT 1046 can achieve higher speed operation while improving the matching of the applied impedance and load. The ODT 1046 can be applied to specific signal lines of the I / O interface 1042, 1022 (e.g., ODT for DQ lines or ODT for CA lines), and is not necessarily applied to all signal lines.

[0139] The memory device 1040 includes a controller 1050, which represents the control logic within the memory device for controlling the internal operation within the memory device. For example, the controller 1050 decodes the command sent by the memory controller 1020 and generates internal operations to execute or satisfy the command. The controller 1050 can be referred to as an internal controller and is separated from the memory controller 1020 of the host. The controller 1050 can determine which mode to select based on the register 1044, and configure the internal execution of the operation or other operation for accessing the memory resource 1060 based on the selected mode. The controller 1050 generates a control signal to control the bit routing within the memory device 1040, thereby providing an appropriate interface for the selected mode and directing the command to the appropriate memory location or address. The controller 1050 includes a command logic 1052, which can decode the command encoding received on the command and address signal lines. Therefore, the command logic 1052 can be or include a command decoder. Using the command logic 1052, the memory device can identify the command and generate internal operations to execute the requested command.

[0140] Referring again to the memory controller 1020, the memory controller 1020 includes command (CMD) logic 1024, which represents the logic or circuit system that generates commands to send to the memory device 1040. The generation of commands can refer to the command before scheduling, or the queued command that is ready to be sent. In general, the signaling in the memory subsystem includes address information within or accompanying the command to indicate or select one or more memory locations where the memory device should execute the command. In response to the transaction scheduling of the memory device 1040, the memory controller 1020 can issue a command via I / O 1022 to cause the memory device 1040 to execute the command. In one example, the controller 1050 of the memory device 1040 receives and decodes the command and address information received from the memory controller 1020 via I / O 1042. Based on the received command and address information, the controller 1050 can control the operation timing of the logic and circuit system within the memory device 1040 to execute the command. The controller 1050 is responsible for complying with the standards or specifications within the memory device 1040, such as timing and signaling requirements. The memory controller 1020 may implement compliance with standards or specifications through access scheduling and control.

[0141] The memory controller 1020 includes a scheduler 1030, which represents a logic or circuit system for generating transactions and ordering transactions to be sent to the memory device 1040. From one perspective, the main function of the memory controller 1020 can be said to be to schedule memory access and other transactions to the memory device 1040. Such scheduling may include generating the transaction itself to implement the processor 1010 request for data and maintain the integrity of the data (e.g., such as commands related to refresh). A transaction may include one or more commands and result in the transmission of commands or data or both within one or more timing cycles (e.g., clock cycles or unit intervals). Transactions may be used for access (e.g., read or write or related commands or combinations), and other transactions may include memory management commands for configuration, setup, data integrity, or other commands or combinations.

[0142] The memory controller 1020 typically includes logic such as a scheduler 1030 to allow transactions to be selected and ordered to improve the performance of the system 1000. Thus, the memory controller 1020 can select which outstanding transactions should be sent to the memory device 1040 in what order, which is typically achieved by logic that is much more complex than a simple first-in, first-out algorithm. The memory controller 1020 manages the transmission of transactions to the memory device 1040 and manages the timing associated with the transactions. In one example, the transactions have deterministic timing, which can be managed by the memory controller 1020 and used to determine how to schedule transactions using the scheduler 1030.

[0143] In one example, the memory controller 1020 includes refresh (REF) logic 1026. The refresh logic 1026 can be used for memory resources that are volatile and need to be refreshed to maintain a deterministic state. In one example, the refresh logic 1026 indicates the location of the refresh and the type of refresh to be performed. The refresh logic 1026 can trigger a self-refresh within the memory device 1040, or perform an external refresh (which can be referred to as an automatic refresh command) by sending a refresh command, or a combination. In one example, the controller 1050 within the memory device 1040 includes refresh logic 1054 to apply refresh within the memory device 1040. In one example, the refresh logic 1054 generates internal operations to perform refresh based on the external refresh received from the memory controller 1020. The refresh logic 1054 can determine whether the refresh is for the memory device 1040, and which memory resources 1060 to refresh in response to the command.

[0144] Fig.111 is a block diagram of an example of a computing system in which an in-band configuration mode can be implemented. System 1100 represents a computing device according to any example herein, and can be a laptop computer, a desktop computer, a tablet computer, a server, a game or entertainment control system, an embedded computing device, or other electronic device. System 1100 represents a system with a storage device according to the example of system 100 or the example of system 200 or the example of system 300.

[0145] In one example, system 1100 includes a memory subsystem 1120, wherein RCD 1124 is located in a memory module. The configuration of RCD 1124 can be programmed using in-band register writes according to any description herein. Memory 1130 can represent a DRAM device, whose configuration can be programmed using in-band register writes according to any description herein. In-band configuration (CONFIG) 1190 represents a component that enables the system to perform in-band register configuration updates in update mode.

[0146] The system 1100 includes a processor 1110, which may include any type of microprocessor, central processing unit (CPU), graphics processing unit (GPU), processing core, or other processing hardware, or combination, to provide processing or execution of instructions for the system 1100. The processor 1110 may be a host processor device. The processor 1110 controls the overall operation of the system 1100 and may be or include one or more programmable general or special purpose microprocessors, digital signal processors (DSPs), programmable controllers, application specific integrated circuits (ASICs), programmable logic devices (PLDs), or combinations of these devices.

[0147] The system 1100 includes a boot / configuration 1116, which represents a storage device for storing boot code (e.g., a basic input / output system (BIOS)), configuration settings, security hardware (e.g., a trusted platform module (TPM)), or other system-level hardware operating outside of a host OS. The boot / configuration 1116 may include a non-volatile storage device, such as a read-only memory (ROM), flash memory, or other memory device.

[0148] In one example, the system 1100 includes an interface 1112 coupled to the processor 1110, which may represent a higher speed interface or a high throughput interface for system components (e.g., a memory subsystem 1120 or a graphics interface component 1140) that require a higher bandwidth connection. The interface 1112 represents an interface circuit, which may be an independent component or integrated onto a processor die. The interface 1112 may be integrated onto a processor die as a circuit or integrated onto a system on a chip as a component. If present, the graphics interface 1140 is coupled to the graphics component to provide a visual display to a user of the system 1100. The graphics interface 1140 may be an independent component or integrated onto a processor die or a system on a chip. In one example, the graphics interface 1140 may drive a high definition (HD) display or an ultra high definition (UHD) display to provide output to the user. In one example, the display may include a touch screen display. In one example, the graphics interface 1140 generates a display based on data stored in the memory 1130, or based on operations performed by the processor 1110, or both.

[0149] Memory subsystem 1120 represents the main memory of system 1100 and provides storage for data values ​​to be used when executing code or routines executed by processor 1110. Memory subsystem 1120 may include one or more random access memories (RAM), such as DRAM, 3DXP (three-dimensional crosspoint), or other memory devices, or a combination of these devices. Memory 1130 stores and hosts operating system (OS) 1132 and other things to provide a software platform for executing instructions in system 1100. Additionally, application 1134 can be executed on the software platform of OS1132 from memory 1130. Application 1134 represents a program with its own operating logic to perform one or more functions. Process 1136 represents an agent or routine that provides auxiliary functions to OS1132 or one or more applications 1134 or a combination. OS1132, application 1134, and process 1136 provide software logic to provide functions for system 1100. In one example, the memory subsystem 1120 includes a memory controller 1122, which is a memory controller for generating commands and issuing commands to the memory 1130. It is understood that the memory controller 1122 can be a physical part of the processor 1110 or a physical part of the interface 1112. For example, the memory controller 1122 can be an integrated memory controller, integrated into a circuit with the processor 1110, such as integrated into a processor die or a system on a chip.

[0150] Although not specifically described, it is understood that the system 1100 may include one or more buses or bus systems between devices, such as a memory bus, a graphics bus, an interface bus, etc. A bus or other signal line may couple components together in a communicative or electrical manner, or couple components in a communicative and electrical manner. A bus may include a physical communication line, a point-to-point connection, a bridge, an adapter, a controller, or other circuit systems or combinations. For example, a bus may include a system bus, a peripheral component interconnect (PCI) bus, a HyperTransport or industry standard architecture (ISA) bus, a small computer system interface (SCSI) bus, a universal serial bus (USB), or one or more of other buses, or a combination thereof.

[0151] In one example, system 1100 includes an interface 1114, which can be coupled to interface 1112. Interface 1114 can be an interface with a lower speed than interface 1112. In one example, interface 1114 represents an interface circuit, which can include independent components and integrated circuit systems. In one example, multiple user interface components or peripheral components or both are coupled to interface 1114. Network interface 1150 provides system 1100 with the ability to communicate with remote devices (e.g., servers or other computing devices) through one or more networks. Network interface 1150 may include an Ethernet adapter, a wireless interconnect component, a cellular network interconnect component, a USB (universal serial bus), or other wired or wireless standard-based or proprietary interfaces. Network interface 1150 can exchange data with a remote device, which can include sending data stored in a memory or receiving data to be stored in a memory.

[0152] In one example, the system 1100 includes one or more input / output (I / O) interfaces 1160. The I / O interfaces 1160 may include one or more interface components through which a user interacts with the system 1100 (e.g., audio, alphanumeric, tactile / touch, or other interfaces). The peripheral interfaces 1170 may include any hardware interface not specifically mentioned above. Peripheral devices generally refer to devices that are dependently connected to the system 1100. A dependent connection is a connection in which the system 1100 provides a software platform or a hardware platform, or both, on which operations are performed and with which a user interacts.

[0153] In one example, the system 1100 includes a storage subsystem 1180 for storing data in a non-volatile manner. In one example, in a particular system implementation, at least certain components of the storage device 1180 may overlap with components of the memory subsystem 1120. The storage subsystem 1180 includes a storage device 1184, which may be or include any conventional media for storing large amounts of data in a non-volatile manner, such as one or more magnetic, solid-state, NAND, 3DXP, or optical disks, or a combination thereof. The storage device 1184 saves code or instructions and data 1186 in a persistent state (i.e., the value is retained even if power to the system 1100 is interrupted). The storage device 1184 can be generally considered to be "memory", although the memory 1130 is typically an execution or operating memory for providing instructions to the processor 1110. Although the storage device 1184 is non-volatile, the memory 1130 may include volatile memory (i.e., if power to the system 1100 is interrupted, the value or state of the data is uncertain). In one example, storage subsystem 1180 includes controller 1182 for interfacing with storage device 1184. In one example, controller 1182 is a physical part of interface 1114 or processor 1110, or may include circuitry or logic in both processor 1110 and interface 1114.

[0154] The power source 1102 provides power to the components of the system 1100. More specifically, the power source 1102 is typically coupled to one or more power supplies 1104 in the system 1100 for powering the components of the system 1100. In one example, the power supply 1104 includes an AC to DC (alternating current to direct current) adapter for plugging into a wall outlet. This AC power can be a renewable energy (e.g., solar) power source 1102. In one example, the power source 1102 includes a DC power source, such as an external AC to DC converter. In one example, the power source 1102 or the power supply 1104 includes wireless charging hardware for charging via proximity to a charging field. In one example, the power source 1102 can include an internal battery or fuel cell source.

[0155] Fig.12 1 is a block diagram of an example of a multi-node network in which an in-band configuration mode can be implemented. System 1200 represents a network of nodes to which adaptive ECC can be applied. In one example, system 1200 represents a data center. In one example, system 1200 represents a server cluster. In one example, system 1200 represents a data cloud or a processing cloud.

[0156] System 1200 represents a system with a storage device according to the example of system 100 or the example of system 200 or the example of system 300. In one example, memory node 1222 includes a memory module (not specifically shown) with an RCD. The configuration of the RCD can be programmed using in-band register writes according to any description herein, as represented by in-band configuration (CONFIG) 1292. System 1200 may include a memory device according to the contents described, and in-band configuration (CONFIG) 1290 represents the ability to program the RCD and / or memory device using in-band register writes according to any description herein.

[0157] One or more clients 1202 send requests to the system 1200 through the network 1204. The network 1204 represents one or more local networks, or wide area networks, or a combination. The client 1202 can be a human or machine client that generates a request for the system 1200 to perform an operation. The system 1200 performs the application or data computing task requested by the client 1202.

[0158] In one example, system 1200 includes one or more racks, which represent structural and interconnection resources for housing and interconnecting multiple computing nodes. In one example, rack 1210 includes multiple nodes 1230. In one example, rack 1210 hosts multiple blade components, blade 1220[0], ..., blade 1220[N-1], collectively referred to as blade 1220. Hosting refers to providing power, structural or mechanical support, and interconnection. Blade 1220 can refer to computing resources on a printed circuit board (PCB), wherein the PCB houses hardware components for one or more nodes 1230. In one example, blade 1220 does not include a chassis or housing or other "box" other than that provided by rack 1210. In one example, blade 1220 includes a housing with exposed connectors to connect to rack 1210. In one example, system 1200 does not include rack 1210, and each blade 1220 includes a chassis or housing that can be stacked or otherwise reside near other blades and allow interconnection of nodes 1230.

[0159] The system 1200 includes a fabric 1270, which represents one or more interconnects for the nodes 1230. In one example, the fabric 1270 includes a plurality of switches 1272 or routers or other hardware for routing signals between the nodes 1230. Additionally, the fabric 1270 can couple the system 1200 to a network 1204 for access by clients 1202. In addition to routing devices, the fabric 1270 can be considered to include cables or ports or other hardware devices to couple the nodes 1230 together. In one example, the fabric 1270 has one or more associated protocols for managing the routing of signals through the system 1200. In one example, the one or more protocols rely, at least in part, on the hardware devices used in the system 1200.

[0160] As shown, rack 1210 includes N blades 1220. In one example, in addition to rack 1210, system 1200 also includes rack 1250. As shown, rack 1250 includes M blade assemblies, blade 1260[0], ..., blade 1260[M-1], collectively referred to as blades 1260. M is not necessarily the same as N; therefore, it should be understood that a variety of different hardware device components can be used and coupled to system 1200 through structure 1270. Blade 1260 can be the same as or similar to blade 1220. Node 1230 can be any type of node, and is not necessarily all nodes of the same type. System 1200 is not limited to homogeneity, nor is it limited to non-homogeneity.

[0161] The nodes in the system 1200 may include computing nodes, memory nodes, storage nodes, accelerator nodes, or other nodes. The rack 1210 is represented by a memory node 1222 and a storage node 1224, which represent shared system memory resources and shared persistent storage devices, respectively. One or more nodes of the rack 1250 may be a memory node or a storage node.

[0162] Node 1230 represents an example of a computing node. For simplicity, only the computing nodes in blade 1220[0] are shown in detail. However, other nodes in system 1200 can be the same or similar. At least some of nodes 1230 are computing nodes, having a processor (proc) 1232 and a memory 1240. A computing node refers to a node having processing resources (e.g., one or more processors) that executes an operating system and can receive and process one or more tasks. In one example, at least some of nodes 1230 are server nodes, where a server is a processing resource represented by processor 1232 and memory 1240.

[0163] Memory node 1222 represents an example of a memory node whose system memory is located outside the compute node. The memory node may include a controller 1282, which represents a processor on the node for managing access to memory. The memory node includes memory 1284 as a memory resource to be shared between multiple compute nodes.

[0164] Storage node 1224 represents an example of a storage server, which refers to a node that has more storage resources than a computing node, and the storage server does not have a processor for performing tasks, but includes processing resources for managing access to storage nodes within the storage server. The storage node may include a controller 1286 for managing access to the storage device 1288 of the storage node.

[0165] In one example, node 1230 includes an interface controller 1234, which represents the logic for controlling node 1230's access to structure 1270. The logic may include hardware resources for interconnecting to physical interconnect hardware. The logic may include software or firmware logic for managing interconnections. In one example, interface controller 1234 is or includes a host fabric interface, which may be a fabric interface according to any example described herein. Interface controllers for memory nodes 1222 and storage nodes 1224 are not explicitly shown.

[0166] Processor 1232 may include one or more individual processors. Each individual processor may include a single processing unit, a multi-core processing unit, or a combination. The processing unit may be a main processor, such as a CPU (central processing unit), a peripheral processor, such as a GPU (graphics processing unit), or a combination. Memory 1240 may be or include a memory device represented by memory 1240 and a memory controller represented by controller 1242.

[0167] In one aspect, an apparatus includes: a hardware interface for interfacing with a command bus, the hardware interface for receiving a configuration register update mode command to trigger entry into a configuration register update mode; a decision feedback equalization (DFE) configuration register storing a first configuration setting for the hardware interface to the command bus; and a second configuration register for configuration settings other than the DFE, the second configuration register storing a second configuration setting for the hardware interface to the command bus; wherein the apparatus is configured to update the second configuration register using an in-band register write in the configuration register update mode.

[0168] In one example of the apparatus, the in-band register write avoids using sideband bus communication to update the second configuration register. According to any previous example of the apparatus, in one example, the configuration register update mode includes a training mode for training all configuration registers. According to any previous example of the apparatus, in one example, the configuration register update mode includes a register word update (RWUPD) mode for registering a clock driver (RCD). According to any previous example of the apparatus, in one example, the in-band register write includes a register word (RW) write based on a command on a command bus without using a system management bus (SMBus). According to any previous example of the apparatus, in one example, the in-band register write includes a register word (RW) write based on a command on a command bus, in combination with using a system management bus (SMBus). According to any previous example of the apparatus, in one example, the configuration register update mode includes a mode register update (MRUPD) mode of a dynamic random access memory (DRAM) device. According to any previous example of the apparatus, in one example, the in-band register write includes a mode register write (MRW) based on a command on the command bus before executing a chip select training mode (CSTM). According to any of the preceding examples of the apparatus, in one example, the in-band register write includes a mode register write (MRW) based on a command on a command bus prior to executing a command / address training mode (CATM). According to any of the preceding examples of the apparatus, in one example, the in-band register write avoids using a multi-purpose command (MPC) to train a DFE configuration register and a second configuration register. According to any of the preceding examples of the apparatus, in one example, the configuration register update mode command includes a first multi-purpose command (MPC) for entering a configuration register update mode, and also includes a second MPC for exiting the configuration register update mode.

[0169] In one aspect, a first computer system includes: a memory controller, the memory controller is coupled to a command bus; and a memory chip, the memory chip is coupled to the command bus using a command bus interface, the memory chip receives a configuration register update mode command from the memory controller to trigger the memory chip to enter a configuration register update mode, the memory chip includes: a decision feedback equalization (DFE) configuration register, which stores a first configuration setting for the command bus interface; and a second configuration register for configuration settings other than the DFE, the second configuration register stores a second configuration setting for the command bus interface; and wherein the memory chip updates the second configuration register using in-band register writes in the configuration register update mode.

[0170] In an example of the first computer system of claim 12, wherein the in-band register write avoids using sideband bus communication to update the second configuration register. According to any of the foregoing examples of the first computer system, in one example, the memory chip includes a registered clock driver (RCD), and wherein the configuration register update mode includes a register word update (RWUPD) mode for the RCD. According to any of the foregoing examples of the first computer system, in one example, the in-band register write includes a register word (RW) write based on a command on a command bus without using a system management bus (SMBus). According to any of the foregoing examples of the first computer system, in one example, the in-band register write includes a register word (RW) write based on a command on a command bus, in combination with using a system management bus (SMBus). According to any of the foregoing examples of the first computer system, in one example, the memory chip includes a dynamic random access memory (DRAM) device, and wherein the configuration register update mode includes a mode register update (MRUPD) mode for the DRAM device. According to any of the foregoing examples of the first computer system, in one example, the in-band register write includes a mode register write (MRW) based on a command on the command bus before executing a chip select training mode (CSTM) and before executing a command / address training mode (CATM). According to any of the foregoing examples of the first computer system, in one example, the in-band register write avoids using a multi-purpose command (MPC) to train the DFE configuration register and the second configuration register. According to any of the foregoing examples of the first computer system, in one example, the first computer system includes one or more of the following: a host processor device, the host processor device is coupled to a memory controller; a display, the display is communicatively coupled to a host processor coupled to the memory controller; a network interface, the network interface is communicatively coupled to a host processor coupled to the memory controller; or a battery, the battery powers the computer system.

[0171] In one aspect, a first method includes: in a device having a decision feedback equalization (DFE) configuration register, the device storing a first configuration setting for a hardware interface to a command bus, and a second configuration register for configuration settings other than the DFE, the second configuration register storing a second configuration setting for the hardware interface to the command bus, receiving a configuration register update mode command to trigger entry into a configuration register update mode; and updating the second configuration register using an in-band register write in the configuration register update mode.

[0172] In one example of the first method, the in-band register write avoids using sideband bus communication to update the second configuration register. According to any of the foregoing examples of the first method, in one example, the configuration register update mode includes a training mode for training all configuration registers. According to any of the foregoing examples of the first method, in one example, the configuration register update mode includes a register word update (RWUPD) mode for registering a clock driver (RCD). According to any of the foregoing examples of the first method, in one example, the in-band register write includes a register word (RW) write based on a command on a command bus without using a system management bus (SMBus). According to any of the foregoing examples of the first method, in one example, the in-band register write includes a register word (RW) write based on a command on a command bus, in combination with using a system management bus (SMBus). According to any of the foregoing examples of the first method, in one example, the configuration register update mode includes a mode register update (MRUPD) mode for a dynamic random access memory (DRAM) device. According to any of the foregoing examples of the first method, in one example, the in-band register write includes a mode register write (MRW) based on a command on the command bus before executing a chip select training mode (CSTM). According to any of the preceding examples of the first method, in one example, the in-band register write includes a mode register write (MRW) based on a command on the command bus prior to executing a command / address training mode (CATM). According to any of the preceding examples of the first method, in one example, the in-band register write avoids using a multi-purpose command (MPC) to train the DFE configuration register and the second configuration register. According to any of the preceding examples of the first method, in one example, the configuration register update mode command includes a first multi-purpose command (MPC) for entering a configuration register update mode, and also includes a second MPC for exiting the configuration register update mode.

[0173] In one aspect, a registered clock driver (RCD) includes: a hardware interface for interfacing with a command bus, the hardware interface being used to receive a command to trigger entry into a register word update (RWUPD) mode; and a register word for configuration settings other than a decision feedback equalization (DFE) configuration, the register word storing configuration settings for the hardware interface to the command bus; wherein the RCD is used to update the register word using in-band register writes in the RWUPD mode.

[0174] In one example of the RCD, in-band register writes avoid using sideband bus communications to update register words. According to any of the foregoing examples of the RCD, in one example, the RWUPD mode includes a training mode configured for all register words. According to any of the foregoing examples of the RCD, in one example, the in-band register writes include register word (RW) writes based on commands on a command bus without using a system management bus (SMBus). According to any of the foregoing examples of the RCD, in one example, the in-band register writes include register word (RW) writes based on commands on a command bus in combination with using a system management bus (SMBus).

[0175] In one aspect, the second computer system includes: a memory controller coupled to a command bus; and a dual in-line memory module (DIMM) having a registered clock driver (RCD) coupled to the command bus via a command bus interface, the RCD receiving a command to trigger entry into a register word update (RWUPD) mode, the RCD including: register words for configuration settings other than decision feedback equalization (DFE) configuration, the register words storing configuration settings for a hardware interface to the command bus; wherein the RCD is used to update the register words using in-band register writes in the RWUPD mode.

[0176] In one example of the second computer system, the in-band register write avoids using sideband bus communications to update register words. According to any of the foregoing examples of the second computer system, in one example, the in-band register write includes a register word (RW) write based on a command on a command bus without using a system management bus (SMBus). According to any of the foregoing examples of the second computer system, in one example, the in-band register write includes a register word (RW) write based on a command on the command bus, in combination with using a system management bus (SMBus). According to any of the foregoing examples of the second computer system, in one example, the in-band register write includes a mode register write (MRW) based on a command on the command bus before executing a chip select training mode (CSTM) and before executing a command / address training mode (CATM). According to any of the foregoing examples of the second computer system, in one example, the in-band register write avoids using a multi-purpose command (MPC) to configure register words. Based on any of the preceding examples of the second computer system, in one example, the second computer system includes one or more of: a host processor device coupled to a memory controller; a display communicatively coupled to the host processor coupled to the memory controller; a network interface communicatively coupled to the host processor coupled to the memory controller; or a battery to power the computer system.

[0177] In one aspect, a second method includes: in a registered clock driver (RCD) having a configuration register that stores a second configuration setting other than decision feedback equalization (DFE) for a hardware interface to a command bus, receiving a command to trigger entry into a register word update (RWUPD) mode; and updating a register word using an in-band register write in the RWUPD mode.

[0178] In one example of the second method, the in-band register write avoids using sideband bus communications to update the register word. According to any of the foregoing examples of the second method, in one example, the RWUPD mode includes a training mode for all register word configurations. According to any of the foregoing examples of the second method, in one example, the in-band register write includes a register word (RW) write based on a command on a command bus without using a system management bus (SMBus). According to any of the foregoing examples of the second method, in one example, the in-band register write includes a register word (RW) write based on a command on a command bus in combination with using a system management bus (SMBus).

[0179] In one aspect, a dynamic random access memory (DRAM) device includes: a hardware interface for interfacing with a command bus, the hardware interface for receiving a command to trigger entry into a mode register update (MRUPD) mode; and a mode register for configuration settings other than a decision feedback equalization (DFE) configuration, the mode register storing configuration settings for the hardware interface to the command bus; wherein the DRAM device is used to update the mode register using in-band register writes in the MRUPD mode.

[0180] In one example of the DRAM, in-band register writes avoid using sideband bus communications to update mode registers. According to any of the foregoing examples of the DRAM, in one example, the MRUPD mode includes a training mode for all mode register configurations. According to any of the foregoing examples of the DRAM, in one example, the in-band register writes include a mode register write (MRW) based on a command on a command bus without using a sideband bus. According to any of the foregoing examples of the DRAM, in one example, the sideband bus includes a memory module management control (M3C) bus. According to any of the foregoing examples of the DRAM, in one example, the in-band register writes include a mode register write (MRW) based on a command on the command bus, in combination with using a sideband bus. According to any of the foregoing examples of the DRAM, in one example, the sideband bus includes a memory module management control (M3C) bus. According to any of the foregoing examples of the DRAM, in one example, the in-band register writes include a mode register write (MRW) based on a command on the command bus before executing a chip select training mode (CSTM). According to any of the foregoing examples of the DRAM, in one example, the in-band register writes include a mode register write (MRW) based on a command on the command bus before executing a command / address training mode (CATM). According to any of the foregoing examples of DRAM, in one example, the in-band register write avoids using a multi-purpose command (MPC) to configure the mode register. According to any of the foregoing examples of DRAM, in one example, the command includes a first multi-purpose command (MPC) for entering MRUPD mode and also includes a second MPC for exiting MRUPD mode.

[0181] In one aspect, a third computer system includes: a memory controller coupled to a command bus; and a dynamic random access memory (DRAM) device coupled to the command bus using a command bus interface, the DRAM device receiving a command from the memory controller to trigger entry into a mode register update (MRUPD) mode, the DRAM device including: a mode register for configuration settings other than a decision feedback equalization (DFE) configuration, the mode register storing configuration settings for a hardware interface to the command bus; wherein the DRAM device is used to update the mode register using in-band register writes in the MRUPD mode.

[0182] In one example of the third computer system, the in-band register write avoids using sideband bus communications to update the mode register. According to any of the foregoing examples of the third computer system, in one example, the MRUPD mode includes a training mode for all mode register configurations. According to any of the foregoing examples of the third computer system, in one example, the in-band register write includes a register word (RW) write based on a command on a command bus without using a sideband bus. According to any of the foregoing examples of the third computer system, in one example, the sideband bus includes a memory module management control (M3C) bus. According to any of the foregoing examples of the third computer system, in one example, the in-band register write includes a mode register write (MRW) based on a command on the command bus, in combination with using a sideband bus. According to any of the foregoing examples of the third computer system, in one example, the sideband bus includes a memory module management control (M3C) bus. According to any of the foregoing examples of the third computer system, in one example, the in-band register write includes a mode register write (MRW) based on a command on the command bus before executing a chip select training mode (CSTM). According to any of the foregoing examples of the third computer system, in one example, the in-band register write includes a mode register write (MRW) based on a command on the command bus prior to executing a command / address training mode (CATM). According to any of the foregoing examples of the third computer system, in one example, the in-band register write avoids using a multi-purpose command (MPC) to configure the mode register. According to any of the foregoing examples of the third computer system, in one example, the command includes a first multi-purpose command (MPC) for entering MRUPD mode, and also includes a second MPC for exiting MRUPD mode. According to any of the foregoing examples of the third computer system, in one example, the third computer system includes one or more of the following: a host processor device coupled to a memory controller; a display communicatively coupled to a host processor coupled to the memory controller; a network interface communicatively coupled to a host processor coupled to the memory controller; or a battery for powering the computer system.

[0183] In one aspect, a third method includes: in a dynamic random access memory (DRAM) device having a mode register that stores a second configuration setting other than decision feedback equalization (DFE) for a hardware interface to a command bus, receiving a command to trigger entry into a mode register update (MRUPD) mode; and updating the mode register using in-band register writes in the MRUPD mode.

[0184] In one example of the third method, the in-band register write avoids using sideband bus communications to update the mode register. According to any of the foregoing examples of the third method, in one example, the MRUPD mode includes a training mode for all mode register configurations. According to any of the foregoing examples of the third method, in one example, the in-band register write includes a register word (RW) write based on a command on a command bus without using a sideband bus. According to any of the foregoing examples of the third method, in one example, the sideband bus includes a memory module management control (M3C) bus. According to any of the foregoing examples of the third method, in one example, the in-band register write includes a register word (RW) write based on a command on the command bus, in combination with using a sideband bus. According to any of the foregoing examples of the third method, in one example, the sideband bus includes a memory module management control (M3C) bus. According to any of the foregoing examples of the third method, in one example, the in-band register write includes a mode register write (MRW) based on a command on the command bus before executing a chip select training mode (CSTM). According to any of the foregoing examples of the third method, in one example, the in-band register write includes a mode register write (MRW) based on a command on the command bus prior to executing a command / address training mode (CATM). According to any of the foregoing examples of the third method, in one example, the in-band register write avoids using a multi-purpose command (MPC) to train the mode register. According to any of the foregoing examples of the third method, in one example, the command includes a first multi-purpose command (MPC) for entering MRUPD mode and also includes a second MPC for exiting MRUPD mode.

[0185] Flowcharts as shown herein provide examples of sequences of various process actions. Flowcharts may indicate operations to be performed by software or firmware routines as well as physical operations. Flowcharts may illustrate examples of implementations of states of finite state machines (FSMs), which may be implemented in hardware and / or software. Although shown in a particular sequence or order, the order of actions may be modified unless otherwise specified. Therefore, the illustrated figures should be understood only as examples, and processes may be performed in different orders, and some actions may be performed in parallel. Additionally, one or more actions may be omitted; therefore, not all implementations will perform all actions.

[0186] To the extent that various operations or functions described herein are concerned, they may be described or defined as software code, instructions, configurations, and / or data. Content may be directly executable ("object" or "executable" form), source code, or differential code ("incremental" or "patch" code). The software content described herein may be provided via a manufactured product storing content, or via a method of operating a communication interface to send data via a communication interface. A machine-readable storage medium may enable a machine to perform the functions or operations, and includes any mechanism for storing information in a form accessible to a machine (e.g., a computing device, an electronic system, etc.), such as a recordable / unrecordable medium (e.g., a read-only memory (ROM), a random access memory (RAM), a disk storage medium, an optical storage medium, a flash memory device, etc.). A communication interface includes any mechanism for engaging with any hardwired, wireless, optical, etc. medium to communicate with another device, such as a memory bus interface, a processor bus interface, an Internet connection, a disk controller, etc. The communication interface may be configured by providing configuration parameters and / or sending signals to prepare the communication interface to provide a data signal describing the software content. The communication interface may be accessed via one or more commands or signals sent to the communication interface.

[0187] The various components described herein may be units for performing the operations or functions described. Each component described herein includes software, hardware, or a combination of these. The components may be implemented as software modules, hardware modules, dedicated hardware (e.g., application specific hardware, application specific integrated circuits (ASICs), digital signal processors (DSPs), etc.), embedded controllers, hardwired circuit systems, etc.

[0188] In addition to what is described herein, various modifications may be made to the disclosed content and implementation of the present invention without departing from its scope. Therefore, the description and examples herein should be understood in an illustrative rather than a restrictive sense. The scope of the present invention should be measured only with reference to the appended claims.

Claims

1. A device for updating a configuration register, comprising: a hardware interface coupled to the command bus, the hardware interface receiving a configuration register update mode command to trigger entry into a configuration register update mode; a decision feedback equalization (DFE) configuration register storing a first configuration setting for the hardware interface to the command bus; as well as a second configuration register for configuration settings other than the DFE, the second configuration register storing second configuration settings for the hardware interface to the command bus; Wherein, the apparatus updates the second configuration register using in-band register writing in the configuration register update mode.

2. The device according to claim 1, wherein: The in-band register write avoids the use of sideband bus communications to update the second configuration register.

3. The device according to claim 1, wherein: The configuration register update mode includes a training mode for training all configuration registers.

4. The device according to claim 1, wherein: The configuration register update mode includes a register word update (RWUPD) mode for a registered clock driver (RCD).

5. The device according to claim 4, wherein: The in-band register write includes a register word (RW) write based on a command on the command bus without using a system management bus (SMBus).

6. The device according to claim 4, wherein: The in-band register write includes a register word (RW) write in conjunction with using a system management bus (SMBus) based on a command on the command bus.

7. The device according to claim 1, wherein: The configuration register update mode includes a mode register update (MRUPD) mode for a dynamic random access memory (DRAM) device.

8. The device according to claim 7, wherein: The in-band register write includes a mode register write (MRW) based on a command on the command bus prior to executing a chip select training mode (CSTM).

9. The device according to claim 7, wherein: The in-band register write includes a mode register write (MRW) based on a command on the command bus prior to executing a command / address training mode (CATM).

10. The device according to claim 7, wherein: The in-band register write avoids the use of a multi-purpose command (MPC) to train the DFE configuration register and the second configuration register.

11. The device according to claim 7, wherein: The configuration register update mode command includes a first multi-purpose command (MPC) for entering the configuration register update mode, and also includes a second MPC for exiting the configuration register update mode.

12. A computer system comprising: a memory controller coupled to the command bus; as well as A memory chip is coupled to the command bus using a command bus interface, the memory chip receives a configuration register update mode command from the memory controller to trigger the memory chip to enter a configuration register update mode, the memory chip comprising: a decision feedback equalization (DFE) configuration register storing a first configuration setting for the command bus interface; and a second configuration register for configuration settings other than the DFE, the second configuration register storing second configuration settings for the command bus interface; and The memory chip updates the second configuration register using in-band register writing in the configuration register update mode.

13. The computer system according to claim 12, wherein: The in-band register write avoids the use of sideband bus communications to update the second configuration register.

14. The computer system according to claim 12, wherein: The memory chip includes a registered clock driver (RCD), and wherein the configuration register update mode includes a register word update (RWUPD) mode for the RCD.

15. The computer system of claim 14, wherein: The in-band register write includes a register word (RW) write based on a command on the command bus without using a system management bus (SMBus).

16. The computer system of claim 14, wherein: The in-band register write includes a register word (RW) write in conjunction with using a system management bus (SMBus) based on a command on the command bus.

17. The computer system according to claim 12, wherein: The memory chip includes a dynamic random access memory (DRAM) device, and wherein the configuration register update mode includes a mode register update (MRUPD) mode for the DRAM device.

18. The computer system of claim 17, wherein: The in-band register write includes a mode register write (MRW) based on a command on the command bus before executing a chip select training mode (CSTM) and before executing a command / address training mode (CATM).

19. The computer system of claim 17, wherein: The in-band register write avoids the use of a multi-purpose command (MPC) to train the DFE configuration register and the second configuration register.

20. The computer system of claim 12, further comprising one or more of the following: a host processor device coupled to the memory controller; a display communicatively coupled to a host processor coupled to the memory controller; a network interface communicatively coupled to a host processor coupled to the memory controller; or A battery provides power to the computer system.

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