Memory device, operating method of memory device, and memory system

Abstract

A memory device, an operating method of the memory device, and a memory system are provided. The memory device includes a memory cell array; a page buffer including buffer units corresponding to the plurality of memory units of the page; and a control logic configured to control the first read operation such that first hard decision data based on a normal read level and first soft decision data based on an offset level for the first page are stored in the page buffer. The control logic is configured to, in response to a first command requesting to read a second page from the memory controller, perform a control operation to output first hard decision data to the memory controller after a second read operation for the second page has been started, and outputting the first soft decision data to the memory controller while performing a second read operation in response to a second command from the memory controller.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the benefit of Korean Patent Application No. 10-2023-0105134 filed on August 10, 2023, and Korean Patent Application No. 10-2023-0141406 filed on October 20, 2023, in the Korean Intellectual Property Office, the disclosures of which are incorporated herein by reference in their entirety. Technical Field

[0003] The inventive concept relates to a memory device, an operating method of the memory device, and a memory system. Background Art

[0004] A nonvolatile memory device includes a plurality of memory cells for storing data nonvolatilely. As an example of a nonvolatile memory device, a flash memory device may be used in mobile phones, digital cameras, personal digital assistants (PDAs), portable computer devices, stationary computer devices, and various other types of devices.

[0005] The memory device may write or read data according to various methods, and for example, the memory device may generate and output hard decision data and soft decision data in response to a read request from a memory controller. The hard decision data may be data read by using a normal read level having a specific voltage level, and the soft decision data may be data read by using an offset level having a specific offset compared to the normal read level. The memory controller may perform soft decision error correction to correct errors in the data by using the hard decision data and the soft decision data together.

[0006] However, since the memory device must output hard decision data and soft decision data together to the memory controller, the time required to output data may increase, and a delay may occur between read operations of a plurality of pages to ensure the time for data output. Summary of the invention

[0007] The present disclosure relates to a memory device having an improved read speed in a system using hard decision data and soft decision data, a memory system including the memory device, and an operating method of the memory device.

[0008] Generally, according to some aspects, a memory device includes: a memory cell array,

[0009] It includes multiple pages, each of which includes multiple memory cells; a page buffer, which includes buffer cells corresponding to the multiple memory cells of the page, wherein each of the buffer cells includes a cache latch and first to N-th latches; and control logic, which is configured to control a first read operation so that first hard decision data based on a normal read level and first soft decision data based on an offset level for a first page among the multiple pages are stored in the page buffer, wherein the control logic is also configured to perform a control operation of outputting the first hard decision data to the memory controller after a second read operation for a second page among the multiple pages has been started in response to a first command from the memory controller requesting to read the second page, and to output the first soft decision data to the memory controller while performing the second read operation in response to a second command from the memory controller.

[0010] Generally, according to some aspects, a memory device includes a page buffer, the page buffer includes buffer units corresponding to a plurality of memory cells, and an operating method of the memory device includes: receiving a read command for a first page of the memory device; storing first hard decision data based on a normal read level to a first latch of each of the buffer units, wherein the first hard decision data is read from the first page by a first read operation corresponding to the read command; storing first soft decision data based on an offset level to a second latch of each of the buffer units, wherein the first soft decision data is read from the first page; receiving a first command from a memory controller, the first command including a read request for a second page of the memory device; outputting the first hard decision data to the memory controller after dumping the first hard decision data to a cache latch of each of the buffer units in response to receiving the first command; receiving a second command from the memory controller while performing a second read operation for the second page; dumping the first soft decision data to the cache latch during a dump-enabled section defined in the second read operation in response to the second command; and outputting the first soft decision data dumped to the cache latch to the memory controller.

[0011] Generally, according to some aspects, a memory system includes: a memory device including a page buffer configured to store data read from a page, wherein the page buffer includes a plurality of buffer cells corresponding to a plurality of memory cells, and each of the buffer cells includes a first latch, a second latch, a third latch, and a cache latch; and a memory controller configured to: receive hard decision data based on a normal read level and soft decision data based on an offset level, wherein the hard decision data and the soft decision data are read from the page, wherein the memory controller is further configured to: control the memory device to sequentially perform a first read operation for a first page and a second read operation for a second page; in response to outputting a first command to the memory device, receive first hard decision data read by the first read operation from the memory device after the second read operation has started; and in response to outputting a second command to the memory device while performing the second read operation, receive first soft decision data read by the first read operation from the memory device before the second read operation is completed. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] Embodiments of the present disclosure will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings.

[0013] Figure 1 is a block diagram of an example of a memory system.

[0014] FIG. 2A to FIG. 2C is a diagram illustrating an example of generating hard decision data and soft decision data.

[0015] Figure 3 is a diagram illustrating a buffer unit of an example of a page buffer.

[0016] Figure 4 is a flowchart illustrating an example of an operating method of a memory device.

[0017] Figure 5 is a diagram showing the timing of an example of a data read operation.

[0018] Figure 6 is a block diagram illustrating an implementation example of a memory device.

[0019] Figure 7 is a flowchart illustrating an example of an operating method of a memory system.

[0020] Figure 8 is a flowchart showing a specific operation example of the memory system.

[0021] Fig. 9 and Fig.10 is a diagram illustrating an example of a memory system and an example of an operation method thereof.

[0022] Figures 11 to 15 is a waveform diagram illustrating an operation example of the memory system.

[0023] Fig.16 is a perspective view showing an example of a memory block.

[0024] Fig.17 is a block diagram illustrating an example of applying a memory device to a solid state drive (SSD) system. DETAILED DESCRIPTION

[0025] Hereinafter, the present disclosure will be described more fully with reference to the accompanying drawings, in which embodiments of the present disclosure are shown.

[0026] Figure 1 is a block diagram of an example of a memory system.

[0027] Reference Figure 1 , the memory system 10 may include a memory controller 100 and a memory device 200. The memory controller 100 may include a command generator 110 and an error correction code (ECC) circuit 120. In addition, the memory device 200 may include a memory cell array 210, a page buffer 220, and a control logic 230, and the control logic 230 may include a command decoder 231 and a dump controller 232. The memory controller 100 may provide a command CMD, an address ADD, and a control signal CTRL to the memory device 200, and the memory controller 100 may exchange data DATA with the memory device 200. Figure 1 In the example of , the command decoder 231 and the dump controller 232 are shown to be provided in the control logic 230 , but the command decoder 231 and the dump controller 232 may also be implemented as separate components outside the control logic 230 .

[0028] The memory system 10 can communicate with the host via various interfaces, and for example, the memory system 10 can communicate with the host through various interfaces (such as a universal serial bus (USB) interface, a multimedia card (MMC) interface, an embedded MMC (eMMC) interface, a peripheral component interconnect (PCI) interface, a PCI Express (PCI-E) interface, an advanced technology attachment (ATA) interface, a serial ATA interface, a parallel ATA interface, a small computer interface (SCSI), an enhanced small disk interface (ESDI), an integrated drive electronics (IDE) interface, a FireWire interface, a universal flash memory (UFS) interface, a non-volatile memory express (NVMe) interface, etc.).

[0029] The memory device 200 may include a non-volatile memory device such as a flash memory. In some embodiments, the memory system 10 may be implemented as a memory built into or detachable from an electronic device. For example, the memory system 10 may be implemented in various forms, such as a UFS memory device, an eMMC, a solid-state drive (SSD), a UFS memory card, a compact flash (CF) memory, a secure digital (SD) memory, a micro SD memory, a mini SD memory, an extreme digital (xD) memory, a memory stick, etc. In addition, because the memory system 10 stores data non-volatilely, the memory system 10 may be referred to as a storage device.

[0030] The memory controller 100 may control the memory device 200 in response to a write / read request from the host HOST to read data stored in the memory device 200 or write (or program) data to the memory device 200. For example, the memory controller 100 may include a processor, and the processor may control all operations of the memory controller 100 and may also control memory operations regarding the memory device 200.

[0031] The memory cell array 210 may include a plurality of pages, and each page may include a plurality of memory cells corresponding to a programming unit and a reading unit. For example, each page may include a flash memory cell. Hereinafter, an embodiment is described based on the case where the memory cell is a NAND flash memory cell. However, the present disclosure is not limited thereto, and in some embodiments, the plurality of memory cells may be resistive memory cells, such as resistive random access memory (RAM) (ReRAM) memory cells, phase change RAM (PRAM) memory cells, or magnetic RAM (MRAM) memory cells.

[0032] In some embodiments, the memory cell array 210 may include a three-dimensional memory cell array, which may include a plurality of NAND strings, and each NAND string may include memory cells respectively connected to word lines vertically stacked on a substrate. However, the present disclosure is not limited thereto, and in some embodiments, the memory cell array 210 may include a two-dimensional memory cell array, and the two-dimensional memory cell array may include a plurality of NAND strings arranged in row and column directions.

[0033] When a read command is provided from the memory controller 100 to the memory device 200, a read operation may be performed under the control of the control logic 230. The page buffer 220 may store data read from the memory device 200 in units of pages, and may include a plurality of buffer units arranged to correspond to a plurality of memory cells. Each of the plurality of buffer units may include one or more latches, and for example, each buffer unit may include a cache latch for exchanging data with an external controller, a sense latch for sensing data according to a voltage of a sense node, and one or more data latches for storing data.

[0034] As an operation example, when reading data of a page, hard decision data and soft decision data may be read for each memory cell. The hard decision data may correspond to data determined based on a normal read level corresponding to a normal read operation, and the soft decision data may correspond to data determined based on an offset level having a specific offset compared to the normal read level. For example, compared to the normal read level, the offset level may include a first offset level having a negative (-) offset and a second offset level having a positive (+) offset, and the soft decision data may be generated based on a combination of values ​​determined according to the first offset level and the second offset level. The memory controller 100 may receive and use the hard decision data and the soft decision data to perform an ECC decoding process, and, for example, the ECC circuit 120 may perform an error correction operation such as a low-density parity check (LDPC).

[0035] The hard decision data and the soft decision data may be provided to the memory controller 100 according to various strategies. For example, when an error occurs in normal data (e.g., hard decision data) read from the memory device 200, the memory device 200 may generate soft decision data under the control of the memory controller 100. Alternatively, regardless of the error detection result of the normal data, the memory device 200 may generate hard decision data and soft decision data under the control of the memory controller 100 and provide the hard decision data and the soft decision data to the memory controller 100.

[0036] In addition, regarding the command to generate soft decision data, a read command separate from a read command requesting to provide normal data may be defined. The memory device 200 may generate hard decision data in response to receiving the read command, and output the generated hard decision data to the memory controller 100. Conversely, when a separate read command is provided to the memory device 200, the memory device 200 may generate hard decision data and soft decision data together, and output the generated hard decision data and soft decision data to the memory controller 100.

[0037] As described above, hard decision data and soft decision data may be generated and output according to various strategies. In the following embodiments, regardless of the error detection result of normal data, it is described that the memory device 200 generates hard decision data and soft decision data together in response to a read command from the memory controller 100, and provides the generated hard decision data and soft decision data to the memory controller 100.

[0038] Specific operation examples according to the embodiments are described below.

[0039] A plurality of commands may be provided to the memory device 200 regarding operations of generating and outputting hard decision data and soft decision data for one or more pages, and a series of operations according to the execution of each command may be controlled based on the decoding result of the command decoder 231. For example, when the memory controller 100 provides a read command requesting to read the first page, the control logic 230 may control a first read operation related to reading the first page, and the first hard decision data and the first soft decision data may be read from the first page through the first read operation. The first hard decision data and the first soft decision data of each memory cell may be stored in a latch of a corresponding buffer unit, and, for example, the first hard decision data may be stored in a sense latch, and the first soft decision data may be stored in a data latch.

[0040] In some embodiments, the first hard decision data and the first soft decision data may be output to the memory controller 100 while performing one read operation. For example, the memory controller 100 may output a command requesting to read the next second page, and the memory device 200 may output the first hard decision data and the first soft decision data together to the memory controller 100 during a second read operation of the second page. The dump controller 232 may control a dump operation between a plurality of latches included in each buffer unit so that the hard decision data and the soft decision data may be output to the memory controller 100 together during one read operation.

[0041] In some embodiments, one or more commands related to the output of hard decision data and soft decision data may be defined. For example, after completing the reading of the first page, a command requesting the output of any one of the hard decision data and the soft decision data together with the read request for the next second page (hereinafter referred to as a cache read command) may be defined, and in addition, a command requesting the output of another data (hereinafter referred to as a dump command CMD_D) may be defined. When it is assumed that the hard decision data is output in response to the cache read command, the memory device 200 may perform a second read operation for the second page in response to the cache read command, and also output the first hard decision data of the first page previously read to the memory controller 100. In addition, the memory device 200 may output the first soft decision data to the memory controller 100 while performing the second read operation in response to the dump command CMD_D.

[0042] When the first read operation is completed, the first soft decision data may be stored in the data latch, and the first soft decision data may be dumped to the cache latch in response to the dump command CMD_D. At this time, the sense latch of the buffer unit may be electrically connected to other latches, and when the dump operation between latches is performed while sensing the value of the data of the second page, noise may be caused, such as a change in the voltage level of the sense node of the sense latch. For example, the read operation may include a precharge section for precharging the voltage of the sense node, a development section for developing the voltage of the sense node, and a sense section for determining the value of the data according to the voltage of the sense node, and the above-mentioned dump operation may be prohibited in some sections including the sense section.

[0043] The dump command CMD_D may be provided to the memory device 200 at any time point, and according to an embodiment, some sections for performing a read operation may be defined as sections that allow dumping. When the memory device 200 receives the dump command CMD_D at a time point where dumping is not allowed, the memory device 200 may queue the dump command CMD_D until the dumping section is allowed to start, and may dump the first soft decision data from the data latch to the cache latch during the dumping section. When the dumping section is allowed to include a portion of the above-mentioned precharge section, the memory device 200 may dump the first soft decision data to the cache latch within the precharge section. Thereafter, the memory device 200 may output the first soft decision data stored in the cache latch to the memory controller 100.

[0044] In some embodiments, the memory device 200 may include a compressor that may perform a compression operation on the first soft decision data stored in the cache latch, and the compressed first soft decision data may be output to the memory controller 100. The compression operation may be performed by various types of compression algorithms, such as lossy compression and lossless compression, and when compression is completed, the size of any one page of soft decision data may be smaller than the size of hard decision data.

[0045] The above-mentioned data dumping operation and output operation can be similarly applied to the read operation of the subsequent page. For example, the memory device 200 can perform a third read operation for the third page in response to the cache read command from the memory controller 100, and can output the second hard decision data of the second page to the memory controller 100 after the third read operation has started. In addition, the memory device 200 can dump the second soft decision data of the second page to the cache latch in response to the dump command CMD_D from the memory controller 100 and output the second soft decision data stored in the cache latch to the memory controller 100.

[0046] According to the above-described embodiment, since both hard decision data and soft decision data can be output to the memory controller 100 during a read operation of any one page, the read speed and performance can be improved. For example, after any one read operation is completed, there is no need to delay the execution of the next read operation to output at least one of the hard decision data and the soft decision data, and according to the embodiment, the read operation for a plurality of pages can be performed or the delay between the read operations can be reduced, and thus the reduction in the read performance according to the delay in the read operation can be prevented.

[0047] Despite Figure 1 Although not shown in the figure, the memory system 10 may control the data dump operation and output operation according to the embodiment based on hardware, software or a combination thereof. For example, a hardware circuit for determining the dump-allowed segment and controlling the dump operation may be implemented in the memory device 200. Alternatively, the memory controller 100 and / or the memory device 200 may be provided with a component for storing instructions and a component for executing the instructions, so that the above-mentioned dump operation and output operation may be controlled by software based on the execution of the instructions.

[0048] FIG. 2A to FIG. 2C is a diagram illustrating an example of generating hard decision data and soft decision data.

[0049] The hard decision data and the soft decision data can be generated together in the same read operation. The hard decision data and the soft decision data can be determined by different read levels, and for example, the hard decision data and the soft decision data can be generated in different sensing sections by applying word line voltages with different levels to the word lines.

[0050] Alternatively, hard decision data corresponding to a normal read level and soft decision data corresponding to an offset level may be generated by using different sensing timings in any one sensing section. For example, when the sensing timing is relatively fast, a data value may be determined based on a relatively low threshold voltage level, and conversely, when the sensing timing is relatively late, a data value may be determined based on a relatively high threshold voltage level. Figure 2B and Figure 2C An example of generating hard decision data and soft decision data by adjusting the sensing timing in the same sensing section as described above is shown.

[0051] Reference Figure 1 and Figure 2A , the memory device 200 may output data determined based on the normal read level as hard decision data HD, and may output data determined based on the offset level as soft decision data SD. The offset level may include a first offset level Offset 1 having a level smaller than the normal read level by a first offset, and a second offset level Offset 2 having a level larger than the normal read level by a second offset. The memory device may generate the soft decision data SD based on a value determined by using the first offset level Offset 1 and the second offset level Offset 2. In addition, the first offset may be the same as or different from the second offset.

[0052] For example, the hard decision data HD of the memory cell having a lower threshold voltage than the normal read level may have a value of “1”, and the hard decision data HD of the memory cell having a higher threshold voltage than the normal read level may have a value of “0”. In addition, although the soft decision data SD of the memory cell having a threshold voltage lower than the first offset level Offset 1 or higher than the second offset level Offset 2 may have a value of “0”, conversely, the soft decision data SD of the memory cell having a threshold voltage between the first offset level Offset 1 and the second offset level Offset 2 may have a value of “1”. The soft decision data SD may include information indicating whether the memory cell has a strong error or a weak error, and various parameters such as coefficients used in error calculation may be calculated based on the hard decision data HD and the soft decision data SD.

[0053] Reference Figure 2B, the read operation may include a plurality of sections, and for example, may include a precharge section, a development section, and a sensing section. In the precharge section, the sensing node may be precharged with a voltage of a specific level. In addition, in the development section, the voltage level of the sensing node may be changed according to the data stored in the memory cell. For example, when the memory cell is programmed to have a relatively low threshold voltage corresponding to a turn-on cell, the voltage level of the sensing node may drop rapidly, and conversely, when the memory cell is programmed to have a relatively high threshold voltage corresponding to a turn-off cell, the voltage level of the sensing node may drop gradually.

[0054] In the sensing section, the sensing operation may be performed at least twice at different sensing timings to determine the hard decision data HD and the soft decision data SD. According to the timings, the data value based on the first offset level Offset 1, the normal read level, and the second offset level Offset 2 in the above embodiment may be determined, and the hard decision data HD and the second offset level Offset 2 may be generated by the sensing operation.

[0055] Reference Figure 2C , each memory cell can store 2 or more bits of data, and the memory cell can have three or more threshold voltage distributions according to its programming state. In this case, in order to determine the data value of each memory cell, it may be necessary to perform a data sensing operation at the location of at least two threshold voltage distributions, and Figure 2C In the embodiment of the present invention, a case where one read operation includes two read sections is described as an example. The first read section may include a first precharge section, a first development section, and a first sensing section, and the second read section may include a second precharge section, a second development section, and a second sensing section. In addition, by using the values ​​determined in the first read section and the second read section, hard decision data HD and soft decision data SD for each memory cell may be generated.

[0056] The same as the first read section and the second read section may be performed in each of the first read section and the second read section. Figure 2B For example, a sensing operation based on the first offset level Offset 1, the normal read level, and the second offset level Offset 2 may be performed in each of the first sensing section and the second sensing section.

[0057] The above-mentioned dump-allowed section may be defined as including various sections. For example, the dump-allowed section may include a portion of the precharge section. Alternatively, the dump-allowed section may be defined as including at least a portion of the precharge section, but excluding the sensing section. In addition, although not shown in the above-mentioned embodiment, the read operation may also include other additional sections, such as a recovery section for performing recovery for various types of nodes or lines after the sensing section, and the dump-allowed section may be defined as including various sections within a range that does not cause noise to the data sensing operation.

[0058] Figure 3 is a diagram illustrating a buffer unit of an example of a page buffer. Figure 3 Schematic configuration of latches included in the buffer unit PBU connected to any one bit line BL is shown. For example, each memory cell can store at least two bits of data, and it is assumed that the buffer unit PBU includes five latches.

[0059] Reference Figure 3 The buffer unit PBU can be connected to the bit line BL through the sensing node SO, and includes a fifth latch (e.g., a cache latch C_LAT), and the cache latch C_LAT can store data received from the outside or output data to the outside. In addition, data DATA can be dumped between the cache latch C_LAT and other latches.

[0060] The buffer unit PBU may further include a first latch (e.g., a sense latch S_LAT), a second latch (e.g., a force latch F_LAT), a third latch (e.g., a first data latch M_LAT), and a fourth latch (e.g., a second data latch L_LAT). For example, the sense latch S_LAT may be a latch for sensing hard decision data HD, and the force latch F_LAT may be used for sensing soft decision data SD. In addition, the force latch F_LAT may also be used to store force information for finely changing the threshold voltage distribution during the programming process of data.

[0061] As an operation example, a value according to a specific calculation result (e.g., XOR calculation) for a value determined by two offset levels may be stored in the buffer unit PBU as soft decision data SD. For example, a value determined based on a first offset level may be dumped and stored in the first data latch M_LAT. In addition, in the process of dumping a value determined based on a second offset level to the first data latch M_LAT, the buffer unit may be implemented so that a value according to an XOR calculation result may be stored.

[0062] The hard decision data HD and the soft decision data SD may be output to the memory controller after being dumped to the cache latch C_LAT. At this time, the sense latch S_LAT and the force latch F_LAT may be electrically connected to other latches, and a sensing operation of determining a data value and an operation of dumping the hard decision data HD and / or the sense latch S_LAT to the cache latch C_LAT may be performed in parallel. Therefore, when the execution of the next read operation is delayed after any one read operation is completed to ensure time for outputting the hard decision data HD and / or the soft decision data SD, a problem of reduced read speed may occur.

[0063] In some embodiments, a dump-enabled section that enables dumping may be defined in the buffer unit PBU, thereby defining a dump command that requests output of soft decision data during a read operation, and the output of the soft decision data becomes possible, and thus the hard decision data HD and the soft decision data SD may be output together to the memory controller in one read operation. Therefore, since the second read operation is continuously performed after the first read operation is completed without an additional delay, or the delay between the first read operation and the second read operation is reduced, the read speed may be increased.

[0064] exist Figure 3 In the embodiments, the soft decision data SD generated based on the first offset level / the second offset level is described as being stored in the first data latch M_LAT, but these embodiments may be implemented in various ways. For example, the buffer unit PBU may be implemented so that the finally generated soft decision data SD is stored in the forcing latch F_LAT.

[0065] In addition, in some embodiments, a case is described in which the soft decision data SD is output to the memory controller based on the dump-allowed section after the hard decision data HD is output to the memory controller for the first time, but the present disclosure is not limited thereto. For example, the memory system may also be implemented such that the hard decision data HD is output to the memory controller based on the dump-allowed section after the soft decision data SD is output to the memory controller for the first time.

[0066] Figure 4 is a flowchart showing an example of an operating method of a memory device. Figure 4 , a case where hard decision data HD and soft decision data SD generated in a first read operation for a first page are output to a memory controller during a second read operation for a second page is described.

[0067] The memory device may generate hard decision data HD and soft decision data SD of the first page by performing a first read operation under the control of the memory controller (S11). The generated hard decision data HD may be stored in a first latch (e.g., a sense latch) within the buffer unit, and the soft decision data SD may be stored in a second latch within the buffer unit. The second latch may be any latch within the buffer unit, and, for example, may be a force latch or a first data latch, and Figure 4 In the example, it is assumed that the soft decision data SD is stored in the forced latch.

[0068] Thereafter, the memory device may perform a second read operation for the second page under the control of the memory controller (S13). In addition, the memory device may dump the hard decision data HD to a third latch (e.g., a cache latch) after the second read operation has started, and may output the hard decision data HD stored in the cache latch to the memory controller (S14). In addition, the memory device may receive a dump command related to the output of the soft decision data SD from the memory controller (S15), and, for example, may receive the dump command from the memory controller at any point in time.

[0069] The memory device may internally determine a section for which a dump operation is possible, and may delay execution of a dump command by queuing the dump command (S16). The memory device may dump soft decision data SD to a cache latch by executing a dump command when the dump-enabled section is activated (S17), and may output the soft decision data SD dumped to the cache latch to a memory controller (S18).

[0070] Because the sense latch and the force latch are used to sense the hard decision data HD and the soft decision data SD in the second read operation for the second page, when the read operation for the second page starts, the hard decision data HD and the soft decision data SD need to be directly dumped to their respective latches. As an operation example, the soft decision data SD may be dumped to another latch (e.g., the first data latch or the second data latch) in parallel or sequentially with the operation of dumping the hard decision data HD to the third latch. Alternatively, when the sensing operation related to the soft decision data SD is performed by the force latch and the first data latch, and the finally determined soft decision data SD is stored in the first data latch, the soft decision data SD may be dumped to the second data latch.

[0071] When the dump command is executed, the soft decision data SD stored in the first data latch or the second data latch may be dumped to the cache latch. In the following embodiments, the operation of dumping the soft decision data SD to the cache latch in response to the dump command may be defined as a concept including the operation of dumping the soft decision data SD stored in any latch (e.g., a force latch or a data latch) within the buffer unit to the cache latch.

[0072] According to the above-described embodiment, the hard decision data HD and the soft decision data SD generated in the first read operation can be output to the memory controller while the second read operation is performed. That is, since the hard decision data HD and the soft decision data SD can be output to the memory controller together during the second read operation, the second read operation can be continuously performed after the first read operation is completed, or the delay between the first read operation and the second read operation can be reduced.

[0073] Figure 5 is a diagram showing the timing of an example of a data read operation. Figure 5 In the embodiment of the present invention, a case is described in which a first plane P0 to a fourth plane P3 are set as a plurality of planes in a memory device, and a read operation is performed in parallel for the first plane P0 to the fourth plane P3. For example, the hard decision data HD and the soft decision data SD of the first plane P0 to the fourth plane P3 may be sequentially output to the memory controller at different time sections. The following describes an operation example of the present disclosure with reference to a read operation for a page of the first plane P0.

[0074] Reference Figure 5 , the hard decision data HD and the soft decision data SD generated by the first read operation for the first page may be stored in the page buffer, and the memory device may perform a second read operation after the first read operation in response to a first command requesting to read data of the second page. After the second read operation has started, the memory device may dump the hard decision data HD previously read and stored in the sense latch to the cache latch and output it to the memory controller.

[0075] Thereafter, the memory device may receive a second command requesting output of soft decision data from the memory controller, and may delay execution of the second command by queuing the second command until the dump-enabled section. The memory device may confirm entry into the dump-enabled section, and execute a second command to dump the soft decision data SD to the cache latch during the dump-enabled section. Thereafter, the memory device may perform a compression operation (Comp) on the soft decision data SD stored in the cache latch, and output the compressed soft decision data SD to the memory controller. The above operation may be performed similarly in a subsequent read operation.

[0076] Figure 6 is a block diagram showing an implementation example of a memory device. Figure 6 , the memory device 300 may include a memory cell array 310, a page buffer 320, a control logic 330, a voltage generator 340, a row decoder 350, and an input / output (I / O) buffer 360. In addition, the control logic 330 may include a command decoder 331, a dump controller 332, and a sector information generator 333.

[0077] The memory cell array 310 may include a plurality of pages, and the memory cell array 310 may be connected to word lines WL, string selection lines SSL, ground selection lines GSL, and bit lines BL. Specifically, the memory cell array 310 may be connected to the row decoder 350 through the word lines WL, string selection lines SSL, and ground selection lines GSL, and may be connected to the page buffer 320 through the bit lines BL.

[0078] The page buffer 320 may be connected to the bit line BL to temporarily store the read data. The page buffer 320 may include a plurality of buffer units (e.g., a first buffer unit PBU 1 to a kth buffer unit PBU K) corresponding to a plurality of memory cells of a page, and each buffer unit may be connected to a corresponding bit line BL through a sensing node and may include a plurality of latches.

[0079] The control logic 330 may program data to or read data from the memory cell array 310 based on a command CMD, an address ADD, and a control signal CTRL from a memory controller. Various internal control signals output from the control logic 330 may be provided to the page buffer 320, the voltage generator 340, and the row decoder 350. Specifically, the control logic 330 may provide a voltage control signal CTRL_vol to the voltage generator 340. The voltage generator 340 may provide a word line voltage VWL of various levels related to a program operation / read operation / erase operation to the row decoder 350. In addition, the control logic 330 may provide a row address X_ADD to the row decoder 350, a column address Y_ADD to the page buffer 320, and also output a dump control signal Ctrl_Dump for controlling a dump operation related to reading and outputting data.

[0080] In some embodiments, the command decoder 331 may decode a command from a memory controller and control a read operation and an output operation of data based on a decoding result. The dump controller 332 may control a dump operation for a latch in the page buffer 320 based on a decoding result, and according to an embodiment, the dump operation may be controlled so that hard decision data and soft decision data may be output to the memory controller together during any one read operation. In addition, the segment information generator 333 may generate segment information Info_D indicating a dump-enabled segment in which data may be dumped to a cache latch while performing a read operation. The control logic 330 may control a dump operation and an output operation of data based on the segment information Info_D of the segment information generator 333.

[0081] according to Figure 6 In the illustrated embodiment, the memory device 300 can control a series of operations for outputting hard decision data and soft decision data based on the command CMD of the memory controller. For example, in a state where the hard decision data and the soft decision data are stored in the page buffer 320, the memory device 300 can control a dump operation of dumping the hard decision data and the soft decision data to the cache latch based on the decoding result of the received command CMD, and can also output the hard decision data and the soft decision data stored in the cache latch to the memory controller.

[0082] Figure 7 is a flowchart illustrating an example of an operating method of a memory system.

[0083] Reference Figure 7 , the memory controller may provide a read command for a first page to the memory device, and the memory device may generate first hard decision data and first soft decision data through a first read operation in response to the read command (S21). In addition, the first hard decision data and the first soft decision data may be stored in latches within the page buffer, and for example, the first hard decision data may be stored in a sense latch, and the first soft decision data may be stored in a force latch (S22).

[0084] Thereafter, the memory device may receive a cache read command from the memory controller (S23), perform a second read operation for the second page for the cache read command, and also dump the first hard decision data stored in the sense latch to the cache latch (S24). In addition, the memory device may output the first hard decision data stored in the cache latch to the memory controller (S25).

[0085] The memory device may receive a dump command from the memory controller at any time point while performing the second read operation (S26). The memory device may check the logic state of the internally generated segment information and queue the dump command until the dump segment is allowed to start (S27). The memory device may execute the dump command in the dump-allowed segment according to the logic state of the segment information, and may dump the first soft decision data to the cache latch when executing the dump command (S28). In addition, the memory device may output the first soft decision data stored in the cache latch to the memory controller (S29), and, for example, the memory device may perform compression on the first soft decision data and output the compressed first soft decision data.

[0086] Figure 8 is a flowchart showing a specific operation example of the memory system.

[0087] Reference Figure 8 , the memory controller may sequentially output a series of commands related to read operations for multiple pages and outputting read hard decision data and soft decision data. In addition, the memory device may perform a series of one or more internal operations in response to any one command from the memory controller. In some embodiments, Figure 8 The first to fifth commands related to the reading and output of hard decision data and soft decision data are shown.

[0088] In operation S31, the memory controller may output a first command corresponding to the read command, and the memory device may read first hard decision data HD1 and first soft decision data SD1 from the first page in response to the first command. A first read operation for the first page may be completed, the first hard decision data HD1 may be stored in a first latch (e.g., a sense latch) within a page buffer of the memory device, and the first soft decision data SD1 may be stored in a second latch (e.g., a force latch) within the page buffer.

[0089] Thereafter, in operation S32, the memory controller may output a second command corresponding to the cache read command, and the memory device may start a second read operation for reading the second hard decision data HD2 and the second soft decision data SD2 from the second page in response to the second command. In addition, the memory device may dump the first hard decision data HD1 stored in the first latch to the cache latch in response to the second command, and output the first hard decision data HD1 stored in the cache latch to the memory controller. Furthermore, the memory device may also perform an operation of dumping the first soft decision data SD1 stored in the second latch to a third latch (e.g., a data latch) in response to the second command.

[0090] Thereafter, in operation S33, the memory controller may output a third command corresponding to the dump command, and the memory device may dump the first soft decision data SD1 stored in the third latch to the cache latch during the dump-allowed section, and output the first soft decision data SD1 stored in the cache latch to the memory controller. In addition, in operation S34, when the second read operation that has been started previously is completed, the second hard decision data HD2 may be stored in the first latch within the page buffer, and the second soft decision data SD2 may be stored in the third latch within the page buffer.

[0091] Thereafter, in operation S35, the memory controller may output a second command corresponding to the cache read command, and the memory device may start a third read operation for reading the third hard decision data HD3 and the third soft decision data SD3 from the third page in response to the second command. In addition, the memory device may dump the second hard decision data HD2 stored in the first latch to the cache latch in response to the second command, and output the second hard decision data HD2 stored in the cache latch to the memory controller.

[0092] Thereafter, in operation S36, the memory controller may output a third command corresponding to the dump command, and the memory device may dump the second soft decision data SD2 stored in the third latch to the cache latch in response to the third command during the dump-allowed section, and output the second soft decision data SD2 stored in the cache latch to the memory controller. In addition, in operation S37, when the third read operation that has been started previously is completed, the third hard decision data HD3 may be stored in the first latch within the page buffer, and the third soft decision data SD3 may be stored in the second latch within the page buffer.

[0093] According to the above operation, the first hard decision data to the third hard decision data and the first soft decision data to the third soft decision data are all read, and the third hard decision data and the third soft decision data correspond to the state that has not been output to the memory controller. In operation S38, the memory controller may provide a fourth command corresponding to the hard decision data read command to the memory device, and the memory device may dump the third hard decision data HD3 to the cache latch, and output the third hard decision data HD3 stored in the cache latch to the memory controller without performing an additional read operation. In addition, in operation S39, the memory controller may provide a fifth command corresponding to the soft decision data read command to the memory device, and the memory device may dump the third soft decision data SD3 to the cache latch, and output the third soft decision data SD3 stored in the cache latch to the memory controller. In some embodiments, because the memory device does not perform a read operation, the third soft decision data SD3 may be dumped to the cache latch to output it to the memory controller regardless of the dump-allowed segment.

[0094] Fig. 9 and Fig.10 is a diagram illustrating an example of a memory system and an example of an operation method thereof.

[0095] Reference Fig. 9 , the memory system may include a memory controller and a memory device, the memory controller may output an address ADD and a command CMD to the memory device, and the hard decision data HD and the soft decision data SD read from the memory device may be provided to the memory controller. In addition, according to the above-mentioned embodiment, a dump-allowed segment may be defined while performing a read operation, and the memory device may generate segment information Info_D indicating a dump-allowed segment, and provide the generated segment information Info_D to the memory controller. For example, when the segment information Info_D has a first logic state, the memory device may dump the hard decision data or the soft decision data to the cache latch. On the contrary, when the segment information Info_D has a second logic state, the operation of dumping the hard decision data or the soft decision data to the cache latch may be prohibited.

[0096] The memory controller may receive hard decision data from the memory device by outputting a cache read command according to the above-mentioned embodiment. In addition, the memory controller may check the logic state of the segment information Info_D, and when the segment information Info_D has a first logic state, may output a dump command to the memory device. When the segment information Info_D has a first logic state, the memory device may dump the soft decision data to the cache latch. The operation of dumping the hard decision data or the soft decision data to the cache latch may correspond to the operation of preparing to output data.

[0097] Reference Fig.10 In operation S41, the memory controller may output a read command RD_N, and the memory device may perform a read operation for the Nth page in response to the read command RD_N. When the read operation for the Nth page is completed, the Nth hard decision data HD(N) may be stored in a first latch (e.g., a sense latch) within the page buffer, and the Nth soft decision data SD(N) may be stored in a second latch (e.g., a force latch) within the page buffer.

[0098] Thereafter, in operation S42, the memory controller may output a cache read command Cache RD_N, and the memory device may start a read operation for the (N+1)th page in response to the cache read command Cache RD_N. In addition, the memory device may dump the Nth hard decision data HD(N) stored in the first latch to the cache latch in response to the cache read command Cache RD_N, and may output the Nth hard decision data HD(N) stored in the cache latch to the memory controller. When defining the terminology of the cache read command Cache RD_N, the symbol "N" is used in relation to outputting the data of the Nth page, but the cache read command Cache RD_N may also be defined as being represented by the symbol "Cache RD_N+1" in relation to the fact that a read request for the next (N+1)th page is included.

[0099] In operation S43, the memory controller may check the logical state of the segment information Info_D provided from the memory device, and may determine whether the state of the memory device corresponds to the allowed dump segment. When it is determined according to operation S44_1 that the state of the memory device corresponds to the allowed dump segment, the memory controller may output a dump command Dump, and the memory device may dump the Nth soft decision data SD(N) stored in the second latch or another latch (e.g., data latch) to the cache latch during the allowed dump segment in response to the dump command Dump. In addition, the memory device may output the Nth soft decision data SD(N) stored in the cache latch to the memory controller.

[0100] On the contrary, when the dump-enabled segment does not exist until the read operation for the (N+1)th page is completed, according to operation S44_2, the storage controller can output a dump command Dump after completing the read operation for the (N+1)th page, and can receive the Nth soft decision data SD(N) from the memory device.

[0101] Thereafter, in operation S45, the memory controller may output a cache read command Cache RD_N+1, and the memory device may start a read operation for the (N+2)th page in response to the cache read command Cache RD_N+1, and may dump the (N+1)th hard decision data HD(N+1) stored in the first latch to the cache latch, and output the (N+1)th hard decision data HD(N+1) to the memory controller. In addition, as in the above-mentioned operation, in operation S46, the memory controller may check the logic state of the segment information Info_D, and based on the check result, according to operation S47_1, when performing a read operation for the (N+2)th page, output a dump command Dump to the memory device. When there is no dump-enabled segment until the read operation for the (N+2)th page is completed, according to operation S47_2, the memory controller may output a dump command Dump after completing the read operation for the (N+2)th page.

[0102] According to the above-mentioned embodiment, since the memory controller can check the logic state of the segment information Info_D to output the dump command, the memory device can perform the dump operation of the data by executing the dump command without queuing the dump command for a long time. In addition, based on the logic state of the dump-enabled segment, when both the hard decision data and the soft decision data may not be output during one read operation, a control operation can be performed after the read operation is completed to output any one data (e.g., the soft decision data), thereby ensuring the stability of data input / output.

[0103] Hereinafter, operation examples of the memory system according to various embodiments are described. Figures 11 to 15 is a waveform diagram showing an operation example of a memory system. Figures 11 to 15 In the embodiment, when each of the memory cells of the memory device stores two or more bits of data, the read operation includes a plurality of read sections for determining at least two threshold voltage distributions, and a case where the read operation includes a first read section and a second read section is described as an example. In addition, the read operation may also include at least one section other than the above-mentioned read section, and for example, the read operation may include an initialization section for performing initialization of various lines and nodes of the page buffer before the start of the read section, and a recovery section for various lines and nodes after the completion of the read section. In addition, for the sake of convenience of explanation, although in Figures 11 to 15 Although not shown in the figure, the read section may also include a development section before the sense section, and the dump-allowed section of the embodiment may include or exclude a part of the development section.

[0104] The dump-allowed segment according to some embodiments may define a segment in the read segment that allows dumping. In segments other than the read segment (e.g., the initialization segment and the recovery segment), a dump operation may be performed regardless of the segment information Info_D. Figures 11 to 15 In the embodiment of , it is assumed that the soft decision data is stored in the forcing latch when the read operation is completed, and the soft decision data is dumped from the forcing latch to the first data latch M_LAT in response to a cache read command.

[0105] Reference Fig.11 , the memory device may store the Nth hard decision data and the Nth soft decision data previously read from the Nth page in a page buffer, and, for example, may store the Nth hard decision data in a first latch (e.g., a sense latch) within the page buffer, and may store the Nth soft decision data in a second latch (e.g., a force latch) within the page buffer.

[0106] The memory device may generate an external ready / busy signal RnBx and an internal ready / busy signal RnBi, and output the external ready / busy signal RnBx to the memory controller. In addition, the memory device may perform various internal operations related to data write operations and data read operations based on the logic state of the internal ready / busy signal RnBi. The internal ready / busy signal RnBi may maintain a logic low state during a read operation. In addition, in some embodiments, the memory device may also generate segment information Info_D indicating that a dump segment is allowed, and Fig.11In the illustrated embodiment, a case is described in which the memory device outputs the sector information Info_D to the memory controller in response to the status read command Status RD from the memory controller.

[0107] During the segment in which the external ready / busy signal RnBx is logic high, the memory device may input / output commands, information, data, etc. to / from the memory controller, and, for example, the memory device may receive a cache read command Cache RD_N+1 from the memory controller. The external ready / busy signal RnBx may change to a logic low state during a specific segment in response to the cache read command Cache RD_N+1, and the memory device may dump the Nth hard decision data HD(N) stored in the first latch to the cache latch and the Nth soft decision data SD(N) stored in the second latch to the first data latch M_LAT during the logic low segment of the external ready / busy signal RnBx, and may also output the Nth hard decision data HD(N) dumped to the cache latch to the memory controller. In addition, the memory device may perform a read operation for the (N+1)th page in parallel with the output of the Nth hard decision data HD.

[0108] In some embodiments, the memory controller may output a status read command Status RD requesting transmission of the segment information Info_D to the memory device, and the memory device may output the segment information Info_D to the memory controller. Fig.11 A case where the status read command Status RD is provided to the memory device after the Nth hard decision data HD(N) is output is shown, but the present disclosure is not limited thereto, and the status read command Status RD may be provided to the memory device at various random time points.

[0109] In each read operation, the allowed dump segment may include one or more segments, and Fig.11A case where the dump-enabling section includes a portion of the precharge section of each of the first read operation and the second read operation is shown. The memory controller may output a dump command Dump in the dump-enabling section, and the memory device may determine whether the dump operation can be completed when the section information Info_D has a first logic state by considering the time Tdump required for the dump operation. When the dump operation is completed, the external ready / busy signal RnBx may change to a logic low state during a specific section in response to the dump command, and the memory device may dump the Nth soft decision data SD(N) to the cache latch and output the Nth soft decision data SD(N) dumped to the cache latch to the memory controller during the logic low section of the external ready / busy signal RnBx. According to the above operation, during the read operation of the next (N+1)th page, the Nth hard decision data HD(N) and the Nth soft decision data SD(N) read from the Nth page may all be provided to the memory controller.

[0110] Reference Fig.12 , the memory device may receive a cache read command Cache RD_N from the memory controller, dump the Nth hard decision data HD(N) stored in the first latch to the cache latch during a logic low section of the external ready / busy signal RnBx, and output the Nth hard decision data HD(N) dumped to the cache latch to the memory controller. In addition, the memory device may perform a read operation for the (N+1)th page in parallel with the output of the Nth hard decision data HD(N).

[0111] The memory controller may output a dump command Dump for outputting the soft decision data to the memory device during the dump-allowed section. At this time, when the dump operation of the Nth soft decision data SD(N) is not completed during the dump-allowed section due to the time Tdump required for the dump operation, the memory device may perform a control operation for delaying the start of the sensing section so that the dump operation of the Nth soft decision data SD(N) is not performed in parallel with the sensing operation for the (N+1)th page.

[0112] In some embodiments, the memory device may dump the Nth soft decision data SD(N) to the cache latch in response to the dump command Dump in a state where the start of the sensing section is delayed, and may start the sensing operation for the (N+1)th page after the dump operation is completed. According to the above operation, during the next read operation of the (N+1)th page, the Nth hard decision data HD(N) and the Nth soft decision data SD(N) read from the Nth page may all be provided to the memory controller. Fig.12In the illustrated embodiment, when the start of the sensing section is delayed, the dump operation for the Nth soft decision data SD(N) may be performed even when the section information Info_D has the second logic state.

[0113] Fig.13 A case is shown in which the memory device receives a dump command from the memory controller without outputting the section information Info_D to the memory controller at any point in time.

[0114] Reference Fig.13 , the memory device may dump the Nth hard decision data HD(N) stored in the first latch to the cache latch in response to the cache read command Cache RD_N, and may output the Nth hard decision data HD(N) dumped to the cache latch to the memory controller. In addition, the memory device may receive a dump command Dump, and when the operation of dumping the Nth soft decision data SD(N) to the cache latch can be completed during the dump-allowed section, the memory device may dump the Nth soft decision data SD(N) to the cache latch in response to the dump command Dump, and output the Nth soft decision data SD(N) stored in the cache latch to the memory controller without performing a separate queue for delaying the execution of the dump command.

[0115] Reference Fig.14 , the memory device may dump the Nth hard decision data HD(N) stored in the first latch in response to the cache read command Cache RD_N, and may output the Nth hard decision data HD(N) dumped to the cache latch to the memory controller. In addition, the memory device may receive the dump command Dump during the first read section, and since the dump command Dump is received after the dump-enabled section present in the first read section, the memory device may queue the dump command without executing the dump command Dump.

[0116] Thereafter, the memory device may enter a second read section, and a portion of the precharge section of the second read section may correspond to a dump-enabled section. The memory device may dump the Nth soft decision data SD(N) to the cache latch when entering the dump-enabled section of the second read section, and may output the Nth soft decision data SD(N) stored in the cache latch to the memory controller.

[0117] Fig.14The case where the dump command Dump is provided to the memory device after the dump-allowed section in the first read section is shown, but the present disclosure is not limited thereto. For example, even when the memory device receives the dump command Dump in the dump-allowed section in the first read section, when the dump operation of the Nth soft decision data SD(N) may not be completed during the dump-allowed section in the first read section, the memory device may queue the dump command Dump and execute the dump command Dump in the dump-allowed section of the second read section.

[0118] Reference Fig.15 , the memory device may dump the Nth hard decision data HD(N) stored in the first latch to the cache latch in response to the cache read command Cache RD_N, and may output the Nth hard decision data HD(N) dumped to the cache latch to the memory controller. In addition, the memory device may receive a dump command Dump at any time point, and Fig.15 The case where the dump command Dump is provided to the memory device at a time point after the dump enabled section defined in the precharge section of the second read section is shown. Since the section information Info_D has the second logic state, the memory device can queue the dump command Dump without executing the dump command Dump.

[0119] When the second read segment for the (N+1)th page is completed, a recovery operation for various lines and nodes within the page buffer may be performed in the recovery segment. In addition, because the recovery segment corresponds to a segment after the second read segment is completed, a data dump operation may be performed in at least a portion of the recovery segment, and according to an embodiment, a segment including a portion of the recovery segment may be defined as a dump-enabled segment. After the second read segment is completed, since the segment information Info_D changes to the first logic state, the memory device may dump the Nth soft decision data SD(N) to the cache latch, and may output the Nth soft decision data SD(N) stored in the cache latch to the memory controller.

[0120] like Fig.15 As shown in , the dump-enabled section according to some embodiments may be defined to include various time sections, and for example may be defined to include at least one other section (such as a recovery section) and a portion of a precharge section. Therefore, even when a dump command from a memory controller is provided to the memory device at any point in time, the memory device may dump the soft decision data to the cache latch in the dump-enabled section at various points in time, and thus may output both the hard decision data and the soft decision data to the memory controller together in any one read operation.

[0121] Fig.16 is a stereoscopic diagram showing an example of a memory block BLKa.

[0122] Reference Fig.16 , the memory block BLKa may correspond to Figure 1 Any one of the multiple memory blocks set in the memory cell array 210. The memory block BLKa is formed in the vertical direction VD relative to the substrate SUB having a first conductivity type (e.g., p-type). In some embodiments, a common source line CSL doped with impurities of a second conductivity type (e.g., n-type) may be provided on the substrate SUB. In some embodiments, the substrate SUB may be implemented with polycrystalline silicon, and the common source line CSL having a plate shape may be arranged on the substrate SUB. A plurality of insulating films IL extending in the second direction H2 may be sequentially provided along the vertical direction VD on the substrate SUB, and the plurality of insulating films IL are spaced apart from each other at specific intervals in the vertical direction VD. For example, the plurality of insulating films IL may include an insulating material such as silicon oxide.

[0123] A plurality of pillars P sequentially arranged in a first direction H1 and penetrating a plurality of insulating films IL in a vertical direction VD are provided on a substrate SUB. For example, a plurality of pillars P may penetrate a plurality of insulating films IL to contact the substrate SUB. Specifically, a surface layer S of each pillar P may include a silicon material having a first type and may be used as a channel region. Therefore, the pillars P may be referred to as a vertical channel structure. An inner layer I of each pillar P may include an insulating material such as silicon oxide or an air gap.

[0124] The charge storage layer CS is arranged along the exposed surfaces of the plurality of insulating films IL, the plurality of pillars P and the substrate SUB. The charge storage layer CS may include a gate insulating layer, a charge capture layer and a blocking insulating layer. For example, the charge storage layer CS may have an oxide-nitride-oxide (ONO) structure. In addition, gate electrodes GE (such as ground selection lines GSL, string selection lines SSL and word lines WL0 to WL7) are arranged on the exposed surface of the charge storage layer CS. The drain electrodes DR are respectively arranged on the plurality of pillars P. For example, the drain electrodes DR may include a silicon material doped with impurities having a second conductivity type. The bit lines BL0 to BL2 extending in the first direction and arranged to be spaced apart from each other by a specific distance in the second direction H2 are respectively arranged on the drain electrodes DR.

[0125] Fig.17 is a block diagram showing an example of applying a memory device to an SSD system 400 .

[0126] Reference Fig.17, the SSD system 400 may include a host 410 and an SSD 420. The SSD 420 exchanges a signal SIG with the host 410 through a signal interface and receives power PWR through a power connector. The SSD 420 may include an SSD controller 421, an auxiliary power supply 422, and memory devices 423_1 to 423_n. Each of the memory devices 423_1 to 423_n may be configured by using the above reference. Figures 1 to 16 The described implementation is implemented.

[0127] That is, the SSD controller 421 may correspond to the memory controller described in the above embodiment, the memory devices 423_1 to 423_n may correspond to the memory devices according to the above embodiment, and hard decision data and soft decision data may be sent and received between the SSD controller 421 and the memory devices 423_1 to 423_n. The SSD controller 421 may include a command generator 421_1, and the command generator 421_1 may generate a series of commands related to the reading and output of the hard decision data and soft decision data of the memory devices 423_1 to 423_n, and output the generated commands to the memory devices 423_1 to 423_n. For example, the command generator 421_1 may generate a dump command requesting dump data when performing a read operation.

[0128] Each of the memory devices 423_1 to 423_n may include a dump controller, and the dump controller may control a dump operation related to the reading and output of the hard decision data and the soft decision data. For example, according to the above embodiment, the dump controller may perform a control operation in a dump-enabled section while performing a read operation so that data is dumped to a cache latch.

[0129] Although this specification contains many specific implementation details, these details should not be interpreted as limitations on the scope of any invention or the scope that may be claimed, but should be regarded as descriptions of features that may be specific to a particular embodiment of a particular invention. Certain features described in this specification in the context of separate embodiments may also be implemented in combination in a single embodiment. Conversely, the various features described in the context of a single embodiment may also be implemented separately in multiple embodiments or in any suitable sub-combination. In addition, although the features may be described above as working in certain combinations, in some cases, one or more features from the combination may be removed from the combination, and the combination may involve a sub-combination or a variant of a sub-combination.

[0130] While the present disclosure has been particularly shown and described with reference to embodiments thereof, it will be understood that various changes in form and details may be made therein without departing from the spirit and scope of the appended claims.

Claims

1. A memory device, comprising: a memory cell array comprising a plurality of pages, wherein each of the plurality of pages comprises a plurality of memory cells; a page buffer comprising a plurality of buffer units corresponding to the plurality of memory cells of each page, wherein each of the plurality of buffer units comprises a cache latch and first to N-th latches, and N is an integer greater than or equal to 2; and, The control logic is configured as follows: controlling a first read operation for a first page of the plurality of pages, wherein the first read operation stores first hard decision data based on a normal read level in the page buffer and stores first soft decision data based on an offset level in the page buffer, outputting the first hard decision data to a memory controller after a second read operation for a second page of the plurality of pages has begun, wherein the second read operation is started in response to a first command requesting to read the second page, and While the second read operation is being performed, the first soft decision data is output to the memory controller in response to a second command from the memory controller.

2. The memory device according to claim 1, wherein: The first soft decision data is compressed in the memory device, and the compressed first soft decision data has a size smaller than the first hard decision data.

3. The memory device according to claim 1, wherein: The first hard decision data is stored in the first latch, and the first soft decision data is stored in the second latch, The control logic is configured to output the first hard decision data stored in the cache latch to the memory controller after dumping the first hard decision data stored in the first latch to the cache latch, and dumping the first hard decision data is performed in response to the first command.

4. The memory device according to claim 3, wherein: N is an integer greater than or equal to 3, wherein the control logic is configured to dump the first soft decision data stored in the second latch to the third latch in response to the first command, and Wherein, the first soft decision data stored in the third latch is dumped to the cache latch in response to the second command, and the first soft decision data stored in the cache latch is output to the memory controller after the first soft decision data stored in the third latch is dumped to the cache latch.

5. The memory device of claim 4 , wherein the second read operation includes a precharge section for precharging a sensing node of each buffer unit, a development section for developing a voltage of the sensing node of each buffer unit, and a sensing section for sensing the voltage of the sensing node of each buffer unit, and in, The first soft decision data is dumped to the cache latch in the precharge section.

6. The memory device according to claim 5, wherein: The memory device includes a sector information generator configured to generate sector information indicating a dump-allowed sector in a read operation for each page, and Wherein, the first soft decision data is dumped to the cache latch while the sector information is activated.

7. The memory device according to claim 6, wherein: receiving the second command before activating the segment information, and The memory device is configured to queue the second command and execute the second command after activating the sector information.

8. The memory device according to claim 6, wherein: The memory device is configured to output the sector information to the memory controller, and receive the second command from the memory controller while activating the sector information.

9. The memory device according to claim 5, wherein: The second read operation includes a first read section and a second read section to determine a different distribution among a plurality of threshold voltage distributions, and each of the first read section and the second read section includes the precharge section, the development section, and the sensing section, and wherein the second command is provided to the memory device in the first read section, and the first soft decision data is dumped to the cache latch in the precharge section of the second read section.

10. A method for operating a memory device, wherein: The memory device includes a page buffer, and the page buffer includes a plurality of buffer units corresponding to a plurality of memory units, and the operating method includes: receiving a read command for a first page of the memory device; storing first hard decision data based on a normal read level in a first latch of each of the plurality of buffer units, wherein the first hard decision data is read from the first page through a first read operation corresponding to the read command; storing first soft decision data based on an offset level into a second latch of each buffer unit of the plurality of buffer units, wherein the first soft decision data is read from the first page; receiving a first command from a memory controller, the first command comprising a read request for a second page of the memory device; outputting the first hard decision data to the memory controller after dumping the first hard decision data to a cache latch of each buffer unit in the plurality of buffer units, the dumping of the first hard decision data being performed in response to receiving the first command; receiving a second command from the memory controller while performing a second read operation for the second page; In response to receiving the second command, dumping the first soft decision data to the cache latch during a dump-enabled section, the dump-enabled section being defined in the second read operation; and The first soft decision data dumped to the cache latch is output to the memory controller.

11. The operating method according to claim 10, wherein: After the second read operation has begun, the first hard decision data is dumped to the cache latch.

12. The operating method of claim 10 , comprising dumping the first soft decision data stored in the second latch to a third latch in response to receiving the first command, in, The first soft decision data stored in the third latch is dumped to the cache latch in response to receiving the second command.

13. The operating method according to claim 10, wherein: The second read operation includes a precharge section for precharging a sensing node of each buffer unit, a development section for developing a voltage of the sensing node of each buffer unit, and a sensing section for sensing the voltage of the sensing node of each buffer unit, and The dump-allowed section includes a portion of the precharge section.

14. The operating method according to claim 13, comprising generating segment information indicating the dump-allowed segment, in, The operation of dumping the first soft decision data to the cache latch is performed when the sector information is in a first logic state. 15 . The operating method of claim 14 , comprising queuing the second command until the sector information changes to the first logic state based on receiving the second command when the sector information is in the second logic state.

16. The operating method according to claim 13, wherein: The second read operation includes a first read section and a second read section to determine a different distribution among a plurality of threshold voltage distributions, and each of the first read section and the second read section includes the precharge section, the development section, and the sensing section, and wherein the second command is provided to the memory device in the first read section, and the first soft decision data is dumped to the cache latch in the precharge section of the second read section. 17 . The operating method according to claim 10 , comprising outputting section information to the memory controller, the section information indicating the dump-enabled section.

18. The operating method according to claim 10, comprising: after completing the second read operation and in response to a third command provided from the memory controller, dumping second hard decision data to the cache latch without performing an additional read operation, the second hard decision data being stored in the first latch and read from the second page; outputting the second hard decision data dumped to the cache latch to the memory controller; in response to a fourth command provided from the memory controller, dumping second soft decision data to the cache latch, the second soft decision data being stored in the second latch and read from the second page; as well as The second soft decision data dumped to the cache latch is output to the memory controller.

19. A memory system comprising: A memory device comprising a page buffer configured to store data read from a page, wherein the page buffer comprises a plurality of buffer units corresponding to a plurality of memory cells, and each of the plurality of buffer units comprises a first latch, a second latch, a third latch, and a cache latch; and A memory controller configured to: receiving hard decision data based on a normal read level and receiving soft decision data based on an offset level, wherein the hard decision data and the soft decision data are read from the page; controlling the memory device to sequentially perform a first read operation for a first page and a second read operation for a second page; in response to outputting a first command to the memory device, receiving first hard decision data from the memory device after the second read operation has started, the first hard decision data being read by the first read operation; and In response to outputting a second command to the memory device while performing the second read operation, first soft decision data is received from the memory device before the second read operation is completed, the first soft decision data being read by the first read operation.

20. The memory system of claim 19, wherein: The second read operation includes a precharge section for precharging a sensing node of each buffer unit, a development section for developing a voltage of the sensing node of each buffer unit, and a sensing section for sensing the voltage of the sensing node of each buffer unit, and Wherein, the memory device is configured as: dumping the first hard decision data stored in the first latch to the cache latch; outputting the first hard decision data stored in the cache latch to the memory controller; In response to receiving the first command, dumping the first soft decision data stored in the second latch to the third latch while performing the second read operation; dumping the first soft decision data stored in the third latch to the cache latch during a dump-allowed section, the dump-allowed section corresponding to a portion of the precharge section; and In response to receiving the second command, the first soft decision data stored in the cache latch is output to the memory controller.

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