System and method for data analysis acceleration

Abstract

A method for data processing is provided that includes receiving, by a first circuit, row data of a page, receiving, by the first circuit, first column data and second column data from the row data, and transmitting, by the first circuit, the first column data and the second column data to a first output port of the first circuit.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to and the benefit of U.S. Provisional Application No. 63 / 531,708, filed on August 9, 2023, entitled “Efficient Scan Filter Acceleration for Row-Based Data Analysis,” the entire contents of which are incorporated herein by reference. Technical Field

[0003] Aspects of some embodiments of the present disclosure relate to systems and methods for data analytics acceleration (eg, data analytics acceleration in a storage device). Background Art

[0004] In the field of computer storage, a system may include a host computer and one or more storage devices connected to (e.g., communicatively coupled to) the host computer. Such computer storage systems have become increasingly popular, in part to allow many different users to share the computing resources of the system. As the number of users of such systems and the number and complexity of applications running on such systems increase, storage requirements increase over time.

[0005] This Background section is intended only to provide context, and the disclosure of any embodiments or concepts in this section does not constitute an admission that such embodiments or concepts are prior art. Summary of the invention

[0006] Aspects of some embodiments of the present disclosure relate to computer storage systems that provide improvements in data acceleration (eg, scan acceleration).

[0007] According to some embodiments of the present disclosure, a method for data processing is provided, the method comprising receiving row data of a page by a first circuit, receiving first column data and second column data from the row data by the first circuit, and sending the first column data and the second column data to a first output port of the first circuit by the first circuit.

[0008] The transmitting may include performing time division multiplexing (TDM) on the first column data and the second column data.

[0009] The first circuit may include a column filter configured to receive first column data and second column data from the row data and output the first column data and the second column data to the first data path based on TDM.

[0010] The first circuit may include a first memory configured to receive first column data and second column data from a first data path, store the first column data and second column data in a buffer in a first order, and output the first column data and second column data in a second order different from the first order.

[0011] The first memory may include random access memory (RAM).

[0012] A first output port of the first circuit may be connected to a first input port of the scan circuit, and a second output port of the first circuit may be connected to a second input port of the scan circuit.

[0013] The first circuit may group the first column data with the third column data output to the second output port.

[0014] The scan circuit may perform a scan operation including comparison of the first column data with the third column data, and may output result data based on the scan operation.

[0015] The result data may include an address for locating the result of the scanning operation.

[0016] The result data may include a length associated with the page.

[0017] The scan circuit may perform a scan operation on one or more columns of the row data.

[0018] According to some other embodiments of the present disclosure, a memory device is provided, including a first circuit to receive row data of a page, receive first column data and second column data from the row data, and send the first column data and the second column data to a first output port of the first circuit.

[0019] The transmitting may include time division multiplexing (TDM) the first column of data and the second column of data.

[0020] The first output port of the first circuit may be connected to the first input port of the scan circuit.

[0021] The scan circuit may perform a scan operation associated with a first input port of the scan circuit and may output result data based on the scan operation.

[0022] The scan circuit may perform a scan operation on one or more columns of the row data.

[0023] According to some other embodiments of the present disclosure, a system is provided, including a processor and a memory storing instructions, wherein the instructions cause the processor to execute, upon execution by the processor: receiving row data of a page, extracting first column data and second column data from the row data, and sending the first column data and the second column data to a first output port of a first circuit.

[0024] The transmitting may include time division multiplexing (TDM) the first column of data and the second column of data.

[0025] The first output port of the first circuit may be connected to the first input port of the scan circuit.

[0026] The scan circuit may perform a scan operation associated with a first input port of the scan circuit and may output result data based on the scan operation. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] Non-limiting and non-exhaustive embodiments of the present disclosure are described with reference to the following figures, wherein like reference numerals refer to like parts throughout the various views unless otherwise specified.

[0028] Figure 1 is a system diagram depicting a data analytics accelerator according to some embodiments of the present disclosure.

[0029] Figure 2A is a diagram depicting extraction and reordering circuitry of a data analytics accelerator according to some embodiments of the present disclosure.

[0030] Figure 2B is a diagram depicting a crossbar configuration associated with extraction and reordering circuits according to some embodiments of the present disclosure.

[0031] Figure 3 is a diagram depicting the operation of an extract and reorder circuit and a scan top circuit according to some embodiments of the present disclosure.

[0032] Figure 4 is a flow chart depicting example operations of a method for data processing for a data analytics accelerator according to some embodiments of the present disclosure.

[0033] Throughout the several views of the drawings, corresponding reference numerals indicate corresponding components. It will be appreciated by those skilled in the art that the elements in the drawings are shown for simplicity and clarity and are not necessarily drawn to scale. For example, the dimensions of some elements, layers, and regions in the drawings may be exaggerated relative to other elements, layers, and regions to help improve clarity and understanding of the various embodiments. In addition, common but well-understood elements and components that are not relevant to the description of the embodiments may not be shown to facilitate less obstruction of the views of these various embodiments and to make the description clear. DETAILED DESCRIPTION

[0034] By referring to the detailed description and the accompanying drawings of one or more embodiments, it is easier to understand the various aspects of the present disclosure and its implementation method. Hereinafter, the embodiments will be described in more detail with reference to the accompanying drawings. However, the described embodiments can be embodied in various different forms and should not be construed as being limited to the embodiments shown herein. On the contrary, these embodiments are provided as examples so that the present disclosure will be thorough and complete, and will fully convey the various aspects of the present disclosure to those skilled in the art. Therefore, the description of processes, elements and technologies that are not necessary for a complete understanding of the various aspects and features of the present disclosure for those of ordinary skill in the art can be omitted.

[0035] Unless otherwise specified, the same reference numerals, characters, or combinations thereof throughout the drawings and written descriptions represent the same elements, and therefore, descriptions thereof will not be repeated. It will be appreciated by those skilled in the art that the elements in the drawings are shown for simplicity and clarity and are not necessarily drawn to scale. For example, the sizes of some elements, layers, and regions in the drawings may be exaggerated relative to other elements, layers, and regions to help improve clarity and understanding of the various embodiments. In addition, common but well-understood elements and components that are not related to the description of the embodiments may not be shown to facilitate less obstruction of the views of these various embodiments and to make the description clear.

[0036] In the detailed description, for purposes of explanation, numerous specific details are set forth in order to provide a thorough understanding of the various embodiments. However, it is apparent that the various embodiments can be practiced without these specific details or with one or more equivalent arrangements.

[0037] It should be understood that although the terms "zeroth", "first", "second", "third", etc. may be used herein to describe various elements, components, regions, layers and / or parts, these elements, components, regions, layers and / or parts should not be limited by these terms. These terms are used to distinguish one element, component, region, layer or part from another element, component, region, layer or part. Therefore, without departing from the spirit and scope of the present disclosure, the first element, component, region, layer or part described below may be referred to as a second element, component, region, layer or part.

[0038] It should be understood that when an element or component is referred to as being "on," "connected to," or "coupled to" another element or component, it can be directly on, connected to, or coupled to the other element or component, or there can be one or more intermediate elements or components. However, "direct connection / direct coupling" refers to a component being directly connected or coupled to another component without intermediate components. At the same time, other expressions describing the relationship between components, such as "between," "immediately between," or "adjacent to," and "directly adjacent to," can be similarly interpreted. In addition, it should also be understood that when an element or component is referred to as being "between" two elements or components, it can be the only element or component between the two elements or components, or there can also be one or more intermediate elements or components.

[0039] The terms used herein are only used for the purpose of describing specific embodiments and are not intended to limit the present disclosure. As used herein, the singular forms "a" and "an" are intended to also include plural forms, unless the context clearly indicates otherwise. It will be further understood that when used in this specification, the terms "comprises", "comprising", "have", "having", "includes" and "including" specify the presence of the features, integers, steps, operations, elements and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components and / or their groups. As used herein, each of the terms "or" and "and / or" includes any and all combinations of one or more associated listed items. For example, the statement "A and / or B" means A, B or A and B.

[0040] For the purposes of this disclosure, expressions such as “at least one of…” when following a list of elements modify the entire list of elements and do not modify the individual elements of the list. For example, “at least one of X, Y, or Z,” “at least one of X, Y, and Z,” and “at least one selected from the group consisting of X, Y, and Z” may be interpreted as only X, only Y, only Z, or any combination of two or more of X, Y, and Z, such as XYZ, XYY, YZ, and ZZ.

[0041] As used herein, the terms "substantially," "approximately," "approximately," and similar terms are used as terms of approximation rather than terms of degree, and are intended to take into account the inherent deviations in measured or calculated values ​​that one of ordinary skill in the art would recognize (i.e., limitations of the measurement system). As used herein, "approximately" or "approximately" is inclusive of the stated value and means within an acceptable range of deviation for a particular value as determined by one of ordinary skill in the art, thereby taking into account the measurement in question and the errors associated with the measurement of the particular quantity (i.e., limitations of the measurement system). For example, "approximately" may mean within one or more standard deviations, or within ±30%, 20%, 10%, 5% of the stated value. In addition, when describing embodiments of the present disclosure, the use of "may" refers to "one or more embodiments of the present disclosure."

[0042] When one or more embodiments can be implemented differently, a specific processing order can be performed differently from the described order. For example, two consecutively described processes can be performed substantially simultaneously or in an order opposite to the described order.

[0043] Any component or any combination of components described (e.g., in any system diagram included herein) may be used to perform one or more operations of any flow diagram included herein. In addition, (i) the operations are merely examples and may involve various additional operations not explicitly covered, and (ii) the temporal order of the operations may be changed.

[0044] Any suitable hardware, firmware (e.g., an application specific integrated circuit), software, or a combination of software, firmware, and hardware may be used to implement the electronic or electrical devices and / or any other related devices or components according to the embodiments of the present disclosure described herein. For example, the various components of these devices may be formed on an integrated circuit (IC) chip or on separate IC chips. In addition, the various components of these devices may be implemented on a flexible printed circuit film, a tape carrier package (TCP), a printed circuit board (PCB), or formed on a substrate.

[0045] In addition, the various components of these devices can be processes or threads running on one or more processors in one or more computing devices, executing computer program instructions and interacting with other system components to perform the various functions described herein. The computer program instructions are stored in a memory that can be implemented in a computing device using a standard memory device, such as, for example, a random access memory (RAM). The computer program instructions can also be stored in other non-transitory computer-readable media, such as, for example, a CD-ROM, a flash drive, etc. In addition, those skilled in the art will recognize that the functions of various computing devices can be combined or integrated into a single computing device, or the functions of a particular computing device can be distributed across one or more other computing devices without departing from the spirit and scope of the embodiments of the present disclosure.

[0046] Any functionality described herein (including any functionality that can be implemented with a host, device, etc., or a combination thereof) can be implemented with hardware, software, firmware, or any combination thereof that executes instructions stored in any type of memory, including, for example, hardware and / or software combinational logic, sequential logic, timers, counters, registers, state machines, volatile memory (such as dynamic RAM (DRAM) and / or static RAM (SRAM)), non-volatile memory (including flash memory), persistent memory (such as cross-grid non-volatile memory), memory with body resistance change, phase change memory (PCM), etc. and / or any combination thereof, complex programmable logic device (CPLD), field programmable gate array (FPGA), application specific IC (ASIC), central processing unit (CPU) including complex instruction set computer (CISC) processor and / or reduced instruction set computer (RISC) processor, graphics processing unit (GPU), neural processing unit (NPU), tensor processing unit (TPU), data processing unit (DPU), etc. In some embodiments, one or more components may be implemented as a system on a chip (SoC).

[0047] Any computing device disclosed herein may be implemented in any form factor (such as 3.5 inches, 2.5 inches, 1.8 inches, M.2, Enterprise and Datacenter Standard Form Factor (EDSFF), NF1, etc.) using any connector configuration (such as Serial Advanced Technology Attachment (SATA), Small Computer System Interface (SCSI), Serial Attached SCSI (SAS), U.2, etc.). Any computing device disclosed herein may be implemented and / or used in conjunction with, in whole or in part, a server chassis, a server rack, a data room, a data center, an edge data center, a mobile edge data center, and / or any combination thereof.

[0048] Any device disclosed herein that may be implemented as a storage device may be implemented with any type of non-volatile storage media based on solid-state media, magnetic media, optical media, etc. For example, in some embodiments, a storage device (e.g., a computational storage device) may be implemented as an SSD based on non-AND (NAND) flash memory, a persistent memory such as a cross-grid non-volatile memory, a memory with a body resistance change, PCM, etc., or any combination thereof.

[0049] Any communication connection and / or communication interface disclosed herein may be implemented using any type of interface and / or protocol utilizing one or more interconnects, one or more networks, a network of networks (e.g., the Internet), etc., or a combination thereof. Examples include Peripheral Component Interconnect Express (PCIe), Non-Volatile Memory Express (NVMe), NVMe-oF, Ethernet, Transmission Control Protocol / Internet Protocol (TCP / IP), Direct Memory Access (DMA) Remote DMA (RDMA), RDMA over Converged Ethernet (ROCE), Fibre Channel, InfiniBand, SATA, SCSI, SAS, Internet Wide Area RDMA Protocol (iWARP), and / or coherent protocols (such as Compute Express Link (CXL), CXL.mem, CXL.cache, CXL.IO, etc., Gen-Z, Open Coherent Accelerator Processor Interface (OpenCAPI), Cache Coherent Interconnect for Accelerators (CCIX), etc.), Advanced Extensible Interface (AXI), any generation of wireless networks including 2G, 3G, 4G, 5G, 6G, etc., any generation of Wi-Fi, Bluetooth, Near Field Communication (NFC), etc., or any combination thereof.

[0050] In some embodiments, the software stack may include a communication layer that may implement one or more communication interfaces, protocols, etc., such as PCIe, NVMe, CXL, Ethernet, NVMe-oF, TCP / IP, etc., to enable a host and / or an application running on the host to communicate with a computing device or a storage device.

[0051] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by those skilled in the art to which the inventive concept belongs. It will be further understood that, unless explicitly defined as such herein, terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant art and / or this specification, and should not be interpreted in an idealized or overly formal sense.

[0052] As described above, in the field of computer storage, a system may include a host and one or more storage devices communicatively coupled to the host. The storage device may include a solid-state drive (SSD). The storage device may be configured to perform functions for applications running on the host. For example, the storage device may be a computational storage device. As used herein, a "computational storage device" is a storage device including a processing circuit, which may also be included in addition to a storage device controller for performing functions near the memory. The processing circuit may include a hardware logic circuit (e.g., an application-specific integrated circuit (ASIC) or a field programmable gate array (FPGA), etc.). The processing circuit may be configured to perform functions for applications running on the host. For example, an application may send a request to perform a data analysis operation (e.g., a scan operation) on data associated with a database page. As used herein, a "database page" (also referred to as a "table") may include a data structure including rows (also referred to as "tuples") and columns associated with data fields in a data set. For example, a request to perform a scan operation may cause the storage device to compare data from one column of a database page (e.g., column data) with data from another column of a database page, and output data associated with the result of the comparison (e.g., a filter result). The storage device may send data associated with the results to the host for further processing.

[0053] Aspects of some embodiments of the present disclosure provide a scan operation architecture (e.g., an on-the-fly scan operation architecture discussed further below) to allow computer storage systems to expand to wider columns and wider database pages in database analysis workloads. Aspects of some embodiments of the present disclosure can reduce some resource constraints (e.g., FPGA resource constraints) of fixed parallel data path data analysis architectures. In some embodiments, software and hardware co-design schemes can be used to allow variable length outputs from filter results.

[0054] In some embodiments, a memory-based (eg, RAM-based) architecture may be used to implement crossbar functionality (eg, crossbar switch matrix functionality) while reducing consumption of hardware resources for performing scan operations.

[0055] In some embodiments, a hardware-generated pointer (eg, an indirect pointer) may be provided to software to locate the results of a variable-length filtered scan operation by indexing into an identified location of a database page.

[0056] Thus, aspects of some embodiments of the present disclosure provide improvements to computational storage, including reducing consumption of hardware resources while increasing flexibility.

[0057] Figure 1 is a system diagram depicting a data analytics accelerator according to some embodiments of the present disclosure.

[0058] refer to Figure 1 , the system 1 may include a host 100 communicatively coupled to a storage device 200 (e.g., a computing storage device). The host 100 may include an application 111. The application 111 may be associated with (e.g., may be run on) a CPU of the host 100. The application may process a workload WL. Based on processing the workload WL, the application 111 may send a command CMD (e.g., a scan command) to the storage device 200 to cause the storage device 200 to perform a scan operation associated with the workload WL. The storage device 200 may include a storage device 250, a memory 260, and a processing circuit 210. The storage device 250 may include a non-volatile memory (e.g., a non-volatile memory express (NVMe) SSD). The memory 260 may include a volatile memory (e.g., a dynamic random access memory (DRAM)). The memory 260 may be used at least in part by the storage device 200 to perform calculations on data stored in the storage device 250. Therefore, the memory 260 may be referred to as a computing memory. For example, data may be moved from the storage device 250 to the memory 260 so that the processing circuit may perform operations on the data associated with the memory 260. For example, the storage device 200 may copy the database page 10 from the storage device 250 to the memory 260 for processing the command CMD. The database page 10 may include column data C corresponding to the corresponding columns of the database page 10. The database page 10 may include row data R corresponding to the corresponding rows of the database page 10. The rows of the database page 10 may also be referred to as "tuples".

[0059] The processing circuit 210 may include a page processor 212, an extraction and reordering circuit 213, and a scan top circuit 220 (e.g., a scan circuit). As used herein, a "scan top circuit" refers to a component associated with the processing circuit 210 (e.g., as a component of the processing circuit 210) and including a scan-related component. The page processor 212 may receive a database page 10 from the memory 260. The page processor 212 may extract row data R from the database page 10. In some embodiments, the page processor 212 may extract the row data R from the database page 10 in a row-by-row (also referred to as "tuple-by-tuple") format.

[0060] The row data R may be further processed by the extraction and reordering circuit 213. The extraction and reordering circuit 213 may process the row data R using multiplexing, such as time division multiplexing (TDM). As used herein, "time division multiplexing" refers to a technique for transmitting data belonging to different columns on the same physical signal path (e.g., the same physical data line / wiring or differential pair wiring) at separate time intervals. The extraction and reordering circuit 213 may add flexibility to the processing of the row data R. The extraction and reordering circuit 213 may include a column filter 214 and a reorderer memory 216. The column filter 214 may receive the row data R from the page processor 212. The column filter 214 may find the column boundaries within the row data R, and may provide the column data C to the scan top circuit 220 through the reorderer memory 216. The functions of the components of the extraction and reordering circuit 213 are described below with respect to Figure 2A-Figure 4 Further detailed discussion.

[0061] The scan top circuit 220 may include one or more scan engines 222 (e.g., scan engine circuits). The output of the scan top circuit 220 may provide a result 262 associated with the command CMD. The processing circuit 210 may save the result 262 to the memory 260. The result of the scan operation may be retrieved based on the result 262 and sent to the host 100. In some embodiments, the result 262 may include a pointer 264 (e.g., an indirect pointer). The pointer 264 may refer to the address and length of the data associated with the database page 10. In such an embodiment, the result of the scan operation may be sent to the host 100 based on the data pointed to by the pointer 264. By using the pointer 264, the storage device 200 may be able to provide a variable length output. For example, in some embodiments, the output of the scan top circuit 220 may be limited to a given size (e.g., an 8-byte (B) format). When the row data R is relatively long (e.g., when the corresponding database page is relatively wide), the given size provided for the output of the scan top circuit 220 may be too small to provide the scan operation result associated with the row data R. However, the size of pointer 264 can be small enough regardless of the size of the data it points to. For example, pointer 264 can include the address and length of a given result, both of which can be encoded in a format with a given size (e.g., encoded in an 8B format).

[0062] Figure 2A is a diagram depicting extraction and reordering circuitry of a data analytics accelerator according to some embodiments of the present disclosure.

[0063] Figure 2B is a diagram depicting a crossbar switch matrix configuration associated with extraction and reordering circuits according to some embodiments of the present disclosure.

[0064] refer to Figure 2A , aspects of some embodiments of the present invention provide flexibility for processing column data C associated with different row sizes by means of extraction and reordering circuit 213. As described above, extraction and reordering circuit 213 may include column filter 214 and reorderer memory 216. In some embodiments, reorderer memory may include RAM. Column filter 214 may receive row data R and extract column data from a particular row. For example, column filter may receive a row including 16 columns. 16 columns may include zeroth column data C0 associated with zeroth column of 16 columns. 16 columns may also include fifteenth column data C15 associated with fifteenth column of 16 columns (e.g., n-1th column of n columns, where n is a positive integer). Column filter 214 may multiplex (e.g., time division multiplex) column data C (e.g., using TDM) onto a data path (e.g., a single data line / wiring or a differential pair wiring) connecting column filter 214 to reorderer memory 216. The reorderer memory 216 may receive the column data C and store the column data C in the buffer 218 in a first order (e.g., the order in which the column data C is received). The reorderer memory 216 may provide the column data C in a second order different from the first order to an output port of the extraction and reordering circuit 213. The output port of the extraction and reordering circuit 213 may be connected to a corresponding input port of the scan engine 222. The extraction and reordering circuit 213 may output the column data C to the scan engine 222 in packets GR (e.g., the zeroth packet GR0 and the fifteenth packet GR15).

[0065] refer to Figure 2B, the reorderer memory 216 can provide a storage and forwarding cross switch matrix implementation mechanism. For example, the reorderer memory 216 can output the column data C in a second order based on the cross switch matrix configuration XB (e.g., a RAM-based cross switch matrix configuration). The cross switch matrix refers to a component with a dedicated signal path from any input port to any output port. As used herein, "cross switch matrix configuration" refers to the configuration of hardware and / or software components, which enables the component to send different input combinations to any output port for further processing by another component. In some embodiments, the reorderer memory 216 can provide the column data C to the first input port PA and the second input port PB in a group GR based on the cross switch matrix configuration XB. For example, the zeroth group GR0 may include the zeroth column data C0 from the zeroth column and the eighth column data C8 from the eighth column. According to the cross switch matrix configuration XB, and based on the command CMD, the reorderer memory 216 can output the zeroth column data C0 to the first output port of the extraction and reordering circuit 213, and can output the eighth column data C8 to the second output port of the extraction and reordering circuit 213. The first output port of the extraction and reordering circuit 213 may be connected to the first input port PA of the scan engine 222. The second output port of the extraction and reordering circuit 213 may be connected to the second input port PB of the scan engine 222. Although the present disclosure discusses two input ports to the scan engine 222, it should be understood that the present disclosure is not limited thereto. For example, the scan engine 222 may have any number of input ports, and the packet GR may include a set of column data corresponding to the number of input ports.

[0066] The reorderer memory 216 can provide more efficient grouping of column data C for a scan operation compared to a fixed column crossbar switch matrix structure. For example, the reorderer memory 216 can allow the scan engine 222 to process wider rows (e.g., rows with more columns). The reorderer memory 216 can allow the scan engine 222 to more efficiently process rows with different widths.

[0067] Figure 3 is a diagram depicting the operation of an extract and reorder circuit and a scan top circuit according to some embodiments of the present disclosure.

[0068] As mentioned above Figure 1As discussed, the processing circuit 210 may include an extraction and reordering circuit 213 and a scan top circuit 220. The extraction and reordering circuit 213 may include a column filter 214 and a reorderer memory 216. The scan top circuit 220 may include a scan engine 222. The scan top circuit 220 may include additional components for processing the output of the scan engine 222. The column filter 214 may extract column data C from a given row data R (e.g., may extract column data C corresponding to each column of a given row, respectively).

[0069] In some embodiments, the column filter 214 may transmit one column at a time to the reorderer memory 216. For example, for a given row, the column filter 214 may send data associated with each column in the given row as the data is extracted, without waiting to extract all column data associated with the given row. Thus, the architecture of the processing circuit 210 may be referred to as an "on-the-fly" streaming architecture. In some embodiments, the column filter 214 may deliver one column at a time using TDM. TDM allows the use of only one scan engine, where a fixed parallel path approach would require more than one scan engine. For example, instead of the column filter 214 extracting all column data C from the row data R and delivering all column data C together to the reorderer memory 216 via separate parallel data paths, the column filter 214 may deliver data associated with the corresponding column of the row to the reorderer memory 216 after (e.g., immediately after or at the time of) extracting each column data C from the row data R. Thus, the processing circuit 210 may perform scan operations on wider rows while using fewer resources than using a fixed parallel path approach.

[0070] In some embodiments, the column data C may be stored at an entry E of a buffer 218 of the reorderer memory 216. In some embodiments, the column data C may be stored in the buffer 218 based on the order in which the column data C is extracted. For example, the column filter 214 may extract the first column data C1 from the row data R. The column filter 214 may send the first column data C1 to the reorderer memory 216 via a first data path DP1 (e.g., using TDM). The reorderer memory 216 may store the first column data C1 at the zeroth entry E0 of the reorderer memory 216. The column filter 214 may extract the second column data C2 from the row data R. The column filter 214 may send the second column data C2 to the reorderer memory 216 via a first data path DP1 (e.g., using TDM). The reorderer memory 216 may store the second column data C2 at the first entry E1 of the reorderer memory 216. The column filter 214 may extract the n-1th column data Cn-1 from the row data R. The column filter 214 may transmit the n-1th column data Cn-1 to the reorderer memory 216 via the first data path DP1 (eg, using TDM). The reorderer memory 216 may store the n-1th column data Cn-1 at the second entry E2 of the reorderer memory 216.

[0071] In some embodiments, the reorderer memory 216 may include a buffer write controller 272, a configuration register 274, and / or a buffer read controller 276. The buffer write controller 272 may write the extracted column data from the column filter 214 to the buffer 218 in sequence (e.g., according to a predefined order). In some embodiments, the first extracted (e.g., filtered) column data C may be saved to the buffer 218 at the zeroth entry E0, and the subsequently extracted column data C may be placed in the next entry (e.g., E1, E2, E3, etc.) in increments of one. In some embodiments, the configuration register 274 may be used to select the input of each scan operation based on the crossbar switch matrix configuration. For example, the first scan operation may include a comparison of the second column data C2 at the first input port PA with the n-1th column data Cn-1 at the second input port PB. The second scan operation may include a comparison of the first column data C1 at the first input port PA with the second column data C2 at the second input port PB. The buffer read controller 276 may retrieve the column data C from the buffer 218 in the order provided by the configuration register 274. The buffer read controller 276 may cause the column data C to be received by the scan engine 222 according to the crossbar switch matrix configuration and based on TDM. The reorderer memory 216 may send the column data C in packets GR to the scan engine 222 based on the crossbar switch matrix configuration, as described above with respect to Figure 2BAs discussed. Scan engine 222 may receive column data from reorderer memory 216 based on TDM according to a crossbar switch matrix configuration. Thus, extraction and reordering circuit 213 may provide paired time-division outputs.

[0072] In some embodiments, the output of scan engine 222 may be saved to scan vector SV. For example, the output of scan engine 222 may be accumulated as it is generated by scan engine 222 and saved to scan vector SV. Scan top circuit 220 may provide result 262 (e.g., data associated with the output of scan engine 222) to memory 260. For example, the output of scan engine 222 may be further processed to generate result 262. Scan top circuit 220 may send result 262 to memory 260.

[0073] In some embodiments, the result 262 may include a pointer 264 (e.g., an indirect pointer) instead of a calculated result of a scan operation. By providing a pointer 264 instead of a calculated result, the processing circuit 210 may perform a scan operation on a wider row with different widths. The pointer 264 may include an address and a length. The address and length may indicate where the calculated result from the scan operation may be found. In some embodiments, the address and length provided by the pointer 264 may correspond to a database page 10 stored in the memory 260. The hardware of the processing circuit 210 may effectively generate the scan operation result while using software to more flexibly process post-processing operations, such as retrieving the result of the scan operation by referring to the address and length provided by the pointer 264. Therefore, the storage device of such an embodiment may combine both software and hardware components to support indirect variable length output.

[0074] Figure 4 is a flow chart depicting example operations of a method for data processing for a data analytics accelerator according to some embodiments of the present disclosure.

[0075] refer to Figure 4 , the method 4000 may include the following example operations. The extraction and reordering circuit 213 (e.g., a first circuit) may receive row data R of a database page 10 (e.g., a page) (operation 4001). The extraction and reordering circuit 213 may extract first column data C and second column data C from the row data R (operation 4002). The extraction and reordering circuit 213 may multiplex (e.g., transmit using TDM) the first column data C and the second column data C so that both the first column data C and the second column data C are output (e.g., transmitted or provided) to a first output port of the extraction and reordering circuit 213 (operation 4003).

[0076] Thus, aspects of some embodiments of the present disclosure can provide improvements to computer storage by allowing a computing storage device to perform data grouping operations using fewer scan engines without performance loss; allowing scan engines to perform scan operations on wider database pages (e.g., database pages with more columns); and allowing the system to process variable length output from wider database pages with rows of different sizes. Thus, aspects of some embodiments of the present disclosure provide more efficient processing of database pages.

[0077] Example embodiments of the present disclosure may be extended to the following statements, but are not limited thereto:

[0078] Statement 1. An example method includes receiving, by a first circuit, row data of a page, receiving, by the first circuit, first column data and second column data from the row data, and sending, by the first circuit, the first column data and the second column data to a first output port of the first circuit.

[0079] Statement 2. An example method includes the method of Statement 1, wherein transmitting includes performing time division multiplexing (TDM) on the first column of data and the second column of data.

[0080] Statement 3. Example methods include the method of any of Statements 1 and 2, wherein the first circuit includes a column filter configured to receive the first column data and the second column data from the row data and output the first column data and the second column data to the first data path based on TDM.

[0081] Statement 4. An example method includes the method of any of Statements 1-3, wherein the first circuit includes a first memory, the first memory configured to receive the first column data and the second column data from the first data path, store the first column data and the second column data in a buffer in a first order, and output the first column data and the second column data in a second order different from the first order.

[0082] Statement 5. An example method includes the method as recited in Statement 4, wherein the first memory comprises random access memory (RAM).

[0083] Statement 6. An example method includes the method of any of Statements 1-5, wherein a first output port of the first circuit is connected to a first input port of the scan circuit, and a second output port of the first circuit is connected to a second input port of the scan circuit.

[0084] Statement 7. Example methods include the method of any of Statements 1-6, wherein the first circuit groups the first column of data with the third column of data output to the second output port.

[0085] Statement 8. An example method includes the method of Statement 7, wherein the scan circuit performs a scan operation including a comparison of the first column data with the third column data, and outputs resultant data based on the scan operation.

[0086] Statement 9. An example method includes the method of Statement 8, wherein the result data includes an address for locating a result of the scanning operation.

[0087] Statement 10. Example methods include the method of any of Statements 8 and 9, wherein the result data includes a length associated with the page.

[0088] Statement 11. Example methods include the method of any of Statements 6-11, wherein the scanning circuit performs a scanning operation on one or more columns of the row data.

[0089] Statement 12. An example apparatus for performing the method of any of Statements 1-11 includes a first circuit.

[0090] Statement 13. An example system for performing the method of any of Statements 1-11 includes a processor and a memory storing instructions, the instructions causing the processor to perform the method of any of Statements 1-11 upon execution by the processor.

[0091] While embodiments of the present disclosure have been particularly shown and described with reference to the embodiments described herein, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the present disclosure as set forth in the appended claims and their equivalents.

Claims

1. A method for data processing, the method comprising: Receiving row data of a page by a first circuit; receiving, by the first circuit, first column data and second column data from the row data; as well as The first column data and the second column data are sent by the first circuit to a first output port of the first circuit.

2. The method according to claim 1, wherein: The sending includes performing time division multiplexing (TDM) on the first column data and the second column data.

3. The method according to claim 1, wherein: The first circuit includes a column filter configured to: receiving the first column data and the second column data from the row data; and The first column data and the second column data are output to a first data path based on TDM.

4. The method according to claim 3, wherein: The first circuit includes a first memory, and the first memory is configured to: receiving the first column data and the second column data from the first data path; storing the first column data and the second column data in a buffer in a first order; as well as The first column data and the second column data are output in a second order different from the first order.

5. The method according to claim 4, wherein: The first memory comprises a random access memory RAM.

6. The method according to claim 1, wherein: The first output port of the first circuit is connected to a first input port of a scanning circuit; and A second output port of the first circuit is connected to a second input port of the scanning circuit.

7. The method according to claim 6, wherein: The first circuit groups the first column data with third column data output to the second output port.

8. The method according to claim 7, wherein: The scanning circuit: performing a scanning operation, the scanning operation comprising comparing the first column of data with the third column of data; and Result data is output based on the scanning operation.

9. The method according to claim 8, wherein: The result data includes an address for locating a result of the scanning operation.

10. The method according to claim 9, wherein: The result data includes a length associated with the page.

11. The method according to claim 8, wherein: The scanning circuit performs a scanning operation on one or more columns of the row data.

12. A storage device comprising a first circuit for: Receive the row data of the page; receiving first column data and second column data from the row data; as well as The first column data and the second column data are sent to a first output port of the first circuit.

13. The storage device according to claim 12, wherein: The sending includes performing time division multiplexing (TDM) on the first column data and the second column data.

14. The storage device according to claim 12, wherein: The first output port of the first circuit is connected to a first input port of a scan circuit.

15. The storage device according to claim 14, wherein: The scanning circuit: performing a scan operation associated with the first input port of the scan circuit; and Result data is output based on the scanning operation.

16. The storage device according to claim 14, wherein: The scanning circuit performs a scanning operation on one or more columns of the row data.

17. A system for data processing, the system comprising: processor; as well as A memory storing instructions, upon execution by the processor, the instructions causing the processor to execute: Receive the row data of the page; extracting first column data and second column data from the row data; as well as The first column data and the second column data are sent to a first output port of a first circuit.

18. The system of claim 17, wherein: The sending includes performing time division multiplexing (TDM) on the first column data and the second column data.

19. The system of claim 17, wherein: The first output port of the first circuit is connected to a first input port of a scan circuit.

20. The system of claim 19, wherein: The scanning circuit: performing a scan operation associated with the first input port of the scan circuit; and Result data is output based on the scanning operation.

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