Serial communication control method and device, electronic equipment and storage medium

Abstract

The invention provides a serial communication control method and device, electronic equipment and a storage medium. The serial communication control method is applied to a digital signal processor (DSP), the DSP comprises a configurable logic block, and the method comprises the following steps: determining a period duration count value according to an agreed baud rate of serial communication and a clock signal of the DSP; the configurable logic block controls the first counter to perform accumulative counting based on the clock signal of the DSP, outputs a first signal in response to the accumulative counting of the first counter reaching a preset second numerical value, outputs a second signal in response to the accumulative counting reaching a preset first numerical value, and resets the first counter; a first clock signal is generated according to the first signal and the second signal, and the frequency of the first clock signal is the frequency corresponding to the agreed baud rate; and controlling the time sequence of the first clock signal to be aligned with the time sequence of the data frame of the bus. The embodiment of the invention is simpler, more flexible and better in effect.

Description

Technical Field

[0001] The present application relates to the field of communication technology, and in particular to a serial communication control method, device, electronic device and storage medium. Background Art

[0002] Serial communication has been widely used because of its simple control circuit and strong anti-interference ability. In actual application scenarios, since there is no transmission synchronization clock, the terminal devices of serial communication must communicate at an agreed baud rate. If the serial communication line is too long, and the working clocks of different devices deviate from the bus clock, the positive and negative errors of the baud rate will accumulate during communication, causing the terminal device to deviate when parsing the timing of each byte, and then the communication frame parsing error. In traditional technology, a separate dedicated integrated circuit is generally used to achieve serial communication anti-interference, but it is more complicated and costly. Summary of the invention

[0003] The present application provides a serial communication control method, device, electronic device and storage medium to solve the problem that the traditional technology uses a separate dedicated integrated circuit to achieve serial communication anti-interference, which is relatively complicated. The following introduces various aspects involved in the present application.

[0004] In a first aspect, the present application provides a serial communication control method, which is applied to a digital signal processor (DSP), wherein the DSP includes a configurable logic block, and the configurable logic block is configured with a first counter; the method includes: determining a preset first value based on the agreed baud rate of the serial communication and the clock signal of the DSP; the preset first value is a cycle duration count value; controlling the first counter to perform cumulative counting based on the clock signal of the DSP, and outputting a first signal in response to the accumulated count of the first counter reaching a preset second value; outputting a second signal and resetting the first counter in response to the accumulated count of the first counter reaching the preset first value; generating a first clock signal based on the first signal and the second signal, the frequency of the first clock signal being the frequency corresponding to the agreed baud rate; and controlling the timing of the first clock signal to be aligned with the timing of the data frame of the bus.

[0005] In the second aspect, the present application provides a serial communication control device, which is applied to a DSP; the DSP includes a configurable logic block; the configurable logic block is configured with a first counter; the serial communication control device includes: a determination unit, which is used to determine a preset first value based on the agreed baud rate of the serial communication and the clock signal of the DSP; the preset first value is a cycle duration count value; a counting unit, which is used to control the first counter to perform cumulative counting based on the clock signal of the DSP, and output a first signal in response to the accumulated count of the first counter reaching a preset second value; in response to the accumulated count of the first counter reaching the preset first value, a second signal is output and the first counter is reset; a generation unit, which is used to generate a first clock signal based on the first signal and the second signal, the frequency of the first clock signal being the frequency corresponding to the agreed baud rate; a corresponding unit, which is used to control the timing of the first clock signal to be aligned with the timing of the data frame of the bus.

[0006] In a third aspect, the present application provides an electronic device, including a memory and a DSP, wherein the memory stores a computer program, and when the DSP executes the computer program, the steps of the method described in the first aspect are implemented.

[0007] In a fourth aspect, the present application provides a non-volatile computer-readable storage medium, which stores a computer program, and when the computer program is executed by a processor, it can implement the method described in the first aspect.

[0008] In a fifth aspect, the present application provides a computer program product, which, when executed on an electronic device, enables the electronic device to implement the method described in the first aspect.

[0009] The embodiment of the present application maps the hardware description language logic of the field programmable gate array to the configurable logic block (CLB) of the DSP. Since the CLB is a built-in module and has hardware resources such as counters, these hardware resources can be interconnected through programming to build the logic circuit required by the user. The CLB cooperates with the DSP clock signal to generate a system clock signal of the agreed baud rate, and aligns the generated system clock signal with the timing of the data frame, which can directly process the data of the serial communication and avoid the problem of serial communication data frame parsing errors caused by baud rate deviation. The embodiment of the present application uses the configurable logic block inside the DSP to realize the anti-interference function of the serial communication, without the need to use a separate dedicated integrated circuit, which is simpler, more flexible, low-cost and more effective. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required for use in describing the embodiments of the present application are briefly introduced below.

[0011] Figure 1 It is a flow chart of a serial communication control method provided in an embodiment of the present application.

[0012] Figure 2 This is a working diagram of a counter.

[0013] Figure 3 yes Figure 1 A flowchart of a possible implementation of the method.

[0014] Figure 4 It is a working schematic diagram of a finite element state machine.

[0015] Figure 5 yes Figure 1 A circuit diagram of a possible implementation of the method.

[0016] Figure 6 yes Figure 1 A circuit diagram of another possible implementation of the method.

[0017] Figure 7 It is a schematic diagram of the composition of the serial communication control device provided in an embodiment of the present application.

[0018] Figure 8 It is a schematic diagram of a component unit / partial component unit of an electronic device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0019] The technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all of the embodiments. The same or similar reference numerals are used in the drawings to represent the same or similar modules. It should be understood that the drawings are only schematic, and the protection scope of the present application is not limited thereto.

[0020] Serial interface (SI) refers to the sequential transmission of data one bit at a time. It is a very commonly used low-speed communication interface. Its characteristic is that the communication line is simple, and two-way communication can be achieved with just one pair of transmission lines. Baud rate is a parameter to measure the communication speed. It indicates the number of bits transmitted per second. The unit of baud rate is baud. The devices connected to the serial port communicate at the agreed baud rate, that is, the devices at both ends of the serial port can only achieve normal communication under the condition of maintaining the same rate, otherwise the debugging instructions will be invalid and garbled characters will be displayed.

[0021] In the control system of the inverter, serial communication has been widely used because of its simple control circuit and strong anti-interference ability. In actual application scenarios, since there is no transmission synchronous clock, the terminal equipment of serial communication must communicate at an agreed baud rate. The receiving device will sample the received communication byte level at the rising edge of the clock according to its own working clock timing, and finally correctly parse a single communication byte.

[0022] In actual applications, if the serial communication line is too long and the working clock of different devices deviates from the bus clock, the positive and negative errors of the baud rate will accumulate during communication, causing the terminal device to deviate when parsing the timing of each byte, and then the communication frame parsing error. Electromagnetic compatibility (EMC) interference on the bus will also affect the waveform of serial communication, resulting in communication frame parsing errors, which will reduce the anti-interference performance of serial communication.

[0023] In order to improve the anti-interference performance of communication, the terminal equipment of serial communication needs to consider the baud rate adaptive method. The related technology uses a separate dedicated integrated circuit to achieve anti-interference. However, the anti-interference of serial communication using a dedicated integrated circuit is relatively complex and costly.

[0024] Therefore, it is necessary to design a relatively simple technical solution for anti-interference of serial communication.

[0025] Based on this, the embodiment of the present application proposes a serial communication control method. The method of the embodiment of the present application is applied to a digital signal processor (DSP), wherein the DSP includes a configurable logic block (CLB), and the configurable logic block is configured with a first counter. The embodiment of the present application directly processes the waveform of the serial communication through the CLB module built into the DSP, so as to realize the anti-interference control of the serial communication. Figure 1 The serial communication control method of the embodiment of the present application is described in detail. Figure 1 As shown, the serial communication control method of the embodiment of the present application may mainly include steps S110 to S140, and these steps are described in detail below.

[0026] It should be pointed out that the size of the serial numbers of the steps in the embodiments of the present application does not mean the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present application.

[0027] In step S110, a preset first value is determined according to the agreed baud rate of the serial communication and the clock signal of the DSP. The preset first value is a cycle duration count value.

[0028] Among them, the cycle duration count value is determined by the baud rate agreed upon for serial communication and is configured before the communication begins. The receiving device must be synchronized to the agreed baud rate sent in order to correctly sample the received data. Ideally, the sampling clock in the receiving device can be an even multiple of the agreed baud rate, such as 16 times the baud rate frequency. The sampling clock counts an even number of bits so that there are an equal number of high pulses and low pulses. For example, when the agreed baud rate is 2MBps and the clock frequency of the high-frequency DSP being sampled is 48MHz, then every 24 sampling clock cycles is equal to the time it takes to transmit one bit, so the cycle duration count value can be set to 24.

[0029] In step S120, the first counter is controlled to perform cumulative counting based on the clock signal of the DSP. In response to the cumulative count of the first counter reaching the preset second value, a first signal is output. In response to the cumulative count of the first counter reaching the preset first value, a second signal is output and the first counter is reset. The first counter is controlled to be cleared and restarted to count, so that the automatic cycle can ensure the accuracy of the data stored in the first counter, thereby improving the stability of the communication clock. Among them, the preset second value is a value less than the cycle duration count value. Preferably, the preset second value is 1 / 2 of the preset first value.

[0030] The counter is a logic element widely used in digital circuits, which is used to count the number of input pulses, and can also be used for functions such as frequency division, timing, and generating beat pulses. The first counter can be any type of counter as long as it meets the function in step S120. The first counter can refer to a single counter or a counter module composed of multiple counters.

[0031] Figure 2 This is a schematic diagram of a counter. Figure 2 As shown, the counter 200 may have 4 input ports and 3 output ports (pins). The 4 input ports are mode 1 (mode1), mode 2 (mode2), event (event), and reset (reset) ports, and the 3 output ports are match 1 (match1), match 2 (match2), and zero (zero) ports. The counter 200 may be a type of first counter. The counter 200 may accumulate counts with the DSP clock signal. When the count matches the preset second value, the match1 port outputs a high-level pulse signal. When the count reaches the preset first value, that is, when the cycle length of the baud rate is reached, the zero port outputs a high-level trigger signal, and the reset port is reset to restart counting.

[0032] The cycle duration count value is an even number, and the DSP clock signal is counted with an even number of bits, so it can have an equal number of high pulses and low pulses, which helps to reduce the baud rate error and improve the stability of communication.

[0033] In step S130, a first clock signal is generated according to the first signal and the second signal, and the frequency of the first clock signal is a frequency corresponding to the agreed baud rate.

[0034] It can be understood that the first signal and the second signal are signals generated alternately. One first signal and one second signal constitute a cycle, and then enter the next cycle.

[0035] In some implementations, the configurable logic block is configured with a first finite element state machine. The method in step S130 may include: controlling the first finite element state machine to output a first level according to an input first signal, the first level being a high level; controlling the first finite element state machine to output a second level according to an input second signal, the second level being a low level; generating a first clock signal according to the first level and the second level, thereby generating a clock signal of the agreed baud rate of the communication. It can be understood that the first level and the second level are signals alternately generated by the first finite element state machine.

[0036] In step S140, the timing of the first clock signal is controlled to be aligned with the timing of the data frame of the bus.

[0037] According to the serial port protocol, when no data is transmitted or the data transmission is completed, the communication data line must be kept at a high level. When the sender starts to send data, it must first send a low level as the start bit data. Specifically, when in the start bit waiting state, when the received serial port data has a falling edge, it indicates that the start bit data has been obtained, and then the first counter is controlled to start counting.

[0038] A typical single frame of data has 10 bits of data, including 1 start bit, 8 data bits and 1 stop bit, so there may be multiple falling edges. In some implementations, the method of step S140 may specifically include: resetting the first counter according to at least one falling edge pulse signal among the multiple falling edge pulse signals of the received data frame, so that the first counter recounts to align the timing of the first clock signal with the timing of the data frame of the bus. Thereby, it can be ensured that the timing of the generated first clock signal is aligned with the timing of the data frame.

[0039] In order to prevent the noise of the data line from being mistakenly judged as the starting data, the serial port data can be collected multiple times to improve the accuracy of the start bit data acquisition. In some implementations, the configurable logic block is configured with a first lookup table. The first input end of the first lookup table is used to receive the signal of the data frame of the bus, and the output end of the first lookup table is connected to the reset port of the first counter. The method of step S140 may include: in response to the first lookup table receiving the first falling edge pulse signal of the data frame, outputting a high level pulse signal, and the high level pulse signal is used to reset the first counter. Usually a data frame has multiple falling edge pulse signals, and the first falling edge pulse signal is any falling edge pulse signal of the multiple falling edge pulse signals of the data frame. Using multiple falling edge pulse signals to perform multiple correction timings helps to avoid timing deviations caused by interference and baud rate deviations, and further enhances the anti-interference ability of serial communication.

[0040] There are usually some spike pulse interferences in the serial communication bus, so it is necessary to filter the pulse signal of the bus. The pulse signal of the bus can be filtered by using a multiplied frequency clock signal.

[0041] In some implementations, the configurable logic block is configured with a second counter. The method of the embodiment of the present application may also include: controlling the second counter to perform cumulative counting based on the clock signal of the DSP, and outputting a third signal in response to the cumulative count of the second counter reaching 1 / 2n of the preset first value. In response to the cumulative count reaching 1 / n of the preset first value, a fourth signal is output, and the second counter is reset, where n is an even number, for example, n can be 4, 8, 16, etc. A second clock signal is generated based on the third signal and the fourth signal. It can be seen that the frequency of the second clock signal is n times the frequency of the first clock signal. That is, the second clock signal is an n-fold frequency signal of the first clock signal, and the pulse signal of the received bus can be filtered according to the second clock signal.

[0042] In some implementations, the configurable logic block is configured with a second finite element state machine. The above-mentioned generating the second clock signal according to the third signal and the fourth signal may include: controlling the second finite element state machine to output a high level and a low level respectively according to the input third signal and the fourth signal; generating the second clock signal according to the alternating high level and the low level.

[0043] In some specific implementations, the configurable logic block is configured with a second lookup table, a third finite element state machine, a third counter and a fourth counter. The received pulse signal of the bus is connected to the reset port of the third counter. The above-mentioned filtering of the received pulse signal of the bus according to the second clock signal may include: using the second lookup table to invert the received pulse signal of the bus, and the inverted pulse signal of the bus is connected to the reset port of the fourth counter; based on the second clock signal, using the third counter to count the high level pulses in the pulse signal of the bus, and using the fourth counter to count the low level pulses in the pulse signal of the bus. In response to the cumulative count of the third counter reaching the preset sampling length, a fifth signal is output, and the preset sampling length is n / 2; in response to the cumulative count of the fourth counter reaching the preset sampling length, a sixth signal is output. The third finite element state machine is controlled to output a high level and a low level respectively according to the input fifth signal and the sixth signal; according to the high level and the low level output by the third finite element state machine periodically, the pulse signal of the filtered bus is output. The multiple n of the multiplication frequency can be 4, for example, and the received pulse signal of the bus can be filtered according to the 4-fold clock signal.

[0044] Since the second clock signal is a multiple frequency signal of the first clock signal, in some implementations, the first counter can count based on the second clock signal generated by the second counter to obtain the first clock signal, which helps to further simplify the circuit.

[0045] The embodiment of the present application maps the hardware description language (VHDL) logic of the field programmable gate array (FPGA) to the CLB of the DSP itself. Since the CLB is a built-in module and has hardware resources such as counters, these hardware resources can be interconnected through programming to build the logic circuit required by the user. The CLB cooperates with the DSP signal to generate a system clock signal of the agreed baud rate, and aligns the generated system clock signal with the timing of the data frame, which can directly process the serial communication data and avoid the problem of serial communication data frame parsing errors caused by baud rate deviation. The embodiment of the present application does not need to use a separate dedicated integrated circuit, and uses the CLB module inside the DSP to realize the anti-interference of serial communication, which is simpler, more flexible, low-cost, and more effective.

[0046] The method of the embodiment of the present application is further explained below in combination with some possible implementation methods of the embodiment of the present application.

[0047] Figure 3 yes Figure 1A flow chart of a possible implementation of the method. Figure 3 As shown, the counting process of the first counter in the embodiment of the present application may mainly include steps S310 to S380, and these steps are described in detail below.

[0048] In step S310, start.

[0049] In step S320, the counter counts up.

[0050] The first counter performs cumulative counting based on the DSP clock signal. The structure of the counter can be as follows: Figure 2 shown.

[0051] In step S330, it is determined whether the count value reaches a preset second value (ie, 1 / 2 of the cycle duration count value).

[0052] If the accumulated count value reaches the preset second value, the process proceeds to step S350; otherwise, the process continues counting.

[0053] In step S340, it is determined whether the count value reaches a preset first value (ie, the cycle duration count value).

[0054] That is, it is determined whether the cycle duration count value is reached. If the accumulated count value reaches the preset first value, the process proceeds to step S360; otherwise, the process continues to count.

[0055] In step S350, the match1 port of the counter outputs a high level pulse signal, that is, outputs a first signal.

[0056] In step S360, the match2 port of the counter outputs a high level pulse signal, that is, outputs a second signal.

[0057] In step S370, it is determined whether the reset port receives a reset signal.

[0058] In step S380, the first counter is reset, and the zero port outputs a high level pulse signal.

[0059] After reaching the cycle length count value of the agreed baud rate, the reset port will be reset and restart counting to start counting the next cycle period, so as to cyclically generate the first signal and the second signal.

[0060] The cycle duration count value is an even number, and the DSP clock signal is counted with an even number of bits, which can have an equal number of high pulses and low pulses, helping to improve the stability of the baud rate and reduce the system's cumulative error.

[0061] Figure 4It is a state diagram of a finite element state machine. The finite element state machine (FSM) consists of a state register and a combinational logic circuit. It can transfer states according to pre-set states based on control signals. It is a control element that coordinates related signal actions and completes specific operations.

[0062] like Figure 4 As shown, when the match1 port of the first counter outputs a high-level trigger signal to the finite element state machine (FSM), the finite element state machine outputs a high-level "1". When the first counter reaches the baud rate cycle length count value, it will be reset, and the zero port will output a high-level trigger signal to the FSM, and the finite element state machine will output a low-level "0". The alternating high-level "1" and low-level "0" generate the first clock signal, that is, the baud rate clock signal agreed upon in the communication.

[0063] Figure 5 yes Figure 1 A circuit diagram of a possible implementation of the method. Figure 5 As shown, the configurable logic block 500 may include: a second counter 510 , a second finite element state machine 520 , a first lookup table 530 , a first counter 540 , a first finite element state machine 550 , a third lookup table 560 , and a fourth lookup table 570 .

[0064] The third lookup table 560 and the fourth lookup table 570 are LUT3, which are lookup tables (LUT) with three inputs. The first lookup table 530 is LUT4, which is a lookup table with four inputs. Lookup tables are usually used to implement combinational logic that any given input combination corresponds to a specific output.

[0065] Figure 5 In the embodiment, it includes two parts: generating a system clock and aligning a clock. The system clock generates two groups of clock signals, one group is a quadruple frequency clock signal (i.e., the second clock signal) for pulse filtering; the other group is a normal baud rate clock signal (i.e., the first clock signal) for clock alignment processing. The configurable logic block 500 uses a counter (COUNT) and a finite element state machine (FSM) to generate a clock signal that meets the serial communication baud rate. The second counter 510, the second finite element state machine 520 and the fourth lookup table 570 are used to generate the second clock signal (i.e., the quadruple frequency clock signal).

[0066] 1) Generate system clock signal.

[0067] First, the cycle length count value is calculated according to the agreed baud rate of the serial communication and the DSP clock signal. According to the cycle length count value, a preset first value and a preset second value are determined. Among them, the preset first value is the cycle length count value of the system baud rate, and the preset second value is half of the cycle length count value.

[0068] According to the cycle length count value, a preset third value and a preset fourth value of the quadruple frequency clock signal are determined, wherein the preset third value is 1 / 4 of the cycle length count value, and the preset fourth value is 1 / 8 of the cycle length count value.

[0069] Based on the DSP clock signal, the second counter 510 performs cumulative counting. When the count value reaches the preset value, the corresponding port will output a high-level pulse signal to drive the subsequent logic unit logic processing. For example, when the count value reaches the preset fourth value, the match1 port of the second counter 510 outputs a high-level trigger signal to the second finite element state machine 520, and the second finite element state machine 520 outputs a high level "1". When the count value reaches the preset third value (1 / 4 of the cycle length count value), it will be reset, and the zero port of the second counter 510 outputs a high-level trigger signal to the second finite element state machine 520, and the second finite element state machine 520 outputs a low level "0". According to the high and low levels alternately generated by the second finite element state machine 520, the fourth lookup table 570 generates a quadruple-frequency baud rate clock signal. The quadruple-frequency clock signal can be used for pulse signal filtering of the bus. The serial communication bus can be, for example, an RS-422 bus or an RS-485 bus.

[0070] Based on the DSP clock signal, the first counter 540 performs cumulative counting. When the count value matches the preset second value, the match1 port of the first counter 540 outputs a high-level trigger signal to the first finite element state machine 550, and the first finite element state machine 550 outputs a high-level "1". When the count value reaches the preset first value (the cycle length count value of the agreed baud rate), the first counter 540 will be reset, and the zero port of the first counter 540 will output a high-level trigger signal to the first finite element state machine 550, and the first finite element state machine 550 will output a low-level "0". According to the high and low levels cyclically output by the first finite element state machine 550, the second lookup table 560 generates a clock signal of the agreed baud rate, that is, the first clock signal.

[0071] 2) Clock alignment processing.

[0072] The configurable logic block 500 uses a LUT4, namely a first lookup table 530, to achieve timing alignment between the first clock signal and the data frame.

[0073] A single frame of data contains a total of 10 bits of data, including 1 start bit, 8 data bits and 1 stop bit, and there may be multiple falling edges. The falling edge pulse signal of the data is connected to the input port i0 of the first lookup table 530. When the falling edge pulse signal (i.e., the first falling edge pulse signal) arrives, the pulse signal drives the output port of the third lookup table 570 to output a high level pulse signal. The output high level pulse signal is connected to the reset port of the first counter 540 and the reset port of the second counter 510, so that the first counter 540 and the second counter 510 are re-counted, that is, the system clock is re-counted, which can ensure that the generated system clock is aligned with the timing of the data frame. In other words, the timing of the first clock signal is aligned with the timing of the data frame, and the timing of the second clock signal is aligned with the timing of the data frame. Multiple falling edge pulse signals in each data frame can be used to perform multiple correction timings, which helps to avoid timing deviations caused by interference and baud rate deviations, and enhance the anti-interference ability of serial communication.

[0074] Figure 6 yes Figure 1 A circuit diagram of another possible implementation of the method. Figure 6 As shown, the configurable logic block 500 may further include: a second lookup table 610, a third counter 620, a fourth counter 630, a third finite element state machine 640, and a fifth lookup table 650. The second lookup table 610 is LUT4, which is a lookup table with four inputs. The fifth lookup table 650 is LUT3, which is a lookup table with three inputs.

[0075] Specifically, the configurable logic block 500 uses the second lookup table 610 to invert the serial communication data input signal, and uses two counters to count the number of pulses of the bus. The third counter 620 and the fourth counter 630 are used for high-level pulse counting and low-level pulse counting, respectively. When any counter reaches the preset sampling length, its match1 port will output a pulse, and the preset sampling length of the filter can be set to 2, and the preset sampling length can be half of the frequency multiplication number (n=4). For example, when the count value of the high-level pulse of the third counter 620 reaches 2, its match1 port will output a pulse to the third finite element state machine 640. When the count value of the low-level pulse of the fourth counter 630 reaches 2, its match1 port will output a pulse to the third finite element state machine 640. The third finite element state machine 640 latches the pulse and implements the flipping of the level signal to determine the level required for its S0 port state output. Then the fifth lookup table 650 is used to transmit the filtered signal output to the peripheral device for parsing the serial data frame.

[0076] The embodiment of the present application maps the hardware description language logic to the CLB of the DSP itself. Since the CLB is a built-in module and has hardware resources such as counters, lookup tables, and state machines, these hardware resources can be interconnected through programming to build the logic circuit required by the user. The CLB cooperates with the DSP signal to generate a system clock signal of the agreed baud rate, and aligns the generated system clock signal with the timing of the data frame, and can directly process the serial communication data. The different levels of the serial communication data are sampled by the quadruple frequency clock signal, and the signal filtering effect is achieved by the counter, which helps to enhance the anti-interference ability to deal with spike pulses and avoid the problem of serial communication data frame parsing errors caused by baud rate deviation. The embodiment of the present application does not need to use a separate dedicated integrated circuit, and uses the CLB module inside the DSP to achieve anti-interference of serial communication, which is simpler, more flexible, and more effective.

[0077] Combination of the above Figure 1-Figure 6 The method embodiment of the present application is described in detail. Figures 7 and 8 The device embodiment of the present application is described in detail. It should be understood that the description of the device embodiment corresponds to the description of the method embodiment, so the parts not described in detail can refer to the previous method embodiment.

[0078] The embodiment of the present application provides a serial communication control device applied to a DSP; the DSP includes a configurable logic block; the configurable logic block is configured with a first counter. Figure 7 Schematic diagram of a serial communication control device provided in an embodiment of the present application. Figure 7 As shown, the serial communication control device 700 may include a determining unit 710 , a counting unit 720 , a generating unit 730 and an aligning unit 740 .

[0079] The determination unit 710 is used to determine a preset first value according to the agreed baud rate of the serial communication and the clock signal of the DSP; the preset first value is a cycle duration count value.

[0080] The counting unit 720 is used to control the first counter to perform cumulative counting based on the clock signal of the DSP, and output a first signal in response to the cumulative count of the first counter reaching a preset second value; in response to the cumulative count of the first counter reaching the preset first value, output a second signal and reset the first counter.

[0081] The generating unit 730 is used to generate a first clock signal according to the first signal and the second signal, wherein the frequency of the first clock signal is a frequency corresponding to the agreed baud rate.

[0082] The alignment unit 740 is used to control the timing of the first clock signal to be aligned with the timing of the data frame of the bus.

[0083] Optionally, the alignment unit 740 is used to reset the first counter according to at least one falling edge pulse signal among multiple falling edge pulse signals of the received data frame to align the timing of the first clock signal with the timing of the data frame of the bus.

[0084] Optionally, the configurable logic block is configured with a first lookup table, a first input end of the first lookup table is used to receive a signal of a data frame of the bus, and an output end of the first lookup table is connected to a reset port of the first counter. The alignment unit 740 is used to output a high-level pulse signal in response to the first lookup table receiving a first falling edge pulse signal of the data frame, the high-level pulse signal is used to reset the first counter, and the first falling edge pulse signal is any falling edge pulse signal among a plurality of falling edge pulse signals.

[0085] Optionally, the configurable logic block is configured with a first finite element state machine. The generation unit 730 is used to control the first finite element state machine to output a first level according to an input first signal; the first level is a high level; control the first finite element state machine to output a second level according to an input second signal; the second level is a low level; and generate a first clock signal according to the first level and the second level.

[0086] Optionally, the configurable logic block is configured with a second counter, and the serial communication control device 700 further includes a filtering unit. The generating unit 730 is used to control the second counter to perform cumulative counting based on the clock signal of the DSP, and output a third signal in response to the cumulative count of the second counter reaching 1 / 2n of the preset first value; in response to the cumulative count reaching 1 / n of the preset first value, output a fourth signal and reset the second counter, where n is an even number; generate a second clock signal based on the third signal and the fourth signal; the frequency of the second clock signal is n times the frequency of the first clock signal. The filtering unit is used to filter the pulse signal of the received bus according to the second clock signal.

[0087] Optionally, the configurable logic block is configured with a second finite element state machine. The generating unit 730 is used to control the second finite element state machine to output a high level and a low level respectively according to the input third signal and fourth signal; and to generate a second clock signal according to the alternately generated high level and low level.

[0088] Optionally, the configurable logic block is configured with a second lookup table, a third finite element state machine, a third counter and a fourth counter, and the pulse signal of the bus is connected to the reset port of the third counter. The filtering unit is used to invert the received pulse signal of the bus using the second lookup table, and the inverted pulse signal of the bus is connected to the reset port of the fourth counter; based on the second clock signal, the third counter is used to count the high-level pulses in the pulse signal of the bus, and the fourth counter is used to count the low-level pulses in the pulse signal of the bus; in response to the cumulative count of the third counter reaching the preset sampling length, the fifth signal is output; the preset sampling length is n / 2; in response to the cumulative count of the fourth counter reaching the preset sampling length, the sixth signal is output; the third finite element state machine is controlled to output a high level and a low level respectively according to the input fifth signal and the sixth signal; according to the high level and the low level alternately generated by the third finite element state machine, the pulse signal of the filtered bus is output.

[0089] An embodiment of the present application also provides an electronic device. Figure 8 Schematic diagram of component units / partial component units of an electronic device provided in an embodiment of the present application. Figure 8 As shown, the electronic device 800 is configured with a digital signal processor 810, and the digital signal processor 810 includes a configurable logic block 500. The electronic device 800 can be, for example, a frequency converter or an encoder. The digital signal processor 810 is used to perform the following operations:

[0090] According to the agreed baud rate of serial communication and the clock signal of DSP, a preset first value is determined, and the preset first value is a cycle duration count value. The first counter is controlled to perform cumulative counting based on the clock signal of DSP, and in response to the cumulative count of the first counter reaching the preset second value, a first signal is output, and in response to the cumulative count of the first counter reaching the preset first value, a second signal is output, and the first counter is reset. According to the first signal and the second signal, a first clock signal is generated, and the frequency of the first clock signal is the frequency corresponding to the agreed baud rate; the timing of the first clock signal is controlled to be aligned with the timing of the data frame of the bus. The preset second value can be 1 / 2 of the preset first value.

[0091] Those skilled in the art will understand that Figure 8 This is only an example of the electronic device 800 and does not constitute a limitation on the electronic device. It may include more or fewer components than shown in the figure, or combine certain components, or different components. The electronic device provided in this embodiment can execute the above method embodiment, and its implementation principle and technical effect are similar, which will not be repeated here.

[0092] An embodiment of the present application further provides a non-volatile computer-readable storage medium, which stores a computer program. When the computer program is executed by a processor, the steps in the above-mentioned method embodiments can be implemented.

[0093] An embodiment of the present application provides a computer program product. When the computer program product runs on an electronic device, the electronic device can implement the steps in the above-mentioned method embodiments when executing the computer program product.

[0094] If the integrated unit is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the present application implements all or part of the processes in the above method embodiments, which can be completed by instructing the relevant hardware through a computer program, and the computer program can be stored in a computer-readable storage medium. When the computer program is executed by the processor, the steps of the above method embodiments can be implemented. Among them, the computer program includes computer program code, which can be in source code form, object code form, executable file or some intermediate form. The computer-readable medium may at least include: any entity or device that can carry the computer program code to the camera / electronic device, recording medium, computer memory, read-only memory (ROM), random access memory (RAM), read-only compact disc (CD-ROM), magnetic tape, floppy disk and optical data storage device. The computer-readable storage medium mentioned in the present application can be a non-volatile storage medium, in other words, it can be a non-transient storage medium.

[0095] In the above embodiments, the description of each embodiment has its own emphasis. For parts that are not described or recorded in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0096] Those of ordinary skill in the art will appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professional and technical personnel can use different methods to implement the described functions for each specific application, but such implementation should not be considered to be beyond the scope of this application.

[0097] In the embodiments provided in the present application, it should be understood that the disclosed devices / equipment and methods can be implemented in other ways. For example, the device / equipment embodiments described above are only schematic, for example, the division of modules or units is only a logical function division, and there may be other division methods in actual implementation, such as multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some interfaces, indirect coupling or communication connection of devices or units, which can be electrical, mechanical or other forms.

[0098] It should be understood that when used in the present specification and the appended claims, the term "comprising" indicates the presence of described features, integers, steps, operations, elements and / or components, but does not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components and / or combinations thereof.

[0099] It should also be understood that the term “and / or” used in the specification and appended claims refers to any and all possible combinations of one or more of the associated listed items, and includes these combinations.

[0100] As used in the specification and appended claims of this application, the term "if" can be interpreted as "when" or "uponce" or "in response to determining" or "in response to detecting", depending on the context. Similarly, the phrase "if it is determined" or "if [described condition or event] is detected" can be interpreted as meaning "uponce it is determined" or "in response to determining" or "uponce [described condition or event] is detected" or "in response to detecting [described condition or event]", depending on the context.

[0101] In addition, in the description of the present application specification and the appended claims, the terms "first", "second", etc. are only used to distinguish the descriptions and cannot be understood as indicating or implying relative importance.

[0102] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present application, rather than to limit it. Although the present application has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or replace some or all of the technical features therein with equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A serial communication control method, characterized in that: Applied to DSP; the DSP includes a configurable logic block; The configurable logic block is configured with a first counter; the method comprises: Determine a preset first value according to the agreed baud rate of the serial communication and the clock signal of the DSP; the preset first value is a cycle duration count value; Control the first counter to perform cumulative counting based on the clock signal of the DSP, and output a first signal in response to the cumulative count of the first counter reaching a preset second value; output a second signal in response to the cumulative count of the first counter reaching the preset first value, and reset the first counter; Generate a first clock signal according to the first signal and the second signal, wherein the frequency of the first clock signal is the frequency corresponding to the agreed baud rate; The timing of the first clock signal is controlled to be aligned with the timing of the data frame of the bus.

2. The serial communication control method according to claim 1, characterized in that: The controlling the timing of the first clock signal to be aligned with the timing of the data frame of the bus includes: The first counter is reset according to at least one falling edge pulse signal among a plurality of falling edge pulse signals of the received data frame, so as to align the timing of the first clock signal with the timing of the data frame of the bus.

3. The serial communication control method according to claim 2, characterized in that: The configurable logic block is configured with a first lookup table, wherein a first input end of the first lookup table is used to receive a signal of a data frame of a bus, and an output end of the first lookup table is connected to a reset port of the first counter; The step of resetting the first counter according to at least one falling edge pulse signal among a plurality of falling edge pulse signals of the received data frame comprises: In response to the first lookup table receiving the first falling edge pulse signal of the data frame, a high level pulse signal is output, and the high level pulse signal is used to reset the first counter. The first falling edge pulse signal is any falling edge pulse signal among the multiple falling edge pulse signals.

4. The serial communication control method according to claim 1, characterized in that: The configurable logic block is configured with a first finite element state machine; the generating a first clock signal according to the first signal and the second signal comprises: Controlling the first finite element state machine to output a first level according to the first input signal; the first level is a high level; Controlling the first finite element state machine to output a second level according to the second input signal; the second level is a low level; The first clock signal is generated according to the first level and the second level.

5. The serial communication control method according to claim 1, characterized in that: The configurable logic block is configured with a second counter; the method further comprises: Control the second counter to perform cumulative counting based on the clock signal of the DSP, and output a third signal in response to the cumulative count of the second counter reaching 1 / 2n of the preset first value; output a fourth signal in response to the cumulative count reaching 1 / n of the preset first value, and reset the second counter, where n is an even number; Generate a second clock signal according to the third signal and the fourth signal; the frequency of the second clock signal is n times the frequency of the first clock signal; The received pulse signal of the bus is filtered according to the second clock signal.

6. The serial communication control method according to claim 5, characterized in that: The configurable logic block is configured with a second finite element state machine, and generating a second clock signal according to the third signal and the fourth signal includes: Controlling the second finite element state machine to output a high level and a low level respectively according to the input third signal and fourth signal; The second clock signal is generated according to the alternately generated high level and low level.

7. The serial communication control method according to claim 5, characterized in that: The configurable logic block is configured with a second lookup table, a third finite element state machine, a third counter and a fourth counter, and the pulse signal of the bus is connected to the reset port of the third counter; The filtering of the received pulse signal of the bus according to the second clock signal comprises: Inverting the received pulse signal of the bus using the second lookup table, and connecting the inverted pulse signal of the bus to the reset port of the fourth counter; Based on the second clock signal, the third counter is used to count the high level pulses in the pulse signal of the bus, and the fourth counter is used to count the low level pulses in the pulse signal of the bus; In response to the accumulated count of the third counter reaching a preset sampling length, a fifth signal is output; the preset sampling length is n / 2; in response to the accumulated count of the fourth counter reaching the preset sampling length, a sixth signal is output; Controlling the third finite element state machine to output a high level and a low level respectively according to the input fifth signal and the sixth signal; According to the high level and the low level alternately generated by the third finite element state machine, a pulse signal of the filtered bus is output.

8. A serial communication control device, characterized in that: Applied to DSP; the DSP includes a configurable logic block; The configurable logic block is configured with a first counter; the serial communication control device comprises: A determination unit, configured to determine a preset first value according to an agreed baud rate of the serial communication and a clock signal of the DSP; the preset first value being a cycle duration count value; a counting unit, configured to control the first counter to perform cumulative counting based on the clock signal of the DSP, and output a first signal in response to the cumulative count of the first counter reaching a preset second value; and output a second signal in response to the cumulative count of the first counter reaching the preset first value, and reset the first counter; A generating unit, configured to generate a first clock signal according to the first signal and the second signal, wherein a frequency of the first clock signal is a frequency corresponding to the agreed baud rate; The corresponding unit is used to control the timing of the first clock signal to be aligned with the timing of the data frame of the bus.

9. An electronic device comprising a memory and a DSP, wherein the memory stores a computer program, characterized in that: When the DSP executes the computer program, the steps of the method according to any one of claims 1 to 7 are implemented.

10. A computer-readable storage medium, characterized in that: A computer program is stored thereon, and when the computer program is executed, the computer program is used to implement the method according to any one of claims 1 to 7.

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