Virtual interface chip data analysis method and device based on state machine migration

Abstract

The invention discloses a virtual interface chip data analysis method and device based on state machine migration. The method comprises the following steps: simplifying a data transmission behavior into a write operation and a read operation; the write operation and the read operation respectively comprise a plurality of sequentially executed steps, and each step is used for writing data into a data register of the interface chip; constructing a finite-state machine based on each step of the write operation and the read operation; the finite-state machine comprises a plurality of states, a plurality of conditions and a plurality of actions; each state corresponds to one step, each condition is determined based on the category, atomicity, randomness and time sequence of each step, each condition is used for conversion between the states, and each action is used for changing the corresponding condition; and for each piece of data written into the data register, determining a step to which the data belongs based on the data and the state of the finite state machine at a moment, and analyzing the data based on the step to which the data belongs. According to the method, the data can be analyzed in real time, and the analysis efficiency and accuracy are high.

Description

Technical Field

[0001] The present invention relates to the technical field of signal processing, and in particular to a virtual interface chip data parsing method and device based on state machine migration. Background Art

[0002] In the construction of some onboard control software test environments, the data paths that need to be completed are usually: (1) the processor sends data to the bus through the interface chip, which is a write operation; (2) the processor reads data on the bus through the interface chip, which is a read operation. All data transmission between the processor and the bus is completed through the interface chip, which is equivalent to the data transmission medium. Only by clarifying the specific ownership of each data in the interface chip can the data analysis be further completed.

[0003] The existing interface chip data analysis method is mainly based on the feature word method, that is, first obtain all the data written to the interface chip data register, then find the feature word from the obtained data set, distinguish different operation types and data attribution according to the feature word, and then realize data analysis. However, this method has the following disadvantages: (1) When the specific data read and written are the same as the read and write feature words, confusion is easy to occur and further distinction is required, and the analysis efficiency and accuracy are low. (2) After the data operation is completed, this data analysis method classifies the acquired data set according to the feature word, and then confirms the specific meaning of the data under different types of operations. The real-time performance is poor, the analysis work is delayed, and it is difficult to meet the real-time judgment requirements.

[0004] Therefore, there is an urgent need for a virtual interface chip data parsing method and device based on state machine migration. Summary of the invention

[0005] The present invention provides a virtual interface chip data analysis method and device based on state machine migration, which can analyze data in real time with high analysis efficiency and accuracy. The technical solution is as follows:

[0006] On the one hand, a virtual interface chip data parsing method based on state machine migration is provided, the method comprising:

[0007] In response to data transmission between the processor and the bus based on the virtual interface chip, the data transmission behavior is simplified into a write operation and a read operation; the write operation and the read operation respectively include a plurality of steps executed in sequence, each of which is used to write data to a data register of the interface chip;

[0008] Based on the steps of the write operation and the read operation, a finite state machine is constructed; the finite state machine includes multiple states, multiple conditions and multiple actions; each state corresponds to one step, each condition is determined based on the category, atomicity, randomness and timing of each step, each condition is used for conversion between corresponding states, and each action is used to change the corresponding condition;

[0009] For each data written into the data register, the step to which the data belongs is determined based on the data and the state of the finite state machine at a previous moment, so that the data is parsed based on the step to which it belongs.

[0010] On the other hand, a virtual interface chip data parsing device based on state machine migration is provided, the device comprising:

[0011] A simplification unit, configured to simplify the data transmission behavior into a write operation and a read operation in response to data transmission between the processor and the bus based on the virtual interface chip; the write operation and the read operation respectively include a plurality of steps executed in sequence, each of which is used to write data to a data register of the interface chip;

[0012] A construction unit, configured to construct a finite state machine based on the steps of the write operation and the read operation; the finite state machine comprises a plurality of states, a plurality of conditions and a plurality of actions; each of the states corresponds to a step, each of the conditions is determined based on the category, atomicity, randomness and timing of each step, each of the conditions is used for conversion between corresponding states, and each of the actions is used for changing the corresponding condition;

[0013] The parsing unit is used to determine, for each data written into the data register, the step to which the data belongs based on the data and the state of the finite state machine at a previous moment, so as to parse the data based on the step to which the data belongs.

[0014] On the other hand, a computer device is provided, which includes a memory and a processor, wherein the memory is used to store a computer program, and the processor is used to execute the computer program stored in the memory to implement the steps of the virtual interface chip data parsing method based on state machine migration described above.

[0015] On the other hand, a computer-readable storage medium is provided, wherein a computer program is stored in the storage medium, and when the computer program is executed by a processor, the steps of the virtual interface chip data parsing method based on state machine migration are implemented.

[0016] On the other hand, a computer program product is provided, including a computer program, wherein when the computer program is executed by a processor, the steps of the virtual interface chip data parsing method based on state machine migration are implemented.

[0017] The embodiment of the present invention provides a virtual interface chip data parsing method based on state machine migration, by simplifying the data transmission behavior into write operation and read operation, and equating each step to each state of a finite state machine, so that the data parsing process can be abstracted into a finite state machine, so as to parse the interface chip data using the transfer conditions between different states. Since the transfer conditions include not only the categories of each step (such as feature words), but also the atomicity, randomness and timing of each step, the parsing errors caused by data confusion are avoided, and the parsing work efficiency and accuracy are greatly improved. In addition, the method does not need to perform feature word recognition and data parsing after the data transmission is completed, which solves the problem of real-time parsing of interface chip data and meets the real-time interpretation requirements. It can be seen that the present application can parse data in real time with high parsing efficiency and accuracy. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0019] Figure 1 It is a flow chart of a virtual interface chip data parsing method based on state machine migration provided by one embodiment of the present invention;

[0020] Figure 2 It is a structural diagram of a virtual interface chip data parsing device based on state machine migration provided by one embodiment of the present invention;

[0021] Figure 3 is a hardware architecture diagram of a computer device provided by an embodiment of the present invention;

[0022] Figure 4 This is a state transition diagram provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0023] In order to make the purpose, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, rather than all the embodiments. Based on the embodiments in the present invention, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of the present invention.

[0024] The specific implementation of the above concept is described below.

[0025] Please refer to Figure 1 , an embodiment of the present invention provides a virtual interface chip data parsing method based on state machine migration, the method comprising:

[0026] Step 100, in response to data transmission between the processor and the bus based on the virtual interface chip, simplifying the data transmission behavior into a write operation and a read operation; the write operation and the read operation respectively include a plurality of steps executed in sequence, each step being used to write data to a data register of the interface chip;

[0027] Step 102, constructing a finite state machine based on each step of the write operation and the read operation; the finite state machine includes multiple states, multiple conditions and multiple actions; each state corresponds to a step, each condition is determined based on the category, atomicity, randomness and timing of each step, each condition is used for conversion between corresponding states, and each action is used to change the corresponding condition;

[0028] Step 104 , for each data written into the data register, the step to which the data belongs is determined based on the data and the state of the finite state machine at the previous moment, so as to parse the data based on the step to which the data belongs.

[0029] In the embodiment of the present invention, by simplifying the data transmission behavior into write operation and read operation, and equating each step to each state of a finite state machine, the data parsing process can be abstracted into a finite state machine, so as to parse the interface chip data using the transfer conditions between different states. Since the transfer conditions include not only the categories of each step (such as feature words), but also the atomicity, randomness and timing of each step, the parsing errors caused by data confusion are avoided, and the parsing work efficiency and accuracy are greatly improved. In addition, the method does not need to perform feature word recognition and data parsing after the data transmission is completed, which solves the problem of real-time parsing of interface chip data and meets the real-time interpretation requirements. It can be seen that the present application can perform real-time parsing of data with high parsing efficiency and accuracy.

[0030] Described below Figure 1 How the various steps are performed.

[0031] First, for step 100, in response to data transmission between the processor and the bus based on the virtual interface chip, the data transmission behavior is simplified into write operations and read operations; the write operation and the read operation respectively include multiple steps executed in sequence, and each step is used to write data to the data register of the interface chip.

[0032] In this step, the data transmission behavior between the processor and the bus is simplified and decomposed, and then refined after being classified into read and write. Among them, the write operation can be subdivided into 3 steps, and the read operation can be subdivided into 2 steps. The steps in the write operation and the read operation are executed in sequence.

[0033] In some embodiments, the write operation includes at least a first step, a second step, and a third step executed in sequence; the first step is to write a first characteristic word into a data register of the interface chip; the second step is to write the address of the data to be written into the data register of the interface chip; and the third step is to write the data to be written into the data register of the interface chip.

[0034] In some embodiments, the read operation includes at least a fourth step and a fifth step executed sequentially; the fourth step is to write the second characteristic word into the data register of the interface chip; the fifth step is to write the address of the data to be read into the data register of the interface chip.

[0035] It should be noted that the steps of write operation and read operation can be expanded as needed to include more or fewer steps, and this application does not make specific limitations. For example, the read operation can also include steps such as reading data from the interface chip data register.

[0036] Then, for step 102, a finite state machine is constructed based on each step of the write operation and the read operation, including:

[0037] A1, abstract each step of the write operation and the read operation into a state of a finite state machine;

[0038] A2, based on the category, atomicity, randomness and timing characteristics of each step, determine multiple conditions that cause the finite state machine to transition between various states; the categories include read operations and write operations; the atomicity is that any write operation or any read operation is not allowed to be interrupted before completion; the randomness is that after any write operation or any read operation is completed, the category of another new operation is not restricted; the timing characteristic is that each step of the read operation and the write operation is executed in sequence according to their respective orders;

[0039] A3, based on the differences between the conditions, determine the actions that change the conditions.

[0040] In step A1, one step corresponds to one state. When the write operation and the read operation include five steps, the finite state machine includes at least five states: the first state to the fifth state. The first state to the fifth state correspond to the first step to the fifth step, respectively, as shown in Table 1:

[0041] Table 1 Correspondence between each step and each state of the finite state machine

[0042]

[0043]

[0044] In some embodiments, step A2 comprises:

[0045] B1, abstracts the conditions for transitions between various states into the first, second and third categories. Among them: the first category is the characteristic words of read and write operations, the second category is the flag of the current operation, and the third category is the timing flag of read and write operations. The sub-conditions in each category are shown in Table 2:

[0046] Table 2 Three types of condition sets

[0047]

[0048] B2, select the corresponding sub-conditions from the three types of conditions and combine them, construct all the transition conditions between various states and delete the redundant conditions, and obtain the unique and definite conditions for the transition between various states of the finite state machine.

[0049] In step B1, the first category is used to distinguish the categories of write operations and read operations; the second category is the flag to which the current operation belongs, that is, whether the current operation belongs to a read operation step or a write operation step. The flag is used to ensure the atomicity of the read operation or the write operation, and ensure that the read operation and the write operation are not interrupted before completion. The third category is the timing flag of the read operation and the write operation, that is, the specific data information in the operation step is not used, but the timing is used to distinguish, so as to avoid data confusion and also help to expand the versatility. In practical applications, different bus operation protocols have indispensable feature words, and the specific steps of the read and write operations may be different. The present invention does not focus on the specific content of the read and write operation steps, but lists the timing flags of its various steps according to the timing relationship, and relies on the timing flags to obtain the step attribution. Therefore, when parsing chip interface data for different buses, it is only necessary to keep the first and second categories for different virtual interface chip read and write specifications, and only expand the third category according to the actual situation.

[0050] In step B2, according to the condition classification in Table 2, the corresponding sub-conditions are selected in each category, so that all the migration conditions between the five states can be constructed, and the redundancy is deleted after combination to form the final conversion condition. According to each condition, the state of the current data can be accurately obtained, and the state information is uniquely determined.

[0051] In some embodiments, the finite state machine includes at least first to fifth states, first to fifth conditions, and first to fifth actions;

[0052] The first state to the fifth state correspond to the first step to the fifth step respectively;

[0053] The conversion relationship between each state includes: based on the first condition, the state machine is transferred from the initial state to the first state; based on the second condition, the state machine is transferred from the first state to the second state; based on the third condition, the state machine is transferred from the second state to the third state; based on the fifth condition, the state machine is transferred from the fourth state to the fifth state; based on the first condition, the state machine is transferred from the third state to the first state; based on the fourth condition, the state machine is transferred from the third state to the fourth state; based on the first condition, the state machine is transferred from the fifth state to the first state; based on the fourth condition, the state machine is transferred from the fifth state to the fourth state;

[0054] The first action is used to convert the first condition into the second condition, the second action is used to convert the second condition into the third condition, the third action is used to convert the third condition into the first condition or the fourth condition, the fourth action is used to convert the fourth condition into the fifth condition, and the fifth action is used to convert the fifth condition into the fourth condition or the first condition.

[0055] like Figure 4 As shown, it is a schematic diagram of the transition between various states. From the figure, it can be seen that the conditions required for the mutual transition between various states, the actions required for the transition between various conditions, and the corresponding relationship between various states and various steps.

[0056] In some implementations, the first condition is: the data written to the data register is a first characteristic word, the write operation flag is false, the read operation flag is false, and the write operation timing flag is 1;

[0057] The second condition is: the write operation flag is true, the read operation flag is false, and the write operation timing flag is 2;

[0058] The third condition is: the write operation flag is true, the read operation flag is false, and the write operation timing flag is 3;

[0059] The fourth condition is: the data written to the data register is the second characteristic word, the write operation flag is false, the read operation flag is false, and the read operation timing flag is 1;

[0060] The fifth condition is: the write operation flag is false, the read operation flag is true, and the read operation timing flag is 2.

[0061] The relationship between each condition and the three major categories is shown in Table 3:

[0062] Table 3 Statistics of the first to fifth conditions

[0063] Category I Category II Category 3 first condition (1)a (2)b; (2)d (3)a Second Condition (2) a; (2) d (3)b The third condition (2) a; (2) d (3)c Fourth condition (1)b (2)b; (2)d (3)d Fifth Condition (2)b; (2)c (3)e

[0064] After determining the current state of the finite state machine, in order to transfer the state to other states, some conditions need to be changed. In the finite state machine theory, the behavior of changing conditions is called "action". The corresponding actions in the first to fifth states are agreed to be the first to fifth actions respectively. The specific contents of the first to fifth actions are obtained according to the differences between the conditions. According to the differences between the different conditions in Table 3, the specific contents of the actions in the five states can be summarized as follows:

[0065] The first action is: set the write operation flag to true and set the write operation timing flag to 2;

[0066] The second action is: setting the write operation timing flag to 3;

[0067] The third action is: set the write operation flag to false and set the write operation timing flag to 1;

[0068] The fourth action is: setting the read operation flag to true and setting the read operation timing flag to 2;

[0069] The fifth action is: setting the read operation flag to false, and setting the read operation timing flag to 1.

[0070] Through the above steps, all elements under the finite state machine can be constructed to form a complete finite state machine. All data written into the interface chip are screened through the first condition to the fifth condition to complete the current state determination. After the current state is determined, in order to continue to parse subsequent data, it is necessary to change the conditions and set the flag according to the current state, that is, set it according to the action corresponding to the current state, so as to meet the needs of subsequent data parsing.

[0071] In some implementations, step 104 includes:

[0072] Set the initial conditions of the finite state machine; the initial conditions are: the write operation flag is false, the read operation flag is false, the write operation timing flag is 1, and the read operation timing flag is 1;

[0073] Traverse each data written into the data register, and execute the following for each traversed data:

[0074] S1, based on the data and the state of the finite state machine at the previous moment, determine the conditions satisfied by the data, and execute S2; for the first data, the state of the finite state machine at the previous moment is the initial condition;

[0075] S2, determine the current state of the finite state machine based on the conditions satisfied by the data, and execute S3;

[0076] S3, determining the step to which the data belongs based on the current state of the finite state machine, and executing S4;

[0077] S4, performing data analysis based on the step to which the data belongs, and determining whether the data is the last data, if so, ending the analysis process, if not, executing S5;

[0078] S5, executing corresponding actions based on the current state of the finite state machine and the conversion relationship between the states to update the state of the finite state machine, and returning to execute S1.

[0079] In the above steps, if it is determined that the current data meets the first condition, the first action is executed, and the data is clearly identified as the data of the first step, and the data is parsed based on the first step.

[0080] If it is determined that the current data meets the second condition, the second action is executed, and the data is clearly identified as the data of the second step, and the data is parsed based on the second step.

[0081] If it is determined that the current data meets the third condition, the third action is executed, and the data is clearly identified as the data of the third step, and the data is parsed based on the third step.

[0082] If it is determined that the current data meets the fourth condition, the fourth action is executed, and the data is clearly identified as the data of the fourth step, and the data is parsed based on the fourth step.

[0083] If it is determined that the current data meets the fifth condition, the fifth action is executed, and the data is clearly identified as the data of the fifth step, and the data is parsed based on the fifth step.

[0084] It should be noted that when performing conditional determination on each data, the present application does not limit the determination order, as long as the conditions satisfied by each data can be accurately determined.

[0085] In order to prove the analytical effect of the present invention, the inventors used the following data as an example for verification:

[0086] When the data written into the data register of the interface chip is 0x02, 0x03, 0x02, 0x03, 0x02 in sequence, and the written address and data are the same as the signature word, there are multiple possibilities according to the existing data parsing method:

[0087] Possibility 1: Write operation 0x02, 0x03, 0x02. Read operation: 0x03, 0x02.

[0088] Possibility 2: Read operation: 0x03, 0x02. Read operation: 0x03, 0x02.

[0089] Possibility 3: Write operations 0x02, 0x03, 0x02.

[0090] The above is only the parsing process of 5 data. In the actual data interaction process, the data volume is large, the structure is complex, and there are many possible parsing results, which brings a huge workload and error possibility to the parsers.

[0091] The virtual interface chip data parsing method based on state machine migration proposed by the present invention no longer relies solely on feature words for parsing. An operation belonging mark and an operation timing mark are added to the judgment condition to uniquely determine the step to which the above data belongs. The above data is parsed using the method of the present application. The process is as follows:

[0092] The first data to arrive is 0x02. After judging that it meets the first condition, it is clear that the data is the data of the first step of the write operation, and it is a characteristic word, indicating that the current operation is a write operation. Then the data to arrive is 0x03. After judging that it meets the second condition, it is clear that the data is the data of the second step of the write operation, that is, data is to be written to the bus address 0x03. The next data to arrive is 0x02. After judging that it meets the third condition, it is clear that the data is the data of the third step of the write operation, that is, the specific data to be written to the bus is 0x02. The next data to arrive is 0x03. After judging that it meets the fourth condition, it is clear that the data is the data of the fourth step of the read operation, and it is a characteristic word, indicating that the current operation is a read operation. The last data to arrive is 0x02. After judging that it meets the fifth condition, it is clear that the data is the data of the fifth step of the read operation, that is, the bus data to be read is located at the address 0x02 of the bus.

[0093] It can be seen that according to the method provided by the present invention, the meaning of the above data is uniquely determined: write operation 0x02, 0x03, 0x02. Read operation: 0x03, 0x02. Data confusion is avoided, and further analysis and confirmation work is not required among multiple possibilities, which greatly improves the efficiency of data analysis and reduces the possibility of erroneous analysis.

[0094] like Figure 2 , Figure 3As shown, the embodiment of the present invention provides a virtual interface chip data parsing device based on state machine migration. The device embodiment can be implemented by software, or by hardware or a combination of software and hardware. From the hardware level, Figure 2 FIG. 1 is a hardware architecture diagram of a computing device where a virtual interface chip data parsing device based on state machine migration is located according to an embodiment of the present invention. Figure 2 In addition to the processor, memory, network interface, and non-volatile memory shown in the figure, the computing device in which the device is located in the embodiment may also generally include other hardware, such as a forwarding chip responsible for processing messages, etc. Taking software implementation as an example, Figure 3 As shown, as a device in a logical sense, the CPU of the computing device in which it is located reads the corresponding computer program in the non-volatile memory into the internal memory and runs it.

[0095] Please refer to Figure 3 The embodiment of the present invention provides a virtual interface chip data parsing device based on state machine migration, the device comprising:

[0096] The simplification unit 300 is used to simplify the data transmission behavior into a write operation and a read operation in response to data transmission between the processor and the bus based on the virtual interface chip; the write operation and the read operation respectively include a plurality of steps executed in sequence, and each step is used to write data to the data register of the interface chip;

[0097] A construction unit 302 is used to construct a finite state machine based on each step of the write operation and the read operation; the finite state machine includes multiple states, multiple conditions and multiple actions; each state corresponds to a step, each condition is determined based on the category, atomicity, randomness and timing of each step, each condition is used for conversion between corresponding states, and each action is used to change the corresponding condition;

[0098] The parsing unit 304 is used to determine, for each data written into the data register, the step to which the data belongs based on the data and the state of the finite state machine at a previous moment, so as to parse the data based on the step to which the data belongs.

[0099] In some implementations, the construction unit 302 is configured to perform the following operations:

[0100] Abstract each step of the write operation and the read operation into a state of a finite state machine;

[0101] Based on the category, atomicity, randomness and timing characteristics of each step, multiple conditions for transition between various states of the finite state machine are determined; the categories include read operations and write operations; the atomicity is that any write operation or any read operation is not allowed to be interrupted before completion; the randomness is that after any write operation or any read operation is completed, the category of another new operation is not restricted; the timing characteristic is that each step of the read operation and the write operation is executed in sequence according to their respective orders;

[0102] Based on the differences between the conditions, actions to change the conditions are determined.

[0103] In some embodiments, the write operation includes at least a first step, a second step, and a third step that are performed in sequence; wherein the first step is to write a first characteristic word into a data register of the interface chip; the second step is to write an address of data to be written into the data register of the interface chip; the third step is to write data to be written into the data register of the interface chip; and / or;

[0104] The read operation at least includes a fourth step and a fifth step executed in sequence; wherein the fourth step is to write the second characteristic word into the data register of the interface chip; and the fifth step is to write the address of the data to be read into the data register of the interface chip.

[0105] In some implementations, multiple conditions for causing transitions between various states of the finite state machine are determined based on the category, atomicity, randomness, and timing characteristics of each step, including:

[0106] The conditions for transitions between various states are abstracted into the first, second and third categories, where: the first category is the characteristic words of read and write operations, and the sub-conditions in the first category are: the data written to the data register is the first characteristic word and the data written to the data register is the second characteristic word; the second category is the flag to which the current operation belongs, and the sub-conditions in the second category are: write operation is true, write operation is false, read operation is true, and read operation is false; the third category is the timing flags of read and write operations, and the sub-conditions in the third category are: write operation timing flag is 1, write operation timing flag is 2, write operation timing flag is 3, read operation timing flag is 1, and read operation timing flag is 2;

[0107] The corresponding sub-conditions are selected from the three types of conditions and combined to construct all the transition conditions between various states and delete the redundant conditions, so as to obtain the unique and definite conditions for the transition between various states of the finite state machine.

[0108] In some embodiments, the finite state machine includes at least first to fifth states, first to fifth conditions, and first to fifth actions;

[0109] The first state to the fifth state correspond to the first step to the fifth step respectively;

[0110] The conversion relationship between each state includes: based on the first condition, the state machine is transferred from the initial state to the first state; based on the second condition, the state machine is transferred from the first state to the second state; based on the third condition, the state machine is transferred from the second state to the third state; based on the fifth condition, the state machine is transferred from the fourth state to the fifth state; based on the first condition, the state machine is transferred from the third state to the first state; based on the fourth condition, the state machine is transferred from the third state to the fourth state; based on the first condition, the state machine is transferred from the fifth state to the first state; based on the fourth condition, the state machine is transferred from the fifth state to the fourth state;

[0111] The first action is used to convert the first condition into the second condition, the second action is used to convert the second condition into the third condition, the third action is used to convert the third condition into the first condition or the fourth condition, the fourth action is used to convert the fourth condition into the fifth condition, and the fifth action is used to convert the fifth condition into the fourth condition or the first condition.

[0112] In some implementations, the first condition is: the data written to the data register is a first characteristic word, the write operation flag is false, the read operation flag is false, and the write operation timing flag is 1;

[0113] The second condition is: the write operation flag is true, the read operation flag is false, and the write operation timing flag is 2;

[0114] The third condition is: the write operation flag is true, the read operation flag is false, and the write operation timing flag is 3;

[0115] The fourth condition is: the data written to the data register is the second characteristic word, the write operation flag is false, the read operation flag is false, and the read operation timing flag is 1;

[0116] The fifth condition is: the write operation flag is false, the read operation flag is true, and the read operation timing flag is 2;

[0117] The first action is: set the write operation flag to true and set the write operation timing flag to 2;

[0118] The second action is: setting the write operation timing flag to 3;

[0119] The third action is: set the write operation flag to false and set the write operation timing flag to 1;

[0120] The fourth action is: setting the read operation flag to true and setting the read operation timing flag to 2;

[0121] The fifth action is: setting the read operation flag to false, and setting the read operation timing flag to 1.

[0122] In some implementations, the parsing unit 304 is configured to perform the following operations:

[0123] Set the initial conditions of the finite state machine; the initial conditions are: the write operation flag is false, the read operation flag is false, the write operation timing flag is 1, and the read operation timing flag is 1;

[0124] Traverse each data written into the data register, and execute the following for each traversed data:

[0125] S1, based on the data and the state of the finite state machine at the previous moment, determine the conditions satisfied by the data, and execute S2; for the first data, the state of the finite state machine at the previous moment is the initial condition;

[0126] S2, determine the current state of the finite state machine based on the conditions satisfied by the data, and execute S3;

[0127] S3, determining the step to which the data belongs based on the current state of the finite state machine, and executing S4;

[0128] S4, performing data analysis based on the step to which the data belongs, and determining whether the data is the last data, if so, ending the analysis process, if not, executing S5;

[0129] S5, executing corresponding actions based on the current state of the finite state machine and the conversion relationship between the states to update the state of the finite state machine, and returning to execute S1.

[0130] It should be noted that the virtual interface chip data parsing device based on state machine migration provided in the above embodiment is only illustrated by the division of the above functional modules. In actual applications, the above functions can be assigned to different functional modules as needed, that is, the internal structure of the device is divided into different functional modules to complete all or part of the functions described above. In addition, the virtual interface chip data parsing device based on state machine migration provided in the above embodiment and the virtual interface chip data parsing method embodiment based on state machine migration belong to the same concept. The specific implementation process is detailed in the method embodiment and will not be repeated here.

[0131] The embodiment of the present application also provides a computer device, please refer to Figure 3 The computer device includes a processor and a memory, in which at least one instruction, at least one program, code set or instruction set is stored, and the at least one instruction, at least one program, code set or instruction set is loaded and executed by the processor to implement the virtual interface chip data parsing method based on state machine migration provided by the above-mentioned method embodiments.

[0132] An embodiment of the present application also provides a computer-readable storage medium, on which is stored at least one instruction, at least one program, code set or instruction set, and the at least one instruction, at least one program, code set or instruction set is loaded and executed by a processor to implement the virtual interface chip data parsing method based on state machine migration provided by the above-mentioned method embodiments.

[0133] An embodiment of the present application also provides a computer program product, which includes a computer program. A processor of a computer device reads the computer program from a computer-readable storage medium, and the processor executes the computer program, so that the computer device executes the virtual interface chip data parsing method based on state machine migration described in any of the above embodiments.

[0134] For the convenience of description, the above system or device is described by dividing it into various modules or units according to its functions. Of course, when implementing the present application, the functions of each unit can be implemented in the same or multiple software and / or hardware.

[0135] It can be known from the description of the above implementation methods that those skilled in the art can clearly understand that the present application can be implemented by means of software plus a necessary general hardware platform. Based on such an understanding, the technical solution of the present application can be essentially or partly contributed to the prior art in the form of a software product, which can be stored in a storage medium such as ROM / RAM, a magnetic disk, an optical disk, etc., and includes several instructions for enabling a computer device (which can be a personal computer, a server, or a network device, etc.) to execute the methods described in the various embodiments of the present application or certain parts of the embodiments.

[0136] Finally, it should be noted that, in this article, relational terms such as first, second, third and fourth are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the statement "comprise a ..." do not exclude the presence of other identical elements in the process, method, article or device including the elements.

[0137] The above is only a preferred implementation of the present application. It should be pointed out that for ordinary technicians in this technical field, several improvements and modifications can be made without departing from the principles of the present application. These improvements and modifications should also be regarded as the scope of protection of the present application.

Claims

1. A virtual interface chip data parsing method based on state machine migration, characterized in that: The method comprises: In response to data transmission between the processor and the bus based on the virtual interface chip, the data transmission behavior is simplified into a write operation and a read operation; the write operation and the read operation respectively include a plurality of steps executed in sequence, each of which is used to write data to a data register of the interface chip; Based on the steps of the write operation and the read operation, a finite state machine is constructed; the finite state machine includes multiple states, multiple conditions and multiple actions; each state corresponds to one step, each condition is determined based on the category, atomicity, randomness and timing of each step, each condition is used for conversion between corresponding states, and each action is used to change the corresponding condition; For each data written into the data register, the step to which the data belongs is determined based on the data and the state of the finite state machine at a previous moment, so that the data is parsed based on the step to which it belongs.

2. The method according to claim 1, characterized in that The steps of constructing a finite state machine based on the write operation and the read operation include: Abstracting each step of the write operation and the read operation into a state of a finite state machine respectively; Based on the category, atomicity, randomness and timing characteristics of each step, multiple conditions for causing the conversion between various states of the finite state machine are determined; the category includes read operation and write operation; the atomicity is that any write operation or any read operation is not allowed to be interrupted before completion; the randomness is that after any write operation or any read operation is completed, the category of another new operation is not restricted; the timing characteristic is that each step of the read operation and the write operation is executed in sequence according to their respective orders; Based on the differences between the conditions, actions to change the conditions are determined.

3. The method according to claim 2, characterized in that The write operation at least includes a first step, a second step and a third step which are executed in sequence; wherein the first step is to write a first characteristic word into the data register of the interface chip; the second step is to write the address of the data to be written into the data register of the interface chip; the third step is to write the data to be written into the data register of the interface chip; and / or; The read operation includes at least a fourth step and a fifth step which are executed in sequence; wherein the fourth step is to write a second characteristic word into a data register of the interface chip; and the fifth step is to write an address of data to be read into the data register of the interface chip.

4. The method according to claim 3, characterized in that The method of determining multiple conditions for causing transitions between various states of the finite state machine based on the category, atomicity, randomness and timing characteristics of each step includes: The conditions for transitions between various states are abstracted into the first category, the second category and the third category, wherein: the first category is the characteristic words of read and write operations, and the sub-conditions in the first category are: the data written to the data register is the first characteristic word and the data written to the data register is the second characteristic word; the second category is the flag to which the current operation belongs, and the sub-conditions in the second category are: write operation is true, write operation is false, read operation is true, and read operation is false; the third category is the timing flags of read and write operations, and the sub-conditions in the third category are: write operation timing flag is 1, write operation timing flag is 2, write operation timing flag is 3, read operation timing flag is 1, and read operation timing flag is 2; Corresponding sub-conditions are selected from the three types of conditions for combination, all transition conditions between various states are constructed and redundant conditions are deleted, so as to obtain the only determined condition for mutual transition between various states of the finite state machine.

5. The method according to claim 4, characterized in that The finite state machine at least includes a first state to a fifth state, a first condition to a fifth condition, and a first action to a fifth action; The first state to the fifth state correspond to the first step to the fifth step respectively; The conversion relationship between each state includes: based on the first condition, the state machine is transferred from the initial state to the first state; based on the second condition, the state machine is transferred from the first state to the second state; based on the third condition, the state machine is transferred from the second state to the third state; based on the fifth condition, the state machine is transferred from the fourth state to the fifth state; based on the first condition, the state machine is transferred from the third state to the first state; based on the fourth condition, the state machine is transferred from the third state to the fourth state; based on the first condition, the state machine is transferred from the fifth state to the first state; based on the fourth condition, the state machine is transferred from the fifth state to the fourth state; The first action is used to convert the first condition into the second condition, the second action is used to convert the second condition into the third condition, the third action is used to convert the third condition into the first condition or the fourth condition, the fourth action is used to convert the fourth condition into the fifth condition, and the fifth action is used to convert the fifth condition into the fourth condition or the first condition.

6. The method according to claim 5, characterized in that The first condition is: the data written to the data register is a first characteristic word, the write operation flag is false, the read operation flag is false, and the write operation timing flag is 1; The second condition is: the write operation flag is true, the read operation flag is false, and the write operation timing flag is 2; The third condition is: the write operation flag is true, the read operation flag is false, and the write operation timing flag is 3; The fourth condition is: the data written to the data register is the second characteristic word, the write operation flag is false, the read operation flag is false, and the read operation timing flag is 1; The fifth condition is: the write operation flag is false, the read operation flag is true, and the read operation timing flag is 2; The first action is: setting the write operation flag to true and setting the write operation timing flag to 2; The second action is: setting the write operation timing flag to 3; The third action is: setting the write operation flag to false and setting the write operation timing flag to 1; The fourth action is: setting the read operation flag to true and setting the read operation timing flag to 2; The fifth action is: setting the read operation flag to false, and setting the read operation timing flag to 1.

7. The method according to claim 1, characterized in that For each data written into the data register, the step to which the data belongs is determined based on the data and the state of the finite state machine at a previous moment, so as to parse the data based on the step to which the data belongs, including: Set the initial conditions of the finite state machine; the initial conditions are: the write operation flag is false, the read operation flag is false, the write operation timing flag is 1, and the read operation timing flag is 1; Traverse each data written into the data register, and for the traversed data, execute: S1, determining the conditions satisfied by the data based on the data and the state of the finite state machine at the last moment, and executing S2; for the first data, the state of the finite state machine at the last moment is the initial condition; S2, determining the current state of the finite state machine based on the conditions satisfied by the data, and executing S3; S3, determining the step to which the data belongs based on the current state of the finite state machine, and executing S4; S4, performing data analysis based on the step to which the data belongs, and determining whether the data is the last data, if so, ending the analysis process, if not, executing S5; S5, executing corresponding actions based on the current state of the finite state machine and the conversion relationship between the states to update the state of the finite state machine, and returning to execute S1.

8. A virtual interface chip data analysis device based on state machine migration, characterized in that: The device comprises: A simplification unit, configured to simplify the data transmission behavior into a write operation and a read operation in response to data transmission between the processor and the bus based on the virtual interface chip; the write operation and the read operation respectively include a plurality of steps executed in sequence, each of which is used to write data to a data register of the interface chip; A construction unit, configured to construct a finite state machine based on the steps of the write operation and the read operation; the finite state machine comprises a plurality of states, a plurality of conditions and a plurality of actions; each of the states corresponds to a step, each of the conditions is determined based on the category, atomicity, randomness and timing of each step, each of the conditions is used for conversion between corresponding states, and each of the actions is used for changing the corresponding condition; The parsing unit is used to determine, for each data written into the data register, the step to which the data belongs based on the data and the state of the finite state machine at a previous moment, so as to parse the data based on the step to which the data belongs.

9. A computer device, characterized in that: The computer device includes a memory and a processor, the memory is used to store a computer program, and the processor is used to execute the computer program stored in the memory to implement the steps of any one of the methods described in claims 1-7.

10. A computer-readable storage medium, characterized in that: The storage medium stores a computer program, and when the computer program is executed by a processor, the steps of the method described in any one of claims 1 to 7 are implemented.

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