PCIe extension line, PCIe device with extension line and signal transmission method

Abstract

The invention discloses a PCIe extension line, PCIe equipment with the extension line and a signal transmission method, the PCIe extension line comprises a first end, the first end comprises a first PCIe connector, a photoelectric module, a detection unit and a ground impedance, and the first PCIe connector is used for sending differential signal pairs and receiving differential signals are in butt joint with the photoelectric module; the ground impedance module is used for connecting received differential signals with the ground impedance; the differential signal butt joint detection unit is used for sending; the second end comprises a second PCIe connector, a photoelectric module, a detection unit and an impedance to ground, and a differential signal pair, used for sending, of the second PCIe connector and a differential signal pair, used for receiving, of the second PCIe connector are in butt joint with the photoelectric module; the differential signal used for sending is butted with the impedance to ground; the docking detection unit is used for receiving differential signals; the detection unit is used for detecting the ground impedance of the received differential signal pair at the opposite end connected with the detection unit; the optical fiber is used for connecting the photoelectric modules at the first end and the second end. According to the scheme, cost and system complexity can be reduced, and power consumption and cost are low.

Description

Technical Field

[0001] The present invention generally relates to the field of cable technology. More specifically, the present invention relates to a PCIe extension cable, a PCIe device with the extension cable, and a signal transmission method of the PCIe extension cable. Background Art

[0002] In modern industry and information industry, high-speed, large-capacity, medium- and short-distance data transmission technology is widely used. PCIe (Peripheral Component Interconnect Express) is widely used as a common communication protocol in computer equipment, but it is a high-speed bus inside the board. How to apply this high-speed bus to medium- and short-distance data transmission so that the PCIe device can be separated from the motherboard? At this time, the PCIe optical transmission solution was proposed and products were developed. For example, in industrial cameras, in order to expand the transmission bandwidth from industrial cameras to the host, improve the quality of collected images, and take advantage of the mature development environment of PCIe and its high real-time performance, some industrial cameras adopt the PCIe interface, but the placement of industrial cameras needs to be far away from the host, which requires an extension cable that can support PCIe protocol data transmission to support the application needs of such industrial cameras. In addition, in some application scenarios, such as medical CT, the host is in the examination room, while the display, keyboard, mouse and other peripherals are outside the examination room. It is necessary to achieve long-distance separation between the peripherals and the host. The controllers in the host used to control these peripherals, such as graphics cards, are generally PCIe devices. Generally, the industry usually uses optical fiber to transmit high-speed signals such as PCIe over long distances.

[0003] In the PCIe link training state machine, there is a "Detect" state, in which the remote termination (termination resistance) is detected. However, the existing PCIe optical transmission solution does not perform termination detection and transmission, and will always turn on termination, even if the termination of the connected PCIe device is turned off. This will cause the PCIe host to judge the termination state of the PCIe device incorrectly and jump to the next "Polling" state, causing link training failure. The PCIe Switch can shield the remote termination detection action of its downstream port and solve this problem by decoding the input data instead. Therefore, a switch chip is generally required in the traditional optical transmission PCIe technology. The addition of an additional chip will increase the cost, power consumption and area, and increase the complexity of the system. Summary of the invention

[0004] In order to at least solve one or more of the technical problems mentioned above, the present invention proposes a PCIe extension cable, a PCIe device with an extension cable, and a signal transmission method of the PCIe extension cable in multiple aspects.

[0005] In a first aspect, the present invention provides a PCIe extension cable, comprising: a first end, the first end comprising a first PCIe connector, an optoelectronic module, a detection unit and an impedance to ground, the first PCIe connector comprising a differential signal pair for sending and a differential signal pair for receiving, the optoelectronic module of the first end is connected to the differential signal pair for sending and the differential signal pair for receiving of the first end; the differential signal pair for receiving of the first end is connected to the impedance to ground of the first end; the differential signal pair for sending of the first end is connected to the detection unit of the first end; the second end, the second end comprising a second PCIe connector, an optoelectronic module, a detection unit and impedance to ground, the second PCIe connector includes a differential signal pair for sending and a differential signal pair for receiving, the optoelectronic module at the second end is connected to the differential signal pair for sending and the differential signal pair for receiving at the second end; the differential signal pair for receiving at the second end is connected to the impedance to ground of the second end; the differential signal pair for sending at the second end is connected to the detection unit at the second end; the detection unit at the first end and the detection unit at the second end are each used to detect the impedance to ground of the differential signal pair for receiving at the opposite end connected thereto; and an optical fiber, the optical fiber is used to connect the optoelectronic module at the first end and the optoelectronic module at the second end.

[0006] In one embodiment, the optoelectronic module at the first end is an optoelectronic module that meets the USB3.X protocol, and the optoelectronic module at the first end is used to convert the differential signal of the differential signal pair for receiving at the first end into an optical signal, and the optical signal is transmitted to the optoelectronic module at the second end by the optical fiber; the optoelectronic module at the second end is an optoelectronic module that meets the USB3.X protocol, and the optoelectronic module at the second end is used to convert the optical signal into a differential signal and transmit it to the differential signal pair for sending at the second end.

[0007] In one embodiment, the optoelectronic module at the first end is used to convert the optical signal from the optical fiber into a differential signal and transmit it to the differential signal pair for sending at the first end; the optoelectronic module at the second end is used to convert the differential signal of the differential signal pair for receiving at the second end into an optical signal, and transmit it to the optoelectronic module at the first end by the optical fiber.

[0008] In one embodiment, the impedance to ground of the differential signal pair for receiving at the first end and the impedance to ground of the differential signal pair for receiving at the second end are respectively consistent with the receiving end input impedance specified by the PCIe protocol.

[0009] In one embodiment, the impedance to ground of the first end and the impedance to ground of the second end are greater than or equal to 40Ω and less than or equal to 60Ω.

[0010] In one embodiment, the impedance of the second end to ground is greater than or equal to 45Ω.

[0011] In one embodiment, the detection circuit of the first terminal is used to detect that an initiator has connected to the first terminal.

[0012] In one embodiment, the detection circuit of the second end is used to detect that a target (Target) has been connected to the second end.

[0013] In one embodiment, the detection unit of the first end detects whether the first end is connected to the initiator by detecting the change of common mode input impedance; the detection unit of the second end detects whether the second end is connected to the target by detecting the change of common mode input impedance.

[0014] In one embodiment, in response to the detection unit at the first end detecting a change in common-mode input impedance and the impedance to ground of the first end being detected, the PCIe channel is a valid PCIe channel; in response to the detection unit at the second end monitoring a change in common-mode input impedance and the impedance to ground of the second end being detected, the PCIe channel is a valid PCIe channel.

[0015] In one embodiment, there are multiple detection units at the first end, multiple impedance to ground at the first end, and multiple detection units at the second end and multiple impedance to ground at the second end. The number of detection units at the first end and the impedance to ground at the first end is the same, which is the same as the number of PCIe channels at the first end; the number of detection units at the second end and the impedance to ground at the second end is the same, which is the same as the number of PCIe channels at the second end.

[0016] In one embodiment, the detection unit at the first end determines whether the first end enters the polling phase of link training by detecting the number of valid PCIe channels twice; the detection unit at the second end determines whether the second end enters the polling phase of link training by detecting the number of valid PCIe channels twice, wherein the number of valid PCIe channels is the number of common-mode input impedance changes detected by the detection unit at the first end and / or the detection unit at the second end.

[0017] In one embodiment, in response to the two common-mode input impedance change times detected by the detection unit of the first end being consistent, the first end enters the polling stage of link training; in response to the two common-mode input impedance change times detected by the detection unit of the first end being inconsistent, the first end enters the detection silent stage of link training; in response to the two common-mode input impedance change times detected by the detection unit of the second end being consistent, the second end enters the polling stage of link training; in response to the two common-mode input impedance change times detected by the detection unit of the second end being inconsistent, the second end enters the detection silent stage of link training; wherein the detection silent stage is a low power consumption state of the PCIe extension line when there is no data transmission.

[0018] In one embodiment, the optoelectronic module includes a photoelectric conversion unit, an electro-optical conversion unit and an optical component, wherein the photoelectric conversion unit is used to convert a received optical signal into a differential signal; the electro-optical conversion unit is used to convert a received differential signal into an optical signal; the photoelectric conversion unit and / or the electro-optical conversion unit are coupled to the optical fiber through the optical component.

[0019] In one embodiment, the optoelectronic module at the first end includes a first optoelectronic module, and the optoelectronic module at the second end includes a second optoelectronic module; the optical fibers include at least three; the first optoelectronic module includes two of the electro-optical conversion units and one of the optoelectronic conversion units; the second optoelectronic module includes two of the optoelectronic conversion units and one of the electro-optical conversion units; the two electro-optical conversion units of the first optoelectronic module are respectively connected to one of the two optoelectronic conversion units of the second optoelectronic module through an optical fiber; the optoelectronic conversion unit of the first optoelectronic module is connected to the electro-optical conversion unit of the second optoelectronic module through an optical fiber.

[0020] In one embodiment, the optoelectronic module at the first end includes a first optoelectronic module and a third optoelectronic module, and the optoelectronic module at the second end includes a second optoelectronic module and a third optoelectronic module; the optical fibers include at least five; the first optoelectronic module includes two electro-optical conversion units and one electro-optical conversion unit; the second optoelectronic module includes two electro-optical conversion units and one electro-optical conversion unit; the third optoelectronic module includes one electro-optical conversion unit and one electro-optical conversion unit; the two electro-optical conversion units of the first optoelectronic module are respectively connected to one of the two photoelectric conversion units of the second optoelectronic module through an optical fiber; the photoelectric conversion unit of the first optoelectronic module is connected to the electro-optical conversion unit of the second optoelectronic module through an optical fiber; the electro-optical conversion unit of the third optoelectronic module at the first end is connected to the photoelectric conversion unit of the third optoelectronic module at the second end through an optical fiber; the photoelectric conversion unit of the third optoelectronic module at the first end is connected to the electro-optical conversion unit of the third optoelectronic module at the second end through an optical fiber.

[0021] In one embodiment, the first end includes a first optoelectronic module and 1, 3, 7 or 15 third optoelectronic modules; the second end includes a second optoelectronic module and 1, 3, 7 or 15 third optoelectronic modules.

[0022] In one embodiment, the first optoelectronic module is connected to the differential signal pair for sending and the differential signal pair for receiving of PCIe channel 0 (LANE0) of the first PCIe connector; the second optoelectronic module is connected to the differential signal pair for sending and the differential signal pair for receiving of PCIe channel 0 (LANE0) of the second PCIe connector.

[0023] In one embodiment, the first optoelectronic module is also connected to the differential signal pair of the first PCIe connector for transmitting the clock signal; the second optoelectronic module is also connected to the differential signal pair of the second PCIe connector for transmitting the clock signal.

[0024] In one embodiment, the two electro-optical conversion units of the first optoelectronic module are respectively connected to the differential signal pair for sending and the differential signal pair for transmitting the clock signal of PCIe channel 0 (LANE0) of the first PCIe connector; the two optoelectronic conversion units of the second optoelectronic module are respectively connected to the differential signal pair for receiving and the differential signal pair for transmitting the clock signal of PCIe channel 0 (LANE0) of the second PCIe connector.

[0025] In one embodiment, the number of third optoelectronic modules at the first end and the number of third optoelectronic modules at the second end are both n, where n=1, 3, 7 or 15; the electro-optical conversion unit of the i-th third optoelectronic module at the first end is connected to the differential signal pair for sending of the PCIe channel i (LANEi) of the first PCIe connector; the optoelectronic conversion unit of the i-th third optoelectronic module at the first end is connected to the differential signal pair for receiving of the PCIe channel i (LANEi) of the first PCIe connector; the electro-optical conversion unit of the i-th third optoelectronic module at the second end is connected to the differential signal pair for sending of the PCIe channel i (LANEi) of the second PCIe connector; the optoelectronic conversion unit of the i-th third optoelectronic module at the second end is connected to the differential signal pair for receiving of the PCIe channel i (LANEi) of the second PCIe connector; where i=1, 2,…, n.

[0026] In one embodiment, an optoelectronic module at the first end and an optoelectronic module at the second end are connected via an optical fiber to form an optoelectronic module pair, and the optical fibers between different optoelectronic module pairs have the same length.

[0027] In one embodiment, the differential signal transmission distances from the differential signal pair of PCIe lane j of the first PCIe connector to the differential signal pair of PCIe lane j (LANEj) of the second PCIe connector are the same, where j=0, 1, 2, . . .

[0028] In one embodiment, between different optoelectronic module pairs, the distance from the optoelectronic module at the first end to the first PCIe connector is equal to the sum of the distances from the optoelectronic module at the corresponding second end to the second PCIe connector.

[0029] In one embodiment, the first end includes a first circuit board, and the first side of the first circuit board is closer to the optical fiber than the other sides of the first circuit board; the first optoelectronic module at the first end is farther away from the first side than the third optoelectronic module at the first end; the second end includes a second circuit board, and the second side of the second circuit board is closer to the optical fiber than the other sides of the second circuit board; the second optoelectronic module at the second end is closer to the first side than the third optoelectronic module at the second end.

[0030] In one embodiment, the third optoelectronic module at the first end is farther away from or closer to the first side than other third optoelectronic modules, and the third optoelectronic module at the second end of the corresponding optoelectronic module pair is closer to or farther from the second side than other third optoelectronic modules.

[0031] In one embodiment, the optoelectronic module at the first end obtains power from the first PCIe connector at the first end; the second end further includes a third connector, and the optoelectronic module at the second end obtains power from the third connector.

[0032] In one embodiment, the optoelectronic module at the first end obtains power from the first PCIe connector at the first end; the second end also includes a power line, and the optoelectronic module at the second end obtains power from the power line.

[0033] In one embodiment, the first end and the second end are connected only by an optical fiber.

[0034] In one embodiment, the PCIe extension cable further includes a metal wire connecting the first end and the second end, which is used to correspond to other signals except the differential signal pair connecting the first PCIe connector at the first end and the second PCIe connector at the second end.

[0035] In a second aspect, the present invention further provides a PCIe device with an extension line, comprising: a first end, the first end comprising a first PCIe connector, an optoelectronic module, a detection unit and an impedance to ground, the first PCIe connector comprising a differential signal pair for sending and a differential signal pair for receiving, the optoelectronic module of the first end is connected to the differential signal pair for sending and the differential signal pair for receiving of the first end; the differential signal pair for receiving of the first end is connected to the impedance to ground; the differential signal pair for sending of the first end is connected to the detection unit; a second end, the second end comprising the optoelectronic module, the detection unit, the impedance to ground ground impedance, a differential signal pair for sending, a differential signal pair for receiving, and a target (Target) compatible with the PCIe protocol, the optoelectronic module at the second end is connected to the differential signal pair for sending and the differential signal pair for receiving at the second end; the differential signal pair for sending at the second end is connected to the ground impedance; the differential signal pair for receiving at the second end is connected to the detection unit; the differential signal pair for sending and the differential signal pair for receiving at the second end are connected to the target (Target); and an optical fiber, the optical fiber is used to connect the optoelectronic module at the first end and the optoelectronic module at the second end.

[0036] In a third aspect, the present invention further provides a PCIe device with an extension cable, comprising: a PCIe extension cable and a target (Target) compatible with the PCIe protocol; the PCIe extension cable is the PCIe extension cable described in one of the embodiments of the first aspect mentioned above; the target (Target) compatible with the PCIe protocol is connected to a second PCIe connector at the second end of the PCIe extension cable.

[0037] In a fourth aspect, the present invention further provides a signal transmission method for a PCIe extension cable, wherein the PCIe extension cable is the PCIe extension cable described in any one of the embodiments of the first aspect, and the method comprises: in response to receiving a differential signal from a differential signal pair for receiving a differential signal, the optoelectronic module at the first end converts the differential signal into an optical signal, and the optical signal is transmitted by the optical fiber to the optoelectronic module at the second end; in response to receiving the optical signal, the optoelectronic module at the second end converts the optical signal into a differential signal and transmits it to the differential signal pair for sending the differential signal at the second end.

[0038] In a fifth aspect, the present invention further provides a signal transmission method for a PCIe extension cable, comprising: in response to the first end of the cable being connected to an initiator, the first end enables the initiator to detect that a target (Target) is connected during a detection phase of a link training process according to a PCIe protocol and enter a polling phase of link training; the first end converts a differential signal received from a differential signal pair for receiving into an optical signal, which is transmitted by the optical fiber to an optoelectronic module at the second end; in response to the second end of the cable being connected to a target (Target), the second end enables the target (Target) to enter a polling phase of link training according to the PCIe protocol. The detection phase of the training process detects that the initiator is connected and enters the polling phase of the link training; the second end converts the differential signal received from the differential signal pair for sending into an optical signal, which is transmitted by the optical fiber to the optoelectronic module of the first end; in response to the first end detecting that the initiator is connected, the first end converts the optical signal received from the optical fiber into a differential signal, which is transmitted by the optical fiber to the differential signal pair for sending at the second end; in response to the second end detecting that the target is connected, the second end converts the optical signal received from the optical fiber into a differential signal, which is transmitted by the optical fiber to the differential signal pair for sending at the second end.

[0039] In one embodiment, in response to the first end causing the initiator to detect a first common-mode input impedance change during the detection phase of the link training process and the first end detecting a third common-mode input impedance change, the current path is a valid PCIe path; in response to the first end causing the initiator not to detect the first common-mode input impedance change during the detection phase of the link training process or the first end not detecting the third common-mode input impedance change, the current path is an invalid PCIe path, and the initiator and the first end enter the detection silent phase of the link training; in response to the second end causing the initiator to detect a second common-mode input impedance change during the detection phase of the link training process and the second end detecting a fourth common-mode input impedance change, the current path is a valid PCIe path; in response to the second end causing the initiator not to detect the second common-mode input impedance change during the detection phase of the link training process or the second end not detecting the fourth common-mode input impedance change, the current path is an invalid PCIe path, and the target (Target) and the second end enter the detection silent phase of the link training.

[0040] In one embodiment, in response to the two detected numbers of valid PCIe channels being consistent, the first end enters the polling phase of link training; in response to the two detected numbers of valid PCIe channels being inconsistent, the first end enters the detection silent phase of link training; in response to the two detected numbers of valid PCIe channels being consistent, the second end enters the polling phase of link training; in response to the two detected numbers of valid PCIe channels being inconsistent, the second end enters the detection silent phase of link training.

[0041] In one embodiment, the time intervals between the two detections of the effective channel are consistent.

[0042] In one embodiment, in response to the first end and the second end entering the polling phase, the first end receives a first sequence and sends the first sequence to the second end; in response to the second end receiving the second sequence, the second end receives a third sequence from the target (Target) and sends the third sequence to the first end; in response to the first sequence, the second sequence and the third sequence meeting the judgment criteria, entering the configuration polling phase of the polling phase; in response to the first sequence, the second sequence or the third sequence not meeting the judgment criteria, entering the compliance polling phase of the polling phase; wherein, the configuration polling means that the polling behavior has been configured or set, and the compliance polling means that the polling behavior complies with specific power management specifications or standards.

[0043] In one embodiment, the judgment criterion is that the first end receives 8 first sequences and the second end receives 8 third sequences; and the time difference between the generation of the first sequence and the generation of the third sequence is 48 ms.

[0044] In one embodiment, in response to entering the compliance polling phase of the polling phase, the first end receives a first sequence and sends the first sequence to the second end; in response to the second end receiving the second sequence, the second end receives a third sequence from the target (Target) and outputs the third sequence to the first end; in response to the first sequence, the second sequence or the third sequence meeting the judgment criteria, entering the configuration polling phase of the polling phase; in response to the first sequence, the second sequence or the third sequence not meeting the judgment criteria, entering the detection activation phase of link training; wherein the detection activation phase is a high power consumption state when the PCIe extension line is in data transmission or communication is required.

[0045] In one embodiment, in response to entering the detection activation phase of the link training and the number of valid PCIe channels of the first end is consistent with the number of valid PCIe channels of the second end, the first end communicates normally with the second end.

[0046] In one embodiment, in response to entering the detection activation phase of the link training and the number of valid PCIe channels at the first end is inconsistent with the number of valid PCIe channels at the second end, entering the link communication detection silence.

[0047] In one embodiment, in response to the inconsistency between the number of valid PCIe channels at the first end and the number of valid PCIe channels at the second end within a limited time, communication is stopped.

[0048] In one embodiment, within the limited time, the first end or the second end performs link training more than twice.

[0049] In one embodiment, the limited time is greater than or equal to 500 ms.

[0050] In one embodiment, in response to the inconsistency between the number of valid PCIe channels at the first end and the number of valid PCIe channels at the second end during the normal communication, the communication is stopped.

[0051] In general, the above technical scheme conceived by the present invention can achieve the following beneficial effects compared with the prior art: the scheme of the present invention verifies whether the effective PCIe channels of the first end and the second end meet the conditions of optical communication based on the detection unit and the impedance to ground, and when the communication conditions are met, the cooperation between the PCIe connector, the optoelectronic module and the optical fiber is used to make the PCIe signal between the initiator and the target to be optically transmitted over a long distance, thereby realizing the long-distance and efficient transmission of the PCIe signal. In this scheme, the optoelectronic modules at the first end and the second end have the detect detection function required in the PCIe protocol, so there is no need to use the Switch chip, which can greatly reduce the cost and system complexity. In addition, in the process of technical implementation, the scheme of the present invention adopts a PCIe extension line composed of devices such as a PCIe connector, an optoelectronic module and an optical fiber to realize signal extension. These devices in the PCIe extension line have the advantages of low power consumption and low cost relative to traditional optical modules, thereby effectively reducing the hardware overhead in the process of technical implementation, thereby effectively reducing the cost of technical implementation. BRIEF DESCRIPTION OF THE DRAWINGS

[0052] By reading the following detailed description with reference to the accompanying drawings, the above and other objects, features and advantages of the exemplary embodiments of the present invention will become readily understood. In the accompanying drawings, several embodiments of the present invention are shown in an exemplary and non-limiting manner, and the same or corresponding reference numerals represent the same or corresponding parts, wherein:

[0053] Figure 1 An exemplary schematic diagram of a PCIe extension cable according to an embodiment of the present invention is shown;

[0054] Figure 2 An exemplary flow chart of a process of powering up and configuring one end of a PCIe extension cable according to an embodiment of the present invention is shown;

[0055] Figure 3 An exemplary flow chart of the power-on to configuration process of the second end (end B) of the PCIe extension cable according to an embodiment of the present invention is shown;

[0056] Figure 4a shows an exemplary circuit diagram of a detection unit according to an embodiment of the present invention;

[0057] Figure 4b shows an exemplary circuit diagram of a detection unit according to another embodiment of the present invention;

[0058] Figure 5 An exemplary circuit diagram showing the connection between a PCIe channel and a detection unit according to an embodiment of the present invention is shown;

[0059] Figure 6An exemplary schematic diagram of a PCIe extension cable end and a Receiver Detection of a PCIe device according to an embodiment of the present invention is shown;

[0060] Figure 7 An exemplary schematic diagram of the receiver detection of two ends of a PCIe extension line and a PCIe device according to an embodiment of the present invention is shown;

[0061] Figure 8 An exemplary principle block diagram of a PCIe extension cable according to an embodiment of the present invention is shown;

[0062] Fig. 9 An exemplary principle block diagram of a PCIe extension cable according to another embodiment of the present invention is shown;

[0063] Fig.10 An exemplary principle block diagram of a PCIe extension cable according to yet another embodiment of the present invention is shown;

[0064] Fig.11 A schematic diagram of the structure of a PCIe extension cable according to an embodiment of the present invention is shown;

[0065] Fig.12 A schematic structural diagram of a PCIe extension cable according to another embodiment of the present invention is shown;

[0066] Fig.13 A specific layout of the optoelectronic module of an embodiment of the present invention at both ends of a PCIe extension line is shown;

[0067] Fig.14 An exploded view of the structure of the TX end of the PCIe extension cable in an embodiment of the present invention is shown;

[0068] Fig.15 An exploded view of the structure of the RX end of the PCIe extension cable in an embodiment of the present invention is shown;

[0069] Fig.16 A schematic diagram showing the structure of a PCIe device with an extension cable according to an embodiment of the present invention

[0070] Fig.17 A schematic structural diagram of a PCIe device with an extension cable according to another embodiment of the present invention is shown;

[0071] Fig.18 An exemplary flow chart of a signal transmission method of a PCIe extension line according to an embodiment of the present invention is shown;

[0072] Fig.19 An exemplary flow chart of a signal transmission method of a PCIe extension line according to another embodiment of the present invention is shown. DETAILED DESCRIPTION

[0073] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present invention.

[0074] It should be understood that the terms "include" and "comprising" used in the description and claims of the present invention indicate the presence of described features, integers, steps, operations, elements and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components and / or combinations thereof.

[0075] It should also be understood that the terms used in this specification of the present invention are only for the purpose of describing specific embodiments and are not intended to limit the present invention. As used in the specification of the present invention and the claims, the singular forms of "a", "an" and "the" are intended to include the plural forms unless the context clearly indicates otherwise. It should also be further understood that the term "and / or" used in the specification of the present invention and the claims refers to any combination of one or more of the associated listed items and all possible combinations, and includes these combinations.

[0076] As used in this specification and claims, the term "if" may be interpreted as "when" or "upon" or "in response to determining" or "in response to detecting," depending on the context. Similarly, the phrase "if it is determined" or "if [described condition or event] is detected" may be interpreted as meaning "upon determination" or "in response to determining" or "upon detection of [described condition or event]" or "in response to detecting [described condition or event]," depending on the context.

[0077] First, explanations of technical terms that may be used in the present invention are given.

[0078] PCIe lane: refers to a group of differential signal pairs, including differential signal pairs for sending signals and differential signal pairs for receiving signals. The differential signal pair for sending includes two lines, TX+ and TX-, and the differential signal pair for receiving includes two lines, RX+ and RX-. Therefore, a lane has four physical lines. In a lane, differential signals can be sent and received at the same time.

[0079] The PCIe physical layer requires link initialization and link training, which are generally completed through the Link Training and Status State Machine (LTSSM). The main process is that after power-on, both sides (i.e., the two ends of mutual communication) enter the LTSSM process according to the PCIe bus protocol. This process is a set of hardware automated processes. Both parties automatically negotiate the rate and width, and adjust the sending and receiving parameters to achieve the best signal quality.

[0080] In the present invention, the main focus is on the two stages of detect and polling in LTSSM. The present invention will be described below in conjunction with specific embodiments to describe these two stages.

[0081] The specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0082] Figure 1 An exemplary schematic diagram of a PCIe extension cable 100 according to an embodiment of the present invention is shown.

[0083] like Figure 1 As shown in , the PCIe extension cable 100 may include a first end 101 , a second end 102 and an optical fiber 103 .

[0084] In one embodiment, the above-mentioned first end 101 may include a first PCIe connector 1011, an optoelectronic module 1012, a detection unit 1013 and a ground impedance 1014. The first PCIe connector 1011 may include a differential signal pair for sending and a differential signal pair for receiving (that is, including a PCIe channel). The optoelectronic module 1012 at the first end is connected to the differential signal pair for sending and the differential signal pair for receiving of the first end 101; the differential signal pair for receiving of the first end 101 is connected to the ground impedance 1014; and the differential signal pair for sending of the first end is connected to the detection unit 1013.

[0085] It can be understood that the differential signal pair for sending connected to the detection unit 1013 and the differential signal pair for sending connected to the optoelectronic module 1012 are the same differential signal pair; the differential signal pair for receiving connected to the ground impedance 1014 and the differential signal pair for receiving connected to the optoelectronic module 1012 are the same differential signal pair. The optoelectronic module 1012, the detection unit 1013 and the ground impedance 1014 can be integrated in the same module or set independently.

[0086] In one embodiment, the second end 102 may include a second PCIe connector 1021, an optoelectronic module 1022, a detection unit 1023, and a ground impedance 1024. The second PCIe connector 1021 may include a differential signal pair for sending and a differential signal pair for receiving (i.e., including a PCIe channel). The optoelectronic module 1022 of the second end 102 is connected to the differential signal pair for sending and the differential signal pair for receiving of the second end 102; the differential signal pair for receiving of the second end 102 is connected to the ground impedance 1024; and the differential signal pair for sending of the second end 102 is connected to the detection unit 1023.

[0087] The differential signal pair for sending in the first end 101 and the second end 102 can be understood as a differential signal pair for sending signals, such as two lines TX+ and TX-, and the differential signal pair for receiving can be understood as a differential signal pair for receiving signals, such as two lines RX+ and RX-. The first PCIe connector 1011 and the second PCIe connector 1021 include at least one PCIe channel (Lane).

[0088] The optical fiber 103 may be used to connect the optoelectronic module 1012 at the first end 101 and the optoelectronic module 1022 at the second end 102 .

[0089] Based on the structure of the PCIe extension cable 100 described above, during link training, the following operations are performed at both ends of the link. Figure 2 An exemplary flow chart of a power-on to configuration process 200 of one end of a PCIe extension cable according to an embodiment of the present invention is shown. The following takes the first end (the optoelectronic module of this end is recorded as end A, and the corresponding PCIe device is the initiator) as an example for explanation, and the second end of the PCIe extension cable 100 is called end B.

[0090] like Figure 2 As shown in the figure, after the PCIe device (initiator) is inserted into the A end and powered on together with the PCIe device, the PCIe device at the A end and the A end will automatically complete the reset (not shown in the figure) and initialization process (step S201). This process is a process controlled by each party and there is no information interaction.

[0091] After initialization, the detection unit of the transmitter (Transmiitter) in each independent Lane will begin to enter the detect process. The detect stage has two sub-states: detect.Quiet (detection silence, step S202) and detect.Active (detection activation, step S203). Detect.Quiet is the first stage. After Δt time (Δt can be 12ms or other values), Δt is the interval value from detect.Quiet to detect.Active specified by the protocol, the transmitter enters the detect.Active state. In the present invention, the devices at both ends of each Lane act as transmitters to perform the detect process on their opposite devices. For example, end A acts as a transmitter, and the PCIe device (initiator) connected to end A acts as a receiver, or the PCIe device (initiator) connected to end A acts as a transmitter, and end A acts as a receiver. During the detect process, the transmitter transmits a detection sequence, and the detector determines whether a receiver exists by detecting the common-mode impedance at the far end. In steps S204 and S205, the detection sequence is sent twice to detect the common mode resistance of the remote end, and the accuracy is improved based on whether the number of valid lanes (Lane) identified twice is consistent.

[0092] Both ends of the PCIe extension cable 100 must perform the above-mentioned detect process, that is, the B end and the PCIe device (target) connected to the B end must also perform the detect process. After the detect process at both ends is successfully completed, both sides (ends) of the PCIe extension cable 100 will start the subsequent polling process through the optical fiber.

[0093] The main function of the polling phase is to obtain bit / symbol lock and synchronize both ends of the link to enter the next configure state. It is basically composed of polling.active (polling activation, step S206), polling.configurate (configuration polling, step S208), and polling.compliance (compliance polling, step S209) sub-state machines. The polling active state means that the device is being polled to check whether it needs to be awakened to the active state.

[0094] Polling.active is the first state of the Polling phase. After this state, the initiator starts to send TS1 sequences to the target at the other end of the PCIe extension line 100. At this time, the initiator will first transmit 1024 TS1 sequences for bit lock and symbol lock. This is to make the initiator and the target work in a synchronous state. Then the corresponding target at the other end should receive 8 TS1 sequences and reply 8 TS2 sequences within t2 (t2 can be 48ms) (step S207). That is, handshake is performed through TS1 and TS2 sequences. At this time, if the reply is successful, the polling.config state of step S208 is entered, otherwise the polling.compliance state of step S209 is entered. In this state, the above process (polling active) is repeated to repair the link. When the repair is successful, the polling.Active state is entered. If the repair is unsuccessful, it falls back to the detect state (step S203). It can be understood that the above polling.active describes the process of executing polling on each lane of PCIe, and each lane will perform the above polling.active process.

[0095] When the PCIe device connected to end A sends a TS1 sequence, the optoelectronic module at that end converts it into an optical signal and transmits it to end B. The optoelectronic module at end B restores it into an electrical signal and sends it to the PCIe device at that end. In this process, the optoelectronic module at end A or end B does not generate a TS1 sequence itself. Entering the polling state does not describe end A and end B, but the PCIe device connected to end A and end B enters this state. At this time, the optoelectronic module is only responsible for transmitting the signal intact, playing the role of a bridge.

[0096] In the polling.config (polling.configurate) state, the number of Lanes and the data rate on each Lane are determined, which can be negotiated through the TS sequence, and FTS (a redundant sequence used to eliminate the problem of inconsistent arrival time from one end to the other during signal transmission) is added to eliminate the skew (timing deviation) between Lanes, and finally normal communication can be achieved.

[0097] If the number of Lanes determined in the polling.config state is completed before the communication is completed, there is a situation where the number of Lanes between the optoelectronic module end (for example, end A) and the host end (for example, the PCIe device corresponding to end A, i.e. the initiator) and the number of Lanes between the optoelectronic module end and the PCIe device (target) end are inconsistent, such as a sudden damage to an optoelectronic module, resulting in inconsistent numbers of Lanes between ends A and B, then since the initiator end has not matched the Lane information, the PCIe device will continue to communicate with the current number of Lanes to match the final number of Lanes. If the number of Lanes has been matched, the sudden damage of the optoelectronic module will directly cause communication failure, and the device needs to be restarted for normal use.

[0098] Figure 3 FIG. 3 is an exemplary flow chart of a power-on to configuration process 300 of the second end (end B) of a PCIe extension cable according to an embodiment of the present invention. It can be understood that the process can be understood as Figure 2 Simplified process of the process. Figure 3 As shown in , method 300 may include, at step S301, powering on and initializing end B, at step S302, resetting end B, and then entering step S303, where end B enters detect. Next, at step S304, it is determined whether the target is inserted; when the target is inserted and working normally, it enters step S305, waits for end A to complete detect, then enters polling, and then starts handshaking by sending signals to each other. In response to the target not being inserted, the method returns to step S303 after, for example, 12 ms.

[0099] Through the study of USB3.0 protocol, it is found that USB has the same Receiver Detection mechanism as PCIe protocol during Link Training (the detection mechanism is described in detail below). Based on the same detection mechanism, the optoelectronic module used to transmit USB high-speed signals can be used to transmit PCIe signals and realize PCIe extension cable. The optoelectronic modules at both ends are described in detail below.

[0100] In one embodiment, the optoelectronic module at the first end may be an optoelectronic module that meets the USB3.X protocol, and the optoelectronic module at the first end may be used to convert the differential signal of the differential signal pair for receiving at the first end into an optical signal, and the optical signal is transmitted to the optoelectronic module at the second end by the optical fiber. Similarly, the optoelectronic module at the second end may be an optoelectronic module that meets the USB3.X protocol, and the optoelectronic module at the second end may be used to convert the optical signal into a differential signal and transmit it to the differential signal pair for sending at the second end. The USB3.X protocol may be the USB3.0 protocol.

[0101] In one embodiment, the optoelectronic module at the first end can be used to convert the optical signal from the optical fiber into a differential signal and transmit it to the differential signal pair for sending at the first end; the optoelectronic module at the second end can be used to convert the differential signal of the differential signal pair for receiving at the second end into an optical signal, and transmit it to the optoelectronic module at the first end by the optical fiber.

[0102] by Figure 1 Taking the PCIe extension cable shown as an example, the optoelectronic module 1012 at the first end can be used to convert the differential signal of the differential signal pair for receiving at the first end 101 into an optical signal, and the optical signal is transmitted to the optoelectronic module 1022 at the second end by the optical fiber 103. Then, the optoelectronic module 1022 at the second end 102 can convert the optical signal into a differential signal and transmit it to the differential signal pair for sending at the second end 102. The optoelectronic module 1022 at the second end 102 can be used to convert the differential signal of the differential signal pair for receiving at the second end 102 into an optical signal, and transmit it to the optoelectronic module 1012 at the first end by the optical fiber 103. Then, the optoelectronic module 1012 at the first end 101 can convert the optical signal from the optical fiber 103 into a differential signal and transmit it to the differential signal pair for sending at the first end 101.

[0103] It can be seen that since the PCIe connector and the optoelectronic module are respectively integrated at both ends of the PCIe extension cable, electrical signals such as differential signals can be converted into optical signals through the cooperation of the PCIe connector at one end of the PCIe extension cable and the optoelectronic module, and the optical signal is transmitted to the optoelectronic module at the other end of the PCIe extension cable (for example, from the first end to the second end) via the optical fiber between the optoelectronic modules, and then the optical signal is restored to a differential signal through the optoelectronic module at this end, and the differential signal is continued to be transmitted through the PCIe connector at this end, thereby realizing the transmission of PCIe signals through optical fiber.

[0104] Receiver Detection is required during link training. As described above, the detect process is bidirectional, so Receiver Detection is also a common behavior, that is, the Tx (transmitter) on the device side (the side where the PCIe device is located) will detect whether the Rx (receiver) on the optoelectronic module side (the side where the optoelectronic module is located) exists, and the Tx (transmitter) of the optoelectronic module will also detect whether the Rx (receiver) on the device side exists.

[0105] In one embodiment, the detection units 1013 and 1023 can be used to detect the ground impedance of the differential signal pair for receiving at the opposite end connected thereto. Figure 4a and Figure 4b The detection unit will be described. Figure 4aAn exemplary circuit diagram of a detection unit 400 according to an embodiment of the present invention is shown, and the diagram shows a circuit when no PCIe device is connected; Figure 4b FIG. 4 is a schematic circuit diagram of a detection unit 400 according to another embodiment of the present invention. The circuit diagram shows a circuit when a PCIe device is connected.

[0106] like Figure 4a and 4b As shown in , the detection unit 400 may include two capacitors C_AC and C_Parasitic, a switch and a resistor R_Detect, wherein the first capacitor C_AC is used to be connected in series with the ground impedance R_Term, and the circuit in which the first capacitor C_AC and the ground impedance R_Term are connected in series is connected in parallel with the second capacitor C_Parasitic.

[0107] Figure 5 FIG. 2 shows an exemplary circuit diagram of a PCIe channel and a detection unit connected according to an embodiment of the present invention. Figure 5 As shown in the figure, the transmitter uses a differential signal pair for sending through PCIe, through the channel ( Figure 5 Lane in one direction) is connected to the receiver, so that the detection unit on the transmitter side ( Figure 5 The impedance Z to ground is connected to the receiver side. RX .

[0108] It is understandable that in a PCIe link, the transmitter (transmitter / transmitter / TX) usually operates at a certain voltage when in the detection state, that is, the common mode voltage on the high-speed differential interconnect (link) is a stable value. The receiver is connected through Lane in one direction (for example, a pair of physical wires). The equivalent circuit diagram at this time is equivalent to Figure 4b . Because Z RX When the transmitter is in the detect.active state, the time it takes to change the common-mode voltage value on the differential pair is related to Z RX There is a clear difference in the time when the voltage changes when it is not connected. The detection unit determines whether the receiver is connected by identifying this time difference, thereby performing Receiver Detection. The value of the above new voltage is specified as a maximum of 600mV in both PCIe and USB3.0 protocols.

[0109] The protocol stipulates that the equivalent circuit diagram of PCIe is as follows Figure 4a and Figure 4b As shown, the charging time is determined by the transmission line impedance, charging capacitor (mentioned above Figure 4a and Figure 4b The charging target voltage and RX termination impedance are determined by the capacitance C-AC and C-parasitic in the PCB and the termination impedance (ground impedance) of the RX end ("receiver" or "receiving end"). In the PCIe protocol, the termination single-ended impedance to ground (ground impedance) of the RX end is between 40Ω and 60Ω, and the single-ended impedance to ground in the USB3.0 protocol is around 45Ω (for example, 45Ω). In summary, the charging target voltage and RX termination impedance of the two are basically the same, and the transmission line capacitance and common-mode input impedance are determined by the PCB board, so the two have very similar waveform characteristics when performing termination detection.

[0110] Based on the above principle, the transmitter can change the DC common mode voltage (DC common mode voltage) on the transmission line of the PCIe channel by means of resistor voltage division, thereby detecting the common mode input impedance of the other end (receiving end) of the transmission line. In general, as long as the receiver on the other end of the transmitter exists and works properly, its DC common mode input impedance is much smaller than the impedance when there is no device on the other end or the receiver of the device does not work properly. Therefore, the transmitter can determine whether the PCIe device on the other end exists by detecting the DC common mode input impedance of the device on the other end.

[0111] When optical fiber transmits PCIe signals, the number of communicable PCIe channels at both ends of the optical fiber may be inconsistent, so it is impossible to ensure that the two ends of the optical fiber can communicate normally. In order to solve this problem, it is necessary to determine whether the number of valid PCIe channels (communicable PCIe channels) at both ends is consistent. The specific method can be as follows:

[0112] First determine whether the initiator (Initator) is connected to the first end of the PCIe extension cable, and whether the target is connected to the second end of the PCIe extension cable. The detection circuit at the first end can be used to detect whether the first end is connected to the initiator, and the detection circuit at the second end can be used to detect whether the second end is connected to the target (Target). In one implementation, the detection unit at the first end can detect whether the first end is connected to the initiator by detecting a change in the common-mode input impedance; similarly, the detection unit at the second end can detect whether the second end is connected to the target (Target) by detecting a change in the common-mode input impedance. It should be noted that the detection unit at the second end is connected to the ground impedance in the target (Target) through the differential signal pair used for sending at the second end. For the detection unit at the second end, the common-mode input impedance of the target (Target) is detected.

[0113] The following scheme combines Figure 6 and Figure 7 Let's explain Receiver Detection.

[0114] In the PCIe protocol, it is stipulated that the detection unit on the transmitter side of the initiator detects whether the receiver of the target is connected; and the detection unit on the transmitter side of the target detects whether the receiver of the initiator is connected. However, after the optical fiber-based PCIe extension line is connected between the initiator and the target, the access detection mechanism between the initiator and the target stipulated in the PCIe protocol is destroyed, because the optical fiber cannot directly transmit electrical signals between the initiator and the target. In order to solve this problem, after the optical fiber-based PCIe extension line is connected between the initiator and the target, the respective detection units of the initiator and the target can still detect the access of the other end when working in accordance with the provisions of the PCIe protocol, and then complete the link training. Detection units are respectively set at both ends of the PCIe extension line according to an embodiment of the present invention.

[0115] Figure 6 An exemplary schematic diagram of a PCIe extension cable end and a Receiver Detection of a PCIe device according to an embodiment of the present invention is shown. Figure 7 An exemplary schematic diagram of Receiver Detection at both ends of a PCIe extension line and a PCIe device according to an embodiment of the present invention is shown. Figure 6 The device end 601 in the figure can be a PCIe device (initiator or target), and Detect is a detection unit.

[0116] like Figure 6 As shown in , the transmitter-side detection unit (Detect) of the device end 601 detects whether the ground impedance of the differential signal pair for receiving connected to it at one end of the PCIe extension line exists, and the detection unit (Detect) of the transmitter at one end of the PCIe extension line also detects the ground impedance of the differential signal pair for receiving connected to it at the device end 601. That is, the detection unit (Detect) in the device end 601 detects whether the ground impedance 6021 of one end of the PCIe extension line meets the conditions described above to determine whether one end of the PCIe extension line is connected, and the detection unit (Detect) in one end of the PCIe extension line detects whether the common-mode input impedance 6011 of the differential signal pair of the received signal of the device end 601 meets the conditions described above to determine whether the device end 601 is inserted.

[0117] exist Figure 7In the embodiment, the detection unit (Detect) of the transmitter in the initiator 7011 detects whether the ground impedance 70121 of the differential signal pair for receiving in the first end 7012 of the PCIe extension line connected to it at one end of the PCIe extension line meets the conditions, so as to determine whether the first end 7012 of the PCIe extension line is connected; the detection unit (Detect) of the transmitter in the first end 7012 of the PCIe extension line also detects whether the common-mode input impedance 70111 of the initiator 7011 connected to it for receiving the differential signal pair meets the conditions described above, so as to determine whether the initiator 7011 is inserted. The detection unit (Detect) of the transmitter in the target 7021 will detect whether the impedance to ground 70211 of the differential signal pair for receiving in the second end 7022 of the PCIe extension cable connected to one end of the PCIe extension cable meets the conditions, so as to determine whether the second end 7022 of the PCIe extension cable is connected; the detection unit (Detect) of the transmitter in the second end 7022 of the PCIe extension cable will detect whether the common-mode input impedance 70221 of the target 7021 connected to it for receiving the differential signal meets the conditions described above, so as to determine whether the target 7021 is inserted.

[0118] Each PCIe channel (Lane) at both ends is detected to identify a valid PCIe channel. For the first end, in response to the detection unit at the first end detecting a change in the common-mode input impedance, and the first end impedance to ground (the first end impedance to ground) is detected, the PCIe channel is a valid PCIe channel. The impedance to ground of the first end here is detected by the initiator (the initiator's detection unit). For the second end, in response to the detection unit at the second end monitoring a change in the common-mode input impedance, and the second end impedance to ground is detected, the PCIe channel is a valid PCIe channel. Similarly, the second end impedance to ground here is detected by the target (the target's detection unit). It can be understood that the above process is for detecting whether a Lane is a valid PCIe channel. When there are multiple Lanes at one end of PCIe, the above process needs to be performed for each Lane to determine whether the current lane is a valid PCIe channel.

[0119] Since there are often multiple PCIe channels, there may also be multiple first-end detection units (first-end detection units), first-end ground impedance (first-end ground impedance), second-end detection units (second-end detection units), and second-end ground impedance (second-end ground impedance). The number of first-end detection units and first-end ground impedances is the same, and the number of PCIe channels at the first end is the same; the number of second-end detection units and second-end ground impedances is the same, and the number of PCIe channels at the second end is the same. That is, each Lane (PCIe channel) has a detection unit and ground impedance.

[0120] In one embodiment, the ground impedance of the differential signal pair for receiving at the first end and the ground impedance of the differential signal pair for receiving at the second end may be consistent with the receiving end input impedance specified by the PCIe protocol. RX Receiver Input Impedance (Receiver Input Impedance) refers to the equivalent input impedance of the PCIe receiver end, which is specified in the PCIe protocol. It is a key parameter that affects the signal integrity and link performance. The range specified in the PCIe protocol is 40-60Ω. Therefore, making the impedance to ground of the differential signal pair for reception at the first end and the impedance to ground of the differential signal pair for reception at the second end consistent with the receiving end input impedance specified in the PCIe protocol can improve the signal integrity and link performance.

[0121] It is understandable that the distance from the first PCIe connector to the initiator and the distance from the second PCIe connector to the target are relatively short, and the impedance to ground detected by the initiator or the target does not change much. Therefore, the first end impedance to ground (the impedance to ground of the first end) and the second end impedance to ground (the impedance to ground of the second end) can be greater than or equal to 40Ω and less than or equal to 60Ω. It is understandable that if the Tx (transmitter) of the PCIe device finds that the impedance to ground of its load is Z RX-DC When the impedance to ground detected by the initiator or target is within the range (40Ω~60Ω), it can be determined that the receiver Rx of the opposite device exists to ensure the integrity of the signal and the performance of the link, which can improve the system compatibility. It can be understood that in the actual communication process, the impedance to ground detected by the initiator or target is slightly less than 40Ω and will not affect the communication.

[0122] As a preferred solution, the impedance to ground of the second end may be greater than or equal to 45Ω. When the impedance to ground of both ends is consistent with 45Ω, the differential impedance between the first end and the second end is 90Ω, and the impedance value of the differential signal pair is 90Ω. It is understandable that the impedance to ground of the first end and the impedance to ground of the second end may be equal or different, and the differential impedance may be 90Ω within the value range, thereby improving system compatibility and reducing the difficulty of design and manufacturing.

[0123] In one implementation, when performing validity detection of a PCIe channel, a detection sequence may be sent to a peer device through a transmitter at one end of a PCIe extension line to apply a common mode voltage on the channel to trigger a detection mechanism for ground impedance (e.g. Figure 2 , or step S204 in the above procedure.

[0124] When performing valid PCIe lane detection, in one embodiment, the detection unit at the first end can determine whether the first end enters the polling phase of link training by detecting the number of valid PCIe lanes twice; similarly, the detection unit at the second end can determine whether the second end enters the polling phase of link training by detecting the number of valid PCIe lanes twice, where the number of valid PCIe lanes is the number of changes in common-mode input impedance detected by the detection unit. Multiple detections can ensure the stability of the number of detected Lanes and that two detections will not use too many resources.

[0125] If the number of valid PCIe channels detected in the above two tests is the same, the polling phase of link training is entered (such as Figure 2 Otherwise, the link training detection silent phase is entered ( Figure 2 In step S202), a detection is performed every t1 (e.g., 12 milliseconds) during the detection silence phase. In another embodiment, the number of detections of the number of valid PCIe channels may also be once, which can save computing resources. In another embodiment, a single Lane termination independent transmission method may be adopted to achieve termination transmission equivalent to copper wire transmission, achieve transparency, and not participate in the specific link training of PCIe.

[0126] Optionally, the first end and the second end of the PCIe extension line enter the polling phase independently. For example, the first end enters the polling phase by itself according to the detection of a valid Lane through the above process. In the polling phase, the first end directly transmits the signal from the initiator (for example, a signal representing the TS1 sequence and the TS2 sequence) to the second end, and expects the initiator and the target (Target) to perform the processing in the polling phase. Similarly, the second end enters the polling phase according to the detection of a valid Lane through the above process. In the polling phase, the second end directly transmits the signal from the initiator and the first end (for example, a signal representing the TS1 sequence and the TS2 sequence) to the target (Target), and expects the initiator and the target (Target) to perform the processing in the polling phase. Thus, the first end and the second end do not need to inform the other end that they have completed the Detect.Active state stage of link training.

[0127] According to the foregoing description, the time for the common-mode input impedance to change is fixed. Therefore, whether the currently detected PCIe channel is a valid PCIe channel can be determined based on whether the time for the common-mode input impedance to change is consistent. Specifically, in response to the consistency of the times for the common-mode input impedance change detected by the first-end detection unit, it is indicated that the PCIe channels detected twice are valid PCIe channels (between the first end and the initiator). In response to the consistency of the number of valid PCIe channels (between the first end and the initiator) obtained from the two detections, the first end enters the polling phase of link training. In response to the inconsistency of the times for the common-mode input impedance change detected by the first-end detection unit, it is indicated that the PCIe channels detected twice are invalid PCIe channels. In response to the inconsistency of the number of valid PCIe channels detected twice, the first end enters the detection silent phase of link training. Similarly, in response to the consistency of the two common-mode input impedance change times detected by the second-end detection unit, it means that the PCIe channels detected twice are valid PCIe channels (between the second end and the target), and in response to the consistency of the number of valid PCIe channels (between the second end and the target) obtained in the two detections, the second end enters the polling phase of the link training in the polling phase; in response to the unequal number of PCIe channels at this end in the two detections, the second end enters the detection silence phase of the link training; wherein the detection silence phase is a low-power state when the PCIe extension line is in no data transmission. It can be understood that the two common-mode input impedance change times detected by the detection unit at the first end detection unit are consistent, and the common-mode input impedance change time is the edge time of the periodically changing common-mode voltage generated after the impedance to the ground is connected, that is, the edge time of the two detections is consistent, indicating that the current Lane is a valid Lane.

[0128] According to the above description, it can be seen that the solution of the present invention verifies whether the effective PCIe channels of the first end and the second end meet the conditions of optical communication based on the detection unit and the impedance to ground, and when the communication conditions are met, the cooperation between the PCIe connector, the optoelectronic module and the optical fiber is used to make the PCIe signal between the initiator and the target perform long-distance optical transmission, thereby realizing the long-distance and efficient transmission of the PCIe signal. In this solution, the optoelectronic modules at the first end and the second end have the detect detection function required in the PCIe protocol, so there is no need to use the Switch chip, which can greatly reduce the cost and system complexity. In addition, in the process of technical implementation, the solution of the present invention uses a PCIe extension line composed of devices such as a PCIe connector, an optoelectronic module and an optical fiber to realize signal extension. These devices in the PCIe extension line have the advantages of low power consumption and low cost relative to traditional optical modules, thereby effectively reducing the hardware overhead in the process of technical implementation, thereby effectively reducing the cost of technical implementation.

[0129] The above describes the link training process of the PCIe of the present solution. The following describes the structure and arrangement of the optoelectronic modules at both ends of the present solution in combination with multiple embodiments.

[0130] First, the structure of the optoelectronic module is introduced. The first end and the second end each include an optoelectronic module, and each optoelectronic module includes only one optoelectronic conversion unit, one electro-optical conversion unit and one optical component. The optoelectronic module may include an optoelectronic conversion unit, an electro-optical conversion unit and an optical component. The optoelectronic conversion unit may be used to convert a received optical signal into a differential signal; the electro-optical conversion unit is used to convert a received differential signal into an optical signal; the optoelectronic conversion unit and / or the electro-optical conversion unit are coupled to the optical fiber through the optical component.

[0131] Figure 8 An exemplary principle block diagram of a PCIe extension cable 800 according to an embodiment of the present invention is shown. As shown in the figure, the PCIe extension cable 800 may include a first end 801, a second end 802 and an optical fiber 803. The first end 801 may include a first PCIe connector 8012, an optoelectronic module 8011, a detection unit 8013 and an impedance to ground 8014. The second end 802 may include a second PCIe connector 8022, an optoelectronic module 8021, a detection unit 8023 and an impedance to ground 8024. For details of the first PCIe connector 8012, the detection unit 8013, the impedance to ground 8014, the second PCIe connector 8022, the detection unit 8023 and the impedance to ground 8024, refer to the relevant descriptions of the above embodiments, which will not be repeated here.

[0132] As shown in the figure, the optoelectronic module 8011 includes an optoelectronic conversion unit 80111, an electro-optical conversion unit 80112 and an optical component 80113, and the optoelectronic module 8021 includes an optoelectronic conversion unit 80211, an electro-optical conversion unit 80212 and an optical component 80213. The optoelectronic conversion unit 80111 is connected to the optoelectronic conversion unit 80211 through the optical fiber 803, and the electro-optical conversion unit 80112 is connected to the electro-optical conversion unit 80212 through the optical fiber 803.

[0133] In some embodiments, the aforementioned photoelectric conversion unit may be implemented by an optical receiver, and the electro-optical conversion unit may be implemented by an optical transmitter. The optical transmitter may be an optical transmitter such as a vertical cavity surface laser transmitter (VCSEL) to achieve electro-optical conversion, the aforementioned optical receiver may be an optical receiver such as a laser diode (PD) to achieve photoelectric conversion, and the aforementioned optical component may include an optical device (such as a lens, etc.).

[0134] In specific applications, the photoelectric conversion unit and the electro-optical conversion unit can be combined with optical components in a variety of ways to achieve coupling with optical fibers. For example, when an optical device such as a lens has an optical fiber fixing installation groove, the optical fiber can be directly plugged into the lens. For another example, the aforementioned optical component can also include a jumper that can couple the optical signal into the optical fiber. In this case, the optical fiber can be coupled to the lens in a bonding manner through the jumper. It should be noted that the description of the coupling method here is an exemplary description, and the solution of the present invention is not limited to this. For example, the optical fiber can also be coupled to the lens in other forms such as a bracket.

[0135] Furthermore, the above-mentioned photoelectric conversion unit, electro-optical conversion unit and optical components can be modularly designed by gluing, bonding and the like. In actual application, the modularly designed photoelectric module can be installed as a conventional electrical device (for example, by welding or plugging). The modular design of the photoelectric module greatly reduces the complexity of the manufacturing process of the PCIe extension cable, and when a certain photoelectric module fails, it can be quickly repaired by replacing the photoelectric module without replacing the entire board. In addition, when it is necessary to increase the data path, the data path can be expanded without affecting the original structure, thereby increasing the scope of use and convenience.

[0136] The structure of the optoelectronic module is described above, and the arrangement of the optoelectronic modules at both ends is described below. It can be understood that the number of optoelectronic modules in the PCIe extension cable is not limited, and can be set and adjusted according to actual needs. Fig. 9 FIG. 8 shows an exemplary principle block diagram of a PCIe extension cable 900 according to another embodiment of the present invention. Fig. 9 As shown in the figure, the PCIe extension cable 900 may include a first end 901, a second end 902 and an optical fiber 903. The first end 901 may include a first PCIe connector 9012, an optoelectronic module 9011, a detection unit 9013 and a ground impedance 9014. The second end 902 may include a second PCIe connector 9022, an optoelectronic module 9021, a detection unit 9023 and a ground impedance 9024. For details of the first PCIe connector 9012, the detection unit 9013, the ground impedance 9014, the second PCIe connector 9022, the detection unit 9023 and the ground impedance 9024, reference may be made to the relevant descriptions of the above embodiments, which will not be repeated here.

[0137] like Fig. 9As shown in , the optoelectronic module 9011 of the first end 901 may include a first optoelectronic module 90111, and the optoelectronic module 9012 of the second end 902 may include a second optoelectronic module 9021; the optical fiber 903 may include at least three. In this embodiment, the optical fiber 903 may be three, four or five. The first optoelectronic module 9011 may include two electro-optical conversion units (electro-optical conversion unit 90111 and electro-optical conversion unit 90112) and one electro-optical conversion unit 90113; the second optoelectronic module 9021 may include two electro-optical conversion units (electro-optical conversion unit 90211 and electro-optical conversion unit 90212) and one electro-optical conversion unit 90213; the two electro-optical conversion units of the first optoelectronic module 9011 are respectively connected to one of the two electro-optical conversion units of the second optoelectronic module 9021 through an optical fiber, for example, the electro-optical conversion unit 90111 is connected to the electro-optical conversion unit 90211, and the electro-optical conversion unit 90112 is connected to the electro-optical conversion unit 90212; the electro-optical conversion unit 90113 of the first optoelectronic module 9011 is connected to the electro-optical conversion unit 90213 of the second optoelectronic module 902 through an optical fiber 903. In this embodiment, the optoelectronic modules (e.g., optoelectronic module 9011, optoelectronic module 9012) may be modularly designed.

[0138] The above describes the case where each end includes one optoelectronic module. The following describes the case where each end includes two optoelectronic modules. Fig.10 FIG. 2 shows an exemplary principle block diagram of a PCIe extension cable 1000 according to another embodiment of the present invention. Fig.10 As shown in , the PCIe extension cable 1000 may include a first end 1001, a second end 1002 and an optical fiber 1003. The first end 1001 may include a first PCIe connector 10012, an optoelectronic module 10011, a detection unit and an impedance to ground, and the second end 1002 may include a second PCIe connector 10022, an optoelectronic module 10021, a detection unit and an impedance to ground. The number of optoelectronic modules matches the detection unit and the impedance to ground, that is, each optoelectronic module constitutes a PCIe channel (Lane), and the differential signal pair for receiving in a PCIe channel of the first end 1002 is connected to the impedance to ground; the differential signal pair for sending in a PCIe channel of the first end 1002 is connected to the detection unit. For details about the detection unit and the impedance to ground and the first PCIe connector 10012 and the second PCIe connector 10022, please refer to the relevant descriptions of the previous embodiments. When one end of the subsequent PCIe extension cable has multiple optoelectronic modules, the detection unit and the impedance to ground are not displayed to simplify the structure.

[0139] As shown in the figure, the optoelectronic module 10011 of the first end 1001 may include a first optoelectronic module (optoelectronic module 0 of the first end in the figure) and a third optoelectronic module (optoelectronic module 1 of the first end in the figure), and the optoelectronic module 10021 of the second end 1002 may include a second optoelectronic module (optoelectronic module 0 of the second end in the figure) and a third optoelectronic module (optoelectronic module 1 of the second end in the figure); the optical fiber 1003 may include at least five. In this embodiment, the optical fibers may be five, six, seven, etc.

[0140] In one embodiment, the above-mentioned first optoelectronic module may include two electro-optical conversion units and one photoelectric conversion unit (not shown in the figure); the second optoelectronic module may include two photoelectric conversion units and one electro-optical conversion unit (not shown in the figure); the third optoelectronic module may include one photoelectric conversion unit and one electro-optical conversion unit; the two electro-optical conversion units of the first optoelectronic module are respectively connected to one of the two photoelectric conversion units of the second optoelectronic module through an optical fiber; the photoelectric conversion unit of the first optoelectronic module is connected to the electro-optical conversion unit of the second optoelectronic module through an optical fiber; the electro-optical conversion unit of the third optoelectronic module at the first end is connected to the photoelectric conversion unit of the third optoelectronic module at the second end through an optical fiber; the photoelectric conversion unit of the third optoelectronic module at the first end is connected to the electro-optical conversion unit of the third optoelectronic module at the second end through an optical fiber.

[0141] In addition to the above two photoelectric module arrangements, each end may also include more photoelectric modules. For example, in another embodiment, the first end may include a first photoelectric module and 1, 3, 7 or 15 third photoelectric modules; the second end may include a second photoelectric module and 1, 3, 7 or 15 third photoelectric modules. The structure of the third photoelectric module may be the same or similar to the above embodiment and will not be described in detail here.

[0142] The previous article describes several situations of the arrangement of optoelectronic modules at both ends. The following describes the connection between the optoelectronic module and the PCIe connector.

[0143] In one embodiment, the above-mentioned first optoelectronic module can be connected to the differential signal pair for sending and the differential signal pair for receiving of PCIe channel 0 (Lane0) of the first PCIe connector; similarly, the second optoelectronic module can be connected to the differential signal pair for sending and the differential signal pair for receiving of PCIe channel 0 (Lane0) of the second PCIe connector.

[0144] In addition to the above connection relationship, the first optoelectronic module can also be connected to the differential signal pair of the first PCIe connector for transmitting the clock signal. Similarly, the second optoelectronic module can also be connected to the differential signal pair of the second PCIe connector for transmitting the clock signal. Fig.10Specifically, the signal (i.e., clock signal) of the REFCLK pin of the first PCIe connector 10012 can be sent to the optoelectronic module 0 in the first end 1001, and after being processed by the optoelectronic module 0 in the first end 1001, the processed signal is transmitted to the optoelectronic module 0 in the second end 1002 through the optical fiber 1003. Then, the optoelectronic module 0 in the second end 1002 processes the received signal and then sends it to the REFCLK pin of the second PCIe connector 10022. At this time, the two electro-optical conversion units of the first optoelectronic module are respectively connected to the differential signal pair for sending and the differential signal pair for transmitting the clock signal of the PCIe channel 0 (Lane0) of the first PCIe connector 10012; the two optoelectronic conversion units of the second optoelectronic module are respectively connected to the differential signal pair for receiving and the differential signal pair for transmitting the clock signal of the PCIe channel 0 (Lane0) of the second PCIe connector 10022.

[0145] Based on the structure of the optoelectronic module, the two electro-optical conversion units of the first optoelectronic module can be respectively connected to the differential signal pair for sending and the differential signal pair for transmitting the clock signal of the PCIe channel 0 (Lane0) of the first PCIe connector 10012; the two optoelectronic conversion units of the second optoelectronic module can be respectively connected to the differential signal pair for receiving and the differential signal pair for transmitting the clock signal of the PCIe channel 0 (Lane0) of the second PCIe connector 10022. Based on this connection, Fig.10 In the embodiment, the signal (i.e., clock signal) of the REFCLK pin of the first PCIe connector 10012 can be sent to the optoelectronic module 0 in the first end 1001, and after being processed by the optoelectronic module 0 in the first end 1001, the processed signal is transmitted to the optoelectronic module 0 in the second end 1002 through the optical fiber. Then, the optoelectronic module 0 in the second end 1002 processes the received signal and sends it to the REFCLK pin of the second PCIe connector 10022.

[0146] It should be noted that in this embodiment, each PCIe channel in the PCIe connector is independent, and the optoelectronic module connected to Lane0 additionally bears the task of transmitting the clock signal, while the structure is consistent with the optoelectronic modules connected to other Lanes. Therefore, when the optoelectronic modules connected to other Lanes fail, communication is still possible, but if the optoelectronic module connected to Lane0 fails, communication is impossible.

[0147] In an embodiment where each of the two ends includes a plurality of third optoelectronic modules, the electro-optical conversion unit of the i-th third optoelectronic module at the first end can be connected to the differential signal pair for sending of the PCIe channel i (Lane i) of the first PCIe connector; the optoelectronic conversion unit of the i-th third optoelectronic module at the first end is connected to the differential signal pair for receiving of the PCIe channel i (Lanei) of the first PCIe connector. The electro-optical conversion unit of the i-th third optoelectronic module at the second end is connected to the differential signal pair for sending of the PCIe channel i (Lane i) of the second PCIe connector; the optoelectronic conversion unit of the i-th third optoelectronic module at the second end is connected to the differential signal pair for receiving of the PCIe channel i (Lane i) of the second PCIe connector; wherein i=1, 2,…, n. n can be a positive integer such as 3, 4, 5, 6, etc.

[0148] That is, the third optoelectronic module at the first end is connected to the differential signal pair for sending and the differential signal pair for receiving of the PCIe channel n (Lane n) of the first PCIe connector, and the third optoelectronic module at the second end is connected to the differential signal pair for sending and the differential signal pair for receiving of the PCIe channel n (Lane n) of the second PCIe connector, where n is not 0. In other words, each third optoelectronic module at the first end is connected in a one-to-one correspondence with other PCIe channels of the first PCIe connector except PCIe channel 0 (Lane0), and the third optoelectronic module at the second end is connected in a one-to-one correspondence with other PCIe channels of the second PCIe connector except PCIe channel 0 (Lane0).

[0149] To further illustrate the above embodiment, the following scheme will be combined with Fig.11 to explain in detail. Fig.11 A schematic structural diagram of a PCIe extension cable 1100 according to an embodiment of the present invention is shown.

[0150] Fig.11 The figure shows a case where each end of the PCIe extension line includes three third optoelectronic modules, that is, n=3. Specifically, Fig.11 FIG. 1 is a schematic diagram of the structure of a PCIe extension cable 1100 according to another embodiment of the present invention. It should be noted that the PCIe extension cable 1100 can be understood as a further limitation or functional expansion of the PCIe extension cable 100, PCIe extension cable 800, PCIe extension cable 900 or PCIe extension cable 1000. Figure 1 , Figure 8 , Fig. 9 and Fig.10 The relevant detailed description of FIG. 1 also applies to this embodiment.

[0151] like Fig.11As shown in, the PCIe extension line 1100 may specifically include a first end 1101, a second end 1102 and an optical fiber 1103. Among them, the first end 1101 of the PCIe extension line 1100 may include a first PCIe connector 11012, an optoelectronic module 11011, a detection unit and an impedance to ground. The second end 1102 of the PCIe extension line 1100 may include a second PCIe connector 11022, an optoelectronic module 11021, a detection unit and an impedance to ground. The optical fiber 1103 may be used to connect the optoelectronic module 11011 of the first end 1101 and the optoelectronic module 11021 of the second end 1102.

[0152] In this embodiment, the first end 1101 includes a first optoelectronic module ( Fig.11 The first end of the optoelectronic module 0) and three third optoelectronic modules (such as Fig.11 The first end 1102 includes a second optoelectronic module ( Fig.11 The optoelectronic module 0 at the second end of the photoelectric module is connected to the optical fiber of the optical fiber module 1 through the optical fiber module 3.

[0153] In this implementation scenario, the number of the third optoelectronic modules at the first end 1101 and the number of the third optoelectronic modules at the second end 1102 are both 3. At this time, the i-th third optoelectronic module at the first end 1101 (eg Fig.11 The electro-optical conversion unit of the optoelectronic module 1, optoelectronic module 2 or optoelectronic module 3 in the first end 1101 is connected to the PCIe channel (Lane1, Lane2 or Lane3) of the first PCIe connector 11012 for sending the differential signal pair. Fig.11 The photoelectric conversion unit of the photoelectric module 1, the photoelectric module 2 or the photoelectric module 3 in the first end is connected to the PCIe channel i of the first PCIe connector 11012 (such as Fig.11 The i-th third optoelectronic module (such as Lane1, Lane2 or Lane3 in the first end) of the second end 1102 is used to receive the differential signal pair. Fig.11 The electro-optical conversion unit of the optoelectronic module 1, optoelectronic module 2 or optoelectronic module 3 in the second end is connected to the PCIe channel i of the second PCIe connector 11022 (such as Fig.11 The i-th third optoelectronic module (such as Lane1, Lane2 or Lane3 in the second end) of the second end 1102 is used to send a differential signal pair. Fig.11 The photoelectric conversion unit of the photoelectric module 1, the photoelectric module 2 or the photoelectric module 3 in the second end is connected to the PCIe channel i of the second PCIe connector 11022 (such as Fig.11 A differential signal pair for receiving in Lane1, Lane2 or Lane3 in the second end.

[0154] In one embodiment, the optoelectronic module at the first end can be connected to the first PCIe connector (such as Fig.10 or Fig.11 In some embodiments, the second end may also include a third connector (e.g., Fig.10 or Fig.11 In another embodiment, the optoelectronic module at the first end can also obtain power from the first PCIe connector at the first end, and the second end can also include a power cord (not shown in the figure), and the optoelectronic module at the second end can obtain power from the power cord. Thus, the two ends of the PCIe extension cable adopt an independent power supply method, which can achieve electrical isolation between the devices connected at the two ends, thereby improving the security of communication.

[0155] For example, in some embodiments, Fig.10 or Fig.11 The first end of the PCIe extension cable can be connected to the PCIe device at the end through the first PCIe connector, and the second end of the PCIe extension cable can be connected to the PCIe device at the end through the second PCIe connector. In particular, when the PCIe device connected to the first end is an initiator and the PCIe device connected to the second end is a target, the PCIe extension cable can not only support efficient and long-distance PCIe signal transmission between the initiator and the target, but also achieve electrical isolation between the initiator and the target, thereby effectively avoiding the problem of large-scale damage caused by a problem with a device at one end.

[0156] According to the embodiments described above, the optoelectronic modules at both ends of the PCIe extension line can include multiple optoelectronic modules. Subject to the skew limit of Lane to Lane, these optoelectronic modules can be specially laid out. For example, in one embodiment, an optoelectronic module at the first end and an optoelectronic module at the second end are connected by optical fiber to form an optoelectronic module pair, and the optical fiber lengths between different optoelectronic module pairs are the same, thereby ensuring that the optical signal has the same transmission distance. In order to achieve the same transmission distance of the signal, in another embodiment, the differential signal transmission distance of the differential signal pair of the PCIe channel j of the first PCIe connector to the differential signal pair of the PCIe channel j (Lane j) of the second PCIe connector is the same, where j = 0, 1, 2, ...

[0157] To further ensure that the transmission distance of the optical signal on each light beam is equal, when there are multiple optical fibers, the optical fiber lengths of each optical fiber used to connect the first end and the second end are equal. In other words, when laying out the optoelectronic modules, between different optoelectronic module pairs, the sum of the distances from the optoelectronic module at the first end to the first PCIe connector is equal to the distances from the optoelectronic module at the second end to the second PCIe connector connected thereto.

[0158] In one embodiment, the first PCIe connector may use a gold finger, and the second PCIe connector may use a board-to-board connector. Fig.12 An embodiment in which the first PCIe connector uses a gold finger and the second PCIe connector uses a board-to-board connector is described below. Fig.12 A structural schematic diagram of a PCIe extension cable 1200 according to yet another embodiment of the present invention is shown.

[0159] like Fig.12 As shown in FIG. 1 , the PCIe extension cable 1200 may include a first end (eg, Fig.12 TX end 1201 in), the second end (such as Fig.12 The first end may include a gold finger 12012, an optoelectronic module 12011, a detection unit, and an impedance to ground (not shown in the figure), and the second end may include a board-to-board connector 12022, an optoelectronic module 12021, a detection unit, and an impedance to ground (not shown in the figure). For details of the optoelectronic module 12011, the optoelectronic module 12021, the detection unit, and the impedance to ground, please refer to the above description in conjunction with the relevant embodiments, and will not be repeated here.

[0160] In this embodiment, the gold finger 12012 can be connected to the initiator 1204 for transmitting signals and supplying power to the TX. The board-to-board connector 12022 is connected to the target 1205 for transmitting signals, etc. The second end can also include a connector 1206, which can be a USB / HDMI / or other form of socket, which can be used to supply power to the target 1205 and the optoelectronic module 12021.

[0161] In a specific implementation, the first end and the second end may include a circuit board in hardware, and the electrical components of each end may be arranged on the circuit board. Fig.13 The first end and the second end are described in detail when the first end includes the first optoelectronic module and the third optoelectronic module, and the second end includes the second optoelectronic module and the third optical film. Fig.13 The figure shows a specific layout of the optoelectronic module of the embodiment of the present invention at both ends of the PCIe extension line. The figure does not show the detection unit and the ground impedance.

[0162] like Fig.13As shown in , the first end may include a first circuit board 1301, the first side of the first circuit board 1301 is closer to the optical fiber 1303 than the other sides of the first circuit board 1301; the first optoelectronic module (e.g., optoelectronic module No. 0) at the first end is farther away from the first side than the third optoelectronic module (e.g., optoelectronic module No. 1, optoelectronic module No. 2) at the first end. The second end includes a second circuit board 1302, the second side of the second circuit board 1302 is closer to the optical fiber 1303 than the other sides of the second circuit board 1302; the second optoelectronic module (e.g., optoelectronic module No. 0) at the second end is closer to the first side than the third optoelectronic module (e.g., optoelectronic module No. 1, optoelectronic module No. 2) at the second end.

[0163] In addition, the third optoelectronic module at the first end is farther away from or closer to the first edge than other third optoelectronic modules, and the third optoelectronic module at the second end of the corresponding optoelectronic module pair is closer to or farther away from the second edge than other third optoelectronic modules. Fig.13 In the embodiment, the No. 1 photoelectric module and the No. 2 photoelectric module in the first end (TX end) are closer to the first side than the No. 3 photoelectric module, that is, the No. 3 photoelectric module in the first end (TX end) is farther away from the first side than the No. 1 photoelectric module and the No. 2 photoelectric module. Through the above arrangement, it is achieved that the sum of the distance from the photoelectric module at the first end to the first PCIe connector and the distance from the photoelectric module at the second end to the second PCIe connector connected thereto is equal between different photoelectric module pairs.

[0164] In other words, within the same optoelectronic module pair, if the optoelectronic module at the first end is farther away from or closer to the first side than other optoelectronic modules, then the optoelectronic module at the corresponding second end is closer to or farther away from the second side than other optoelectronic modules at that end. Fig.13 In the TX end, the No. 0 optoelectronic module and the No. 3 optoelectronic module are closer to the gold finger connection than the No. 1 optoelectronic module and the No. 2 optoelectronic module, which means that the traces of Lane0 and Lane3 on the first circuit board 1301 are smaller than those of Lane1 and Lane2. On the RX end, the layout of the optoelectronic modules thereon is opposite to that of the TX end. Specifically, the traces of Lane1 and Lane2 on the second circuit board 1302 in the RX end are smaller than those of Lane0 and Lane3. As a result, the RX end and the TX end complement each other, so that the deviation between Lanes is controlled within a certain range (for example, 1CM). At the same time, this layout method also compensates for the length difference caused by the optical fiber, making it negligible.

[0165] Therefore, the solution of this embodiment can transmit PCIe signals commonly used in computer devices in the form of optical signals. Fig.13The layout design shown can support signal transmission of different PCIe rates and different channel numbers. In specific applications, the TX end of the PCIe extension cable can be connected to the M.2 slot of the computer motherboard using connection methods such as M.2 gold fingers. The onboard optoelectronic module can convert the PCIe signal into an optical signal for transmission. In addition, the TX end is powered by the power provided by the motherboard M.2 slot (e.g., 3.3V power).

[0166] In addition, Fig.13 In the figure, the optical modules numbered 0, 1, 2, and 3 correspond to the PCIe channels (Lane0 to Lane3) they are responsible for transmitting. In addition to transmitting the differential signal of the PCIe channel (Lane0), the optical module numbered 0 is also responsible for transmitting the PCIe clock signal.

[0167] In addition, the PCIe extension cable of this embodiment can support the number of data links X1, X2 (such as Fig.10 As shown), X4 (as Fig.11 In some embodiments, if the photoelectric module No. 2 or the photoelectric module No. 3 fails unexpectedly, the system will be reduced to running with an X2 link instead of failing completely. If the photoelectric module No. 1 fails, it will run with an X1 link. Only the failure of the photoelectric module No. 0 will cause the entire system to fail.

[0168] In one embodiment, the first end and the second end may be connected only by an optical fiber. In another embodiment, the PCIe extension cable may further include a metal wire (e.g., a copper wire) connecting the first end and the second end, for correspondingly connecting other signals except the differential signal pair of the first PCIe connector at the first end and the second PCIe connector at the second end.

[0169] The above describes the PCIe extension cable from the perspective of circuit structure. The following scheme describes the mechanical structure of the first end and the second end of the PCIe extension cable to facilitate understanding of the scheme of the present invention.

[0170] Fig.14 The structure of the TX end 1400 in the PCIe extension cable of the embodiment of the present invention is shown in the exploded view, and the detection unit and the ground impedance are not shown in the figure. Fig.14 In the embodiment, the circuit board (PCB) of the TX end 1400 of the PCIe extension cable is provided with an optoelectronic module, a gold finger 1406 (other connection methods are also possible), a mounting hole (such as Fig.14 The fixed half hole 1409 in the photoelectric module may be omitted), the power chip 1410 (which is used for voltage conversion). The detection unit and the ground impedance are not shown in this figure. In addition, in some embodiments, the TX end is far away from the circular hole of the optoelectronic module end to increase the grounding point of the TX end.

[0171] Fig.15 The structure explosion diagram of the RX end of the PCIe extension cable in the embodiment of the present invention is shown, and the detection unit and the ground impedance are not shown in the figure. Fig.15 In the embodiment, the RX end PCB board is provided with an optoelectronic module, a board-to-board connector 1407, a fixing nut 1511, a nut welding hole 1512, a connector 1408, a fixing hole 1513, a power chip (which is used for voltage conversion), etc. Among them, there are multiple fixing nuts 1511 and they are arranged at intervals, which are used to install fixing screws to abut the remote device between the board-to-board connector 1407 and the fixing nut 1511. Multiple fixing nuts 1511 are arranged at intervals to adapt to remote devices of different sizes. The fixing nut 1511 is connected to the GND of the PCB, which can increase the grounding point of the remote device and improve the signal stability.

[0172] Specifically, in Fig.14 and Fig.15 In the embodiment, the optoelectronic module may specifically include an optoelectronic IC 1421 and an optical component. Among them, the optoelectronic IC 1421 may include an IC die 1421A, a light transmitter (VCSEL), and a light receiver (PD) 1421B. In this embodiment, the IC die 1421A may be understood as a driver, serving as a driver for the optoelectronic module. The VCSEL may be understood as a specific implementation of an electro-optical conversion unit, and the PD may be understood as a specific implementation of a photoelectric conversion unit. The optical component may include a lens optical component 1422 and / or a jumper 1423. In this embodiment, it is preferred that the optoelectronic module assembly and the optical fiber fixation and jumper assembly are assembled separately and independently to improve production efficiency.

[0173] In some embodiments, Fig.14 and Fig.15 The optoelectronic IC 1421 in the TX end 1400 may include multiple optoelectronic ICs 1421 numbered 0 may specifically include 2 VCSELs and 1 PD, and the optoelectronic ICs 1421 with other numbers may include 1 VCSEL and 1 PD, and each VCSEL and PD is connected to a power supply and powered by the power supply. The optoelectronic IC 1421 numbered 0 in the Rx end specifically includes 2 PDs and 1 VCSEL. The VCSEL at the TX end is connected to the PD at the RX end through an optical fiber, and the VCSEL at the RX end is connected to the PD at the TX end through an optical fiber.

[0174] Furthermore, in some embodiments, the above-mentioned optoelectronic IC 1421 can adopt a modular design. Specifically, the Lens, IC bare chip, VCSEL and PD can be connected to one side of the substrate by glue and bonding, and electrical contacts (including solder joints or board-to-board connectors for connection with the PCB) are provided at the bottom of the substrate (i.e., the other side). Therefore, when installing, it is only necessary to weld (or install) the modular optoelectronic IC as a conventional device. This design greatly reduces the complexity of the entire manufacturing process, and when a certain optoelectronic module fails, it can be quickly repaired by replacing the optoelectronic module without replacing the entire board. In addition, when it is necessary to increase the data path, the data path can be expanded without affecting the original structure, thereby increasing the scope of use and convenience.

[0175] exist Fig.14 and Fig.15 In the embodiment, the PCB board of the TX end and the RX end also reserves the pad 1514 of other PCIe low-speed signals, which increases the copper wire transmission mode of the PCIe low-speed signals. In addition, the PCB board of the TX end is also provided with an IC pull-up resistor 1515.

[0176] The above describes the transmission structure and principle of PCIe high-speed signals. The following describes the processing method of PCIe low-speed signals. PCIe low-speed signals generally include WAKE# (wake-up signal), PERST# (reset signal), PRSNT1# (PRSNT is a signal used to indicate whether the device has been inserted into the PCIe slot) and PRSNT2#. Among them, PERST# is responsible for the global reset of the target, and the WAKE# signal is responsible for transmitting the wake-up request to the host (initiator) when the target is dormant. This signal needs to be used with the Vaux auxiliary power supply (which can provide Vaux-3.3V voltage). PRSNT1# and PRSNT2# are hot plug detection signals. The host determines whether a PCIe device is inserted or unplugged by detecting the level of the signal.

[0177] For the above PCIe low-speed signal, this embodiment proposes three processing solutions: Solution 1: In some cases, the PCIe device is powered on along with the host and does not need to support hot plugging. In order to save cost and space, normal communication can be achieved without transmitting the PCIe low-speed signal. Usually, when the PCIe host (host) WAKE# signal is fixed high, the PERST# signal is fixed high, the PRSNT1# signal is fixed low, and the PRSNT2# signal is fixed low, and the PCIe device end WAKE# signal is fixed high, the PERST# signal is fixed high, the PRSNT1# signal is fixed low, and the PRSNT2# signal is fixed low, normal communication can be achieved. The reason is that the target will automatically perform a reset during the power-on stage. This process does not require the intervention of the PERST# signal (used to indicate the state of the device when the power supply is stable), and in the application scenarios of some low-power PCIe devices, such as SSD (Solid State Disk or Solid State Drive) and USB (Universal SerialBus) expansion cards, such devices will be in working state throughout the power-on cycle, and due to their low power consumption, they have no sleep function.

[0178] When PCIe low-speed signals need to be transmitted, it can be done through copper wire direct connection and optical transmission. Here we involve solution 2: copper wire direct connection is to connect the corresponding signals of TX and RX ends by welding wires to the board connector. Since PCIe low-speed signals only involve high and low level changes to indicate the working status, copper wires can also support longer distances.

[0179] Solution 3: In the optical transmission solution, since the optoelectronic module still has idle data transmission channels, the level changes of the PCIe low-speed signal can be transmitted through these channels. Specifically, the PCIe low-speed signal is connected to the pins of the optoelectronic module through PCB routing. The MCU built into the module can transmit the level information of these pins. The transmission method can be switching light, such as light represents a high level, and no light represents a low level. It can also use optical pulses to transmit high and low level states. The duty cycle, frequency or length of the optical pulses are different to represent the state information. In addition, it is also possible to encode multiple low-speed signals, use optical pulses to represent different code types for transmission, and then deserialize the signals at the receiving end to restore them to multiple low-speed signals. In addition, a single optoelectronic module can be used to transmit PCIe low-speed signals.

[0180] In addition, during the transmission of PCIe high-speed signals, these PCIe low-speed signals will not be transmitted or when the idle channel of a certain optoelectronic module is used to transmit PCIe low-speed signals, the PCIe high-speed signal transmission may be destroyed. Therefore, the time division multiplexing technology can also be used to multiplex the optoelectronic modules of the high-speed channel to transmit PCIe low-speed signals. In other words, since the PCIe low-speed signal sends a level to indicate the status before the communication is established, the currently used high-speed channel can be used to multiplex the PCIe low-speed signal with any one or more optoelectronic modules before high-speed data communication to transmit the PCIe low-speed signal. The PCIe low-speed signal multiplexing high-speed channel transmission method can transmit the high and low levels of a single low-speed signal on a certain high-speed channel by switching light or optical pulses. The same strategy of using a dedicated optical transmission channel to transmit low-speed signals for PCIe low-speed signals can reduce the number of optical paths, reduce costs and power consumption. The multiplexed high-speed channel can be a clock channel or any lane of one or more optoelectronic modules.

[0181] The flexible selection of the above three solutions can greatly increase the application scope of the solution of the present invention. In addition, it is also possible to choose not to transmit the PCIe low-speed signal.

[0182] According to the foregoing description, it can be seen that the solution of the present invention can realize the transmission of PCIe signals using optical signals based on PCIe extension cables to support long-distance transmission of PCIe signals. In addition, the solution of the present invention uses fewer circuit elements, which reduces hardware overhead, and therefore has great advantages in equipment maintenance, manufacturing costs, and power consumption overhead. In addition, each PCIe channel in the PCIe connector in the solution of the present invention is independent, and the failure of a certain IC (non-No. 0) will not cause the complete failure of the overall function, thereby reducing the failure probability. Furthermore, in the solution of the present invention, independent power supply is used at both ends of the PCIe extension cable, which can achieve electrical isolation between the initiator and the target, and enhance the safety system of the communication system. The optoelectronic module in the solution of the present invention adopts modularization, which is convenient for maintenance and expansion.

[0183] Fig.16 A schematic structural diagram of a PCIe device 1600 with an extension cable according to an embodiment of the present invention is shown.

[0184] like Fig.16 The PCIe device shown in the figure may include a first end 1601 , a second end 1602 , and an optical fiber 1603 .

[0185] In one embodiment, the first end 1601 may include a first PCIe connector 16012, an optoelectronic module 16011, a detection unit 6013, and a ground impedance 16014. The first PCIe connector 16012 may include a differential signal pair for sending and a differential signal pair for receiving. The optoelectronic module 16011 of the first end 1601 is connected to the differential signal pair for sending and the differential signal pair for receiving of the first end 1601; the differential signal pair for receiving of the first end 1601 is connected to the ground impedance 16014; and the differential signal pair for sending of the first end 1601 is connected to the detection unit 16013. This part has the same structure and principle as the first end of the PCIe extension cable described above. For details, please refer to the description of the embodiment in the above text, and will not be described in detail here.

[0186] In one embodiment, the above-mentioned second end 1602 may include an optoelectronic module 16021, a detection unit 16023, an impedance to ground 16024, a differential signal pair for sending, a differential signal pair for receiving, and a target 16025 (Target) compatible with the PCIe protocol. The optoelectronic module 16021 of the second end 1602 is connected to the differential signal pair for sending and the differential signal pair for receiving of the second end 1602; the differential signal pair for receiving of the second end 1602 is connected to the impedance to ground 16024; the differential signal pair for sending of the second end 1602 is connected to the detection unit 16023; the differential signal pair for sending and the differential signal pair for receiving of the second end 1602 are connected to the target 16025 (Target). The optoelectronic module, detection unit, ground impedance, differential signal pair for sending, and differential signal pair for receiving of this part are the same as the structures and principles of the PCIe extension cable described in the previous embodiments. For details, please refer to the description of the previous embodiments and will not be described in detail here.

[0187] In one embodiment, the optical fiber 1603 can be used to connect the optoelectronic module 16011 at the first end 1601 and the optoelectronic module 16021 at the second end 1602. This part has the same structure and principle as the optical fiber part described above, and will not be described in detail.

[0188] In this embodiment, a set of differential signal pairs for transmission and differential signal pairs for reception can be referred to as a PCIe channel (i.e., Lane), and the optoelectronic module 16021 and the target 16025 (Target) in the second end of the PCIe device 1600 can be directly connected through the PCIe channel. That is, the optoelectronic module 16021 and the target 16025 (Target) in the second end 1602 of the PCIe device 1600 can be designed in an integrated manner (e.g., integrated on the same substrate).

[0189] In some embodiments, the differential signal pair for transmission and the differential signal pair for reception may be integrated in the target 16025. In this case, the optoelectronic module 16011 of the first end 1601 is used to convert the differential signal of the differential signal pair for transmission of the first end 1601 into an optical signal, and the optical signal is transmitted to the optoelectronic module 16021 of the second end 1602 by the optical fiber 1603. The optoelectronic module 16021 of the second end 1602 is used to convert the optical signal into a differential signal and transmit it to the differential signal pair for reception, and then transmit it to the target 16025. In addition, the optoelectronic module 16011 at the first end 1601 can also be used to convert the optical signal from the optical fiber 1603 into a differential signal and transmit it to the differential signal pair for receiving at the first end 1601, and the optoelectronic module 16021 at the second end 1602 is used to convert the differential signal of the differential signal pair for sending at the second end 1602 into an optical signal, and transmit it from the optical fiber 1603 to the optoelectronic module 16011 at the first end 1601.

[0190] In this implementation scenario, the first end 1601 in the PCIe device 1600 can be understood as Figure 1 , Figure 8 to Figure 13 The first end of the PCIe extension cable and the second end of the PCIe device 1600 as a whole can be understood as Figure 1 , Figure 8 to Figure 13 That is, the functions and structures of the first PCIe connector 16012, the optoelectronic module 16011, the detection circuit 16013 and the ground impedance 16014 in the first end 1601 of the PCIe device 1600 can be similar to those of Figure 1 , Figure 8 to Figure 13 The first PCIe connector, optoelectronic module, detection circuit and ground impedance in the first end of the PCIe extension cable described above. The optoelectronic module 16021, detection unit 16023, ground impedance 16024, differential signal pair for sending and differential signal pair for receiving in the second end of the PCIe device 1600 can be similar in function and structure. Figure 1 , Figure 8 to Figure 13 The optical module, detection unit, ground impedance, differential signal pair for sending and differential signal pair for connecting in the second end of the PCIe extension cable described. The structure and function of the optical fiber 1603 in the PCIe device 1600 are similar Figure 1 , Figure 8 to Figure 13 Therefore, the specific connection method and working principle of each component in the PCIe device 1600 can be referred to. Figure 1 , Figure 8 to Figure 13 The connection relationship and specific working principle of each component in the PCIe extension cable will not be repeated here.

[0191] According to the description of multiple embodiments of the PCIe extension line in the foregoing text, the PCIe device 1600 of the present invention verifies whether the effective PCIe channels of the first end and the second end meet the conditions of optical communication based on the detection unit and the impedance to ground, and when the communication conditions are met, the cooperation between the PCIe connector, the optoelectronic module and the optical fiber is used to make the PCIe signal between the initiator and the target perform long-distance optical transmission, thereby realizing the long-distance and efficient transmission of the PCIe signal. In this solution, the optoelectronic modules at the first end and the second end have the detect detection function required in the PCIe protocol, so there is no need to use a Switch chip, which can greatly reduce the cost and system complexity. In addition, in the process of technical implementation, the solution of the present invention uses a PCIe extension line composed of devices such as a PCIe connector, an optoelectronic module and an optical fiber to realize signal extension. These devices in the PCIe extension line have advantages such as low power consumption and low cost relative to traditional optical modules, thereby effectively reducing the hardware overhead in the process of technical implementation, thereby effectively reducing the cost of technical implementation.

[0192] Fig.17 A schematic structural diagram of a PCIe device 1700 with an extension cable according to another embodiment of the present invention is shown.

[0193] like Fig.17 The PCIe device 1700 shown in the figure may include a PCIe extension line and a target 1704 (Target) compatible with the PCIe protocol. In one embodiment, the above-mentioned PCIe extension line may be a PCIe extension line according to one of the above-mentioned embodiments. Therefore, the specific description of the first end 1701, the first PCIe connector 17012, the optoelectronic module 17011, the detection unit 17013, the impedance to ground 17014, the second end 1702, the second PCIe connector 17022, the optoelectronic module 17021, the detection unit 17023, the impedance to ground 17024 and the optical fiber 1703 in this embodiment can refer to the relevant description in the PCIe extension line in each of the above-mentioned embodiments, which will not be described in detail here. The above-mentioned target 1704 (Target) compatible with the PCIe protocol can be connected to the second PCIe connector 17022 at the second end of the PCIe extension line.

[0194] According to the description of the multiple embodiments of the PCIe extension line in the foregoing text, the PCIe device 1700 of the present invention verifies whether the effective PCIe channels of the first end 1701 and the second end 1702 meet the conditions of optical communication based on the detection unit and the impedance to ground, and when the communication conditions are met, the cooperation between the PCIe connector, the optoelectronic module and the optical fiber is used to make the PCIe signal between the initiator and the target perform long-distance optical transmission, thereby realizing the long-distance and efficient transmission of the PCIe signal. In this solution, the optoelectronic modules of the first end 1701 and the second end 1702 have the detect detection function required in the PCIe protocol, so there is no need to use the Switch chip, which can greatly reduce the cost and system complexity. In addition, in the process of technical implementation, the scheme of the present invention adopts a PCIe extension line composed of devices such as a PCIe connector, an optoelectronic module and an optical fiber to realize signal extension. These devices in the PCIe extension line have advantages such as low power consumption and low cost relative to traditional optical modules, thereby effectively reducing the hardware overhead in the process of technical implementation, thereby effectively reducing the cost of technical implementation.

[0195] Fig.18 An exemplary flow chart of a signal transmission method 1800 of a PCIe extension line according to an embodiment of the present invention is shown. The PCIe extension line in this embodiment is the PCIe extension line described in any of the above embodiments.

[0196] like Fig.18 As shown in , the signal transmission method 1800 may include, at step S1801, in response to receiving a differential signal from a differential signal pair for receiving a differential signal, the optoelectronic module at the first end converts the differential signal into an optical signal, and the optical signal is transmitted to the optoelectronic module at the second end by an optical fiber. At step S1802, in response to receiving the optical signal, the optoelectronic module at the second end converts the optical signal into a differential signal and transmits it to the differential signal pair for sending a differential signal at the second end.

[0197] According to the foregoing description, the solution of the present invention utilizes the cooperation between the optoelectronic module and the optical fiber to enable the PCIe signal between the initiator connected at the first end and the target connected at the second end to be optically transmitted over a long distance, thereby realizing the long-distance and efficient transmission of the PCIe signal. The use of this method can eliminate the need for a Switch chip, thereby greatly reducing costs and system complexity. In addition, in the process of technical implementation, the solution of the present invention can use a PCIe extension line composed of devices such as a PCIe connector (differential signal pairs for sending and differential signal pairs for receiving), an optoelectronic module, and optical fiber to realize signal extension. These devices have advantages such as low power consumption and low cost relative to traditional optical modules, thereby effectively reducing the hardware overhead in the process of technology implementation, thereby effectively reducing the cost of technology implementation.

[0198] Fig.19 An exemplary flow chart of a signal transmission method 1900 for a PCIe extension line according to another embodiment of the present invention is shown.

[0199] like Fig.19 As shown in , the signal transmission method 1900 may include at step S1901, in response to the first end of the cable being connected to the initiator, the first end enables the initiator to detect that the target (Target) is connected during the detection phase of the link training process according to the PCIe protocol and enter the polling phase of the link training.

[0200] Next, at step S1902, the first end converts the differential signal received from the differential signal pair for receiving into an optical signal, and transmits it to the optoelectronic module at the second end via the optical fiber.

[0201] At step S1903, in response to the second end of the cable being connected to the target, the second end enables the target to detect that the initiator has been connected during the detection phase of the link training process according to the PCIe protocol and enter the polling phase of the link training.

[0202] Then, at step S1904, the second end converts the differential signal received from the differential signal pair for transmission into an optical signal, and transmits it to the optoelectronic module at the first end via the optical fiber.

[0203] At step S1905, in response to the first end detecting that the initiator has been connected, the first end converts the optical signal received from the optical fiber into a differential signal, which is transmitted by the optical fiber to a differential signal pair for sending at the second end.

[0204] At step S1906, in response to the second end detecting that the target (Target) is connected, the second end converts the optical signal received from the optical fiber into a differential signal, which is transmitted by the optical fiber to the differential signal pair for sending at the second end.

[0205] According to the foregoing description, the solution of the present invention utilizes the cooperation between the optoelectronic module and the optical fiber to enable the PCIe signal between the initiator and the target to be optically transmitted over a long distance when the effective PCIe channel at the first end and the second end meets the conditions of optical communication, thereby realizing the long-distance and efficient transmission of the PCIe signal. The use of this method can eliminate the need to use a Switch chip, thereby greatly reducing costs and system complexity. In addition, in the process of technical implementation, the solution of the present invention can use a PCIe extension line composed of devices such as a PCIe connector (differential signal pairs for sending and differential signal pairs for receiving), an optoelectronic module, and an optical fiber to realize signal extension. These devices have advantages such as low power consumption and low cost relative to traditional optical modules, thereby effectively reducing the hardware overhead in the process of technical implementation, thereby effectively reducing the cost of technical implementation.

[0206] According to the foregoing description, it is necessary to perform validity detection of the PCIe path at both ends of the link, and the detection can be achieved by detecting the common-mode input impedance. Therefore, in one embodiment, in response to the first end causing the initiator to detect a change in the first common-mode input impedance during the detection phase of the link training process and the first end detecting a change in the third common-mode input impedance, the current path is a valid PCIe path. Correspondingly, in response to the first end causing the initiator to fail to detect a change in the first common-mode input impedance during the detection phase of the link training process or the first end failing to detect a change in the third common-mode input impedance, the current path is an invalid PCIe path, and the initiator and the first end enter the detection silence phase of the link training.

[0207] Similar to the detection of the first end and the initiator, in response to the second end causing the target to detect the second common-mode input impedance change during the detection phase of the link training process and the second end detecting the fourth common-mode input impedance change, the current path is a valid PCIe path. Correspondingly, in response to the second end causing the target to not detect the second common-mode input impedance change during the detection phase of the link training process or the second end not detecting the fourth common-mode input impedance change, the current path is an invalid PCIe path, and the target (Target) and the second end enter the detection silence phase of the link training.

[0208] According to the above description, the number of PCIe lanes can be detected twice at each end of the link to ensure the stability of the number of lanes. Based on this, in one embodiment, in response to the two detected valid PCIe lane numbers being consistent, the first end enters the polling phase of link training; in response to the two detected valid PCIe lane numbers being inconsistent, the first end enters the detection silent phase of link training.

[0209] Similarly, in response to the two detected valid PCIe channel numbers being consistent, the second end enters the polling phase of link training; in response to the two detected valid PCIe channel numbers being inconsistent, the second end enters the detection silent phase of link training. In one implementation, the time interval between the two detections of valid channels can be consistent, for example, 20-100 milliseconds.

[0210] In response to the first end and the second end entering the polling phase, the first end receives the first sequence and sends the first sequence to the second end; in response to the second end receiving the second sequence, the second end receives the third sequence from the target (Target) and sends the third sequence to the first end; in response to the first sequence, the second sequence and the third sequence meeting the judgment criteria, it indicates that the number of valid PCIe channels at both ends is consistent, and the configuration polling phase of the polling phase is entered. Correspondingly, in response to the first sequence, the second sequence or the third sequence not meeting the judgment criteria, the compliance polling phase of the polling phase is entered. Among them, configuration polling means that the polling behavior has been configured or set, and compliance polling means that the polling behavior complies with specific power management specifications or standards. In compliance polling, link repair (such as physical repair) can be performed to ensure that the PCIe channel can communicate normally after the repair, so that the number of valid PCIe channels at both ends of the link is consistent.

[0211] According to the foregoing description, the above judgment criterion may be that the first end receives 8 first sequences and the second end receives 8 third sequences; and the time difference between the generation of the first sequence and the generation of the third sequence may be 48 ms.

[0212] In one embodiment, in response to entering the compliance polling phase of the polling phase, the first end receives the first sequence and sends the first sequence to the second end. In response to the second end receiving the second sequence, the second end receives the third sequence from the target (Target) and outputs the third sequence to the first end. In response to the first sequence, the second sequence or the third sequence meeting the judgment criteria, the configuration polling phase of the polling phase is entered; in response to the first sequence, the second sequence or the third sequence not meeting the judgment criteria, the detection activation phase (detect.Active phase) of link training is entered. At this time, the high-speed link may be connected, but the physical link caused by poor signal quality cannot meet the PCIE rate requirements; wherein, the detection activation phase is a high-power consumption state when the PCIe extension line is in data transmission or communication is required.

[0213] In one embodiment, in response to entering the detection activation phase of link training, and the number of valid PCIe channels at the first end is consistent with the number of valid PCIe channels at the second end, the first end and the second end can communicate normally. Accordingly, in response to entering the detection activation phase of link training, and the number of valid PCIe channels at the first end is inconsistent with the number of valid PCIe channels at the second end, link communication detection silence is entered, and the two ends cannot communicate normally.

[0214] It is understandable that if the number of valid PCIe channels at both ends of the link is still inconsistent within a certain period of time, it means that the link repair at this time may have failed, and continuing to perform link repair will cause the link training time to be too long, resulting in increased power consumption of the communication link. In this case, no further detection is required. Therefore, in one embodiment, in response to the number of valid PCIe channels at the first end and the second end being inconsistent within a limited time, communication is stopped. In one implementation, the above-mentioned limited time can be greater than or equal to 500ms, such as 500ms, 600ms or 700ms.

[0215] In order to ensure the accuracy of link training, the first end or the second end may perform link training more than twice within a limited time.

[0216] The above describes the link training process before communication. It can be understood that during the communication process, the valid PCIe channel between the two ends may also fail due to some reasons. At this time, communication should be stopped. Therefore, in one embodiment, in response to the inconsistency between the number of valid PCIe channels at the first end and the number of valid PCIe channels at the second end during normal communication, communication is stopped.

[0217] It should be understood that the terms "first", "second", "third" and "fourth" etc. in the claims, specifications and drawings of the present invention are used to distinguish different objects rather than to describe a specific order. The terms "include" and "comprise" used in the specification and claims of the present invention indicate the presence of the described features, wholes, steps, operations, elements and / or components, but do not exclude the presence or addition of one or more other features, wholes, steps, operations, elements, components and / or their collections.

[0218] Although multiple embodiments of the present invention have been shown and described herein, it will be apparent to those skilled in the art that such embodiments are provided by way of example only. Those skilled in the art may conceive of many changes, modifications, and alternatives without departing from the thought and spirit of the present invention. It should be understood that in the process of practicing the present invention, various alternatives to the embodiments of the present invention described herein may be adopted. The appended claims are intended to define the scope of protection of the present invention, and therefore cover equivalents or alternatives within the scope of these claims.

Claims

1. A PCIe extension cable, characterized in that: include: A first end, wherein the first end includes a first PCIe connector, an optoelectronic module, a detection unit, and a ground impedance, wherein the first PCIe connector includes a differential signal pair for sending and a differential signal pair for receiving, wherein the optoelectronic module of the first end is connected to the differential signal pair for sending and the differential signal pair for receiving of the first end; the differential signal pair for receiving of the first end is connected to the ground impedance of the first end; and the differential signal pair for sending of the first end is connected to the detection unit of the first end; The second end includes a second PCIe connector, an optoelectronic module, a detection unit, and an impedance to ground. The second PCIe connector includes a differential signal pair for sending and a differential signal pair for receiving. The optoelectronic module of the second end is connected to the differential signal pair for sending and the differential signal pair for receiving of the second end; the differential signal pair for receiving of the second end is connected to the impedance to ground of the second end; the differential signal pair for sending of the second end is connected to the detection unit of the second end; The detection unit at the first end and the detection unit at the second end are each used to detect the impedance to ground of the differential signal pair for receiving at the opposite end connected thereto; as well as An optical fiber is used to connect the optoelectronic module at the first end and the optoelectronic module at the second end.

2. The PCIe extension cable according to claim 1, characterized in that: The optoelectronic module at the first end is an optoelectronic module that meets the USB3.X protocol, and the optoelectronic module at the first end is used to convert the differential signal of the differential signal pair for receiving at the first end into an optical signal, and the optical signal is transmitted to the optoelectronic module at the second end by an optical fiber; The optoelectronic module at the second end is an optoelectronic module that meets the USB3.X protocol, and the optoelectronic module at the second end is used to convert the optical signal into a differential signal and transmit it to the differential signal pair for sending at the second end.

3. The PCIe extension cable according to claim 1 or 2, characterized in that: The optoelectronic module at the first end is used to convert the optical signal from the optical fiber into a differential signal and transmit it to the differential signal pair for sending at the first end; The optoelectronic module at the second end is used to convert the differential signal of the differential signal pair for receiving at the second end into an optical signal, and transmit the optical signal to the optoelectronic module at the first end through the optical fiber.

4. The PCIe extension cable according to any one of claims 1 to 3, characterized in that: The impedance to ground of the first end and the impedance to ground of the second end are respectively consistent with the input impedance of the receiving end specified by the PCIe protocol.

5. The PCIe extension cable according to any one of claims 1 to 4, characterized in that: The detection circuit at the first end is used to detect that the initiator has been connected to the first end; the detection circuit at the second end is used to detect that the target (Target) has been connected to the second end; the detection unit at the first end detects whether the first end is connected to the initiator by detecting a change in common-mode input impedance; the detection unit at the second end detects whether the second end is connected to the target (Target) by detecting a change in common-mode input impedance.

6. The PCIe extension cable according to claim 5, characterized in that: In response to the detection unit at the first end detecting a change in common-mode input impedance and the impedance of the first end to ground being detected, the PCIe channel between the first end and the initiator is a valid PCIe channel; in response to the detection unit at the second end monitoring a change in common-mode input impedance and the impedance of the second end to ground being detected, the PCIe channel between the second end and the target is a valid PCIe channel.

7. The PCIe extension cable according to any one of claims 1 to 6, characterized in that: There are multiple detection units at the first end, multiple impedance to ground at the first end, multiple detection units at the second end, and multiple impedance to ground at the second end, respectively. The number of detection units at the first end and the impedance to ground at the first end is the same, which is the same as the number of PCIe channels at the first end; the number of detection units at the second end and the impedance to ground at the second end is the same, which is the same as the number of PCIe channels at the second end.

8. The PCIe extension cable according to claim 7, characterized in that: The first end detection unit determines whether the first end enters the polling phase of link training by detecting the number of valid PCIe channels twice; The detection unit at the second end determines whether the second end enters the polling phase of link training by detecting the number of valid PCIe channels twice, wherein the number of valid PCIe channels is the number of PCIe channels in which the common-mode input impedance change is detected by the detection unit at the first end and / or the detection unit at the second end.

9. The PCIe extension cable according to claim 8, characterized in that: In response to the two common-mode input impedance change times detected by the detection unit of the first end being consistent, the first end enters a polling phase of link training; In response to the two common-mode input impedance change times detected by the detection unit of the first end being inconsistent, the first end enters a detection silence phase of link training; in response to the two common-mode input impedance change times detected by the detection unit of the second end being consistent, the second end enters a polling phase of link training in a polling phase; In response to the inconsistency in the time of the two common-mode input impedance changes detected by the detection unit of the second end, the second end enters the detection silence phase of link training; wherein, the detection silence phase is a low power consumption state when the PCIe extension line is in no data transmission.

10. A signal transmission method for a PCIe extension line, comprising: In response to the first end of the cable being connected to the initiator, the first end enables the initiator to detect that the target (Target) is connected during a detection phase of a link training process according to the PCIe protocol and enter a polling phase of the link training; The first end converts the differential signal received from the differential signal pair for receiving into an optical signal, and transmits the optical signal to the optoelectronic module of the second end through the optical fiber; In response to the second end of the cable being connected to the target (Target), the second end enables the target (Target) to detect that the initiator has been connected during a detection phase of a link training process according to the PCIe protocol and enter a polling phase of the link training; The second end converts the differential signal received from the differential signal pair for transmission into an optical signal, and transmits it to the optoelectronic module of the first end through the optical fiber; In response to the first end detecting that the initiator has been connected, the first end converts the optical signal received from the optical fiber into a differential signal, which is transmitted by the optical fiber to the differential signal pair for transmission at the second end; In response to the second end detecting that the target (Target) has been connected, the second end converts the optical signal received from the optical fiber into a differential signal, which is transmitted by the optical fiber to the differential signal pair for sending at the second end.

11. The signal transmission method of the PCIe extension line according to claim 10, characterized in that: In response to the first end causing the initiator to detect a first common-mode input impedance change during the detection phase of the link training process and the first end detecting a third common-mode input impedance change, the current path is a valid PCIe path; In response to the first end causing the initiator not to detect a first common-mode input impedance change during a detection phase of a link training process or the first end not to detect a third common-mode input impedance change, the current PCIe channel is invalid, and the initiator and the first end enter a detection silent phase of link training; In response to the second end causing the target (Target) to detect a second common-mode input impedance change during the detection phase of the link training process and the second end detecting a fourth common-mode input impedance change, the current path is a valid PCIe path; in response to the second end causing the target (Target) not to detect a second common-mode input impedance change during the detection phase of the link training process or the second end not detecting a fourth common-mode input impedance change, the current path is an invalid PCIe path, and the target (Target) and the second end enter a detection silence phase of link training.

12. The signal transmission method of the PCIe extension line according to claim 11, characterized in that: In response to the two detected numbers of valid PCIe channels being consistent, the first end enters a polling phase of link training; In response to the two detected valid PCIe channel numbers being inconsistent, the first end enters a detection silent phase of link training; In response to the two detected numbers of valid PCIe channels being consistent, the second end enters a polling phase of link training; In response to the two detected valid PCIe channel numbers being inconsistent, the second end enters a detection silent phase of link training.

13. The signal transmission method of the PCIe extension cable according to any one of claims 10 to 12, characterized in that: In response to the first end and the second end entering a polling phase, the first end receives a first sequence and sends the first sequence to the second end; In response to the second end receiving the second sequence, the second end receives a third sequence from the target and sends the third sequence to the first end; In response to the first sequence, the second sequence, and the third sequence satisfying a judgment criterion, entering a configuration polling phase of the polling phase; In response to the first sequence, the second sequence or the third sequence not satisfying the judgment criteria, entering the compliance polling phase of the polling phase; wherein the configuration polling means that the polling behavior has been configured or set, and the compliance polling means that the polling behavior complies with specific power management specifications or standards.

14. The signal transmission method of the PCIe extension line according to claim 13, characterized in that: In response to entering a compliance polling phase of the polling phase, the first end receives a first sequence and sends the first sequence to the second end; In response to the second end receiving the second sequence, the second end receives a third sequence from the target and outputs the third sequence to the first end; In response to the first sequence, the second sequence or the third sequence satisfying the judgment criterion, entering a configuration polling phase of the polling phase; In response to the first sequence, the second sequence or the third sequence not satisfying the judgment criterion, entering the detection activation phase of link training; wherein the detection activation phase is a high power consumption state when the PCIe extension line is in data transmission or communication is required.

15. The signal transmission method of the PCIe extension cable according to any one of claims 10 to 14, characterized in that: In response to entering the detection activation phase of the link training, and the number of valid PCIe channels of the first end is consistent with the number of valid PCIe channels of the second end, the first end communicates normally with the second end; In response to entering the detection activation phase of the link training and the number of valid PCIe channels at the first end being inconsistent with the number of valid PCIe channels at the second end, entering the link communication detection silence.

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