Channel switching method based on FPGA multi-channel data communication and FPGA

Abstract

The invention belongs to the field of data communication, and particularly discloses a channel switching method based on FPGA multi-channel data communication and an FPGA. According to the method and the device, on the premise that all links are connected, when the FPGA serves as a receiving end and the first area of the local cache is not full, the CPU is started to write data to the first area of the local cache, and otherwise, the CPU is stopped to write data to the first area of the local cache; when the local cache first area is not empty, the service board corresponding to the channel number reads data from the local cache first area; when the service board serves as a sending end and a second local cache area is not full, which channel is occupied is judged by polling different channel numbers, and the service board corresponding to the channel writes data to the second local cache area, otherwise, the service board corresponding to the current channel is suspended to write data to the second local cache area; and when the local cache second area is not empty, the CPU reads data from the local cache second area. Caching of multi-channel data and channel switching polling are achieved through the FPGA, and the problems that the number of interfaces is small, the communication protocol is single, and the rate is fixed are effectively solved.

Description

Technical Field

[0001] The present application belongs to the field of data communication, and more specifically, to a channel switching method and FPGA based on FPGA multi-channel data communication. Background Art

[0002] In the fields of network communication, industrial control, data transmission, etc., multi-channel data communication is converged on a certain processor and is widely used in these fields. In some communication scenarios, there is a controller that controls the data processing function of multiple services, but due to the interface limitations of the chip itself, it is impossible to have the characteristics of multiple data channels. Therefore, multiple channels are converged to one bus and transmitted to the controller for processing, and the data protocols, communication rates, etc. of the multiple channels may be different. Summary of the invention

[0003] In view of the defects of the prior art, the purpose of this application is to provide a channel switching method and FPGA based on FPGA multi-channel data communication, aiming to solve the problems of few interfaces, single communication protocol and fixed communication rate limited by processor chips.

[0004] To achieve the above objectives, in a first aspect, the present application provides a channel switching method based on FPGA multi-channel data communication, wherein the FPGA is used as a receiving end, one side of which communicates with a CPU, and the other side of which communicates with a multi-channel service board, and the method comprises:

[0005] S1. Check whether the links between FPGA and CPU and the links between FPGA and all business boards are all connected. If so, go to S2. Otherwise, continue to check the link connection status.

[0006] S2. When the first area of ​​the FPGA local cache is not full, the CPU is enabled to write data to the first area of ​​the FPGA local cache. Otherwise, the CPU is paused from writing data to the first area of ​​the FPGA local cache. When the first area of ​​the FPGA local cache is not empty, the business board corresponding to the channel number reads data from the first area of ​​the FPGA local cache.

[0007] Preferably, when the first area of ​​the FPGA local cache is not full, the CPU is enabled to write data to the first area of ​​the FPGA local cache, otherwise, the CPU is suspended from writing data to the first area of ​​the FPGA local cache, as follows:

[0008] S21. If it is detected that the first area of ​​the FPGA local cache is not full, the link ready signal for communicating with the CPU is pulled high so that the CPU starts writing data to the FPGA after detecting the signal, and enters S22. Otherwise, the link ready signal for communicating with the CPU is pulled low so that the CPU stops writing data to the FPGA after detecting the signal;

[0009] S22. When receiving the data written by the CPU to the FPGA, store it in the first area of ​​the FPGA local cache.

[0010] Preferably, when the first area of ​​the FPGA local cache is not empty, the service board corresponding to the channel number reads data from the first area of ​​the FPGA local cache as follows:

[0011] When receiving data written by the CPU to the FPGA, the channel number in the data is detected;

[0012] When the first area of ​​the FPGA local cache is not empty, data is read from the first area of ​​the FPGA local cache in sequence according to the detected channel number and sent to the service board corresponding to the channel.

[0013] To achieve the above purpose, in a second aspect, the present application provides a channel switching method based on FPGA multi-channel data communication, wherein the FPGA acts as a transmitting end, one side of the FPGA communicates with the CPU, and the other side of the FPGA communicates with a multi-channel service board, and the method includes:

[0014] T1. Check whether the links between FPGA and CPU and the links between FPGA and all business boards are all connected. If so, proceed to T2. Otherwise, continue to check the link connection status.

[0015] T2. When the second area of ​​the FPGA local cache is not full, it is determined which channel is occupied by polling different channel numbers, and the business board corresponding to the channel writes data to the second area of ​​the FPGA local cache. Otherwise, the business board corresponding to the current channel is suspended from writing data to the second area of ​​the FPGA local cache. When the second area of ​​the FPGA local cache is not empty, the CPU reads data from the second area of ​​the FPGA local cache.

[0016] Preferably, the method of determining which channel is occupied by polling different channel numbers, and the service board corresponding to the channel writes data to the second area of ​​the FPGA local cache, is specifically as follows:

[0017] (1) Pull up the ready signal of the communication link with the service board in the order of channel numbers;

[0018] (2) At the same time, check whether the channel has a data frame being sent. If not, increase the channel number by one and go to (1). If yes, store the sent data frame into the second area of ​​the FPGA local cache.

[0019] Preferably, step (2) is as follows:

[0020] (21) If it is detected that the communication interface of the current channel has a data frame to send, and if the second area of ​​the FPGA local cache is not full, the ready signal of the current channel is pulled high, and the ready signals of other channels are pulled low at the same time, so as to suspend data transmission of other channels;

[0021] (22) Detect whether there is a data frame sent on the current channel within two cycles. If yes, occupy the channel and enter (23); if no, release the right to occupy the channel, increase the current channel number by one, and enter (21);

[0022] (23) The received data frame is stored in the second area of ​​the FPGA local cache. During the normal data frame sending process of the current channel, the frame structure of the data frame sent on the current channel is detected in real time to see if it is complete. If so, enter (22). Otherwise, if the frame end signal is not detected, an end signal of the frame is generated, the self-healing state is entered, the current data frame is discarded, and enter (22). If the frame end signal is not detected within more than 2500 cycles or any signal of the data frame is not detected within one millisecond, exit the current channel, increase the channel number by one, and enter (21).

[0023] Preferably, when the second area of ​​the FPGA local cache is not empty, the CPU reads data from the second area of ​​the FPGA local cache, specifically as follows:

[0024] Determine whether the second area of ​​the FPGA local cache is not empty and the link ready signal communicating with the CPU is high. If so, read data from the second area of ​​the FPGA local cache and send it to the CPU; otherwise, continue waiting.

[0025] To achieve the above objectives, in a third aspect, the present application provides an FPGA, comprising at least one processor and at least one memory;

[0026] The at least one memory is used to store computer instructions;

[0027] The at least one processor is used to execute at least part of the computer instructions to implement the channel switching method described in the first aspect or the second aspect.

[0028] Preferably, the FPGA communicates with the CPU via RGMII, and communicates with multiple service boards via multiple AURORA buses.

[0029] In general, the above technical solutions conceived by this application have the following beneficial effects compared with the prior art:

[0030] The present application proposes a channel switching method and FPGA based on FPGA multi-channel data communication. Under the premise that the link communicating with the CPU and the link communicating with all business boards are fully connected, when the FPGA located between the CPU and the multi-channel business board is used as the receiving end, when the first area of ​​the FPGA local cache is not full, the CPU is enabled to write data to the first area of ​​the FPGA local cache, otherwise, the CPU is suspended from writing data to the first area of ​​the FPGA local cache; when the first area of ​​the FPGA local cache is not empty, the business board corresponding to the channel number reads data from the first area of ​​the FPGA local cache; when the FPGA located between the CPU and the multi-channel business board is used as the sending end, when the second area of ​​the FPGA local cache is not full, by polling different channel numbers, it is determined which channel is occupied, and the business board corresponding to the channel writes data to the second area of ​​the FPGA local cache, otherwise, the business board corresponding to the current channel writes data to the second area of ​​the FPGA local cache; when the second area of ​​the FPGA local cache is not empty, the CPU reads data from the second area of ​​the FPGA local cache. The caching of multi-channel data and the channel switching polling function are realized in the FPGA, which effectively solves the problem that some processor chips have few interfaces themselves, but need to perform multi-channel data communication and each communication protocol and rate have different communication modes. Compared with traditional communication modes, it is flexible and programmable, and can effectively solve problems such as the limited number of interfaces, single communication protocol, and fixed communication rate of processor chips, greatly improving feasibility and R&D efficiency, increasing success rate and saving project costs. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] Figure 1 It is a block diagram of the hardware system structure provided in the embodiment of the present application.

[0032] Figure 2 This is the multi-channel data frame format provided in the embodiment of the present application.

[0033] Figure 3 It is a flow chart of a channel switching method for multi-channel data communication when the FPGA provided in an embodiment of the present application is used as a receiving end.

[0034] Figure 4 It is a flow chart of a channel switching method for multi-channel data communication when the FPGA provided in an embodiment of the present application is used as a transmitting end.

[0035] Figure 5 This is the working process of the multi-channel FPGA transmitting end channel switching state machine provided in the embodiment of the present application. DETAILED DESCRIPTION

[0036] In order to make the purpose, technical solution and advantages of the present application more clearly understood, the present application is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and are not used to limit the present application.

[0037] The term "and / or" in this article is a description of the association relationship of associated objects, indicating that there can be three relationships. For example, A and / or B can represent: A exists alone, A and B exist at the same time, and B exists alone. The symbol " / " in this article indicates that the associated objects are in an or relationship, for example, A / B means A or B.

[0038] The terms "first" and "second" in the specification and claims herein are used to distinguish different objects rather than to describe a specific order of the objects. For example, a first response message and a second response message are used to distinguish different response messages rather than to describe a specific order of the response messages.

[0039] In the embodiments of the present application, words such as "exemplary" or "for example" are used to indicate examples, illustrations or descriptions. Any embodiment or design described as "exemplary" or "for example" in the embodiments of the present application should not be interpreted as being more preferred or more advantageous than other embodiments or designs. Specifically, the use of words such as "exemplary" or "for example" is intended to present related concepts in a specific way.

[0040] In the description of the embodiments of the present application, unless otherwise specified, "multiple" means two or more than two. For example, multiple processing units refer to two or more processing units, etc.; multiple elements refer to two or more elements, etc.

[0041] Next, the technical solutions provided in the embodiments of the present application are introduced.

[0042] In order to solve the problem of one-to-one multi-channel data communication due to the limitation of the number of interfaces of some processors, and to meet the communication requirements of special scenarios where multi-channel data communication and the characteristics of the processor chip itself are limited, this application utilizes the programmable characteristics of FPGA to expand the communication rates of any channel and different buses at any time by modifying the FPGA logic when the printed circuit board has been produced, and implements multi-channel data switching technology to achieve the above functions. Utilizing the rich interface and programmable characteristics of FPGA, N-channel channel polling arbitration, abnormal exit and self-healing of channels, data caching and other functions are implemented in FPGA. At the same time, the data of each channel is monitored by JTAG debugging means, which improves the reliability and monitorability of multi-channel serial ports. In summary, this application has the advantages of high reliability, flexibility, low cost, and multi-channel switching that meets different needs in different scenarios.

[0043] On the one hand, the present application provides a channel switching method based on FPGA multi-channel data communication, wherein the FPGA is used as a receiving end, one side communicates with the CPU, and the other side communicates with a multi-channel service board, and the method includes:

[0044] S1. Check whether the links between FPGA and CPU and the links between FPGA and all business boards are all connected. If so, go to S2. Otherwise, continue to check the link connection status.

[0045] S2. When the first area of ​​the FPGA local cache is not full, the CPU is enabled to write data to the first area of ​​the FPGA local cache. Otherwise, the CPU is paused from writing data to the first area of ​​the FPGA local cache. When the first area of ​​the FPGA local cache is not empty, the business board corresponding to the channel number reads data from the first area of ​​the FPGA local cache.

[0046] Preferably, when the first area of ​​the FPGA local cache is not full, the CPU is enabled to write data to the first area of ​​the FPGA local cache, otherwise, the CPU is suspended from writing data to the first area of ​​the FPGA local cache, as follows:

[0047] S21. If it is detected that the first area of ​​the FPGA local cache is not full, the link ready signal for communicating with the CPU is pulled high so that the CPU starts writing data to the FPGA after detecting the signal, and enters S22. Otherwise, the link ready signal for communicating with the CPU is pulled low so that the CPU stops writing data to the FPGA after detecting the signal;

[0048] S22. When receiving the data written by the CPU to the FPGA, store it in the first area of ​​the FPGA local cache.

[0049] Preferably, when the first area of ​​the FPGA local cache is not empty, the service board corresponding to the channel number reads data from the first area of ​​the FPGA local cache as follows:

[0050] When receiving data written by the CPU to the FPGA, the channel number in the data is detected;

[0051] When the first area of ​​the FPGA local cache is not empty, data is read from the first area of ​​the FPGA local cache in sequence according to the detected channel number and sent to the service board corresponding to the channel.

[0052] On the other hand, the present application provides a channel switching method based on FPGA multi-channel data communication, wherein the FPGA acts as a transmitting end, one side of the FPGA communicates with the CPU, and the other side of the FPGA communicates with a multi-channel service board, and the method includes:

[0053] T1. Check whether the links between FPGA and CPU and the links between FPGA and all business boards are all connected. If so, proceed to T2. Otherwise, continue to check the link connection status.

[0054] T2. When the second area of ​​the FPGA local cache is not full, it is determined which channel is occupied by polling different channel numbers, and the business board corresponding to the channel writes data to the second area of ​​the FPGA local cache. Otherwise, the business board corresponding to the current channel is suspended from writing data to the second area of ​​the FPGA local cache. When the second area of ​​the FPGA local cache is not empty, the CPU reads data from the second area of ​​the FPGA local cache.

[0055] Preferably, the method of determining which channel is occupied by polling different channel numbers, and the service board corresponding to the channel writes data to the second area of ​​the FPGA local cache, is specifically as follows:

[0056] (1) Pull up the ready signal of the communication link with the service board in the order of channel numbers;

[0057] (2) At the same time, check whether the channel has a data frame being sent. If not, increase the channel number by one and go to (1). If yes, store the sent data frame into the second area of ​​the FPGA local cache.

[0058] Preferably, step (2) is as follows:

[0059] (21) If it is detected that the communication interface of the current channel has a data frame to send, and if the second area of ​​the FPGA local cache is not full, the ready signal of the current channel is pulled high, and the ready signals of other channels are pulled low at the same time, so as to suspend data transmission of other channels;

[0060] (22) Detect whether there is a data frame sent on the current channel within two cycles. If yes, occupy the channel and enter (23); if no, release the right to occupy the channel, increase the current channel number by one, and enter (21);

[0061] (23) The received data frame is stored in the second area of ​​the FPGA local cache. During the normal data frame sending process of the current channel, the frame structure of the data frame sent on the current channel is detected in real time to see if it is complete. If so, enter (22). Otherwise, if the frame end signal is not detected, an end signal of the frame is generated, the self-healing state is entered, the current data frame is discarded, and enter (22). If the frame end signal is not detected within more than 2500 cycles or any signal of the data frame is not detected within one millisecond, exit the current channel, increase the channel number by one, and enter (21).

[0062] Preferably, when the second area of ​​the FPGA local cache is not empty, the CPU reads data from the second area of ​​the FPGA local cache, specifically as follows:

[0063] Determine whether the second area of ​​the FPGA local cache is not empty and the link ready signal communicating with the CPU is high. If so, read data from the second area of ​​the FPGA local cache and send it to the CPU; otherwise, continue waiting.

[0064] Example

[0065] In this embodiment, the CPU communicates with the FPGA via the RGMII bus, and the FPGA communicates data with the multi-channel service board via the AURORA bus, thereby implementing multi-channel data caching and channel switching polling functions in the FPGA.

[0066] After the hardware is ready, the specific implementation is divided into the following steps:

[0067] 1. After power-on, the CPU loads its firmware and the FPGA loads its firmware. In the entire multi-channel switching data process, the data format is as follows Figure 2 As shown in the figure, it consists of a frame header, frame tail, frame valid, data, etc. Among them, data_eof represents the frame tail indication signal of the data frame. The signal changes from low level to high level to mark the last bit of a frame of data. Its waveform Figure 2 As shown in the figure, data_sof indicates the frame header indication signal of the data frame. The signal changes from low level to high level to mark the first bit of a frame of data. Figure 2 As shown in . data indicates the data bit in the data frame transmitted on the channel. data_valid indicates the data valid indication signal in the data frame. A high level indicates that the data bit is valid, and a low level indicates that the data bit is invalid.

[0068] like Figure 3 As shown in the figure, after the CPU completes its initialization, the FPGA starts to detect the RGMII and AURORA link status. If the link is not fully connected, it continues to wait for the link status to be detected. If the link is fully connected, the empty and full flags of the local cache FIFO_RX at the FPGA receiving end are detected. If the local cache FIFO_RX empty and full flags are full, the rgmii_ready signal of RGMII is pulled down, and the main controller is suspended from sending data to the slave processor FPGA through RGMII. If the local cache FIFO_RX empty and full flags are not full, the rgmii_ready signal of RGMII is pulled up, and the main controller CPU starts sending data.

[0069] The slave controller receives the data sent by the main controller through RGMII, detects the channel number in the data, and stores the data in the local cache FIFO_RX. It also starts the corresponding channel read and write control signal to read the cache data from the local cache FIFO, and sends it to the corresponding business board through AURORA. Before reading the data in the local cache FIFO_RX, it is necessary to detect the empty and full flag of FIFO_RX. If FIFO_RX is empty, the data cannot be read. The data in FIFO_RX can be read and sent to the corresponding channel only when FIFO_RX is not empty. Figure 3As shown, the entire multi-channel switching receiving end workflow is completed.

[0070] like Figure 4 As shown, the slave processor FPGA detects that the link status of AURORA and RGMII is good. When the local cache FIFO_TX empty and full flag is not full, AURORA pulls up the aurora_ready signal in the order of the channel number, and detects whether the channel has data frames being sent. If no data frame is detected, the channel number is increased by one, and the next channel is polled to continue to detect whether there are data frames being sent. If a data frame is sent, the sent data frame is stored in the local cache FIFO_TX. When the send rgmii_ready of RGMII is high, the data is read from the local cache FIFO_TX and sent to the main controller CPU through RGMII for processing. If the send rgmii_ready of RGMII is low, continue to wait. If the local cache FIFO_TX empty and full flag is full, the aurora_ready signal of AURORA of the channel can be pulled down to suspend the channel from continuing to send data frames. When the local cache data FIFO_TX is not full, the sending of the channel is started. As shown Figure 4 As shown in the figure, the entire multi-channel transmitter workflow is completed. Through this channel switching, the function of sending multi-channel service data from the processor FPGA to the RGMII of the main processor CPU is realized.

[0071] like Figure 5 As shown, the working process of the channel switching state machine of the multi-channel transmitting end from the processor FPGA is as follows: detect whether the AURORA interface of the current channel has data frames to send, and when the local cache FIFO_TX is not full, pull up the AURORA of the current channel to send the aurora_ready signal, and at the same time pull down the aurora_ready signal of other channels, suspend the data transmission of other channels, and detect whether there are data frames to be sent on the current channel within two cycles. If there are data frames to be sent, occupy the channel, store the received data frames in the local cache FIFO_TX, and read the RGMII bus for data transmission to the main controller CPU for processing, so as to realize the function of sending data from multiple channels to one channel; if no data frame is detected within two cycles, release the occupancy right of the channel, increase the current channel number by one, switch to the next channel for detection, and repeat the above detection state.

[0072] Normal transmission of data frames in the current channel may also cause abnormalities, requiring the state machine to perform self-healing processing. If during normal data frame transmission in the current channel, a valid frame signal and a frame start signal are detected, but a frame end signal is not detected; a frame start signal is not detected for more than 2500 cycles (the number of cycles depends on the maximum length of the data frame, which can be slightly larger than the maximum length of the data frame); no signal of the data frame is detected within one millisecond (the time depends on the maximum time interval between data frames, which can be larger than the interval), etc., the slave processor FPGA enters the self-healing state, generates a frame end signal, discards the current data, exits the current channel, increases the channel number by one, and enters the next channel polling. If the data frame is discarded, the data frame can be retransmitted the next time the channel is polled.

[0073] It can be understood that the detailed functional implementation of each of the above-mentioned units / modules can be found in the introduction of the aforementioned method embodiment, and will not be repeated here.

[0074] It should be understood that the above-mentioned device is used to execute the method in the above-mentioned embodiment. The implementation principle and technical effect of the corresponding program module in the device are similar to those described in the above-mentioned method. The working process of the device can refer to the corresponding process in the above-mentioned method, which will not be repeated here.

[0075] Based on the method in the above embodiment, an embodiment of the present application provides a computer-readable storage medium, which stores a computer program. When the computer program runs on a processor, the processor executes the method in the above embodiment.

[0076] Based on the method in the above embodiment, an embodiment of the present application provides a computer program product. When the computer program product runs on a processor, the processor executes the method in the above embodiment.

[0077] It is understandable that the processor in the embodiment of the present application can be a central processing unit (CPU), or other general-purpose processors, digital signal processors (DSP), application specific integrated circuits (ASIC), field programmable gate arrays (FPGA) or other programmable logic devices, transistor logic devices, hardware components or any combination thereof. The general-purpose processor can be a microprocessor or any conventional processor.

[0078] The method steps in the embodiments of the present application can be implemented by hardware or by a processor executing software instructions. The software instructions can be composed of corresponding software modules, and the software modules can be stored in random access memory (RAM), flash memory, read-only memory (ROM), programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), registers, hard disks, mobile hard disks, CD-ROMs, or any other form of storage medium known in the art. An exemplary storage medium is coupled to a processor so that the processor can read information from the storage medium and write information to the storage medium. Of course, the storage medium can also be a component of the processor. The processor and the storage medium can be located in an ASIC.

[0079] In the above embodiments, it can be implemented in whole or in part by software, hardware, firmware or any combination thereof. When implemented using software, it can be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on a computer, the process or function described in the embodiment of the present application is generated in whole or in part. The computer may be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. The computer instructions may be stored in a computer-readable storage medium or transmitted through the computer-readable storage medium. The computer instructions may be transmitted from a website site, a computer, a server or a data center to another website site, a computer, a server or a data center by wired (e.g., coaxial cable, optical fiber, digital subscriber line (DSL)) or wireless (e.g., infrared, wireless, microwave, etc.) means. The computer-readable storage medium may be any available medium that a computer can access or a data storage device such as a server or a data center that includes one or more available media integrated. The available medium may be a magnetic medium (e.g., a floppy disk, a hard disk, a tape), an optical medium (e.g., a DVD), or a semiconductor medium (e.g., a solid state disk (SSD)), etc.

[0080] It should be understood that the various numerical numbers involved in the embodiments of the present application are only used for the convenience of description and are not used to limit the scope of the embodiments of the present application.

[0081] It will be easily understood by those skilled in the art that the above description is only a preferred embodiment of the present application and is not intended to limit the present application. Any modifications, equivalent substitutions and improvements made within the spirit and principles of the present application shall be included in the scope of protection of the present application.

Claims

1. A channel switching method based on FPGA multi-channel data communication, characterized in that: The FPGA is used as a receiving end, one side of which communicates with the CPU, and the other side of which communicates with the multi-channel service board. The method includes: S1. Check whether the links between FPGA and CPU and the links between FPGA and all business boards are all connected. If so, go to S2. Otherwise, continue to check the link connection status. S2. When the first area of ​​the FPGA local cache is not full, the CPU is enabled to write data to the first area of ​​the FPGA local cache. Otherwise, the CPU is paused from writing data to the first area of ​​the FPGA local cache. When the first area of ​​the FPGA local cache is not empty, the business board corresponding to the channel number reads data from the first area of ​​the FPGA local cache.

2. The channel switching method according to claim 1, characterized in that: When the first area of ​​the FPGA local cache is not full, the CPU is enabled to write data to the first area of ​​the FPGA local cache. Otherwise, the CPU is suspended from writing data to the first area of ​​the FPGA local cache. Specifically, as follows: S21. If it is detected that the first area of ​​the FPGA local cache is not full, the link ready signal for communicating with the CPU is pulled high so that the CPU starts writing data to the FPGA after detecting the signal, and enters S22. Otherwise, the link ready signal for communicating with the CPU is pulled low so that the CPU stops writing data to the FPGA after detecting the signal; S22. When receiving the data written by the CPU to the FPGA, store it in the first area of ​​the FPGA local cache.

3. The channel switching method according to claim 1, characterized in that: When the first area of ​​the FPGA local cache is not empty, the service board corresponding to the channel number reads data from the first area of ​​the FPGA local cache as follows: When receiving data written by the CPU to the FPGA, the channel number in the data is detected; When the first area of ​​the FPGA local cache is not empty, data is read from the first area of ​​the FPGA local cache in sequence according to the detected channel number and sent to the service board corresponding to the channel.

4. A channel switching method based on FPGA multi-channel data communication, characterized in that: The FPGA is used as a transmitting end, one side of which communicates with the CPU, and the other side of which communicates with a multi-channel service board. The method includes: T1. Check whether the links between FPGA and CPU and the links between FPGA and all business boards are all connected. If so, proceed to T2. Otherwise, continue to check the link connection status. T2. When the second area of ​​the FPGA local cache is not full, it is determined which channel is occupied by polling different channel numbers, and the business board corresponding to the channel writes data to the second area of ​​the FPGA local cache. Otherwise, the business board corresponding to the current channel is suspended from writing data to the second area of ​​the FPGA local cache. When the second area of ​​the FPGA local cache is not empty, the CPU reads data from the second area of ​​the FPGA local cache.

5. The channel switching method according to claim 4, characterized in that: The decision of which channel is occupied is made by polling different channel numbers, and the service board corresponding to the channel writes data to the second area of ​​the FPGA local cache, as follows: (1) Pull up the ready signal of the communication link with the service board in the order of channel numbers; (2) At the same time, check whether the channel has a data frame being sent. If not, increase the channel number by one and go to (1). If yes, store the sent data frame into the second area of ​​the FPGA local cache.

6. The channel switching method according to claim 5, characterized in that: Step (2) is as follows: (21) If it is detected that the communication interface of the current channel has a data frame to send, and if the second area of ​​the FPGA local cache is not full, the ready signal of the current channel is pulled high, and the ready signals of other channels are pulled low at the same time, so as to suspend data transmission of other channels; (22) Detect whether there is a data frame sent on the current channel within two cycles. If yes, occupy the channel and enter (23); If not, release the occupancy right of the channel, increase the current channel number by one, and enter (21); (23) The received data frame is stored in the second area of ​​the FPGA local cache. During the normal data frame sending process of the current channel, the frame structure of the data frame sent on the current channel is detected in real time to see if it is complete. If so, enter (22). Otherwise, if the frame end signal is not detected, an end signal of the frame is generated, the self-healing state is entered, the current data frame is discarded, and enter (22). If the frame end signal is not detected within more than 2500 cycles or any signal of the data frame is not detected within one millisecond, exit the current channel, increase the channel number by one, and enter (21).

7. The channel switching method according to claim 4, characterized in that: When the second area of ​​the FPGA local cache is not empty, the CPU reads data from the second area of ​​the FPGA local cache, as follows: Determine whether the second area of ​​the FPGA local cache is not empty and the link ready signal communicating with the CPU is high. If so, read data from the second area of ​​the FPGA local cache and send it to the CPU; otherwise, continue waiting.

8. An FPGA, characterized in that: comprising at least one processor and at least one memory; The at least one memory is used to store computer instructions; The at least one processor is used to execute at least part of the computer instructions to implement the channel switching method according to any one of claims 1 to 7.

9. The FPGA according to claim 8, wherein: The FPGA communicates with the CPU via RGMII and communicates with multiple service boards via multiple AURORA buses.

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