Reconfigurable computing array, reconfiguration controller architecture, chip and reconfigurable computing method

Abstract

The application discloses a reconfigurable computing array, a reconfiguration controller architecture, a chip and a reconfigurable computing method, comprising a master control module, a state machine module, a computing decoder module, a memory access resource controller module, a reconfiguration controller module, a reconfigurable computing array, an input buffer module and an output buffer module; the state machine module controls the whole reconfigurable computing process through state switching; the reconfiguration controller module configures the connection mode of the PE unit in the reconfigurable computing array according to the decoding result of the computing decoder module, and realizes multiple computing functions to complete different types of data computing tasks. The application dynamically configures multiple computing units in the reconfigurable computing array, so that the hardware architecture can be adjusted in real time according to different algorithm requirements, the reconfigurable computing array is accurately configured to complete different computing tasks, and special hardware does not need to be designed for each task, so that the flexibility of chip configuration is improved and the resource utilization rate is improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of computer architecture, in particular to a reconfigurable computing array, a reconfiguration controller architecture, a chip and a reconfigurable computing method. BACKGROUND

[0002] DSP algorithms are widely used in various fields, such as modulation and demodulation in communication systems, noise reduction in audio processing, filtering in image processing, etc. Since DSP chips have programmable ability, allowing processing algorithms to be adjusted as needed, and being able to perform complex operations at extremely high speed, DSP chips play a crucial role in these applications. Traditional DSP chips usually use fixed hardware architecture and preset operation units, lack of computing flexibility, and cannot meet the requirements of new algorithm and performance optimization. When processing complex and diversified digital signal processing algorithms, reprogramming and resource configuration are required, resulting in low resource utilization and low design efficiency of the chip.

[0003] A patent with publication number CN102799563B discloses a reconfigurable computing array and a construction method, including a preset number of single cores and an interconnection module, wherein any single core includes a reconfigurable computing module, a reconfigurable storage module, a reconfigurable control logic module and a configuration module. The reconfigurable computing module, the reconfigurable storage module and the reconfigurable control logic module are constructed with reference to the hardware structure of the basic algorithm core set contained in a certain application set. The preset number of single cores can support all basic algorithm cores contained in the application set. The interconnection module interconnects the preset number of single cores with reference to the hardware implementation of each application in the application set based on the basic algorithm core set.

[0004] The above patents all have the problems raised in the background: using fixed hardware architecture and preset operation units, lack of computing flexibility, unable to meet the requirements of new algorithm and performance optimization, and requiring reprogramming and resource configuration when processing complex and diversified digital signal processing algorithms, resulting in low resource utilization and low design efficiency of the chip. To solve these problems, the present application proposes a reconfigurable computing array, a reconfiguration controller architecture, a chip and a reconfigurable computing method. SUMMARY

[0005] In view of the deficiencies of the prior art, the main purpose of the present application is to provide a reconfigurable computing array, a reconfiguration controller architecture, a chip and a reconfigurable computing method, which can effectively solve the problems in the background. The specific technical solutions of the present application are as follows:

[0006] A reconfigurable computing array, comprising:

[0007] The single-precision array implements multiple operation functions of real numbers and complex numbers according to reconstruction interconnections among multiple PE calculation units, wherein the reconstruction interconnection manners in the real number mode and the complex number mode are completely same.

[0008] The double-precision array implements multiple operation functions according to reconstruction interconnections among multiple calculation units.

[0009] The MUX selects the connection manner among different calculation units according to a preset configuration manner, so that the reconfigurable calculation array can adapt to multiple calculation tasks by integrating common operators of different algorithms and combining a unified input / output buffer.

[0010] Specifically, the single-precision array and the double-precision array include:

[0011] The single-precision array includes multiple 1 / 2PE units and a multiply-add bypass, the 1 / 2PE unit is composed of a complex adder, a comparator and a complex multiplier, and the multiply-add bypass is composed of a complex multiplier, a complex adder and a divider.

[0012] The double-precision array is composed of a double-precision comparator unit, a double-precision adder unit, a double-precision multiply-add unit and a double-precision divider unit.

[0013] A reconfigurable calculation method is used to configure the reconfigurable calculation array, including:

[0014] The single-precision array implements multiply-accumulate operation, multiply-add operation and multiply-subtract operation through the reconstruction manner of PE internal reconstruction.

[0015] The single-precision array implements comparison tree operation, accumulation tree operation, multiply-accumulate tree operation and mean accumulation tree operation through the reconstruction manner of PE inter-reconstruction.

[0016] The double-precision array implements double-precision addition operation, double-precision subtraction operation, double-precision multiplication operation, double-precision division operation, double-precision comparison operation, double-precision multiply-accumulate operation and double-precision accumulation operation through the reconstruction interconnection among the double-precision comparator unit, the double-precision adder unit, the double-precision multiply-add unit and the double-precision divider unit.

[0017] Specifically, the single-precision array implements multiply-accumulate operation, multiply-add operation and multiply-subtract operation through the reconstruction manner of PE internal reconstruction, including:

[0018] In each 1 / 2PE unit, a complex multiplier and two complex adders are interconnected to implement multiply-accumulate operation, the complex multiplier performs multiplication calculation on input data to obtain a first result, the first result is input into a first complex adder to obtain an accumulation result, and the accumulation result and the first result are input into a second complex adder to obtain a multiply-accumulate calculation result.

[0019] In each 1 / 2PE unit, a multiplication-addition operation and a multiplication-subtraction operation are implemented by interconnecting a complex multiplier and a complex adder, the complex multiplier performs multiplication calculation on input data to obtain a multiplication calculation result, and the complex adder inputs the multiplication calculation result and the input data to perform calculation to obtain a multiplication-addition or multiplication-subtraction calculation result.

[0020] Specifically, the reconstruction mode of reconstructing the single-precision array through the inter-PE reconstruction to implement the comparison tree operation, the accumulation tree operation, the multiplication-accumulation tree operation, and the mean accumulation tree operation includes:

[0021] The comparison tree operation is implemented by interconnecting a plurality of comparators between each 1 / 2PE unit, the comparators perform comparison on input data to obtain a comparison result, and the comparison result is input into a next comparator to perform comparison to obtain a final comparison result.

[0022] The accumulation tree operation is implemented by interconnecting a plurality of complex adders of each 1 / 2PE unit and a plurality of complex adders of a multiplication-addition bypass, two 1 / 2PE units perform accumulation calculation through the plurality of complex adders to obtain a first 1 / 2PE unit accumulation result and a second 1 / 2PE unit accumulation result, and the first 1 / 2PE unit accumulation result and the second 1 / 2PE unit accumulation result are input into the complex adders in the multiplication-addition bypass to perform calculation to obtain a final accumulation tree calculation result.

[0023] The multiplication-accumulation tree operation is implemented by interconnecting a plurality of complex multipliers and complex adders of each 1 / 2PE unit and a plurality of complex adders of a multiplication-addition bypass, two 1 / 2PE units perform accumulation calculation by inputting the calculation result of the complex multiplier into the plurality of complex adders to obtain a first 1 / 2PE unit multiplication-accumulation result and a second 1 / 2PE unit multiplication-accumulation result, and the first 1 / 2PE unit multiplication-accumulation result and the second 1 / 2PE unit multiplication-accumulation result are input into the complex adders in the multiplication-addition bypass to perform calculation to obtain a final multiplication-accumulation tree calculation result.

[0024] The mean accumulation tree operation is implemented by interconnecting a plurality of complex adders of each 1 / 2PE unit and a plurality of complex adders of a multiplication-addition bypass and a divider, two 1 / 2PE units perform accumulation calculation through the plurality of complex adders to obtain a third 1 / 2PE unit accumulation result and a fourth 1 / 2PE unit accumulation result, the third 1 / 2PE unit accumulation result and the fourth 1 / 2PE unit accumulation result are input into the plurality of complex adders in the multiplication-addition bypass to perform accumulation calculation, and the calculation result is input into the divider to obtain a final mean accumulation tree calculation result.

[0025] A reconstruction controller architecture for implementing a reconstruction calculation method includes:

[0026] A master module, a state machine module, a calculation decoder module, a memory access resource controller module, a reconstruction controller module, a reconfigurable calculation array, an input buffer module, and an output buffer module.

[0027] The master module sends a control signal to the state machine module and sends a master instruction to the computing decoder module;

[0028] The state machine module switches states according to the received control signal to control the entire reconstruction computing process;

[0029] The computing decoder module decodes the received master instruction to obtain a decoding result, and receives a configuration instruction of the memory access resource controller module;

[0030] The reconstruction controller module configures the connection mode of the reconfigurable computing array according to the decoding result, and sets a counter to control the time interval of data transmission;

[0031] The reconfigurable computing array is an array composed of a plurality of PE units interconnected, and based on the configuration of the reconstruction controller module, the connection mode of the PE units is reorganized to realize a plurality of computing functions to complete data computation, and the computing result is transmitted to the output buffer module;

[0032] The input buffer module is used to receive input data and transmit the input data to the reconfigurable computing array;

[0033] The output buffer module is used to receive the computing result of the reconfigurable computing array and output the computing result.

[0034] Specifically, the state machine module switches states according to the received control signal to control the entire reconstruction computing process, including:

[0035] The state machine enters the IDLE state after the chip is started, and waits for the master signal;

[0036] After the state machine receives the start signal sent by the master module, it enters the DECODE state to control the computing decoder module to decode;

[0037] After the decoding of the computing decoder module is completed, the state machine enters the RECONFIG state to control the reconstruction controller module to configure the reconfigurable computing array;

[0038] After the configuration process of the reconstruction controller module is completed, the fixed computing delay of the reconfigurable computing array is transmitted back to the master module, and the state machine enters the COMPUTE state, and the reconfigurable computing array starts computing the input data;

[0039] After the state machine receives the end signal sent by the master module, it returns to the DECODE state;

[0040] After the state machine receives the reset signal sent by the master module, it returns to the IDLE state.

[0041] Specifically, the computing decoder module decodes the received master control instruction to obtain a decoding result, and receives a configuration instruction of the memory resource controller module, including:

[0042] The computing decoder module decodes the received master control instruction to determine the operation type and the corresponding reconfigurable interconnection mode;

[0043] The configuration instruction of the memory resource controller is received and decoded to determine the data memory strategy.

[0044] Specifically, the reconfiguration controller module configures the connection mode of the reconfigurable computing array according to the decoding result, and controls the time interval of data transmission by setting a counter, including:

[0045] The reconfiguration controller module controls the control end of the MUX gate in the reconfigurable computing array according to the operation type and the connection mode of the reconfigurable computing array to configure the reconfigurable computing array;

[0046] The time interval of data transmission is controlled by setting a counter to meet the calculation delay of different operation types.

[0047] A chip, the chip is internally provided with the module of the reconfiguration controller architecture.

[0048] Compared with the prior art, the present application has the following beneficial effects:

[0049] The application realizes multiply-accumulate operation, multiply-add operation, multiply-subtract operation, comparison tree operation, accumulation tree operation, multiply-accumulate tree operation and mean accumulation tree operation through the reconstruction interconnection between multiple PE calculation units of a single-precision array, adopts the mode of 2 1 / 2PE units and multiply-add bypass interconnection, can flexibly support multiple operation modes, can support the independent execution of each 1 / 2PE unit and can support the communication between 1 / 2PE; realizes addition operation, subtraction operation, multiplication operation, division operation, comparison operation, multiply-accumulate operation and accumulation operation through the reconstruction interconnection between multiple calculation units of a double-precision array; through the dynamic configuration of multiple calculation units, the hardware architecture can be adjusted in real time according to different algorithm requirements, the calculation array can adapt to different digital signal processing tasks, and a special hardware does not need to be designed for each task, thereby improving the flexibility of DSP chip configuration, optimizing the calculation performance and improving the resource utilization rate. The application controls the reconfigurable calculation array through the reconstruction controller architecture, completes the efficient mapping deployment of the signal processing algorithm in a data flow driving mode, the design complexity of the data and control channels is reduced, the difficulty of physical implementation can be effectively reduced, thereby realizing the efficient reconfiguration on the multi-dimensional slice of the space dimension, the time dimension and the resource dimension, and the reconfigurable calculation array is accurately configured to complete different calculation tasks. BRIEF DESCRIPTION OF DRAWINGS

[0050] Figure 1 It is a structure schematic diagram of a reconfigurable calculation array of the application;

[0051] Figure 2 It is a structure schematic diagram of a 1 / 2PE unit in embodiment 1 of the application;

[0052] Figure 3 It is a structure schematic diagram of multiply-add bypass in embodiment 1 of the application;

[0053] Figure 4 It is a reconstruction interconnection diagram of multiply-accumulate operation in embodiment 2 of the application;

[0054] Figure 5 It is a reconstruction interconnection diagram of multiply-add / multiply-subtract operation in embodiment 2 of the application;

[0055] Figure 6 It is a reconstruction interconnection diagram of comparison tree operation in embodiment 2 of the application;

[0056] Figure 7 It is a reconstruction interconnection diagram of accumulation tree operation in embodiment 2 of the application;

[0057] Figure 8 It is a reconstruction interconnection diagram of multiply-accumulate tree operation in embodiment 2 of the application;

[0058] Figure 9Reconfiguration interconnection diagram for mean accumulation tree operation in embodiment 2 of the present application

[0059] Figure 10 Module schematic diagram of a reconfiguration controller architecture of the present application

[0060] Figure 11 State machine state jump schematic diagram in embodiment 3 of the present application. DETAILED DESCRIPTION

[0061] In order to make the above objectives, features and advantages of the present application more apparent, specific embodiments of the present application are described in detail below with reference to the accompanying drawings.

[0062] In the following description, a large number of specific details are set forth in order to facilitate a thorough understanding of the present application, but the present application can also be implemented in other ways different from those described herein, and those skilled in the art can make similar generalizations without departing from the concept of the present application, therefore the present application is not limited to the specific embodiments disclosed below.

[0063] Secondly, the "one embodiment" or "embodiment" referred to herein means that a specific feature, structure or characteristic can be included in at least one implementation of the present application. "In one embodiment" appearing in different places in the specification does not mean the same embodiment, nor is it an embodiment that is separate or alternative to other embodiments.

[0064] Embodiment 1

[0065] The embodiment provides a reconfigurable computing array, and a specific scheme is as follows: Figure 1 As shown in the figure, the reconfigurable computing array comprises:

[0066] a single-precision array, which realizes a plurality of operation functions of real numbers and complex numbers according to reconfiguration interconnections between a plurality of PE computing units, wherein the reconfiguration interconnection manners in the real number and complex number modes are completely same;

[0067] a double-precision array, which realizes a plurality of operation functions according to reconfiguration interconnections between a plurality of computing units;

[0068] a MUX selector, which configures the connection manner between different computing units according to a preset configuration manner, so that the reconfigurable computing array is adapted to a plurality of computing tasks by integrating common operators of different algorithms and combining a unified input / output buffer.

[0069] In this embodiment, the single-precision array is composed of a plurality of PE computing units, including 2 1 / 2 PE units and a multiplication-addition bypass. The PE computing unit is composed of a plurality of basic operation units, such as adders, multipliers, etc. Each computing unit is connected through a programmable interconnection structure. According to the actual calculation requirement, the connection mode between the computing units can be dynamically changed to support various operations. For example, to realize multiplication operation, the corresponding basic operation units can be connected together for parallel processing, and the input data is calculated. According to different operation requirements, the system is reconfigured to support a wide range of application scenarios, has higher flexibility, and can execute multiple to-be-processed operation tasks synchronously through parallel processing, realizes faster calculation speed, and dynamically allocates computing resources among different computing tasks to avoid resource waste under fixed architecture.

[0070] The double-precision array of this embodiment is also composed of a plurality of computing units, including comparators, multipliers, dividers, etc. Double-precision floating-point operation is adopted to meet higher calculation precision requirements. Similar to the single-precision array, the double-precision array also relies on a programmable interconnection structure to realize dynamic connection between computing units. The double-precision array supports more complex calculations and can meet application scenarios that require high reliability. Generally, the energy consumption of double-precision operation is higher, but through dynamic reconfiguration, energy efficiency can be optimized and resources can be saved on specific tasks.

[0071] The MUX gate of this embodiment uses the multiplexing principle to select different input connections to the output through a control signal, so as to realize flexible configuration of the connection mode between a plurality of computing units. According to the actual calculation task requirement, the MUX gate configures the connection mode between the computing units according to the preset configuration mode, integrates the common operators of various algorithms in the DSP, quantizes a set of reconfiguration mode, outputs and inputs the buffer area through a unified specification interface, reduces the complexity of external interconnection, solves the problem of wiring redundancy, and is no longer connected to the computing resource through a kind of interconnection line as in the traditional method. Through fast switching of the connection mode, the computing array can be quickly switched between different computing tasks to adapt to diversified requirements. According to the current task, the resource usage is dynamically adjusted, which can improve the calculation efficiency and system response speed.

[0072] The application realizes multiply-accumulate operation, multiply-add operation, multiply-subtract operation, comparison tree operation, accumulation tree operation, multiply-accumulate tree operation and mean accumulation tree operation through the reconstruction interconnection between multiple PE calculation units of a single-precision array, adopts the mode of two 1 / 2PE units and multiply-add bypass interconnection, can flexibly support multiple operation modes, can support the independent execution of each 1 / 2PE unit and can support the communication between 1 / 2PE; realizes addition operation, subtraction operation, multiplication operation, division operation, comparison operation, multiply-accumulate operation and accumulation operation through the reconstruction interconnection between multiple calculation units of a double-precision array; through the dynamic configuration of multiple calculation units, the hardware architecture can be adjusted in real time according to different algorithm requirements, the calculation array can adapt to different digital signal processing tasks, and a special hardware does not need to be designed for each task, thereby improving the flexibility of DSP chip configuration, optimizing the calculation performance and improving the resource utilization rate. The application controls the reconfigurable calculation array through the reconfiguration controller architecture, completes the efficient mapping deployment of the signal processing algorithm in a data flow driving mode, the design complexity of the data and control channels is reduced, the difficulty of physical implementation can be effectively reduced, thereby realizing the efficient reconfiguration on the multi-dimensional slice of the space dimension, the time dimension and the resource dimension, and the reconfigurable calculation array is accurately configured to complete different calculation tasks.

[0073] Further, the single-precision array and the double-precision array include:

[0074] The single-precision array includes multiple 1 / 2PE units and multiply-add bypass, the 1 / 2PE unit is composed of a complex adder, a comparator and a complex multiplier, and the multiply-add bypass is composed of a complex multiplier, a complex adder and a divider;

[0075] The double-precision array is composed of a double-precision comparator unit, a double-precision adder unit, a double-precision multiply-add unit and a double-precision divider unit.

[0076] The single-precision array in the embodiment includes two 1 / 2PE units and multiply-add bypass, as Figure 2 Each 1 / 2PE unit is composed of 16 complex adders, 8 comparators and 8 complex multipliers, the complex adder is used for executing addition operation, the comparator is used for comparing different input values to make conditional judgment, and the complex multiplier is used for executing multiplication operation, multiple complex adders and complex multipliers are arranged in the 1 / 2PE unit, multiple operations can be processed at the same time, the calculation speed can be improved, different operation units can be connected, and multiple operation requirements and complex logic operations can be met. Figure 3, the multiplication-addition bypass is composed of 4 complex multipliers, 4 complex adders and 1 divider, the multiplication-addition bypass provides efficient multiplication-addition operation, through the bypass structure, these operations can be carried out in parallel, thereby reducing the delay and improving the flexibility of the system. The double-precision array is composed of a double-precision comparator unit, a double-precision adder unit, a double-precision multiplication-addition unit and a double-precision division unit, and can meet the double-precision calculation.

[0077] Embodiment 2

[0078] A reconstruction calculation method for configuring the reconfigurable calculation array, comprising:

[0079] The single-precision array realizes multiplication-accumulation operation, multiplication-addition operation and multiplication-subtraction operation through the reconstruction mode of PE reconstruction;

[0080] The single-precision array realizes comparison tree operation, accumulation tree operation, multiplication-accumulation tree operation and mean accumulation tree operation through the reconstruction mode of PE reconstruction;

[0081] The double-precision array realizes double-precision addition operation, double-precision subtraction operation, double-precision multiplication operation, double-precision division operation, double-precision comparison operation, double-precision multiplication-accumulation operation and double-precision accumulation operation through the reconstruction interconnection between the double-precision comparator unit, the double-precision adder unit, the double-precision multiplication-addition unit and the double-precision division unit.

[0082] The single-precision array in the embodiment realizes multiplication-accumulation operation, multiplication-addition operation and multiplication-subtraction operation through the reconstruction mode of PE reconstruction, and connects the complex adder and the complex multiplier in 1 / 2 PE into a summation network or a multiplication network through dynamic reconfiguration, so as to adapt to the requirements of specific operation, realize multiplication-accumulation operation, multiplication-addition operation and multiplication-subtraction operation, adjust the input-output path and the data flow direction according to different operation requirements through different connection modes, have high flexibility, can quickly adapt to different mathematical operations, reduce the delay caused by hardware change, allow multiple operations to be alternately performed on the same hardware platform, do not need to design separate hardware for each operation, and reduce the waste of hardware resources.

[0083] The single-precision array in the embodiment realizes comparison tree operation, accumulation tree operation, multiply-accumulate tree operation and mean accumulation tree operation through inter-PE reconfiguration. Through reconfiguration of the connection of adjacent PEs, a relatively complex operation structure such as a tree structure is formed among multiple PEs to realize comparison tree operation, accumulation tree operation, multiply-accumulate tree operation and mean accumulation tree operation. For example, the accumulators between different PEs are connected to form an accumulation tree. Through parallel processing of multiple inputs, multiple operations can be performed simultaneously to improve overall efficiency, especially when large-scale data processing is performed, which can significantly improve the calculation efficiency. The complex operation function is modularized, which facilitates maintenance and upgrading and improves flexibility. Through the design of a reasonable single-precision array, the use of two 1 / 2 PE units and multiply-add bypass, and the combination of flexible internal and external reconfiguration mechanisms, diversified operation requirements can be effectively supported, which not only improves the operation efficiency but also greatly enhances the flexibility and reconfigurability of the system.

[0084] In the embodiment, the double-precision array includes a double-precision comparator unit, a double-precision adder unit, a double-precision multiply-add unit and a double-precision division unit. The double-precision array realizes comparison operation, addition operation, multiply-add operation and division operation of double-precision through multiple units. The configuration of the double-precision array allows the units to be dynamically interconnected. According to the current required operation type, the connection mode between the calculation units is configured to adapt to different operation requirements. For example, when multiply-accumulate operation is performed, the multiply-add unit and the adder unit are connected. When comparison operation is performed, the input is connected to the comparator unit. Through reconfiguration interconnection design, different operations can be completed on the same hardware to adapt to different calculation requirements and improve flexibility. Different operations share the same hardware resources, which reduces redundancy and hardware cost and improves resource utilization. The double-precision unit can accurately process floating-point calculation to meet the demand for high precision.

[0085] Further, the multiply-accumulate operation, multiply-add operation and multiply-subtract operation realized by the single-precision array through intra-PE reconfiguration include:

[0086] In each 1 / 2 PE unit, a multiply-accumulate operation is realized by interconnecting one complex multiplier and two complex adders. The complex multiplier performs multiplication calculation on the input data to obtain a first result. The first result is input into the first complex adder to obtain an accumulation result. The accumulation result and the first result are input into the second complex adder to obtain a multiply-accumulate calculation result.

[0087] In each 1 / 2 PE unit, a multiply-add operation and a multiply-subtract operation are realized by interconnecting one complex multiplier and one complex adder. The complex multiplier performs multiplication calculation on the input data to obtain a multiplication calculation result. The multiplication calculation result and the input data are input into the complex adder to obtain a multiply-add or multiply-subtract calculation result.

[0088] In the embodiment, as shown in Figure 4 Inside the 1 / 2PE unit, the multiplication and accumulation operation is realized by interconnecting one complex multiplier and two complex adders, the complex multiplier performs multiplication calculation on the input data to obtain a first result, the first result is input into the first complex adder to perform accumulation to obtain an accumulation result, and the accumulation result and the first result are input into the second complex adder to calculate a multiplication and accumulation calculation result.

[0089] Specifically, the complex multiplier receives two complex input data A and B, A=(a1, a2) and B=(b1, b2), and performs multiplication to obtain a first result, that is, the first result=A×B=(a1b1-a2b2, a1b2+a2b1), the first result is input into the first complex adder to perform accumulation, the first result and the first result are added to obtain an accumulation result, that is, the accumulation result=first result+first result, and the accumulation result and the first result are input into the second complex adder to calculate a multiplication and accumulation calculation result, that is, the multiplication and accumulation result=accumulation result+first result. For example, input data The first result obtained by inputting A and B into the complex multiplier is The accumulation result obtained by inputting the first result into the first complex adder is The multiplication and accumulation result obtained by inputting the first result and the accumulation result into the second complex adder is By using the combination of the complex multiplier and the complex adder, the multiplication and accumulation calculation can be quickly completed, the calculation efficiency is improved, and compared with the traditional multiplication and addition step-by-step execution, the two operations are fused, so that the area and power consumption can be saved in hardware implementation.

[0090] In the embodiment, as shown in Figure 5 Inside the 1 / 2PE unit, the multiplication and accumulation operation is realized by interconnecting one complex multiplier and two complex adders, the complex multiplier performs multiplication calculation on the input data to obtain a first result, the first result is input into the first complex adder to perform accumulation to obtain an accumulation result, and the accumulation result and the first result are input into the second complex adder to calculate a multiplication and accumulation calculation result.

[0091] Specifically, the complex multiplier receives two complex input data C and D, C=(c1, c2) and D=(d1, d2), and performs multiplication to obtain a multiplication calculation result, that is, the multiplication calculation result=C×D=(c1d1-c2d2, c1d2+c2d1), the multiplication calculation result and input data E are input into the complex adder to perform operation to obtain a multiplication and addition or multiplication and subtraction calculation result. For example, input data The multiplication calculation result obtained by inputting C and D into the complex multiplier is The multiplication and addition result obtained by inputting the multiplication calculation result and E into the complex adder is By using the combination of complex multiplier and complex adder, the multiply-add and multiply-subtract calculations can be quickly completed, the calculation efficiency is improved, and compared with the traditional multiply and add step-by-step execution, two operations are fused, so that the area and power consumption can be saved in hardware implementation.

[0092] Further, the reconstruction mode of reconstructing the single-precision array through the inter-PE reconstruction is used to implement comparison tree operation, accumulation tree operation, multiply-accumulate tree operation and mean accumulation tree operation.

[0093] The plurality of comparators between each 1 / 2PE unit are interconnected to implement comparison tree operation, the comparators compare input data to obtain comparison results, and the comparison results are input into the next comparator for comparison to obtain a final comparison result.

[0094] The plurality of complex adders of each 1 / 2PE unit and the plurality of complex adders of the multiply-add bypass are interconnected to implement accumulation tree operation, two 1 / 2PE units are calculated by the plurality of complex adders to obtain first 1 / 2PE unit accumulation result and second 1 / 2PE unit accumulation result, and the first 1 / 2PE unit accumulation result and the second 1 / 2PE unit accumulation result are input into the complex adder in the multiply-add bypass for calculation to obtain a final accumulation tree calculation result.

[0095] The plurality of complex multipliers and complex adders of each 1 / 2PE unit and the plurality of complex adders of the multiply-add bypass are interconnected to implement multiply-accumulate tree operation, two 1 / 2PE units are calculated by inputting the calculation result of the complex multiplier into the plurality of complex adders to obtain first 1 / 2PE unit multiply-accumulate result and second 1 / 2PE unit multiply-accumulate result, and the first 1 / 2PE unit multiply-accumulate result and the second 1 / 2PE unit multiply-accumulate result are input into the complex adder in the multiply-add bypass for calculation to obtain a final multiply-accumulate tree calculation result.

[0096] The plurality of complex adders of each 1 / 2PE unit and the plurality of complex adders of the multiply-add bypass and the divider are interconnected to implement mean accumulation tree operation, two 1 / 2PE units are calculated by the plurality of complex adders to obtain third 1 / 2PE unit accumulation result and fourth 1 / 2PE unit accumulation result, and the third 1 / 2PE unit accumulation result and the fourth 1 / 2PE unit accumulation result are input into the plurality of complex adders in the multiply-add bypass for accumulation calculation, and the calculation result is input into the divider to obtain a final mean accumulation tree calculation result.

[0097] In the embodiment, as Figure 6 The plurality of comparators between two 1 / 2PE units are interconnected to implement comparison tree operation, the comparators compare input data to obtain comparison results, and the comparison results are input into the next comparator for comparison to obtain a final comparison result.

[0098] Specifically, multiple data to be compared are provided as input to the first level of comparators, each comparator receives two input data, compares and outputs the comparison result. The comparator outputs the larger or smaller value, for example, the comparator receives and When the maximum value is required, when the output is The comparison result of the previous layer of comparators is input to the comparators of the next layer for further comparison, forming a tree structure, each layer of comparators processes the comparison result of the previous layer, two 1 / 2PE units calculate the first 1 / 2PE unit comparison result and the second 1 / 2PE unit comparison result respectively, the two 1 / 2PE units are connected, the first 1 / 2PE unit comparison result and the second 1 / 2PE unit comparison result are input to the comparator for comparison to obtain the final comparison result. The comparison tree structure allows multiple comparisons to be performed simultaneously, significantly improving the processing speed. By adjusting the structure or depth of the comparison tree, different quantities and types of data can be flexibly handled.

[0099] In this embodiment, as Figure 7 The multiple adders of the two 1 / 2PE units are interconnected with the multiple adders of the multiplication-addition bypass to implement accumulation tree operation, the two 1 / 2PE units calculate the first 1 / 2PE unit accumulation result and the second 1 / 2PE unit accumulation result through the multiple adders, and the first 1 / 2PE unit accumulation result and the second 1 / 2PE unit accumulation result are input to the adder in the multiplication-addition bypass for calculation to obtain the final accumulation tree calculation result.

[0100] Specifically, for example, there are multiple input data The two 1 / 2PE units accumulate the input data respectively, the first 1 / 2PE unit accumulates , and the second 1 / 2PE unit accumulates The input data are input to the adder of the first level for calculation, and the calculation result of the adder of the previous layer is input to the adder of the next layer for further calculation, forming an accumulation tree structure, the first 1 / 2PE unit accumulation result and the second 1 / 2PE unit accumulation result are calculated in each 1 / 2PE unit, the two 1 / 2PE units are connected with the adder of the multiplication-addition bypass respectively, the first 1 / 2PE unit accumulation result and the second 1 / 2PE unit accumulation result are input to the adder of the multiplication-addition bypass for calculation to obtain the final accumulation tree calculation result. Different adders can process multiple inputs simultaneously, greatly improving the overall calculation speed. Through the hierarchical structure, partial results can be calculated at each layer, reducing the delay from input to final output.

[0101] In this embodiment, as Figure 8The multiple complex multipliers and complex adders of the two 1 / 2PE units are interconnected with the multiple complex adders of the multiply-add bypass to implement multiply-accumulate tree operation, the two 1 / 2PE units input the calculation results of the complex multipliers into the multiple complex adders to accumulate and calculate to obtain a first 1 / 2PE unit multiply-accumulate result and a second 1 / 2PE unit multiply-accumulate result, and input the first 1 / 2PE unit multiply-accumulate result and the second 1 / 2PE unit multiply-accumulate result into the complex adders in the multiply-add bypass to calculate to obtain a final multiply-accumulate tree calculation result.

[0102] Specifically, for example, there are multiple input data , two 1 / 2PE units input the input data two by two into the complex multipliers to calculate, the first 1 / 2PE unit performs multiplication calculation on , the second 1 / 2PE unit performs multiplication calculation on , and inputs the calculation results of each two complex multipliers into the complex adders to calculate, inputs the calculation results of the complex adders in the previous layer into the complex adders in the next layer to calculate, and adds up the calculation results of the complex adders to obtain a first 1 / 2PE unit multiply-accumulate result and a second 1 / 2PE unit multiply-accumulate result, connects the two 1 / 2PE units with the complex adders of the multiply-add bypass, and inputs the first 1 / 2PE unit multiply-accumulate result and the second 1 / 2PE unit multiply-accumulate result into the complex adders of the multiply-add bypass to calculate to obtain a final multiply-accumulate tree calculation result. Through the parallel work of multiple complex multipliers and complex adders, the calculation efficiency can be significantly improved, large-scale data can be quickly processed, and high efficiency, flexibility and excellent resource utilization rate are achieved.

[0103] In the embodiment, as Figure 9 , the multiple complex adders of the two 1 / 2PE units are interconnected with the multiple complex adders and dividers of the multiply-add bypass to implement mean accumulation tree operation, the two 1 / 2PE units input the calculation results of the complex adders into the multiple complex adders to accumulate and calculate to obtain a third 1 / 2PE unit accumulation result and a fourth 1 / 2PE unit accumulation result, input the third 1 / 2PE unit accumulation result and the fourth 1 / 2PE unit accumulation result into the multiple complex adders in the multiply-add bypass to accumulate and calculate, and input the calculation results into the dividers to obtain a final mean accumulation tree calculation result.

[0104] Specifically, the mean accumulation tree operation is based on the accumulation tree operation, the accumulation tree calculation result is input into the dividers in the multiply-add bypass to average to obtain a final mean accumulation tree calculation result, parallel calculation is achieved by using multiple complex adders and multiply-add bypass, thereby accelerating the operation efficiency, large-scale data sets can be quickly calculated, and multiple complex adders and dividers are connected to save hardware resources and improve calculation flexibility.

[0105] Embodiment 3

[0106] The embodiment provides a reconfiguration controller architecture for implementing a reconfiguration computing method of the embodiment 2, such as Figure 10 The reconfiguration controller architecture comprises:

[0107] a master module, a state machine module, a computing decoder module, a memory access resource controller module, a reconfiguration controller module, a reconfigurable computing array, an input buffer module and an output buffer module.

[0108] The master module sends a control signal to the state machine module and sends a master instruction to the computing decoder module.

[0109] The state machine module switches states according to the received control signal and controls the whole reconfiguration computing process.

[0110] The computing decoder module decodes the received master instruction to obtain a decoding result and receives a configuration instruction of the memory access resource controller module.

[0111] The reconfiguration controller module configures a connection mode of the reconfigurable computing array according to the decoding result and controls a time interval of data transmission by setting a counter.

[0112] The reconfigurable computing array is an array composed of a plurality of PE units, and based on the configuration of the reconfiguration controller module, the connection mode of the PE units is recombined to realize a plurality of computing functions to complete data computing, and the computing result is transmitted to the output buffer module.

[0113] The input buffer module is used for receiving input data and transmitting the input data to the reconfigurable computing array.

[0114] The output buffer module is used for receiving the computing result of the reconfigurable computing array and outputting the computing result.

[0115] The reconfigurable controller architecture of the embodiment includes a master module, a state machine module, a compute decoder module, a memory resource controller module, a reconfigurable controller module, a reconfigurable compute array, an input buffer module and an output buffer module. The master module generates control signals and instructions by receiving user input or preset tasks, is responsible for sending control signals and master instructions to coordinate the functions of other modules, sends control signals to the state machine module to start and manage the compute flow, and sends master instructions to the compute decoder module to indicate the required compute task. By centrally managing the compute process, the controllability and consistency of the system are improved, and the control signals and instructions can be quickly adjusted according to different compute requirements; the state machine module switches states according to the received control signals, controls the entire reconfigurable compute process, and the state machine module switches between different states, such as an initial state, a compute state and a transmission state. Through state transition logic, the control signals guide other modules to complete specific tasks, and the state machine can quickly respond to signal changes and dynamically control the compute flow.

[0116] The compute decoder module is responsible for decoding the master instructions to obtain actual compute instructions, and receiving configuration instructions from the memory resource controller module to configure compute resources. By decoding the master instructions sent by the master module, the compute decoder module generates instructions that can be understood and executed by other modules, improves compute efficiency, and at the same time receives configuration instructions from the memory resource controller, reasonably allocates and manages compute resources according to the configuration instructions, and improves resource utilization efficiency. The memory resource controller module is responsible for managing data access, receiving data requests, and reading data from the input buffer or the output buffer. The memory resource controller module can quickly manage data access and reduce compute latency.

[0117] The reconfigurable controller module of the embodiment configures the connection mode of the reconfigurable computing array according to the decoding result, selects a corresponding connection mode according to the computing requirement to configure the computing array, controls the time interval of data transmission by setting a counter to ensure the validity of data, quickly reconfigures the connection mode according to different computing tasks to adapt to various operations, and improves the ability of processing data by controlling the data transmission frequency. The reconfigurable computing array is composed of a plurality of PE units interconnected to perform actual computing tasks. According to the configuration of the reconfigurable controller, the connection mode between the PE units is dynamically adjusted to adapt to different computing algorithms, input data is accepted, computation is performed, and the result is sent to the output buffer. A plurality of computing functions can be realized by different reconfiguration modes, and the parallel processing of a plurality of PE units can significantly improve the operation speed. The input buffer module is used to receive input data and transmit the input data to the reconfigurable computing array; the output buffer module is used to receive the computing result of the reconfigurable computing array and output the computing result. The reconfigurable controller architecture realizes efficient and flexible data computing function through the cooperative work of each module. Each module plays an important role in operation, data flow management and control, and the overall computing efficiency and performance of the system are improved through reasonable design.

[0118] Further, the state machine module switches states according to the received control signal to control the entire reconfigurable computing process, including: Figure 11

[0119] The state machine enters the IDLE state after the chip is started, and waits for the main control signal;

[0120] After the state machine receives the start signal sent by the main control module, it enters the DECODE state to control the computing decoder module to decode;

[0121] After the decoding of the computing decoder module is completed, the state machine enters the RECONFIG state to control the reconfigurable controller module to configure the reconfigurable computing array;

[0122] After the configuration process of the reconfigurable controller module is completed, the fixed computing delay of the reconfigurable computing array is transmitted back to the main control module, and the state machine enters the COMPUTE state, and the reconfigurable computing array starts computing the input data;

[0123] After the state machine receives the end signal sent by the main control module, it returns to the DECODE state;

[0124] After the state machine receives the reset signal sent by the main control module, it returns to the IDLE state.

[0125] As Figure 11 ​, the state machine controls the whole reconfigurable computing process through the switching of states. After the chip is started, it enters the IDLE state and waits for the signal sent by the master module. At this time, the system is in a standby mode and does not perform any calculation. By keeping in the IDLE state, the unused reconfigurable computing array and other modules are reduced to reduce resource consumption. When the state machine receives the start signal sent by the master module, it enters the DECODE state. In this state, the state machine instructs the computing decoder module to perform the decoding process, generates the corresponding computing configuration according to the received instruction, switches the system from the low-power state to the preparation state, and ensures timely response to the master signal. After the decoding of the computing decoder module is completed, the state machine enters the RECONFIG state. In this state, the state machine controls the reconfiguration controller module to configure the reconfigurable computing array to realize specific computing functions, flexibly modifies the structure of the computing array according to the decoding result, and supports variable computing requirements. After the configuration process of the reconfiguration controller module is completed, the fixed computing delay of the reconfigurable computing array is transmitted back to the master module, and the state machine enters the COMPUTE state. In this state, the reconfigurable computing array starts to perform the calculation on the input data and performs the actual numerical processing, giving full play to the high efficiency of the computing array and quickly processing the input data. After the state machine receives the end signal sent by the master module, it returns to the DECODE state. This state allows the system to prepare to accept new computing instructions and decode again. By quickly switching back to the decoding state, it adapts to multiple consecutive computing tasks, maintains the efficiency and flexibility of system computing, and returns to the IDLE state after receiving the reset signal sent by the master module. The system enters the standby state again and waits for the next round of tasks. By returning to the initial state, the data residue of the current state is eliminated, ensuring that each calculation is independent and stable, and entering the low-power state in time when the calculation is no longer needed to avoid unnecessary resource waste or accidental operation.

[0126] Through the control of the whole reconfigurable computing process by the state machine, clear task management and efficient resource utilization can be realized. Each step and its state transition helps to improve the performance and flexibility of the system, so that the reconfigurable computing array can adapt to various application requirements and maintain high computing power, which helps to improve the response speed, stability and reusability of the whole system.

[0127] Further, the decoding result obtained by decoding the received master instruction by the computing decoder module and the configuration instruction received by the memory resource controller module include:

[0128] The computing decoder module decodes the received master instruction to determine the operation type and the corresponding reconfiguration interconnection mode.

[0129] The configuration instruction of the memory resource controller is received and decoded to determine the data memory strategy.

[0130] In the embodiment, the computing decoder module receives the host instruction from the host module and decodes the host instruction to identify the operation type (such as addition operation, multiplication operation, comparison operation, etc.) represented by the instruction, and according to the identified operation type, the decoder provides the corresponding reconstruction interconnection mode to the reconstruction controller module to configure the connection mode of the reconfigurable computing array; by translating the complex host instruction into explicit execution operation, the control logic of the entire computing process is simplified, and the readability and maintainability of the system are improved; the computing decoder module also receives the configuration instruction from the memory access controller, which is responsible for managing the data access rules, decodes the configuration instruction to obtain the specific data storage strategy, including access mode, cache strategy, data prefetching, etc., generates control signals, and feeds back to the memory resource controller to realize efficient data access, improves the utilization level of storage resources through data access strategy, and reduces the delay that may be caused during data access through fast analysis and processing of the configuration instruction, and improves the data access efficiency.

[0131] Further, the reconstruction controller module configures the connection mode of the reconfigurable computing array according to the decoding result, and controls the time interval of data transmission by setting a counter, including:

[0132] The reconstruction controller module controls the control end of the MUX gate in the reconfigurable computing array according to the operation type and the connection mode of the corresponding reconfigurable computing array, and configures the reconfigurable computing array;

[0133] By setting the counter to control the time interval of data transmission, the calculation delay of different operation types can be transmitted after the correct number of beats.

[0134] In the embodiment, the reconstruction controller module determines the connection mode of the corresponding reconfigurable computing array according to the operation type transmitted by the computing decoder, controls the control end of the MUX gate in the reconfigurable computing array, establishes appropriate signal paths between PE units, and realizes the configuration of the reconfigurable computing array. The configuration of the MUX gate enables the same hardware to be reconfigured according to different operation types, maximizes the use of hardware resources, and reduces unnecessary energy consumption or operation redundancy; by setting the counter, the time interval between data transmission is controlled and adjusted, which can prevent data conflict and ensure that data is transmitted within the correct time window. Each operation type may correspond to different calculation delays, and the reconstruction controller adjusts the value of the counter according to these delay information, so that the operation module receives the result of the previous step at the appropriate time. Through effective time control, the risk of errors in the data transmission process is reduced, and the accuracy of the calculation is ensured.

[0135] A chip, the chip is internally provided with the module of the reconstruction controller architecture.

[0136] Specifically, the resources inside the chip are divided in a modular manner, and each module can work independently. This structure makes the communication and control between modules more flexible and simple. By setting the modules of the reconfigurable controller architecture, the control of the reconfigurable computing array is realized. Through dynamic reconfiguration, the limited hardware resources can be effectively utilized, and the configuration is optimized according to different computing requirements, so that the chip can quickly respond to different computing tasks, reduce the fixedness in hardware design, increase the flexibility of the chip, and when the device is in standby state, most of the resources can be closed, only the basic monitoring function runs, thereby saving power to the maximum. By setting the modules of the reconfigurable controller architecture inside the chip, the flexibility, performance and energy efficiency of the chip can be significantly improved. This design method not only can adapt to various application scenarios, but also brings higher resource utilization and longer product life cycle, meets various computing requirements and optimizes user experience.

[0137] The above shows and describes the basic principles and main features of the present application and the advantages of the present application. Those skilled in the art should understand that the present application is not limited to the above-mentioned embodiments, and the above-mentioned embodiments and descriptions in the specification are only to illustrate the principles of the present application. Without departing from the spirit and scope of the present application, various changes and improvements can be made to the present application, and these changes and improvements all fall within the scope of the claimed present application. The scope of protection of the present application is defined by the appended claims and their equivalents.

Claims

1. A reconfigurable computing array, characterized in that, include: A single-precision array implements various arithmetic functions for real and complex numbers based on the reconfigured interconnection between multiple PE computing units. The reconfigured interconnection method is identical in both real and complex number modes, including: Multiple comparators between each 1 / 2PE unit are interconnected to implement a comparator tree operation. The comparator compares the input data to obtain a comparison result, and then inputs the comparison result into the next comparator for comparison to obtain the final comparison result. Multiple adders in each 1 / 2PE unit are interconnected with multiple adders in the multiply-accumulate bypass to realize the accumulation tree operation. Two 1 / 2PE units are accumulated and calculated through multiple adders to obtain the accumulation result of the first 1 / 2PE unit and the accumulation result of the second 1 / 2PE unit. The accumulation result of the first 1 / 2PE unit and the accumulation result of the second 1 / 2PE unit are input into the adders in the multiply-accumulate bypass for calculation to obtain the final accumulation tree calculation result. Multiple complex multipliers and complex adders in each 1 / 2PE unit are interconnected with multiple complex adders in the multiply-add bypass to realize multiply-accumulate tree operation. Two 1 / 2PE units are calculated by inputting the calculation results of the complex multipliers into multiple complex adders and accumulating them to obtain the first 1 / 2PE unit multiply-accumulate result and the second 1 / 2PE unit multiply-accumulate result. The first 1 / 2PE unit multiply-accumulate result and the second 1 / 2PE unit multiply-accumulate result are input into the complex adders in the multiply-add bypass for calculation to obtain the final multiply-accumulate tree calculation result. Multiple adders in each 1 / 2PE unit are interconnected with multiple adders and dividers in the multiply-accumulate bypass to achieve mean-accumulate tree operation. Two 1 / 2PE units are accumulated and calculated through multiple adders to obtain the accumulation results of the third 1 / 2PE unit and the fourth 1 / 2PE unit. The accumulation results of the third 1 / 2PE unit and the fourth 1 / 2PE unit are input into multiple adders in the multiply-accumulate bypass for accumulation and calculation, and the calculation results are input into the divider to obtain the final mean-accumulate tree calculation result. A double-precision array enables various computational functions through the reconfigured interconnection of multiple computing units. The MUX gate configures the connection between different computing units according to a preset configuration method, enabling the reconfigurable computing array to adapt to various computing tasks by integrating common operators of different algorithms with a unified input / output buffer.

2. The reconfigurable computing array according to claim 1, characterized in that, The single-precision array and double-precision array include: The single-precision array includes multiple 1 / 2PE units and a multiply-accumulate bypass. The 1 / 2PE unit consists of a complex adder, a comparator, and a complex multiplier. The multiply-accumulate bypass consists of a complex multiplier, a complex adder, and a divider. The double-precision array consists of a double-precision comparator unit, a double-precision adder unit, a double-precision multiply-accumulate unit, and a double-precision divider unit.

3. A reconfigurable computing method for configuring a reconfigurable computing array as described in any one of claims 1 to 2, characterized in that, include: Multiply-accumulate, multiply-add, and multiply-subtract operations are implemented in a single-precision array through internal reconstruction within the PE. The single-precision array is reconstructed through inter-PE reconstruction to perform comparison tree operations, accumulation tree operations, multiplication accumulation tree operations, and mean accumulation tree operations. The double-precision array is interconnected with double-precision comparator units, double-precision adder units, double-precision multiply-accumulate units, and double-precision divider units to realize double-precision addition, double-precision subtraction, double-precision multiplication, double-precision division, double-precision comparison, double-precision multiply-accumulate, and double-precision accumulation operations.

4. The reconstruction calculation method according to claim 3, characterized in that, The method of implementing multiply-accumulate, multiply-add, and multiply-subtract operations by reconstructing a single-precision array within a PE includes: Within each 1 / 2PE unit, a multiply-accumulate operation is achieved by interconnecting a complex multiplier and two complex adders. The complex multiplier performs multiplication on the input data to obtain a first result, the first result is input into the first complex adder for accumulation to obtain an accumulation result, and the accumulation result and the first result are input into the second complex adder to calculate the multiply-accumulate result. Within each 1 / 2PE unit, multiplication-addition and multiplication-subtraction operations are implemented by interconnecting a complex multiplier and a complex adder. The complex multiplier performs multiplication calculations on the input data to obtain the multiplication result, and the multiplication result and the input data are input into the complex adder to calculate the multiplication-addition or multiplication-subtraction result.

5. A reconfigurable controller architecture for implementing the reconfiguration computation method as described in any one of claims 3 to 4, characterized in that, include: The main control module, state machine module, computation decoder module, memory access resource controller module, reconfiguration controller module, reconfigurable computing array, input buffer module, and output buffer module are all included. The main control module sends control signals to the state machine module and sends main control commands to the calculation decoder module; The state machine module switches states according to the received control signals to control the entire reconstruction calculation process; The computation decoder module decodes the received master control instructions to obtain the decoding result, and receives the configuration instructions from the memory access resource controller module; The reconfiguration controller module configures the connection mode of the reconfigurable computing array according to the decoding result, and controls the time interval of data transmission by setting a counter; The reconfigurable computing array is an array composed of multiple interconnected PE units. Based on the configuration of the reconfiguration controller module, the connection method of the PE units is reconfigured to realize various computing functions to complete data calculation and transmit the calculation results to the output buffer module. The input buffer module is used to receive input data and transmit the input data to the reconfigurable computing array. The output buffer module is used to receive the calculation results of the reconfigurable computing array and output the calculation results.

6. A reconfigurable controller architecture according to claim 5, characterized in that, The state machine module switches states according to the received control signals, controlling the entire reconstruction calculation process, including: The state machine enters the IDLE state after the chip starts up, waiting for the master control signal; After receiving the start signal sent by the main control module, the state machine enters the DECODE state and controls the calculation decoder module to perform decoding. After the computation decoder module completes decoding, the state machine enters the RECONFIG state, controlling the reconfiguration controller module to configure the reconfigurable computation array. After the configuration process of the reconfigurable controller module is completed, the fixed computation delay of the reconfigurable computing array is sent back to the main control module, the state machine enters the COMPUTE state, and the reconfigurable computing array begins to compute the input data. After receiving the end signal sent by the main control module, the state machine returns to the DECODE state; After receiving the reset signal sent by the main control module, the state machine returns to the IDLE state.

7. A reconfigurable controller architecture according to claim 5, characterized in that, The computation decoder module decodes the received master control instructions to obtain the decoding result, and receives configuration instructions from the memory access resource controller module, including: The computation decoder module decodes the received master control instructions and determines the type of operation to be performed and the corresponding reconstruction interconnection method. Receive and decode the configuration instructions from the memory access resource controller to determine the data memory access strategy.

8. A reconfigurable controller architecture according to claim 5, characterized in that, The reconfiguration controller module configures the connection mode of the reconfigurable computing array according to the decoding result, and controls the data transmission time interval by setting a counter, including: The reconfiguration controller module controls the control terminal of the MUX selector in the reconfigurable computing array according to the operation type and the connection method of the corresponding reconfigurable computing array, and configures the reconfigurable computing array. By setting a counter to control the time interval of data transmission, the calculation delay of different types of operations can be exchanged after the correct number of clock cycles.

9. A chip, characterized in that... The chip is internally provided with a module for reconfiguring the controller architecture as described in any one of claims 5 to 8.

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