Fractional order differential equation set solving circuit and method of pipeline structure

Abstract

The invention discloses a circuit and a method for solving a Grunwald-Letnikov fractional order differential equation set of a pipeline structure. The solving circuit comprises a pipelined continuous multiply accumulation module, a pipelined differential equation right side function operation module, a pre-estimation correction module and a recursion module. The solving method comprises the steps that the successive multiplication and accumulation module and the recursion module work in parallel and cooperatively, and the recursion algorithm for solving the numerical value of the Grunwald-Letnikov fractional order differential equation set is achieved; the differential equation right function calculation module adopts a pipeline structure; and the pre-estimation and correction module is used for solving the problem of output hysteresis of the differential equation right side function operation module introduced by the pipeline structure. According to the scheme, the defects that an existing circuit implementation scheme cannot respond to input excitation signals in real time, and the data processing speed is limited due to high combinational logic time delay are overcome; a circuit design of a pipeline structure is adopted, and the method is characterized in that an externally input excitation signal can be responded in real time, a solution of a fractional order differential equation set at a time point can be calculated in a single clock period at a high throughput rate, and the calculation speed of hardware solution is improved.

Description

Technical Field

[0001] The invention relates to the field of signal processing and system control, and in particular to a circuit design and method for solving a Grünwald-Letnikov fractional-order differential equation group in a pipeline circuit form. Background Art

[0002] Fractional differentials are an extension of conventional integer differential operations. Unlike the locality of traditional integer differentials, fractional differentials can characterize non-local properties with "time memory effect". Systems with memory effects are difficult to accurately model and analyze using classical integer differential equations, and the unique non-local properties of fractional differential equations make them a powerful mathematical tool for analyzing such systems. At present, fractional differentials have been applied to many occasions such as weather and climate prediction, medical image enhancement processing, and nonlinear system control.

[0003] The numerical solution methods of fractional differential equations are divided into two categories. One is to convert the fractional differential equations into integer differential equations according to the Riemann-Liouville or Caputo definition of fractional differentials, and then use the Runge-Kutta method and other numerical algorithms to solve integer differential equations. The other is to discretize the fractional differential equations directly according to the Grünwald-Letnikov definition of fractional differentials, and then solve the numerical solutions at discrete time points with fixed time intervals by recursive iteration. Among them, the core of the latter algorithm is the recursive formula; the calculation formula of the numerical solution x of the next time step only contains the numerical solutions known in the previous several time steps, but not x itself. Therefore, the latter algorithm is more suitable for implementation with hardware circuits.

[0004] The existing scheme for solving the Grünwald-Letnikov fractional differential equations by hardware uses a state machine to control the aforementioned recursive process, which has the following shortcomings: (I) It takes multiple clock cycles to calculate the numerical solution at the next time point, and it cannot respond to the external input signal in real time within a single clock cycle, and cannot achieve the effect of high-speed output; (II) In actual systems, the expression on the right side of the differential equation group often contains multi-level multiplication and other operations, and the combinational logic of the corresponding function calculation module takes a long time; and according to the recursive formula of the Grünwald-Letnikov fractional differential equation, the numerical solution x at the previous moment is calculated. n-1 Input the function calculation module, and the recursive module calculates the numerical solution x at the next moment. n The entire combinational logic chain in the middle has a complex structure and long time delay, which can easily become the key path and bottleneck step of the entire circuit, seriously hindering the improvement of data processing speed.

[0005] The hardware circuit for solving fractional-order differential equations with pipeline structure can solve the above problems. The key to achieving pipeline effect is how to overcome the output hysteresis problem introduced by pipeline structure. According to the recursive formula for solving Grünwald-Letnikov fractional-order differential equations, t n The numerical solution x of the unknown quantity x at time n , depends on the numerical solution x at the previous moment n-1 Substitute the function expression on the right side of the equation to get the result F; the corresponding circuit is the right side function calculation module of the W-level pipeline structure, from x n-1 There is a hysteresis of W clock cycles from input to output F, and the calculation result of F cannot be given immediately in the current clock cycle, resulting in the inability to carry out recursive iteration.

[0006] To this end, the present invention designs a pipeline structure for solving a group of fractional differential equations to solve the problems that the existing circuit implementation scheme cannot respond to input excitation signals and process data in real time within a single clock cycle, and the solution operation speed is limited due to the long combinational logic time delay.

[0007] Compared with the prior art, the beneficial effects of the present invention are as follows. Different from the existing multi-cycle implementation scheme of the state machine, the present invention adopts a pipeline structure circuit, which can process the external input excitation signal in real time in a single cycle and perform high-throughput solution operations, and output the numerical solution in real time in a single cycle. At the same time, the continuous multiplication and accumulation module and the right-hand function operation module of the pipeline structure can avoid a large number of continuous additions and multiplications in a single clock cycle, thereby reducing the delay of these critical paths that restrict the speed of the circuit, and improving the maximum clock frequency of the circuit and the overall data processing speed. Summary of the invention

[0008] In order to improve the processing speed and data throughput of a circuit for solving a group of fractional differential equations, the present invention provides a hardware circuit for solving a group of fractional differential equations with a pipeline structure and a matching solving method.

[0009] In a first aspect, the present invention provides a hardware solving circuit for a group of fractional-order differential equations with a pipeline structure.

[0010] It is used to solve a system of fractional differential equations that can be equivalent to the following general form,

[0011] ,

[0012] Where N is the number of fractional differential equations, x1~x N There are N unknown quantities to be determined, D α x i (t) is the i-th unknown quantity x i The α-order differential operator with respect to time t, α1~α Nare the fractional orders of the N fractional equations; F1~F N are the right-hand side functions of N fractional-order differential equations, s1(t)~s N (t) are the external inputs of N fractional-order differential equations;

[0013] According to the definition of Grünwald-Letnikov fractional differential, the fractional differential equations are discretized to derive a method that can be implemented in hardware to calculate the nth discrete time point t n The quantity to be determined at any time x1~x N The numerical recursion formula of

[0014] ,

[0015] Where L is the expansion series of numerical calculation, h is the interval step size of discrete time points; ω i (r) is the coefficient of the ith consecutive multiplication and accumulation term of the rth differential equation; F r (x1,x2...x N ,s r (t n-1 )) is t n-1 The value of the right-hand side function of the differential equation at time r, whose input parameter is t n-1 x1~x at time N , and external excitation signal s i (t n-1 );

[0016] Its characteristics include:

[0017] N pipelined multiplication and accumulation modules are used to calculate the second terms of the right-hand side expressions of the N numerical recursive formulas respectively. , r=1~N;

[0018] N pipelined right-hand side function calculation modules are respectively used to calculate the first term of the right-hand side expressions of the N numerical recursive formulas. , r=1~N;

[0019] N estimation correction modules, respectively used to correct the output results of the N pipelined right-side function calculation modules;

[0020] N recursive modules are used to calculate the results of the right-hand side expressions of the N numerical recursive formulas, and recursively output the next group x1~x N The value of

[0021] The global reset signal, when set to the valid level, the unknown quantity of the fractional differential equation system is set to the initial value x 1,0 ~x N,0, otherwise, the operation of the recursive formula is performed;

[0022] The fractional order differential equation solving circuit inputs N groups of external excitation signals s in each clock cycle. r (t n-1 ), r=1~N; at the same time, recursively output the next group, which is the same as the current time t n-1 t with interval h n N groups of numerical solutions x1(t n )~x N (t n ).

[0023] The hardware solving circuit for the fractional differential equation system is characterized in that it contains N pipelined multiplication and accumulation modules, and completes one accumulation of L-level expansion terms in each clock cycle, and accumulates successively in L-1 cycles, and the intermediate result after each level of accumulation is saved in the accumulation register of the level; the rth pipelined multiplication and accumulation module includes:

[0024] L multipliers M C.1 ~M C,L , L-1 adders A C.1 ~A C,L-1 and L-1 accumulator registers R C.1 ~R C,L-1 ;

[0025] The module input is the output x of the recursive module r,f , the output is the first adder A C.1 Output C;

[0026] The i-th multiplier M C.i The two input terminals are x r.f and the coefficient of the continuous multiplication and accumulation term ω in the numerical recursion formula i (r) ;

[0027] The i-th adder A C.i The two input terminals are M C.i The output of R C.i Output:

[0028] The ith accumulation register R C.i , the input end is the output of the i+1th adder;

[0029] The R C.1 ~R C,L-1 Both have a reset terminal to connect to the global reset signal.

[0030] The hardware circuit for solving the fractional-order differential equations is characterized in that it contains N pipelined right-hand side function calculation modules, and the rth module includes:

[0031] The right-hand side function expression F r The corresponding large-scale combinational logic operation circuit;

[0032] The combinational logic circuit is divided into W r The W pipeline is a small-scale, delay-balanced pipeline. r Combinational logic blocks;

[0033] A set of pipeline registers is inserted after each level of combinational logic blocks to temporarily store the intermediate results of the combinational logic output of the pipeline at that level;

[0034] The input of this module is the output x1 of N recursive modules. f ~x N , f and external input signals r , output f r,in It is the output of the last stage pipeline register.

[0035] The hardware solving circuit for fractional differential equations is characterized in that it comprises N estimation correction modules, the rth module being used to correct the introduced W r The delay of the function calculation module on the right side after the pipeline stage is W r +1 cycle output f r,in ,include:

[0036] t n At this moment, the input of this module is f r,in , the output is the estimated corrected t n-1 Moment f r,out ;

[0037] Register R1, input is the f r,in , the output is f r,in2 , used to temporarily store the output results of the current right-hand function calculation module;

[0038] Subtractor S1, whose two inputs are respectively, the f r,in and f r,in2 , used to estimate the right-hand side function F r First-order difference in time;

[0039] The two inputs of multiplier M1 are the output of the subtractor and the constant W. r +1; output Δf r.in ;

[0040] Adder A1, whose two inputs are, Δf r,in and f r,in , whose output is the estimated t n-1 Time Fr The value of

[0041] Register R2 is used to temporarily store the output result of A1. Its input is the output of A1 and its output is f r,out That is the output of this module;

[0042] The right-hand function calculation module has W from input to output r The lag of one clock cycle plus the lag of one clock cycle introduced by register R2 inside this module is W r +1 cycle, so the first-order difference approximation F r The corrected formula is:

[0043] ;

[0044] When the number of pipeline stages W r When the optimization value is 1 or 3, the Δf in the correction formula is r,in ×(W r +1) can be further simplified; for fixed-point numbers, the multiplication is simplified to left shifting 1 or 2 bits; for floating-point numbers, the multiplication is simplified to adding 1 or 2 to the exponent.

[0045] The hardware circuit for solving the fractional differential equation system is characterized in that it contains N recursive modules, and the rth module includes:

[0046] Its input is the output f of the estimation correction module r,out , and the output C of the multiplication and accumulation module; its output is the solution x of the unknown quantity r,f ;

[0047] Multiplier M2, whose two inputs are f r,out and constant h ɑr , where ɑ r is the fractional order of the rth differential equation;

[0048] Subtractor S2, whose two inputs are the output of the multiplier and the output C of the multiplication and accumulation module, has an output x r,s ;

[0049] Module W r +1 counter cnt, counting range 0~W r , the global reset signal is cancelled and the counting starts. When the count reaches W r Stop at number W r On, it will return to zero after the next global reset;

[0050] The two inputs of the two-choice data selector MUX are the x r,s and x r Initial value x r,0, the strobe signal is the cnt count value is W r , when the condition is met, it outputs x r,m Strobe x r,s , otherwise select x r,0 ;

[0051] Register R3, whose input is the output x of the MUX r,m , the output of which is the x r,f .

[0052] In a second aspect, the present invention proposes a pipeline-structured hardware solution method for a group of fractional-order differential equations.

[0053] The invention is characterized in that the multiplication and accumulation module and the recursion module work in parallel and collaboratively to realize the recursion algorithm for numerical solution of Grünwald-Letnikov fractional-order differential equations; the right-hand side function calculation module of the differential equation adopts a pipeline structure; the estimation and correction module is used to solve the output hysteresis problem of the right-hand side function operation module of the differential equation introduced by the pipeline structure; the solution method of the rth fractional-order differential equation comprises the following steps:

[0054] Step S1, applying a global reset signal to reset all registers;

[0055] Step S2, front W r clock cycles, x r Assign initial value to x r,0 , then x r Assign the value x of the previous recursive update r,f ;

[0056] Step S3A.1, x r,f Enter W r The right-hand function operation module of the pipeline outputs f r,in ;

[0057] Step S3A.2, f r,in Send it to the estimation correction module to estimate the value of the function on the right at the current time point f r,out ;

[0058] Step S3B, x r,f Send it to the continuous multiplication and accumulation module and output C;

[0059] Step S4, the above C and f r,out Substitute into the recursive module and calculate x r The value x at the next time point r,m ;

[0060] Step S5, x r,m Stored in register R3 as x for the next iteration r,f ;

[0061] Among them, steps S3A.1 and S3A.2 are executed in sequence, and the two together are parallel with step S3B in time, and the three together constitute step S3; steps S1, S2, S3, S4, and S5 are executed in the order of numbers. BRIEF DESCRIPTION OF THE DRAWINGS

[0062] Figure 1 It is the overall schematic diagram of the fractional differential equation solving circuit;

[0063] Figure 2 It is the schematic diagram of the continuous multiplication and accumulation module in the fractional differential equation solving circuit;

[0064] Figure 3 It is a flow chart of the calculation method of the circuit for solving fractional differential equations;

[0065] Figure 4 is a circuit schematic diagram corresponding to an embodiment of the present invention;

[0066] Figure 5 is a function graph of a numerical solution obtained by hardware simulation and software calculation in the above embodiment;

[0067] Figure 6 It is a local detail of the simulation timing diagram of the fractional differential equation solving circuit. DETAILED DESCRIPTION

[0068] The technical solution of the present invention is further illustrated below with reference to the accompanying drawings and through specific implementation cases.

[0069] Without loss of generality, let's take solving the following system of fractional differential equations containing 2 equations as an example:

[0070]

[0071] Among them, u(t) is the external input excitation signal, which is set as a square wave here; y(t) and z(t) are the unknown quantities to be solved in the differential equations. The initial values ​​of y and z at time t=0 are 0.2 and 0.9 respectively; the fractional orders of the two equations are 0.9 and 0.8 respectively. The time t of the numerical solution ranges from 0 to 10, and the time step h=0.01.

[0072] Real number operations can be implemented using floating-point numbers or fixed-point numbers. In this case, floating-point numbers use half-precision type; fixed-point numbers use a 6-bit integer part (including the highest sign bit) and an 18-bit decimal part format. The range and accuracy of the calculation results of the above two implementations meet the requirements; the circuit area of ​​the fixed-point version is smaller.

[0073] refer to Figure 1 , the overall schematic diagram of the circuit for solving fractional-order differential equations is given. Figure 1The internal circuit structure of the multiplication and accumulation module is referenced Figure 2 .

[0074] The following combines an estimation correction module, a recursive module and a continuous multiplication and accumulation module corresponding to an equation in the equation group into a General solver .

[0075] This case has two differential equations, so two general solvers A and B are needed to give the numerical solutions of y and z at each discrete time point with an interval of h in the form of time series, and output the solution of one time point in one CLK cycle. General solvers A and B each have a paired right-hand function calculation module F A and F B , which are used to calculate the values ​​of the functions on the right sides of the two differential equations in the equation group. The outputs y and z of the general solvers A and B, and the external input excitation signal u(t), are F A and F B The input of the module. A and F B The modules adopt a pipeline structure, and in this case the number of pipeline stages for both is 1.

[0076] The coefficients ω1~ω in the two consecutive multiplication and accumulation modules in A and B L , calculated according to the following formulas:

[0077]

[0078] The following explains Figure 1 The circuit shown here works by solving a single differential equation. For the corresponding calculation flow chart, refer to Figure 3 The circuit for solving the entire differential equation system is shown in Figure 2. Figure 4 .

[0079] Before starting the general solver, the external circuit first gives a global reset pulse. Figure 1 and Figure 2 All DQ flip-flops in the circuit are reset to clear data storage units such as accumulator registers. After the reset signal is released, the universal solver starts to work. In the first clock cycle after the start, the y0 and z0 branches in the two-to-one data selector are selected as the iterative initial values ​​of the two quantities y and z. In each subsequent clock cycle, the circuit sequentially gives the numerical solutions of the quantities y and z at each discrete time point with an interval of h.

[0080] t n-1 The numerical solution of the differential equation y(t n-1 ), and the external input excitation signal u(t n-1), as the input of the right-hand function operation module of the first-level pipeline structure. This module gives the value of the right-hand function under this input after a lag of 1 clock cycle; the current output of this module is the value of the right-hand function F 1 cycle ago A (t n-2 ) and F B (t n-2 ).

[0081] In order to overcome the output lag problem introduced by the above pipeline structure, the function operation module F A and F B The output hysteresis value is sent to the estimation correction module in A and B for correction. Under the first-order difference approximation, at the current moment F A (t n-1 ) and F B (t n-1 ) can be obtained by the hysteresis value F A (t n-2 ) and F B (t n-2 ) and other estimates:

[0082]

[0083] The multiplication by 2 is due to the fact that the pipeline of the function calculation module on the right has a lag of 1 clock cycle from input to output, plus a lag of 1 clock cycle introduced by register R2 inside the estimation correction module, for a total of 2 clock cycles. The multiplication by 2 operation can be further optimized: for fixed-point numbers, it is simplified to left shift by 1; for floating-point numbers, it is simplified to exponent plus 1.

[0084] According to the fractional order Grünwald-Letnikov definition, the recursive formula for the numerical solution of y and z at each discrete time point with an interval of h is derived as follows:

[0085]

[0086] Among them, the first term F on the right side of the recursive formula A (t n-1 ) and F B (t n-1 ) corresponds to the output of the estimation correction module, the second term corresponds to the output C of the multiplication and accumulation module; L is the number of approximate expansion and truncation terms of the accumulation and summation.

[0087] The outputs of the estimation correction module and the continuous multiplication and accumulation module are sent to the recursive module to recursively calculate the next time point t n The numerical solution of y and z is s and z s .

[0088] Reference Figure 1Circuit, the recursive modules of the general solvers A and B respectively, realize the above y through the two-choice data selector MUX and cnt counter s and y0, z s When the cnt counter counts from 0 to W, it stops counting, and the number remains at W until it returns to zero after the next global reset. When the count value of cnt is not equal to W, the MUX selects the output of the initial values ​​y0 and z0; when the count value is equal to W, the MUX selects the output of y s and z s .

[0089] After the first W clock cycles, the output of MUX after selection is the next time point t n The numerical solution of the differential equation y(t n ) and z(t n ); both are connected to the input of register R3 in the general solver. In the next clock cycle, y(t n ) and z(t n ) is sent from the output end of R3 to the continuous multiplication and accumulation module and the right-hand function calculation module as the input y(t n-1 ) and z(t n-1 ) to implement a recursive algorithm for numerical solutions.

[0090] By repeating the recursive iteration in this way, the solver can continuously output the numerical solutions of the quantities y and z at each discrete time point with an interval of h when each clock trigger edge arrives.

[0091] The hardware circuit of this case is implemented with Verilog HDL and functional simulation is performed; the software calculation is implemented with C language programming. The latter has no lag introduced by the pipeline and serves as the reference solution of the fractional differential equation system. When the number of terms L=40, the function graphs of the software reference solutions (y-exact and z-exact) and the hardware simulation numerical solutions (y-sim and z-sim) of y and z are shown in Figure 2. Figure 5 ;The hardware simulation and software calculation results are highly consistent.

[0092] For details of the circuit simulation timing diagram, refer to Figure 6 This figure shows how the differential equation solving circuit works, listing the local details of the following groups of signals: the outputs y and z of the two general solvers; and the outputs F of the two function calculation modules. A and F B It can be seen that the circuit can respond to the external input excitation signal u(t) in real time within a single clock cycle, and can output the numerical solutions of the differential equations at each discrete time point in sequence and continuously within a single clock cycle.

[0093] For more complex function calculation modules, the number of pipeline stages can be appropriately increased, which will significantly improve the circuit operation speed. However, on the other hand, the area and power consumption of the circuit will also increase. In practical applications, the setting of the number of pipeline stages should be weighed according to needs.

[0094] It should be noted that the case described above is only one embodiment of the present invention, not all embodiments; the details involved in the above description and the reference drawings are only exemplary illustrations of the present invention, not limitations of the present invention. In other embodiments of the present invention, the method may have more, fewer or different steps. Based on the embodiments of the present invention, all other embodiments obtained by technicians without making creative work are within the scope of protection of the present invention.

Claims

1. A pipeline structured fractional order differential equation hardware solving circuit, used to solve a fractional order differential equation that can be equivalent to the following general form, ， Where N is the number of fractional differential equations, x1~x N There are N unknown quantities to be determined, D α x i (t) is the i-th unknown quantity x i The α-order differential operator with respect to time t, α1~α N are the fractional orders of the N fractional equations; F1~F N are the right-hand side functions of N fractional-order differential equations, s1(t)~s N (t) are the external inputs of N fractional-order differential equations; According to the definition of Grünwald-Letnikov fractional differential, the fractional differential equations are discretized to derive a method that can be implemented in hardware to calculate the nth discrete time point t n The quantity to be determined at any time x1~x N The numerical recursion formula of ， Where L is the expansion series of numerical calculation, h is the interval step size of discrete time points; ω i (r) is the coefficient of the ith consecutive multiplication and accumulation term of the rth differential equation; F r (x1,x2...x N ,s r (t n-1 )) is t n-1 The value of the right-hand side function of the differential equation at time r, whose input parameter is t n-1 x1~x at time N , and external excitation signal s i (t n-1 ); Its characteristics are: include: N pipelined multiplication and accumulation modules are used to calculate the second terms of the right-hand side expressions of the N numerical recursive formulas respectively. , r=1~N; N pipelined right-hand side function calculation modules are respectively used to calculate the first term of the right-hand side expressions of the N numerical recursive formulas. , r=1~N; N estimation correction modules, respectively used to correct the output results of the N pipelined right-side function calculation modules; N recursive modules are used to calculate the results of the right-hand side expressions of the N numerical recursive formulas, and recursively output the next group x1~x N The value of The global reset signal, when set to the valid level, the unknown quantity of the fractional differential equation system is set to the initial value x 1,0 ~x N,0 , otherwise, the operation of the recursive formula is performed; The fractional order differential equation solving circuit inputs N groups of external excitation signals s in each clock cycle. r (t n-1 ), r=1~N; at the same time, recursively output the next group, which is the same as the current time t n-1 t with interval h n N groups of numerical solutions x1(t n )~x N (t n ).

2. The hardware circuit for solving fractional order differential equations according to claim 1, characterized in that: Contains N pipelined multiplication and accumulation modules, which complete one accumulation of L-level expansion items in each clock cycle, and accumulate successively in L-1 cycles. The intermediate results after each stage of accumulation are saved in the accumulation register of that stage; The rth pipelined multiplication-accumulation module includes: L multipliers M C.1 ~M C,L , L-1 adders A C.1 ~A C,L-1 and L-1 accumulator registers R C.1 ~R C,L-1 ; The module input is the output x of the recursive module r,f , the output is the first adder A C.1 Output C; The i-th multiplier M C.i The two input terminals are x r.f and the coefficient of the continuous multiplication and accumulation term ω in the numerical recursion formula i (r) ; The i-th adder A C.i The two input terminals are M C.i The output of R C.i Output: The ith accumulation register R C.i , the input end is the output of the i+1th adder; The R C.1 ~R C,L-1 Both have a reset terminal to connect to the global reset signal.

3. The hardware circuit for solving fractional order differential equations according to claim 1, characterized in that: Contains N pipelined right-hand function calculation modules, the rth module includes: The right-hand side function expression F r The corresponding large-scale combinational logic operation circuit; The combinational logic circuit is divided into W r The W pipeline is a small-scale, delay-balanced pipeline. r Combinational logic blocks; A set of pipeline registers is inserted after each level of combinational logic blocks to temporarily store the intermediate results of the combinational logic output of the pipeline at that level; The input of this module is the output x1 of N recursive modules. f ~x N , f and external input signals r , output f r,in It is the output of the last stage pipeline register.

4. The hardware circuit for solving fractional order differential equations according to claim 1, characterized in that: Contains N estimation correction modules, the rth module is used to correct the introduction of W r The delay of the function calculation module on the right side after the pipeline stage is W r +1 cycle output f r,in ,include: t n At this moment, the input of this module is f r,in , the output is the estimated corrected t n-1 Moment f r,out ; Register R1, input is the f r,in , the output is f r,in2 , used to temporarily store the output results of the current right-hand function calculation module; Subtractor S1, whose two inputs are respectively, the f r,in and f r,in2 , used to estimate the right-hand side function F r First-order difference in time; The two inputs of multiplier M1 are the output of the subtractor and the constant W. r +1; output Δf r.in ; Adder A1, whose two inputs are, Δf r,in and f r,in , whose output is the estimated t n-1 Time F r The value of Register R2 is used to temporarily store the output result of A1. Its input is the output of A1 and its output is f r,out That is the output of this module; The right-hand function calculation module has W from input to output r The lag of one clock cycle plus the lag of one clock cycle introduced by register R2 inside this module is W r +1 cycle, so the first-order difference approximation F r The corrected formula is: ； When the number of pipeline stages W r When the optimization value is 1 or 3, the Δf in the correction formula is r,in ×(W r +1) can be further simplified; for fixed-point numbers, the multiplication is simplified to left shifting 1 or 2 bits; for floating-point numbers, the multiplication is simplified to adding 1 or 2 to the exponent.

5. The hardware circuit for solving fractional order differential equations according to claim 1, characterized in that: Containing N recursive modules, the rth module includes: Its input is the output f of the estimation correction module r,out , and the output C of the multiplication and accumulation module; its output is the solution x of the unknown quantity r,f ; Multiplier M2, whose two inputs are f r,out and the constant h ɑr , where ɑ r is the fractional order of the rth differential equation; Subtractor S2, whose two inputs are the output of the multiplier and the output C of the multiplication and accumulation module, has an output x r,s ; Module W r +1 counter cnt, counting range 0~W r , the global reset signal is cancelled and the counting starts. When the count reaches W r Stop at number W r On, it will return to zero after the next global reset; The two inputs of the two-choice data selector MUX are the x r,s and x r Initial value x r,0 , the strobe signal is the cnt count value is W r , when the condition is met, it outputs x r,m Strobe x r,s , otherwise select x r,0 ; Register R3, whose input is the output x of the MUX r,m , the output of which is the x r,f .

6. A pipeline structured hardware solution method for fractional order differential equations, characterized in that: The multiplication and accumulation module and the recursion module work in parallel and collaboratively to realize the recursion algorithm for numerical solution of Grünwald-Letnikov fractional-order differential equations; the function calculation module on the right side of the differential equation adopts a pipeline structure; The estimation correction module is used to solve the problem of output hysteresis of the function operation module on the right side of the differential equation introduced by the pipeline structure; The method for solving the rth fractional-order differential equation comprises the following steps: Step S1, applying a global reset signal to reset all registers; Step S2, front W r clock cycles, x r Assign initial value to x r,0 , then x r Assign the value x of the previous recursive update r,f ; Step S3A.1, x r,f Enter W r The right-hand function operation module of the pipeline outputs f r,in ; Step S3A.2, f r,in Send it to the estimation correction module to estimate the value of the function on the right at the current time point f r,out ; Step S3B, x r,f Send it to the continuous multiplication and accumulation module and output C; Step S4, the above C and f r,out Substitute into the recursive module and calculate x r The value x at the next time point r,m ; Step S5, x r,m Stored in register R3 as x for the next iteration r,f ; Among them, steps S3A.1 and S3A.2 are executed in sequence, and the two together are parallel with step S3B in time, and the three together constitute step S3; steps S1, S2, S3, S4, and S5 are executed in the order of numbers.

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