Deadlock checking method of integrated circuit

Abstract

The invention discloses a deadlock checking method for an integrated circuit. The deadlock checking method comprises the following steps: extracting a finite-state machine; generating a security attribute according to the reachable state of each state, and generating an active attribute according to each state transition condition; marking transfer paths existing among all the states, and marking the transfer path through which the security attribute and the active attribute pass as a first mark; traversing the transfer path, for the currently traversed transfer path, judging whether the states of the two ends of the currently traversed transfer path have the transfer path with the first mark, if not, marking the currently traversed transfer path as a second mark, if so, judging whether the states of the two ends of the currently traversed transfer path have the transfer path changing from the first mark to the second mark, and if not, marking the currently traversed transfer path as the second mark; if so, marking the currently traversed transfer path as a second mark, otherwise, marking the currently traversed transfer path as a first mark; and judging whether the integrated circuit has deadlock or not according to the marks of all the transfer paths. According to the invention, the deadlock in the integrated circuit can be effectively checked in a low-cost manner.

Description

Technical Field

[0001] The present invention relates to the technical field of formal verification of integrated circuits, and in particular to a deadlock checking method for integrated circuits. Background Art

[0002] Deadlock occurs when an integrated circuit design enters a state from which it can never escape, or once it enters a state, it remains in that state by avoiding opportunities to escape.

[0003] It is almost impossible to check deadlocks through simulation in integrated circuit design. The main reasons are: 1) It is impossible to directly detect whether the design will deadlock as in the simulation; 2) It is impossible to determine through simulation whether it has entered a state that can never be escaped or has stayed in this state for some reason; 3) The correct stimulus must be provided to find deadlocks through simulation. The computational complexity of checking deadlocks through simulation technology is N*f(T), where N is the number of states of the finite state machine and f(T) is the number of cycles of the finite state machine jump. In order to ensure the completeness of the check, f(T) will be much larger than N, so the cost of finding deadlocks through simulation is very high.

[0004] Therefore, how to perform fast deadlock check on the design of integrated circuits is a technical problem to be solved. Summary of the invention

[0005] In order to solve the technical problem that the deadlock problem in the integrated circuit cannot be quickly checked in the prior art, the present invention proposes a deadlock checking method for the integrated circuit.

[0006] The deadlock detection method of an integrated circuit proposed by the present invention comprises:

[0007] Generate safety properties based on the reachable states of each state, and generate liveness properties based on each state transition condition;

[0008] Marking the transition paths existing between all states, wherein the transition path through which the safety attribute and the activity attribute pass is marked as a first mark;

[0009] Traverse all transfer paths, and for the currently traversed transfer path, determine whether there is a transfer path with the first mark in the states at both ends of the transfer path. If not, the currently traversed transfer path is marked with the second mark. If so, determine whether there is a transfer path whose states at both ends change from the first mark to the second mark. If so, the currently traversed transfer path is marked with the second mark, otherwise it is marked with the first mark.

[0010] After all the transfer paths are traversed, it is determined whether the integrated circuit is deadlocked based on the marks of all the transfer paths.

[0011] Furthermore, the first mark and the second mark are respectively represented by at least one character.

[0012] Furthermore, when the transition paths through which the safety attribute and the liveness attribute pass are marked, the remaining transition paths are marked as temporary marks.

[0013] Furthermore, the temporary mark is represented by at least one character.

[0014] Furthermore, the characters include at least one of numbers, letters, Chinese characters, and symbols.

[0015] Further, judging whether the integrated circuit is deadlocked according to the marks of all the transfer paths includes:

[0016] When the flag of the transfer path has the second flag, it is determined that the integrated circuit is deadlocked.

[0017] Further, judging whether the integrated circuit is deadlocked according to the marks of all the transfer paths includes:

[0018] When the marks of the transfer paths are all the first marks, it is determined that there is no deadlock in the integrated circuit.

[0019] The present invention automatically generates safety attributes and activity attributes by extracting the reachable states and transfer conditions of the finite state machine, and then marks the known safe transfer paths, traverses the transfer paths, marks the transfer paths that may deadlock when there are transfer paths, and updates them if there are none, and finally determines whether there is a deadlock based on the final mark of the transfer path, thereby achieving the effect of automatically checking deadlock. Compared with simulation technology, the present invention does not require writing test stimuli, does not require iterating different cycles, and checks deadlock problems more completely by traversing the entire state space. In addition, compared with the computational complexity of simulation, the computational complexity of this technology is N 2 , where N is the number of states of the finite state machine. The longer the simulation cycle, the more obvious the advantage of this technology. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] The present invention is described in detail below with reference to the embodiments and accompanying drawings, wherein:

[0021] Figure 1 is a flow chart of an embodiment of the present invention.

[0022] Figure 2 It is a state transition diagram of a finite state machine according to an embodiment of the present invention.

[0023] Figure 3 It is a schematic diagram of marking in a path traversal process according to an embodiment of the present invention. DETAILED DESCRIPTION

[0024] In order to make the technical problems, technical solutions and beneficial effects to be solved by the present invention more clearly understood, the present invention is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not used to limit the present invention.

[0025] Thus, a feature indicated in this specification will be used to illustrate one of the features of an embodiment of the present invention, rather than implying that each embodiment of the present invention must have the described feature. In addition, it should be noted that this specification describes many features. Although some features can be combined together to illustrate possible system designs, these features can also be used in other combinations that are not explicitly described. Thus, unless otherwise stated, the described combinations are not intended to be limiting.

[0026] like Figure 1 As shown, the deadlock detection method of the integrated circuit proposed by the present invention mainly includes the following steps.

[0027] Extract finite state machines from design files for integrated circuits.

[0028] Determine the states that the finite state machine can reach and the transition conditions for each state.

[0029] For example, suppose a finite state machine has three states A, B, and C, where the next state of A is B, and the condition for the jump is that the input is 1. Then for A, B is its reachable state, and the condition for the state to transfer is that the input is 1.

[0030] Safety properties are generated based on the reachable states of each state, and liveness properties are generated based on each state transition condition.

[0031] For example, a finite state machine has three states A, B, and C, where A's next state is B. For A, its safety property is that A's next state will not be A or C. If a finite state machine has three states A, B, and C, where A's next state is B, then for A, its liveness property is that A's next state will eventually be B.

[0032] Mark the transition paths between all states, and mark the transition paths that pass the safety attribute and the liveness attribute as the first mark. Since there will be no deadlock in the transition paths involved in the safety attribute and the liveness attribute, the transition path can be marked as the first mark, that is, a mark that does not exist in deadlock.

[0033] Traverse all the transition paths, and for the currently traversed transition path, determine whether there is a transition path with the first mark in the states at both ends of the transition path. If not, the currently traversed transition path is marked with the second mark. If so, determine whether there is a transition path with the states at both ends changing from the first mark to the second mark. If so, the currently traversed transition path is marked with the second mark, otherwise it is marked with the first mark. In specific implementation, the traversal can be started from the transition path involved in the start state.

[0034] After all the transfer paths are traversed, it is determined whether the integrated circuit is deadlocked based on the marks of all the transfer paths.

[0035] The present invention extracts the finite state machine of the integrated circuit, generates corresponding security attributes and activity attributes, marks each transfer path, and updates the transfer path mark according to the states at both ends of the transfer path. Finally, it is determined whether a deadlock exists by the transfer path mark. Compared with the prior art, the present invention is simpler and easier to implement.

[0036] In one embodiment, the first mark and the second mark are respectively represented by at least one character.

[0037] The implementation of the present invention can ultimately realize automatic deadlock checking through programming, so at least one character is used to represent it, which is conducive to automatic implementation.

[0038] In one embodiment, when the transition paths through which the safety attribute and the liveness attribute pass are marked, the remaining transition paths are marked as temporary marks.

[0039] Since other transfer paths are uncertain, for the sake of easy observation, other transfer paths can be marked as temporary marks.

[0040] Likewise, the temporary mark may also be represented by at least one character.

[0041] The characters of the present invention include at least one of numbers, letters, Chinese characters, and symbols. For example, the first mark is represented by 1, the temporary mark is represented by 0, the second mark is represented by 2, etc. Those skilled in the art can design each mark according to their own naming habits.

[0042] In a further embodiment, determining whether the integrated circuit is deadlocked according to the marks of all the transfer paths includes:

[0043] When the flag of the transfer path has the second flag, it is determined that the integrated circuit is deadlocked.

[0044] When the marks of the transfer paths are all the first marks, it is determined that there is no deadlock in the integrated circuit.

[0045] Let's assume that the following is extracted from an integrated circuit: Figure 2 The finite state machine shown.

[0046] It can be seen that the finite state machine has four states, namely start, IDLE, CLEAR, and STOP. Taking the state Start as an example, its next state can be Start itself, IDLE, or STOP. The transition condition from the state START to the state IDLE is rst_n, and the transition condition from the state START to the state STOP is A==0, where rst_n and A are variables.

[0047] Therefore, a safety property can be generated: the next state of state START will not be state CLEAR.

[0048] If the arrow in the middle of START→STOP is taken as the currently traversed transfer path X, then the states at both ends of the transfer path X are START and STOP. There are three transfer paths corresponding to START, path 1: START→START, path 2: START→IDEL, path 3: START→STOP.

[0049] like Figure 3 As shown, if after verifying the safety property and the liveness property, paths 1 and 2 pass and are marked as 1, and path 3 fails and is marked as 0, because path 3 is not marked as 1, then path 3 is marked as 2. If there is a path marked as 2 in the finite state machine, then the finite state machine is deadlocked.

[0050] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions and improvements made within the spirit and principles of the present invention should be included in the protection scope of the present invention.

Claims

1. A deadlock detection method for an integrated circuit, characterized in that: include: Extract finite state machines from integrated circuit design files; Determine the states that the finite state machine can reach and the transition conditions for each state; Generate safety properties based on the reachable states of each state, and generate liveness properties based on each state transition condition; Marking the transition paths existing between all states, wherein the transition path through which the safety attribute and the activity attribute pass is marked as a first mark; Traverse all transfer paths, and for the currently traversed transfer path, determine whether there is a transfer path with the first mark in the states at both ends of the transfer path. If not, the currently traversed transfer path is marked with the second mark. If so, determine whether there is a transfer path whose states at both ends change from the first mark to the second mark. If so, the currently traversed transfer path is marked with the second mark, otherwise it is marked with the first mark. After all the transfer paths are traversed, it is determined whether the integrated circuit is deadlocked based on the marks of all the transfer paths.

2. The deadlock detection method of an integrated circuit as claimed in claim 1, characterized in that: The first mark and the second mark are respectively represented by at least one character.

3. The deadlock detection method of an integrated circuit as claimed in claim 1, characterized in that: When the transition paths through which the safety attribute and the liveness attribute pass are marked, the remaining transition paths are marked as temporary marks.

4. The deadlock detection method of an integrated circuit as claimed in claim 1, characterized in that: The temporary mark is represented by at least one character.

5. The deadlock detection method of an integrated circuit as claimed in claim 2 or 4, characterized in that: The characters include at least one of numbers, letters, Chinese characters, and symbols.

6. The deadlock detection method for an integrated circuit according to any one of claims 1 to 5, characterized in that: Judging whether an integrated circuit has a deadlock based on the marks of all transfer paths includes: When the flag of the transfer path has the second flag, it is determined that the integrated circuit is deadlocked.

7. The deadlock detection method for an integrated circuit according to any one of claims 1 to 5, characterized in that: Judging whether an integrated circuit has a deadlock based on the marks of all transfer paths includes: When the marks of the transfer paths are all the first marks, it is determined that there is no deadlock in the integrated circuit.

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