Chip surface defect detection method

Abstract

The invention provides a chip surface defect detection method which comprises the following steps: positioning a chip to obtain a to-be-detected area, and cutting the to-be-detected area to obtain a to-be-detected image; the terminal obtains an image path and sends a detection request to the appearance defect detection system; the method comprises the following steps: inputting images as input quantities in batches into a chip appearance defect detection system, starting multi-thread detection, performing complete detection on one image as a thread, and processing a plurality of images at the same time; and returning the obtained result to the terminal and visualizing the result. The problems that an existing chip defect detection method is too high in manufacturing cost, unstable and low in efficiency are solved.

Description

Technical Field

[0001] The present invention relates to the technical field of chip detection, and in particular to a chip surface defect detection method. Background Art

[0002] Semiconductor chips are the most critical components of electronic products. In the process of informatization in various industries, semiconductor chips play an indispensable and important role. In the actual production process, various defects will appear on the surface. Therefore, defect detection on the chip appearance can avoid affecting the overall performance of the chip. It can also trace back the production process of the previous station based on the test results, which can effectively feedback the production process while reducing costs.

[0003] Currently, most of the known chip packaging substrate appearance defect detection relies on manual visual inspection and AOI (Automated Optical Inspection) equipment. Quality inspectors perform manual visual inspections on chips, but the high-intensity quality inspection work will cause visual fatigue of quality inspectors, resulting in a decrease in the accuracy of their inspections, which is far from meeting the needs of mass quality inspections.

[0004] AOI uses camera technology to output the reflected light intensity of the inspected object in a quantitative grayscale value, compares it with the grayscale value of the standard image, and analyzes and determines it with the set value for classification. However, the cost of AOI equipment is too high, and most of it relies on imports; AOI equipment detection is easily affected by factors such as lighting conditions, production batches, and equipment status during the production process. The apparent characteristics of the same type of defects, such as size, contrast, and grayscale value, show large changes, and the defect characteristics do not follow the same distribution; AOI equipment parameters are difficult to set, and it does not have good adaptability in complex environments. Summary of the invention

[0005] In view of this, the problem to be solved by the present invention is to provide a chip surface defect detection method.

[0006] In order to solve the above technical problems, the technical solution adopted by the present invention is: a chip surface defect detection method, comprising positioning the chip to obtain a region to be detected, and cutting the region to be detected to obtain an image to be detected;

[0007] The terminal obtains the image path and sends a detection request to the appearance defect detection system;

[0008] Input the batch of images as input to the chip appearance defect detection system, start multi-threaded detection, and perform a complete detection of one image as one thread, processing multiple images at the same time;

[0009] The obtained results are returned to the terminal and visualized.

[0010] In the present invention, preferably, positioning the chip is specifically performed by cropping part of the wafer image to obtain a wafer template image, obtaining the two-dimensional position information of the wafer template image, obtaining the two-dimensional position information of the area to be detected, and traversing the wafer template image on the image to be detected from left to right and from top to bottom to calculate the similarity between the wafer template image and the image to be detected.

[0011] In the present invention, preferably, after cropping, the angle offset of the four corners of the image to be detected is calculated using inverse trigonometric functions to perform angle correction, and the image position is corrected by affine transformation.

[0012] In the present invention, preferably, the same method as that of obtaining the wafer template image is adopted to obtain the wire template image and the wire contact template image, and the areas to be inspected are marked respectively to obtain the wire area and wire contact area to be inspected, which are marked and an information file is saved, wherein the information file contains the position information corresponding to each wire contact and wire on the wire template image and the wire contact template image.

[0013] In the present invention, preferably, after cropping the wire area, wire contact area and wafer area, corrected wire area to be detected image, wire contact area to be detected image and wafer area to be detected image of the same size as the wire template image, wire contact template image and wafer template image are obtained respectively.

[0014] In the present invention, preferably, the complete inspection includes: inputting the cropped wire area to be inspected image and the wire contact area to be inspected image into the trained MobelNetV3 convolutional neural network respectively to classify good products and defective products, marking the defective products in the image and recording the defect location information;

[0015] The wafer area is input into the trained Yolox target detection network model to detect foreign objects and scratches, and the coordinates of foreign objects and scratches are output and then marked and the defect location information is recorded;

[0016] The wafer scratches and foreign object defects detected by Yolox and the wire and wire contact defects detected by MobileNetV3 are summarized.

[0017] In the present invention, preferably, the similarity formula for calculating the wafer template image and the image to be detected is:

[0018] In the present invention, preferably, the process of calculating the angle offset is specifically to obtain the position information of the upper left corner (x0, y0) and the center point position information of the lower left corner (x2, y2) of the chip wafer, x0-x2 is obtained, y2-y0 is obtained, and the angle value θ is obtained by the inverse tangent function arctan, where θ is the chip angle deflection value, and the image angle offset caused by improper wafer placement during the production process is completed for the wire image, wire contact image, and wafer image respectively through the built-in cv2.getRotationMatrix2D() and cv2.warpAffine() functions in opencv.

[0019] In the present invention, preferably, the mathematical expression of the affine transformation is as follows:

[0020] The advantages and positive effects of the present invention are:

[0021] (1) Defect detection is performed on the acquired target area images, and image classification of wire contacts and wires is performed based on the improved MobileNetV3. MobileNetV3 is a lightweight neural network. While maintaining a high accuracy, it reduces the size of the model and the computational cost, and improves the running speed. However, the SE module in MobileNetV3 obtains nonlinear channel weights through global average pooling, full connection, and nonlinear activation functions. In order to reduce the number of parameters, the parameter r is set to reduce the dimension of the channel. The dimension reduction process will cause the SE module to lose important feature information, which will bring side effects to the SE module and the model. To address the above problems, the SE module in MobileNetV3 is replaced by the ECA module. The ECA module does not use the dimensionality reduction operation, but uses a lightweight one-dimensional convolution to obtain more accurate channel weights and realize cross-channel information interaction, realize the attention mechanism, better perform feature screening, and complete the detection task, solving the problems of the existing chip defect detection method being too expensive, unstable, and inefficient.

[0022] (2) Based on the improved Yolox target detection algorithm, the wafer part is inspected. In order to enhance the ability to identify small target defects and defects under complex backgrounds, the activation function Swish used in the backbone feature extraction network of the traditional Yolox target detection algorithm is improved to a smoother Mish activation function. The Mish activation function can still maintain a relatively high classification accuracy when the network is getting deeper and deeper, which is better than the Swish activation function. At the same time, the module of the backbone feature extraction network is improved, and the original 3×3 convolution is replaced with the CoT module, giving the backbone feature extraction network a more powerful global attention mechanism to complete the detection task. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] The accompanying drawings are used to provide a further understanding of the present invention and constitute a part of the specification. Together with the embodiments of the present invention, they are used to explain the present invention and do not constitute a limitation of the present invention. In the accompanying drawings:

[0024] Figure 1 It is a structural diagram of an implementation environment of a chip surface defect detection method of the present invention;

[0025] Figure 2 It is a structure diagram of the SE attention mechanism of a chip surface defect detection method of the present invention;

[0026] Figure 3 It is a network structure diagram of an ECA attention mechanism of a chip surface defect detection method of the present invention;

[0027] Figure 4 This is the traditional Yolox target detection algorithm network structure diagram;

[0028] Figure 5 It is a schematic diagram of a 3×3 convolution module of a chip surface defect detection method of the present invention;

[0029] Figure 6 It is a schematic diagram of a CoT module of a chip surface defect detection method of the present invention;

[0030] Figure 7 It is a schematic flow chart of a chip surface defect detection method of the present invention;

[0031] Figure 8 It is a complete chip image of a chip surface defect detection method of the present invention;

[0032] Fig. 9 A cut wafer is used as a template image in a chip surface defect detection method of the present invention;

[0033] Fig.10 It is a schematic diagram of the image angle deviation effect of a chip surface defect detection method of the present invention;

[0034] Fig.11 It is a schematic diagram of coordinate transformation effect of a chip surface defect detection method of the present invention;

[0035] Fig.12 It is a schematic diagram of the effect of a marking operation of a chip surface defect detection method of the present invention;

[0036] Fig.13 It is a schematic diagram of the effect after cutting of a chip surface defect detection method of the present invention;

[0037] Fig.14 It is a schematic diagram of classification of good and defective wires in a chip surface defect detection method of the present invention;

[0038] Fig.15 It is a schematic diagram of classification of good and defective wire contacts of a chip surface defect detection method of the present invention;

[0039] Fig.16 It is a schematic diagram of defective position information of defective marking of wires and wire contacts of a chip surface defect detection method of the present invention;

[0040] Fig.17 It is a defect summary schematic diagram of a chip surface defect detection method of the present invention;

[0041] In the figure: 101, camera end; 102, defect detection system; 103, hard disk. DETAILED DESCRIPTION

[0042] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0043] It should be noted that when a component is referred to as being "fixed to" another component, it may be directly on the other component or there may also be a component centered. When a component is considered to be "connected to" another component, it may be directly connected to the other component or there may also be a component centered. When a component is considered to be "set on" another component, it may be directly set on the other component or there may also be a component centered. The terms "vertical", "horizontal", "left", "right" and similar expressions used herein are for illustrative purposes only.

[0044] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art of the present invention. The terms used herein in the specification of the present invention are only for the purpose of describing specific embodiments and are not intended to limit the present invention. The term "and / or" used herein includes any and all combinations of one or more related listed items.

[0045] The present invention provides a chip surface defect detection method, comprising positioning the chip to obtain a to-be-detected area, and cutting the to-be-detected area to obtain an to-be-detected image;

[0046] The terminal obtains the image path and sends a detection request to the appearance defect detection system;

[0047] Input the batch of images as input to the chip appearance defect detection system, start multi-threaded detection, and perform a complete detection of one image as one thread, processing multiple images at the same time;

[0048] The obtained results are returned to the terminal and visualized.

[0049] In this embodiment, further, the chip is positioned specifically by cropping part of the wafer image to obtain a wafer template image, obtaining the two-dimensional position information of the wafer template image, obtaining the two-dimensional position information of the area to be detected, and traversing the wafer template image on the image to be detected from left to right and from top to bottom to calculate the similarity between the wafer template image and the image to be detected.

[0050] In this embodiment, further, after cropping, the angle offset of the four corners of the image to be detected is calculated using inverse trigonometric functions to perform angle correction, and the image position is corrected through affine transformation.

[0051] In this embodiment, further, the same method as that of obtaining the wafer template image is adopted to obtain the wire template image and the wire contact template image, and the areas to be inspected are marked respectively to obtain the wire area and wire contact area to be inspected, which are marked and an information file is saved, wherein the information file contains the position information corresponding to each wire contact and wire on the wire template image and the wire contact template image.

[0052] In this embodiment, further, after cropping the wire area, wire contact area, and wafer area, corrected wire area to be detected images, wire contact area to be detected images, and wafer area to be detected images of the same sizes as the wire template image, the wire contact template image, and the wafer template image are obtained respectively.

[0053] In this embodiment, further, the complete detection includes: inputting the cropped wire area to be detected image and the wire contact area to be detected image into the trained MobelNetV3 convolutional neural network respectively to classify good products and defective products, marking the defective products in the image and recording the defect location information;

[0054] The wafer area is input into the trained Yolox target detection network model to detect foreign objects and scratches, and the coordinates of foreign objects and scratches are output and then marked and the defect location information is recorded;

[0055] The wafer scratches and foreign object defects detected by Yolox and the wire and wire contact defects detected by MobileNetV3 are summarized.

[0056] In this embodiment, further, the similarity formula for calculating the wafer template image and the image to be detected is:

[0057] In this embodiment, further, the process of calculating the angle offset is specifically to obtain the position information of the upper left corner of the chip wafer (x0, y0) and the center point position information of the lower left corner (x2, y2), x0-x2 is used to obtain x, y2-y0 is used to obtain y, and the angle value θ is obtained by the inverse tangent function arctan, where θ is the chip angle deflection value. The built-in cv2.getRotationMatrix2D() and cv2.warpAffine() functions in opencv are used to complete the image angle offset caused by improper wafer placement during the production process for the wire image, wire contact image, and wafer image, respectively.

[0058] In this embodiment, further, the mathematical expression of the affine transformation is as follows:

[0059] See also Figure 1 , which shows a schematic diagram of the structure of the implementation environment involved in a chip appearance defect detection method provided by an embodiment of the present invention. Figure 1 As shown, the implementation environment includes a camera end 101, a defect detection system 102 and a hard disk 103. Among them, the defect detection system 102 is specifically in the form of a server, and the defect detection system 102 and the hard disk 103 are configured on the same server. The defect detection system 102 stores the image obtained from the camera in the hard disk 103, and then reads the image to be detected for detection.

[0060] The core algorithm of the defect detection system is divided into two parts, including the detection of wire contacts and wires based on the improved MobileNetV3 convolutional neural network, and the detection of foreign objects on the wafer based on the improved Yolox.

[0061] MobileNetV3 is a convolutional neural network. Unlike traditional computer vision technology, convolutional neural networks have a faster running speed while maintaining a high accuracy. MobileNetV3 uses the SE attention mechanism. For the structure of the SE attention mechanism, see Figure 2 ;

[0062] The SE attention mechanism is to assign different weights (or attention scores) to different parts of the input data, so that the model can identify the most important information. The SE attention mechanism compresses and stimulates the channel information in the input feature map, adaptively learns the importance of each channel, and thus improves the performance of the model. sq (u c ) represents the compressed structure, the compression operation F sq (u c ) is as follows:

[0063] Among them, U represents the input feature vector, and the compression operation is to compress the input features into a 1×1×C feature matrix without changing the number of channels through a global average pooling operation. Figure 2 Medium F ex (., W) represents the excitation structure. The excitation operation is to obtain the channel characteristics of the input channel. The 1×1×C feature matrix is ​​fully connected twice. A real number r is set that is lower than the number of channels C. The input 1×1×C is fully connected and ReLU activated to reduce the number of channels and increase nonlinearity. It is adjusted to 1×1×C / r to reduce the amount of calculation and redistribute the weights of the C-layer features. After the second full connection and Sigmoid nonlinear activation normalization, the input feature matrix channel is restored to 1×1×C. The characteristic of the Sigmoid activation function is to map the input value to between 0 and 1, which is the weight of each channel. The mathematical expression of the excitation operation is as follows: s=F ex (Z e , W) = σ(W2δ(W1Z c ))

[0064] The SE module obtains nonlinear channel weights through global average pooling, full connection, and nonlinear activation functions. In order to reduce the number of parameters, the parameter r is set to reduce the dimension of the channel. The dimension reduction process will cause the SE module to lose important feature information, which will bring side effects to the SE module and model. In order to better meet the needs of chip surface defect detection, the SE module in MobileNetV3 is improved to the ECA module to address the above problems. For the network structure of the ECA attention mechanism, see Figure 3 :

[0065] The ECA module does not use dimensionality reduction operations, but uses lightweight one-dimensional convolution to obtain more accurate channel weights and realize cross-channel information interaction, realize attention mechanism, and better perform feature screening. The ECA attention mechanism uses global average pooling operation in the first layer. Global average pooling transforms the input features of size H×W×C into a feature matrix of 1×1×C. The feature matrix contains the channel features of the input matrix, and then uses a one-dimensional convolution with a convolution kernel size of k to perform a convolution operation. After that, the Sigmond activation function is used to obtain the weights of each channel. k represents the size of the adjacent channels covered. Cross-channel information interaction is realized through convolution, but the setting of k is very important. The calculation formula of k is as follows:

[0066] C is the number of input channels, b=1, γ=2, the local cross-channel interaction information is completely independent of each other and the number of parameters is relatively small. All channels in the ECA attention mechanism share weights, and the weight calculation formula is as follows: C1D krepresents a one-dimensional convolution operation with a convolution kernel of k, where Represents the channel y i k adjacent channels, y i represents the channel, W i is channel y i The weight of

[0067] After obtaining the 1×1×C weight matrix, multiply it with the original feature map to obtain the feature map output under different weights. The SE attention mechanism is replaced by the ECA attention mechanism, which improves the model's feature expression ability and increases the model's receptive field while adding a few parameters, thus enhancing the ability of MobileNetV3 in chip appearance defect detection.

[0068] After preliminary preparation, the position information of each wire contact and wire part is obtained and cropped according to the position information. The cropped images are batch-input into the trained improved MobelNetV3 convolutional neural network model, and the GPU is used to improve the execution speed of the model, and the classification of good and defective products is obtained. The two-dimensional position information of the defective products is marked in the image and recorded to complete the detection task of this stage.

[0069] The detection performance of the Yolox target detection algorithm depends to a certain extent on the ability to extract features. There is still room for improvement in the accuracy of detecting small target defects, super large target defects, and surface defects that are difficult to detect under complex backgrounds that often appear on chip surface defects. For this reason, an improved Yolox algorithm is proposed to extract more effective target features and improve the model detection performance. The traditional Yolox target detection algorithm network structure can be found in Figure 4 ;

[0070] The overall YOLOX network structure is divided into three modules, including the backbone feature extraction network for extracting features, the enhanced feature extraction network for enhancing the output of the three different scales of the fused backbone feature extraction network, and the prediction part responsible for parsing and regressing the different scale outputs of the enhanced feature extraction network. This paper improves the bottleneck of the backbone feature extraction network and replaces the 3×3 convolution module in the bottleneck with the CoT (Contextual Transformer Block) attention mechanism. Compared with the 3×3 convolution module, the CoT attention mechanism belongs to the Transformer structure. The fusion of static and dynamic contextual feature representations output by the CoT attention mechanism on the basis of the Transformer greatly enhances the visual representation ability of the target detection model, and can adaptively allocate attention to different visual and language inputs, thereby better completing the target detection task. For the 3×3 convolution module and the CoT module, see Figure 5and Figure 6 ;

[0071] The CoT module integrates the representation and analysis of the contextual information of the input features and the learning of Self-Attention into the same structure. In the CoT module, for the input feature X, three variables Q = X, K = X, V = XW are first defined. v First, a k×k group convolution is performed on K, so that the obtained matrix has a certain local context information representation, denoted as K, which is equivalent to a static context representation on the local information. Then K and Q are concatenated, and then the concatenated result is convolved twice in succession. The formula is as follows: A = [K1, Q] W θ W δ .

[0072] Different from the traditional Self-Attention module, the A feature matrix in CoT is obtained by the feature interaction between the Query information and the Key local context information, rather than just the information position relationship between the Query and the Key. The CoT module further enhances the self-attention mechanism through the local context information representation of the K feature matrix. Finally, the AttentionMap A feature matrix is ​​dot-multiplied with the V feature matrix that has undergone a 1×1 convolution operation to learn the dynamic multi-head attention matrix, and finally the dynamic context information representation result is obtained. The formula is as follows:

[0073] The improvement of Yolox backbone feature extraction network does not require adding more parameters or computational overhead. The CoT module uses static and dynamic context information to more fully understand the input feature map, thereby improving visual recognition capabilities and enhancing Yolox's capabilities in chip appearance defect detection. After preliminary preparation, the position information of the wafer part is obtained and cropped according to the position information. The cropped image is input into the trained improved Yolox, and the GPU is used to improve the execution speed of the model. The position information and category of the detection target are inferred, and the two-dimensional position information and category of the target are annotated and recorded in the image to complete the detection task at this stage.

[0074] See also Figure 7 ;

[0075] 301. After the terminal obtains the image path, it sends a detection request to the appearance defect detection system and inputs the image batches into the system as input, starts multi-threading for simultaneous detection, and performs a complete detection of an image as one thread. The images are put into different threads in batches and multi-threading is started to detect the images in sequence. For the complete chip image, see Figure 8 , the wire, wire contact 1, wire contact 2, and wafer are marked in the image respectively.

[0076] 302. The chip appearance inspection tasks are divided into detecting whether there are foreign objects or scratches on the wafer; detecting whether the wires are missing or bent; and detecting whether the wire contacts are displaced or deformed. Considering the computing cost and response speed, the complex inspection tasks are split into simple and efficient single defect detection to improve production efficiency. Therefore, the complete chip image to be inspected is cropped separately, and defect detection is performed in the order of wafer inspection, wire inspection, and wire contact inspection. Since the mechanical transmission structure for photographing the chip appearance is not precise, the position of the chip in the image is not fixed. It is necessary to locate the chip and crop the part to be inspected before inspection. In the system preparation stage, the cropped wafer part is used as a template image, see Fig. 9 :

[0077] For the chip image with image size h, w, take the upper left corner as the coordinate origin, traverse from left to right, from top to bottom, and calculate from top to bottom to indicate the similarity between the template and the specific area of ​​the original image. The calculation formula is as follows:

[0078]

[0079] The best match is 0, the worse the match, the greater the match value. mid and mid Then, the two-dimensional position information of the wafer area to be inspected is obtained through the known width and height information from the center point of the template to the wafer boundary h0, w0, h1, w1, etc., and the area is cut for use. Similarly, the known width and height information from the center point of the template to the wire boundary and the wire contact boundary is used for cutting.

[0080] For the cropped wafer image, the upper left corner is used as the origin to obtain the upper left corner position information (x0, y0) and the lower left center point position information (x2, y2) of the chip wafer through the above positioning method. x0-x2 is used to obtain x, y2-y0 is used to obtain y, and the inverse tangent function arctan is used to obtain the angle value θ, which is the chip angle deflection value. The built-in cv2.getRotationMatrix2D() and cv2.warpAffine() functions in opencv are used to complete the image angle offset caused by improper wafer placement during the production process for the wire image, wire contact image, and wafer image, respectively. See the effect diagram for details. Fig.10 :

[0081] At the same time, in order to solve the offset and deformation of the image to be detected due to jitter, mechanical structure failure and other reasons during the production process, an affine transformation is performed on part of the wafer image. Affine transformation is a known algorithm, and its mathematical expression is as follows:

[0082]

[0083] In the figure, x and y are the actual coordinates, and x′ and y′ are the transformed coordinates. Fig.11 :

[0084] According to the above method, the coordinate values ​​of the four corner center points of the wafer part of the image to be detected are obtained through the template image, the coordinate values ​​of the template image are used as x′, y′, the coordinate values ​​of the image to be detected are used as x, y respectively, and the coordinates of each pixel point of the image to be detected are input into the formula to obtain the corrected image.

[0085] 303. In the preparation stage, use the labeling tool to mark the areas to be inspected on the wire template image, wire contact template image, and wafer template image, mark and save the wire area and wire contact area to be inspected. The file contains the corresponding position information of each wire contact on the template image and the wire in the template photo. Fig.12 :

[0086] After the wire area, wire contact area, and wafer area are cropped by operation 302 for the image to be inspected, the rectified wire area image to be inspected, the wire contact area image to be inspected, and the wafer area image to be inspected having the same size as the template image are obtained. The wire and wire contact position information of the corresponding positions marked and saved in the template photo in the preparation stage is applied to the image to be inspected, and the wire area image to be inspected and the wire contact area image to be inspected are cropped in turn. The effect diagram after cropping is shown in FIG. Fig.13 :

[0087] 304. Input the cropped wire area to be inspected image and the wire contact area to be inspected image into the trained improved MobelNetV3 convolutional neural network respectively: obtain the classification of good and defective products respectively, mark the defective products in the image and record the defect location information. See the schematic diagram of the classification of good and defective wires and wire contacts for details. Fig.14 , Fig.15 and Fig.16 ;

[0088] After completing the wire detection and wire contact detection, the wafer area is input into the trained improved Yolox target detection network model for foreign object and scratch detection. After the foreign object and scratch coordinates are output, they are marked and the defect location information is recorded. The wafer scratches and foreign object defects detected by Yolox and the wire and wire contact defects detected by MobileNetV3 are summarized. See the effect diagram for details. Fig.17 ;

[0089] 305. Return the obtained results to the terminal and visualize them.

[0090] The characteristics of the present invention are: (1) defect detection is performed on the acquired target area images to be detected, and image classification of wire contacts and wires based on the improved MobileNetV3 is performed. MobileNetV3 is a lightweight neural network. While maintaining a high accuracy rate, it reduces the size of the model and the computational cost, and improves the running speed. However, the SE module in MobileNetV3 obtains nonlinear channel weights through global average pooling, full connection and nonlinear activation functions. In order to reduce the number of parameters, the parameter r is set to perform dimensionality reduction processing on the channel. The dimensionality reduction processing will cause the SE module to lose important feature information, which brings side effects to the SE module and the model. In view of the above problems, the SE module in MobileNetV3 is replaced by the ECA module. The ECA module does not use the operation of reducing the dimension, but uses a lightweight one-dimensional convolution to obtain more accurate channel weights and realize cross-channel information interaction, realize the attention mechanism, better perform feature screening, complete the detection task, and solve the problems of the existing chip defect detection method being too expensive, unstable, and inefficient.

[0091] (2) Based on the improved Yolox target detection algorithm, the wafer part is inspected. In order to enhance the ability to identify small target defects and defects under complex backgrounds, the activation function Swish used in the backbone feature extraction network of the traditional Yolox target detection algorithm is improved to a smoother Mish activation function. The Mish activation function can still maintain a relatively high classification accuracy when the network is getting deeper and deeper, which is better than the Swish activation function. At the same time, the module of the backbone feature extraction network is improved, and the original 3×3 convolution is replaced with the CoT module, giving the backbone feature extraction network a more powerful global attention mechanism to complete the detection task.

[0092] The embodiments of the present invention are described in detail above, but the contents described are only preferred embodiments of the present invention and cannot be considered to limit the scope of implementation of the present invention. All equivalent changes and improvements made within the scope of the present invention should still fall within the scope of this patent.

Claims

1. A chip surface defect detection method, characterized in that: Position the chip to obtain the area to be detected, and crop the area to be detected to obtain the image to be detected; The terminal obtains the image path and sends a detection request to the appearance defect detection system; Input the batch of images as input to the chip appearance defect detection system, start multi-threaded detection, and perform a complete detection of one image as one thread, processing multiple images at the same time; The obtained results are returned to the terminal and visualized.

2. A chip surface defect detection method according to claim 1, characterized in that: The chip positioning is specifically to crop part of the wafer image to obtain a wafer template image, and traverse the wafer template image on the image to be detected from left to right and from top to bottom to calculate the similarity between the wafer template image and the image to be detected.

3. A chip surface defect detection method according to claim 1, characterized in that: After cropping, the inverse trigonometric function is used to calculate the angle offset of the four corners of the image to be detected, and the angle correction is performed, and the image position correction is performed through affine transformation.

4. A chip surface defect detection method according to claim 2, characterized in that: The same method as that of obtaining the wafer template image is adopted to obtain the wire template image and the wire contact template image, and the detection area is marked respectively to obtain the wire area and wire contact area to be detected, which are marked and the information file is saved. The information file contains the position information corresponding to each wire contact and wire on the wire template image and the wire contact template image.

5. A chip surface defect detection method according to claim 4, characterized in that: After cropping the wire area, wire contact area and wafer area, the corrected wire area to be detected image, wire contact area to be detected image and wafer area to be detected image of the same size as the wire template image, wire contact template image and wafer template image are obtained respectively.

6. A chip surface defect detection method according to claim 5, characterized in that: The complete inspection includes: inputting the cropped wire area to be inspected image and the wire contact area to be inspected image into the trained MobelNetV3 convolutional neural network to classify good products and defective products, marking the defective products in the image and recording the defect location information; The wafer area is input into the trained Yolox target detection network model to detect foreign objects and scratches, and the coordinates of foreign objects and scratches are output and then marked and the defect location information is recorded; The wafer scratches and foreign object defects detected by Yolox and the wire and wire contact defects detected by MobileNetV3 are summarized.

7. A chip surface defect detection method according to claim 2, characterized in that: The formula for calculating the similarity between the wafer template image and the image to be detected is:

8. A chip surface defect detection method according to claim 3, characterized in that: The process of calculating the angle offset is to obtain the position information of the upper left corner of the chip wafer (x0, y0) and the center point position information of the lower left corner (x2, y2), x0-x2 is used to obtain x, y2-y0 is used to obtain y, and the angle value θ is obtained through the inverse tangent function arctan. θ is the chip angle deflection value. The built-in cv2.getRotationMatrix2D() and cv2.warpAffine() functions in opencv are used to complete the image angle offset caused by improper wafer placement during the production process for the wire image, wire contact image, and wafer image respectively.

9. A chip surface defect detection method according to claim 3, characterized in that: The mathematical expression of affine transformation is as follows:

Images