Gate drive circuit and display panel

Abstract

The invention discloses a gate drive circuit and a display panel, the gate drive circuit comprises a plurality of shift registers, the Nth shift register comprises a level transmission signal selection module, a pull-up control module, a first filtering module, a second filtering module, a first output module, a first phase inversion module, an isolation module and a second output module, by accessing the voltage signal smaller than the top gate potential of the second transistor to the bottom gate of the second transistor, the threshold voltage of the second transistor can be adjusted to shift forward, so that the threshold voltage of the second transistor obtains a larger forward range, and the limit range of the threshold voltage of the second transistor is relieved; in addition, the on-state current of the second transistor in the off state is reduced, and the high potential of the second gate drive signal output by the second output module is improved and stabilized.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to a gate drive circuit and a display panel. Background Art

[0002] In a display panel, a gate driving circuit generally provides a required gate driving signal to a transistor corresponding to a pixel circuit.

[0003] However, the threshold voltage drift of some transistors in the gate drive circuit not only limits the range of the threshold voltage of these transistors, but also leads to a decrease in the stability of the pulse amplitude of the gate drive signal provided by the gate drive circuit. Therefore, this becomes one of the reasons for improving the gate drive circuit. Summary of the invention

[0004] The present application provides a gate driving circuit and a display panel to alleviate the technical problem that the threshold voltage drift of a transistor will limit the range of the threshold voltage and reduce the stability of the pulse amplitude of a gate driving signal.

[0005] In a first aspect, the present application provides a gate drive circuit, which includes a plurality of shift registers, the shift register including a level transmission signal selection module, a pull-up control module, a first filter module, a second filter module, a first output module, a first inversion module, an isolation module, and a second output module, the level transmission signal selection module is electrically connected between the first node and the first wiring; the pull-up control module controls the potential of the second node according to the potential of the first node and the potential of the first clock signal; the first filter module is electrically connected between the second node and the third node, and the control end of the first filter module is connected to the reset signal; the second filter module is electrically connected between the first filter module and the third node, and the control end of the second filter module is connected to the filter control signal; the first output module controls the potential of the second node according to the potential of the third node and the potential of the fourth node A first gate drive signal corresponding to the potential output; a first inverting module is electrically connected between the second node and the fourth node; an isolation module is connected in series between the second node and the fifth node, and a control end of the isolation module is connected to the first clock signal; a second output module includes a first transistor and a second transistor, a first electrode of the first transistor is electrically connected to the high potential line, a gate of the first transistor is electrically connected to the fifth node, a second electrode of the first transistor outputs a corresponding second gate drive signal, and the first transistor is a P-channel transistor; the second transistor is an N-channel transistor, a first electrode of the second transistor is electrically connected to the second electrode of the first transistor, a second electrode of the second transistor is electrically connected to the low potential line, a top gate of the second transistor is electrically connected to the fifth node, and a bottom gate of the second transistor is connected to a voltage signal with a potential less than the fifth node.

[0006] In the second aspect, the present application provides a display panel, which includes a pixel circuit and a gate driving circuit in at least one of the above-mentioned embodiments, the pixel circuit includes a write transistor for controlling the input of a data signal and a compensation transistor for controlling the input of the data signal to the gate of the driving transistor; the output end of the first output module is electrically connected to the gate of the write transistor, and the output end of the second output module is electrically connected to the gate of the compensation transistor.

[0007] The gate drive circuit and display panel provided in the present application can adjust the threshold voltage of the second transistor to shift toward the positive direction by connecting a voltage signal that is less than the top gate potential of the second transistor to the bottom gate of the second transistor, which not only enables the threshold voltage of the second transistor to obtain a larger positive range, but also removes the restriction range on the threshold voltage of the second transistor, and reduces the on-state current of the second transistor in the cut-off state, thereby improving and stabilizing the high potential of the second gate drive signal output by the second output module. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] The technical solution and other beneficial effects of the present application will be made apparent by describing in detail the specific implementation methods of the present application in conjunction with the accompanying drawings.

[0009] Figure 1 It is a structural schematic diagram of a pixel circuit in the related art.

[0010] Figure 2 for Figure 1 A timing diagram of the pixel circuit.

[0011] Figure 3 It is a schematic diagram of the first structure of a gate drive circuit in the related art.

[0012] Figure 4 for Figure 3 The timing diagram of the gate drive circuit shown.

[0013] Figure 5 It is a second structural schematic diagram of a gate driving circuit in the related art.

[0014] Figure 6 for Figure 5 The timing diagram of the gate drive circuit shown.

[0015] Figure 7 A timing diagram of the generation of the Nth level negative pulse gate drive signal provided in an embodiment of the present application.

[0016] Figure 8 for Figure 5 Schematic diagram of the potentials of some nodes in the gate drive circuit shown.

[0017] Fig. 9 for Figure 5Schematic diagram of the effect of the threshold voltage drift of the second transistor in the gate drive circuit on the output.

[0018] Fig.10 A schematic diagram of the relationship between electrical parameters of transistors provided in an embodiment of the present application.

[0019] Fig.11 A schematic diagram of the structure of a gate drive circuit provided in an embodiment of the present application.

[0020] Fig.12 for Figure 3 or Figure 5 Schematic diagram of the cascade structure between shift registers in the gate drive circuit shown.

[0021] Fig.13 A schematic diagram of the structure of a display panel provided in an embodiment of the present application.

[0022] Fig.14 A schematic diagram of the structure of a pixel circuit provided in an embodiment of the present application.

[0023] Fig.15 for Fig.14 A timing diagram of the pixel circuit. DETAILED DESCRIPTION

[0024] The technical solutions in the embodiments of the present application will be described clearly and completely below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present application.

[0025] In addition, the terms "first" and "second" are used for descriptive purposes only and cannot be understood as indicating or suggesting relative importance or implicitly indicating the number of technical features indicated. Therefore, the features specified as "first" and "second" may explicitly or implicitly include one or more of the said features. In the description of the present invention, "multiple" means two or more, unless otherwise clearly and specifically defined.

[0026] In the gate drive circuit in the invention application with application number 202310191137.9, the N-th level negative pulse gate drive signal Pout[N] has one negative pulse in one frame. The N-th level positive pulse gate drive signal Nout[N] has two positive pulses in one frame, and the pulse widths of the two positive pulses must be equal and both have a width of 2H. This limits the width of the positive pulse of the N-th level positive pulse gate drive signal Nout[N] to remain consistent and cannot be changed, so that when the width of the positive pulse of the N-th level positive pulse gate drive signal Nout[N] is greater than 2H, the number of negative pulses of the N-th level negative pulse gate drive signal Pout[N] in one frame will increase.

[0027] Therefore, this will limit Figure 1 The pixel circuit shown is in accordance with Figure 2 Specifically, Figure 1 The pixel circuit shown may include at least one of a write transistor T2P, a drive transistor T1P, a first light emission control transistor T5P, a second light emission control transistor T6P, a first initialization transistor T4P, a second initialization transistor T7P, a third initialization transistor T8P, a compensation transistor T3P, a light emitting device D1, a storage capacitor Cst, and a bootstrap capacitor CbOst.

[0028] The first power line is electrically connected to the first electrode of the first light-emitting control transistor T5P and one end of the storage capacitor Cst, the second electrode of the first light-emitting control transistor T5P is electrically connected to the first electrode of the driving transistor T1P and the first electrode of the writing transistor T2P, the second electrode of the driving transistor T1P is electrically connected to the first electrode of the compensation transistor T3P and the first electrode of the second light-emitting control transistor T6P, the second electrode of the second light-emitting control transistor T6P is electrically connected to the first electrode of the second initialization transistor T7P and the anode of the light-emitting device D1, and the cathode of the light-emitting device D1 is electrically connected to the second power line.

[0029] The light emission control line is electrically connected to the gate of the first light emission control transistor T5P and the gate of the second light emission control transistor T6P.

[0030] The second electrode of the write transistor T2P is electrically connected to the data line, the gate of the write transistor T2P is electrically connected to one end of the bootstrap capacitor CbOst, and is connected to the Nth level negative pulse gate drive signal Pout[N]. The second electrode of the second initialization transistor T7P is electrically connected to the second initialization line, and the gate of the second initialization transistor T7P is connected to the gate drive signal Pscan2.

[0031] The second electrode of the compensation transistor T3P is electrically connected to the gate of the driving transistor T1P, and the gate of the compensation transistor T3P is connected to the Nth stage positive pulse gate driving signal Nout[N].

[0032] The gate of the driving transistor T1P is electrically connected to the other end of the storage capacitor Cst, the other end of the bootstrap capacitor CbOst, and the first electrode of the first initialization transistor T4P.

[0033] The second electrode of the first initialization transistor T4P is electrically connected to the first initialization line, and the gate of the first initialization transistor T4P is connected to the N-1th stage positive pulse gate driving signal Nout[N-1].

[0034] A first electrode of the third initialization transistor T8P is electrically connected to a first electrode of the driving transistor T1P, a second electrode of the third initialization transistor T8P is electrically connected to a third initialization line, and a gate of the third initialization transistor T8P and a gate of the second initialization transistor T7P share a gate driving signal Pscan2.

[0035] It should be noted that the second initialization line may also be replaced by the first initialization line, which can reduce one wiring required for the pixel circuit and is beneficial to increase the density of the pixel circuit in the display panel.

[0036] In the present application, the first electrode may be one of the source electrode and the drain electrode, and the second electrode may be the other of the source electrode and the drain electrode. For example, when the first electrode is the source electrode, the second electrode is the drain electrode; or when the first electrode is the drain electrode, the second electrode is the source electrode.

[0037] Among them, the first power line is used to transmit the positive power signal VDD, the second power line is used to transmit the negative power signal VSS, and the potential of the positive power signal VDD is higher than the potential of the negative power signal VSS. The data line is used to transmit the data signal Data. The light control line is used to transmit the light control signal EM. The first initialization line is used to transmit the first initialization signal Vi1. The second initialization line is used to transmit the second initialization signal. The third initialization line is used to transmit the third initialization signal Vi3. The first gate drive line is used to transmit the Nth level negative pulse gate drive signal Pout[N]. The second gate drive line connected to the shift register of different levels is used to transmit the N-1th level positive pulse gate drive signal Nout[N-1] and the Nth level positive pulse gate drive signal Nout[N] respectively.

[0038] As can be seen from the above, in the gate drive circuit shown in the invention application with application number 202310191137.9, the principle of generating a negative pulse in one frame of the Nth level negative pulse gate drive signal Pout[N] is formed by filtering out the first pulse of the start control signal STV or the NYth level positive pulse gate drive signal Nout[NY] through the second pulse of the reset signal RST. Therefore, the widths of the two positive pulses of the start control signal STV or the NYth level positive pulse gate drive signal Nout[NY] must be equal.

[0039] exist Figure 1 In the pixel circuit shown in the figure, in order to realize the synchronous conduction of the compensation transistor T3P and the first initialization transistor T4P, the pulse of the N-1th level positive pulse gate drive signal Nout[N-1] and the pulse of the Nth level positive pulse gate drive signal Nout[N] need to partially overlap, which is also Figure 1 The reason why the first initialization transistor T4P in the pixel circuit shown must be connected to the N-1th stage positive pulse gate driving signal Nout[N-1].

[0040] Furthermore, in order to complete the transmission of the third initialization signal Vi3 via node A and node B to node Q in sequence to reset the potentials of node A, node B, and node Q, the third initialization transistor T8P and the compensation transistor T3P need to be turned on synchronously, which requires the pulse of the gate drive signal Pscan2 to partially overlap with the pulse of the Nth level positive pulse gate drive signal Nout[N].

[0041] And for Figure 1 The pixel circuit shown can continue to use the gate drive signal Pscan2 with a pulse width of only 1H, which requires adjustment Figure 2 The driving timing of the pixel circuit shown in FIG. Figure 1 The gate drive circuit shown is improved.

[0042] In this context, in order to alleviate the technical problem that the gate drive signal pulse is difficult to meet the requirements in terms of time and width, the Figure 3 The gate drive circuit shown in FIG. Figure 4 The gate drive circuit works in the timing shown. The description of the gate drive circuit is described in detail in the invention application with application number 202310922942.4, which can be referenced.

[0043] However, in order to overcome Figure 3 The gate drive circuit shown in the figure is affected by the coupling of the Nth level negative pulse gate drive signal Pout[N] during the period when the Nth level positive pulse gate drive signal Nout[N] outputs a high potential, and adopts Figure 5 The gate drive circuit shown in FIG. Figure 6 The gate drive circuit works in the timing shown. The description of the gate drive circuit is also described in detail in the invention application with application number 202310922942.4, which can be referenced.

[0044] Based on the record of the invention application with application number 202310922942.4, Figure 7The negative pulse generation process of the Nth level negative pulse gate drive signal Pout[N] is shown. For the sake of clear description, the two pulses from right to left in the same signal are called the first pulse and the second pulse. The second node K transmits the first pulse and the second pulse in one frame. The high potential of the first part of the two pulses of the N-2th level positive pulse gate drive signal Nout[N-2] controls the second filter module 80 to filter out the latter part of the first pulse and the latter part of the second pulse output by the second node K; the high potential of the latter part of the first pulse of the reset signal RST controls the first filter module 30 to filter out the first part of the second pulse output by the second node K. At this point, the width of the second pulse of the node W has also narrowed; the second pulse output by the second node K is completely filtered out, and only the first part of the first pulse output by the second node K forms a negative pulse at the third node Q. The negative pulse of the third node Q opens the pull-up module 40, forming a negative pulse of the Nth level negative pulse gate drive signal Pout[N] with a fixed width.

[0045] Figure 8 Shows Figure 5 Schematic diagram of the waveform of the fifth node N, the second gate drive signal, i.e., the Nth level positive pulse gate drive signal Nout[N]. For example, when the low potential signal VGL is set to -8V and the voltage of the fifth node N is -3.15V, the gate-source voltage difference of the second transistor T10 as indium gallium zinc oxide, i.e., Vgs=4.85v, at this time, the second transistor T10 is in the on state, and there will be a relatively small leakage current output. Among them, the high level output by the Nth level positive pulse gate drive signal Nout[N] is determined by the high potential signal VGH and the low potential signal VGL. Therefore, after the threshold voltage Vth of the second transistor T10 drifts negatively (shift), the leakage current of the second transistor T10 will increase, and the high potential of the Nth level positive pulse gate drive signal Nout[N] will drop to 7.04V. The threshold voltage of the second transistor T10 drifts negatively, resulting in the threshold voltage of the second transistor T10 being unable to obtain a larger positive threshold voltage, which not only severely limits the operating range of the threshold voltage of the second transistor T10, but also leads to abnormal high-voltage output of the Nth-level positive pulse gate drive signal Nout[N].

[0046] Specific as Fig. 9 As shown, during the high potential output of the N-th level positive pulse gate drive signal Nout[N], as the threshold voltage of the second transistor T10 changes more and more negatively, that is, from △Vth=6V to △Vth=0V, the leakage current or on-state current I-T10 flowing through the second transistor T10 also becomes larger and larger, and the drop amplitude of the high potential of the N-th level positive pulse gate drive signal Nout[N] also becomes larger and larger, while the stability influence of the high potential of the N-th level negative pulse gate drive signal Pout[N] becomes smaller and smaller.

[0047] Through the study of the electrical properties of dual-gate indium gallium zinc oxide (IGZO) thin film transistors, it was found that Fig.10 As shown, after the threshold voltage Vth is positively biased, the drain-source current Ids will become smaller under the same gate-source voltage difference Vgs; the more negative the bottom gate voltage applied to the bottom gate, the more positive Vth is, and the mobility does not change much.

[0048] Based on the above analysis, this embodiment provides a gate driving circuit, such as Fig.11 As shown, the gate drive circuit includes multiple shift registers, and the shift registers include a stage signal selection module 10, a pull-up control module 20, a first filter module 30, a second filter module 80, a first output module 46, a first inversion module 50, an isolation module 75, and at least one of the second output modules 70.

[0049] The level transmission signal selection module 10 is electrically connected to the first node O[N] and the first wiring. The first wiring may be a start control line or a positive pulse gate drive line of the NYth level, where Y is an integer greater than or equal to 1.

[0050] The pull-up control module 20 controls the potential of the second node K according to the potential of the first node O[N] and the potential of the first clock signal XCK.

[0051] The first filter module 30 is electrically connected between the second node K and the third node Q, and the control end of the first filter module 30 is connected to the reset signal RST. The reset signal RST can be the NX-th level positive pulse gate drive signal Nout[NX] or other adapted positive pulse signals, and the NX-th level positive pulse gate drive signal Nout[NX] can be transmitted through the NX-th level positive pulse gate drive line, and X is an integer greater than or equal to 2.

[0052] The second filter module 80 is electrically connected between the first filter module 30 and the third node Q, and the control end of the second filter module 80 is connected to the filter control signal RST2. The filter control signal RST2 can be a positive pulse gate drive signal of other stages, for example, the N-2 stage positive pulse gate drive signal Nout[N-2], the N-3 stage positive pulse gate drive signal Nout[N-3].

[0053] The first output module 46 outputs a corresponding first gate driving signal according to the potential of the third node Q and the potential of the fourth node P.

[0054] The first inversion module 50 is electrically connected between the second node K and the fourth node P.

[0055] The isolation module 75 is connected in series between the second node K and the fifth node N, and a control terminal of the isolation module 75 is connected to the first clock signal XCK.

[0056] The second output module 70 includes a first transistor T9 and a second transistor T10. The first electrode of the first transistor T9 is electrically connected to the high potential line, the gate of the first transistor T9 is electrically connected to the fifth node N, the second electrode of the first transistor T9 outputs a corresponding second gate drive signal, and the first transistor T9 is a P-channel transistor.

[0057] The second transistor T10 is an N-channel transistor, a first electrode of the second transistor T10 is electrically connected to the second electrode of the first transistor T9, a second electrode of the second transistor T10 is electrically connected to the low potential line, a top gate of the second transistor T10 is electrically connected to the fifth node N, and a bottom gate of the second transistor T10 is connected to a voltage signal with a potential less than the fifth node N.

[0058] It can be understood that the gate drive circuit provided in this embodiment can adjust the threshold voltage of the second transistor T10 to shift toward the positive direction by connecting a voltage signal that is less than the top gate potential of the second transistor T10 to the bottom gate of the second transistor T10, which not only enables the threshold voltage of the second transistor T10 to obtain a larger positive range, but also removes the restriction range of the threshold voltage of the second transistor T10, and reduces the on-state current of the second transistor T10 in the cut-off state, thereby improving and stabilizing the high potential of the second gate drive signal output by the second output module 70.

[0059] It should be noted that Figure 5 Compared with the gate drive circuit shown, Fig.11 In the gate driving circuit shown, the bottom gate of the second transistor T10 is not connected to the top gate thereof, but is independently connected to a voltage signal having a lower potential than the top gate thereof.

[0060] In one embodiment, the voltage signal is used to adjust the threshold voltage of the second transistor T10 to shift to the positive direction, which can not only reduce the leakage current, but also improve and stabilize the high potential output by the second output module 70 .

[0061] In one embodiment, the voltage signal is also used to adjust the threshold voltage of the second transistor T10 to be greater than 0 V. This can further limit the positive offset range of the threshold voltage of the second transistor T10, thereby further reducing the leakage current, and further improving and stabilizing the high potential output by the second output module 70.

[0062] In one embodiment, the voltage signal is a constant voltage signal, or the voltage signal has two negative pulses in one frame.

[0063] It should be noted that when the second transistor T10 is in the cut-off state, the potential of the fifth node N is a negative potential, so that the potential of the voltage signal of this embodiment is more negative than the negative potential of the fifth node N, and the threshold voltage of the second transistor T10 can be adjusted to shift toward the positive direction, which can not only reduce the leakage current, but also improve and stabilize the high potential output by the second output module 70.

[0064] In one embodiment, when the voltage signal is a constant voltage signal, the voltage signal is derived from the low potential line.

[0065] It should be noted that the low potential signal VGL with a fixed voltage in the low potential line can also reduce leakage current, and can also improve and stabilize the high potential output by the second output module 70; at the same time, the low potential line can also be shared, which can reduce the number of wiring of the gate drive circuit.

[0066] In one embodiment, when the voltage signal has two negative pulses in one frame, the voltage signal originates from the second node K or the first node O[N+1] in the next stage shift register.

[0067] It should be noted that under the control of the potential of the second node K with two negative pulses or the first node in the shift register of the next level, namely O[N+1], the leakage current can also be reduced, and the high potential output by the second output module 70 can be increased and stabilized; at the same time, the second node K or the first node in the shift register of the next level, namely O[N+1], can also be shared, which can reduce the number of external wiring of the gate drive circuit.

[0068] In one embodiment, the first inversion module 50 includes a third transistor T3 and a fourth transistor T1, a first electrode of the third transistor T3 is electrically connected to the high potential line, a gate of the third transistor T3 is electrically connected to the second node K, a second electrode of the third transistor T3 is electrically connected to the fourth node P, and the third transistor T3 is a P-channel transistor; the fourth transistor T1 is an N-channel transistor, a first electrode of the fourth transistor T1 is electrically connected to the second electrode of the third transistor T3, a second electrode of the fourth transistor T1 is electrically connected to the low potential line, a top gate of the fourth transistor T1 is electrically connected to the second node K, and a bottom gate of the fourth transistor T1 is connected to a voltage signal with a potential less than the second node K.

[0069] It should be noted that, by connecting a voltage signal whose potential is less than the top gate potential of the fourth transistor T1 to the bottom gate of the fourth transistor T1, the threshold voltage of the fourth transistor T1 can be adjusted to shift toward the positive direction, which not only enables the threshold voltage of the fourth transistor T1 to obtain a larger positive range, but also removes the restriction range of the threshold voltage of the fourth transistor T1, and reduces the on-state current of the fourth transistor T1 in the cut-off state, thereby improving and stabilizing the high potential of the fourth node P.

[0070] In one of the embodiments, when the fourth transistor T1 is in the cut-off state, the potential of the second node K is a negative potential, so that the potential of a constant voltage or a voltage signal having two negative pulses in one frame is more negative than the negative potential of the second node K, and the threshold voltage of the fourth transistor T1 can be adjusted to shift toward the positive direction, which can not only reduce the leakage current but also increase and stabilize the high potential of the fourth node P.

[0071] In one embodiment, the low potential line transmits a low potential signal VGL, and when the voltage signal is a constant voltage signal, the voltage signal is a low potential signal VGL. The low potential signal VGL with a fixed voltage in the low potential line can also reduce the leakage current of the fourth transistor T1, and can also increase and stabilize the high potential of the fourth node P; at the same time, the low potential line can be shared, which can reduce the number of wirings of the gate drive circuit.

[0072] In one embodiment, when the voltage signal has two negative pulses in one frame, the voltage signal originates from the second node K or the first node O[N+1] in the next stage shift register.

[0073] It should be noted that, under the control of the potential of the second node K with two negative pulses or the first node in the shift register of the next level, namely O[N+1], the leakage current of the fourth transistor T1 can also be reduced, and the high potential of the fourth node P can be increased and stabilized; at the same time, the second node K or the first node in the shift register of the next level, namely O[N+1], can also be shared, which can reduce the number of external wiring of the gate drive circuit.

[0074] In one embodiment, the voltage signal is also used to adjust the threshold voltage of the fourth transistor T1 to shift positively and be greater than 0 V. This can further limit the positive shift range of the threshold voltage of the fourth transistor T1, thereby further reducing the leakage current and further improving and stabilizing the high potential of the fourth node P.

[0075] In one embodiment, the voltage transmission line for transmitting the voltage signal is electrically connected to the first node O[N+1] in the shift register of the next stage.

[0076] It should be noted that the advantage of such a setting is that the signal frequency of the fifth node N and the first node in the shift register of the next stage, namely O[N+1], is not only the same, but also because there will be no voltage division influence of the pull-up control transistor T2, the voltage of O[N+1] can be more negative, thereby further reducing the leakage current, and can further increase and stabilize the high potential of the fourth node P or the Nth stage positive pulse gate drive signal Nout[N].

[0077] In summary, when the potential of the fifth node N is -3V, the voltage of O[n+1] is -8V. At this time, the bottom gate of the second transistor T10 and / or the fourth transistor T1 is biased by a voltage of about -8V, and the Vth of the second transistor T10 and / or the fourth transistor T1 is forward biased to 2.5V. Figure 5 The structural design shown can increase the positive range of the threshold voltage of 2V, thereby increasing the reliability of the gate drive circuit.

[0078] It needs to be explained that Fig.11 For further explanation of the gate drive circuit shown, please refer to Figure 3 The gate drive circuit shown is described in detail in the invention application with application number 202310922942.4 or Figure 5 The gate drive circuit shown is described in detail in the invention application with application number 202310922942.4.

[0079] Fig.12 for Figure 3 , Figure 5 or or Fig.11 The schematic diagram of the structure of cascading different shift registers in the gate driving circuit shown in the figure, wherein the first-stage shift register, the second-stage shift register, the third-stage shift register, the Nth-stage shift register, and the N+1th-stage shift register are arranged in sequence from top to bottom. Each shift register works according to the first clock signal XCK and the second clock signal CK respectively.

[0080] Among them, the control end of the first filter module 30 and the control end of the second filter module 80 in the first-stage shift register are both connected to the low potential signal VGL, and the input end (IN) of the first-stage shift register connected to the start control line is connected to the start control signal STV. The first-stage shift register outputs the corresponding first-stage negative pulse gate drive signal Pout[1] and first-stage positive pulse gate drive signal Nout[1]. The first-stage negative pulse gate drive signal Pout[1] and the first-stage positive pulse gate drive signal Nout[1] are used to drive dummy pixels (Dummy) or are suspended.

[0081] The control end of the first filter module 30 and the control end of the second filter module 80 in the second-stage shift register are both connected to the low potential signal VGL, and the start control line connected to the second-stage shift register is connected to the cascade signal, i.e., the first-stage positive pulse gate drive signal Nout[1]. The second-stage shift register outputs the corresponding second-stage negative pulse gate drive signal Pout[2] and second-stage positive pulse gate drive signal Nout[2]. The second-stage negative pulse gate drive signal Pout[2] and second-stage positive pulse gate drive signal Nout[2] are used to drive dummy pixels (Dummy) or are left hanging.

[0082] The control end of the first filter module 30 and the control end of the second filter module 80 in the third-stage shift register are both connected to the low potential signal VGL, and the start control line connected to the third-stage shift register is connected to the cascade signal, i.e., the second-stage positive pulse gate drive signal Nout[2]. The third-stage shift register outputs the corresponding third-stage negative pulse gate drive signal Pout[3] and third-stage positive pulse gate drive signal Nout[3]. The third-stage negative pulse gate drive signal Pout[3] and the third-stage positive pulse gate drive signal Nout[3] are used to drive dummy pixels (Dummy) or are left floating.

[0083] The same logic can be applied to other control terminals, until the control terminals of the first filter module 30 and the second filter module 80 in the Nth stage shift register are connected to the NXth stage positive pulse gate drive signal Nout[NX] and the N-2th stage positive pulse gate drive signal Nout[N-2] respectively, and the starting control line connected to the Nth stage shift register is connected to the cascade signal, i.e., the N-1th stage positive pulse gate drive signal Nout[N-1]. The Nth stage shift register outputs the corresponding Nth stage negative pulse gate drive signal Pout[N] and the Nth stage positive pulse gate drive signal Nout[N]. The Nth stage negative pulse gate drive signal Pout[N] and the Nth stage positive pulse gate drive signal Nout[N] are used to drive the first row of pixel circuits (Pixel).

[0084] The control end of the first filter module 30 and the control end of the second filter module 80 in the N+1-th shift register are respectively connected to the N-X+1-th positive pulse gate drive signal Nout[N-X+1] and the N-1-th positive pulse gate drive signal Nout[N-1], and the starting control line connected to the N+1-th shift register is connected to the cascade signal, that is, the N-th positive pulse gate drive signal Nout[N]. The N+1-th shift register outputs the corresponding N+1-th negative pulse gate drive signal Pout[N+1] and the N+1-th positive pulse gate drive signal Nout[N+1]. The N+1-th negative pulse gate drive signal Pout[N+1] and the N+1-th positive pulse gate drive signal Nout[N+1] are used to drive the second row of pixel circuits (Pixel).

[0085] The same can be said for other subsequent shift registers. It should be noted that, since the output ends of some shift registers are connected to virtual pixels or are suspended, the output ends of the Nth-stage shift register are not connected to the Nth-row pixel circuit, but the number of rows of connected pixel circuits needs to be determined according to the number of shift registers connected to virtual pixels or suspended. For example, if the 1st to 3rd-stage shift registers are connected to virtual pixels, then the output ends of the Nth-stage shift register are connected to the N-3rd-row pixel circuit.

[0086] Fig.13 The display panel shown includes pixel circuits (Pixel) distributed in an array in the display area, a first gate driving circuit 151 providing a light-emitting control signal EM, a fourth gate driving circuit 154 providing a gate driving signal Pscan2, a second gate driving circuit 152 providing an N-th level negative pulse gate driving signal Pout[N] and a gate driving signal Nscan, and a third gate driving circuit 153 providing an N-th level negative pulse gate driving signal Pout[N] and a gate driving signal Nscan.

[0087] The first gate driving circuit 151 may be located on the left side of the display area. The output end of each shift register in the first gate driving circuit 151 provides a light emitting control signal EM to two adjacent rows of pixel circuits through a corresponding light emitting control line, which is a unilateral drive.

[0088] The fourth gate driving circuit 154 may be located on the right side of the display area. The output end of each shift register in the fourth gate driving circuit 154 provides a gate driving signal Pscan2 to a row of pixel circuits through a corresponding gate driving line, which belongs to unilateral driving.

[0089] The second gate driving circuit 152 is located between the first gate driving circuit 151 and the display area. The third gate driving circuit 153 is located between the fourth gate driving circuit 154 and the display area. A gate driving line that transmits the Nth level negative pulse gate driving signal Pout[N] is electrically connected to the output end of a shift register in the second gate driving circuit 152, the output end of a shift register in the third gate driving circuit 153, and a row of pixel circuits, and a gate driving line that transmits the gate driving signal Nscan is electrically connected to the output end of a shift register in the second gate driving circuit 152, the output end of a shift register in the third gate driving circuit 153, and a row of pixel circuits, which belongs to bilateral driving.

[0090] The second gate drive circuit 152 and the third gate drive circuit 153 can both adopt Figure 3 , Figure 5 or Fig.11The gate driving circuit shown in the figure. The gate driving signal Nscan may include the Nth level positive pulse gate driving signal Nout[N] and the N-3th level positive pulse gate driving signal Nout[N-3].

[0091] because Figure 1 There is a necessary reason why the gate of the first initialization transistor T4P in the pixel circuit shown is connected to the N-1th level positive pulse gate drive signal Nout[N-1], Fig.14 After the gate of the write transistor T2P in the pixel circuit shown is connected to the Nth level negative pulse gate drive signal Pout[N] and the gate of the compensation transistor T3P is connected to the Nth level positive pulse gate drive signal Nout[N], not only can the gate of the third initialization transistor T8P continue to use the existing gate drive signal Pscan2 (no need to improve the fourth gate drive circuit 154), but the gate of the first initialization transistor T4P can also be replaced with the N-3th level positive pulse gate drive signal Nout[N-3].

[0092] After that, Fig.14 The pixel circuit shown can work not only in one frame Fig.15 In addition to the existing stage P12, an additional stage P11 can be added. In the stage P11, the first initialization transistor T4P and the compensation transistor T3P can be synchronously turned on to reset the potential of the three terminals (Q, A, B) of the driving transistor T1P to reduce the drift of the threshold voltage of the driving transistor T1P, thereby improving the flicker under different refresh frequencies.

[0093] In one of the embodiments, the present embodiment provides a display panel, which includes the gate driving circuit and the pixel circuit in at least one of the above embodiments.

[0094] It can be understood that, since the display panel provided in this embodiment includes the gate driving circuit in at least one of the above-mentioned embodiments, the threshold voltage of the second transistor T10 can be adjusted to shift toward the positive direction by connecting a voltage signal that is less than the top gate potential of the second transistor T10 to the bottom gate of the second transistor T10, which not only enables the threshold voltage of the second transistor T10 to obtain a larger positive range, but also removes the restriction range of the threshold voltage of the second transistor T10, and reduces the on-state current of the second transistor T10 in the cut-off state, thereby improving and stabilizing the high potential of the second gate driving signal output by the second output module 70.

[0095] In the above embodiments, the description of each embodiment has its own emphasis. For parts that are not described in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0096] The gate drive circuit and display panel provided in the embodiments of the present application are introduced in detail above. Specific examples are used in this article to illustrate the principles and implementation methods of the present application. The description of the above embodiments is only used to help understand the technical solutions and core ideas of the present application. Ordinary technicians in this field should understand that they can still modify the technical solutions recorded in the aforementioned embodiments, or replace some of the technical features therein with equivalents; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A gate drive circuit, characterized in that: The gate driving circuit includes a plurality of shift registers, and the Nth stage shift register includes: a level transmission signal selection module, wherein the level transmission signal selection module is electrically connected between the first node and the first wiring; A pull-up control module, wherein the pull-up control module controls the potential of the second node according to the potential of the first node and the potential of the first clock signal; A first filtering module, wherein the first filtering module is electrically connected between the second node and the third node, and a control terminal of the first filtering module is connected to a reset signal; A second filtering module, the second filtering module is electrically connected between the first filtering module and the third node, and a control end of the second filtering module is connected to a filtering control signal; a first output module, wherein the first output module outputs a corresponding first gate driving signal according to the potential of the third node and the potential of the fourth node; A first inverting module, wherein the first inverting module is electrically connected between the second node and the fourth node; an isolation module, the isolation module being connected in series between the second node and the fifth node, and a control end of the isolation module being connected to the first clock signal; and A second output module, wherein the second output module comprises: a first transistor, wherein a first electrode of the first transistor is electrically connected to the high potential line, a gate of the first transistor is electrically connected to the fifth node, a second electrode of the first transistor outputs a corresponding second gate driving signal, and the first transistor is a P-channel transistor; A second transistor, the second transistor is an N-channel transistor, a first electrode of the second transistor is electrically connected to a second electrode of the first transistor, a second electrode of the second transistor is electrically connected to a low potential line, a top gate of the second transistor is electrically connected to the fifth node, and a bottom gate of the second transistor is connected to a voltage signal having a potential less than that of the fifth node.

2. The gate driving circuit according to claim 1, characterized in that: The voltage signal is a constant voltage signal, or the voltage signal has two negative pulses in one frame.

3. The gate driving circuit according to claim 2, characterized in that: When the voltage signal is a constant voltage signal, the voltage signal is derived from the low potential line.

4. The gate driving circuit according to claim 2, characterized in that: When the voltage signal has two negative pulses in one frame, the voltage signal originates from the second node or the first node in the shift register of the next stage.

5. The gate driving circuit according to claim 1, characterized in that: The voltage signal is used to adjust the threshold voltage of the second transistor to shift toward a positive direction.

6. The gate driving circuit according to claim 5, characterized in that: The voltage signal is further used to adjust the threshold voltage of the second transistor to be greater than 0V.

7. The gate driving circuit according to claim 1, characterized in that: The first inversion module comprises: a third transistor, wherein a first electrode of the third transistor is electrically connected to the high potential line, a gate of the third transistor is electrically connected to the second node, a second electrode of the third transistor is electrically connected to the fourth node, and the third transistor is a P-channel transistor; A fourth transistor, wherein the fourth transistor is an N-channel transistor, a first electrode of the fourth transistor is electrically connected to the second electrode of the third transistor, a second electrode of the fourth transistor is electrically connected to the low potential line, a top gate of the fourth transistor is electrically connected to the second node, and a bottom gate of the fourth transistor is connected to the voltage signal having a potential less than that of the second node.

8. The gate driving circuit according to claim 7, characterized in that: The voltage signal is a constant voltage signal, or the voltage signal has two negative pulses in one frame.

9. The gate driving circuit according to claim 8, characterized in that: The low potential line transmits a low potential signal. When the voltage signal is a constant voltage signal, the voltage signal is the low potential signal.

10. The gate driving circuit according to claim 8, characterized in that: When the voltage signal has two negative pulses in one frame, the potential of the voltage signal is the potential of the second node or the potential of the first node in the shift register of the next stage.

11. The gate driving circuit according to claim 7, characterized in that: The voltage signal is further used to adjust the threshold voltage of the fourth transistor to shift to a positive direction and be greater than 0V.

12. A display panel, characterized in that: The display panel comprises: a pixel circuit including a write transistor for controlling input of a data signal and a compensation transistor for controlling input of the data signal to a gate of a drive transistor; and According to the gate drive circuit as described in any one of claims 1 to 11, the output end of the first output module is electrically connected to the gate of the write transistor, and the output end of the second output module is electrically connected to the gate of the compensation transistor.

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