Gate drive circuit and display panel

Abstract

The invention discloses a gate driving circuit and a display panel, and the gate driving circuit comprises a plurality of cascaded gate driving units, and each gate driving unit at least comprises a first cascade unit which is connected with the gate driving unit of the previous stage; the first output unit is connected with the first cascade unit and is used for controlling and outputting a scanning signal according to a cascade signal of the first cascade unit; the scanning signal comprises a turn-on voltage and a turn-off voltage; the overvoltage output unit is connected with the first cascade unit and is used for outputting an overvoltage scanning signal according to a cascade signal of the first cascade unit after the first output unit outputs the starting voltage; wherein the overvoltage scanning signal is greater than the cut-off voltage of the scanning signal. Through the circuit, the blank time is shortened, and the circuit is suitable for a high-refresh panel.

Description

Technical Field

[0001] The present invention relates to the field of display panels, and in particular to a gate driving circuit and a display panel. Background Art

[0002] As display technology becomes increasingly mature, high refresh rate, high frequency dimming and extremely narrow bezel technologies have emerged one after another. All of the above are technical upgrades around GOA (gate on array) circuits.

[0003] Similar to other forms of display devices, OLED (Organic Light Emitting Display) uses row refresh as the basic operating logic, that is, within one frame, the driver chip outputs data signals to each row of the panel in turn. At this time, it is required that the data signal is input when the switch transistor connected to one end of the storage capacitor in the pixel circuit of the row is fully turned on. At the same time, when the switch transistor of the row is fully turned off and the corresponding switch transistor of the pixel circuit of the next row in the refresh direction is turned on, the data of the next row is input.

[0004] Obviously, due to the parasitic capacitance between the scanning signal line of the panel display area and the gate and source and drain of the switching transistor, it takes a certain recovery charging time for the switching transistor to reach the threshold voltage of full closure, so there must be a gap between the two data signal transmissions of the same data line, that is, there must be a certain blank time (H-Blanking) between every two rows of data signal transmission, otherwise there may be a mischarging phenomenon, that is, the data signal that should be charged into the n+1th row is charged into the nth and n+1th rows because the switching transistor of the nth row is not completely closed, thereby affecting the display effect. Especially when facing high refresh or high resolution, especially when there are many rows in the scanning direction, the charging / switching time of one frame or one row needs to be further compressed, and the demand for low H-Blanking is greater. Summary of the invention

[0005] The main technical problem solved by the present application is to provide a gate drive circuit and a display panel, which shorten the blank time and are suitable for high refresh panels.

[0006] To solve the above problems, the present application provides a gate driving circuit in a first aspect, wherein the gate driving circuit includes: a plurality of cascaded gate driving units, each of the gate driving units includes at least: a first cascade unit, connected to the gate driving unit of the previous level; a first output unit, connected to the first cascade unit, for controlling the output of a scan signal according to a cascade signal of the first cascade unit; the scan signal includes a start-up voltage and a cut-off voltage; an overvoltage output unit, connected to the first cascade unit, for outputting an overvoltage scan signal according to the cascade signal of the first cascade unit after the first output unit outputs the start-up voltage; wherein the overvoltage scan signal is greater than the cut-off voltage of the scan signal.

[0007] The first output unit includes a first transistor; the gate of the first transistor is connected to the output end of the first cascade unit, and the input end of the first transistor is connected to the first jump signal line; the first jump signal line transmits a high / low level jump signal.

[0008] The first output unit further includes a first capacitor, a first plate of which is connected to the gate of the first transistor, the output end of the first cascade unit and the input end of the overvoltage output unit, and is used to store the gate voltage charged to the first transistor.

[0009] Wherein, the overvoltage output unit includes: a bootstrap capacitor; a first control unit, arranged between the first electrode plate of the bootstrap capacitor and the first cascade unit, and used to control the first cascade unit to charge the first electrode plate of the bootstrap capacitor with a first voltage; a second cascade unit, a control end connected to the gate drive unit of the next level, an input end connected to the first signal line, and an output end connected to the first electrode plate of the bootstrap capacitor, and used to charge the first electrode plate of the bootstrap capacitor with a second voltage; wherein, the second voltage is greater than the first voltage.

[0010] Wherein, the overvoltage output unit comprises: an overvoltage output control unit connected to the second electrode plate of the bootstrap capacitor and used for controlling the output of the overvoltage scanning signal.

[0011] Among them, the overvoltage output unit also includes: a third cascade unit, the control end of the third cascade unit is connected to the gate drive unit of the next level, the input end is connected to the first signal line, and the output end is connected to the second plate of the bootstrap capacitor, which is used to charge the second voltage to the second plate of the bootstrap capacitor.

[0012] Wherein, the third cascade unit and the overvoltage output control unit include a group of transistors with opposite driving characteristics; the third cascade unit and the second cascade unit include a group of transistors with opposite driving characteristics; wherein, the third cascade unit includes an N-type transistor.

[0013] Wherein, the gate driving unit further includes: a second output unit connected to the first signal line and used for outputting a cut-off voltage of the scanning signal.

[0014] Among them, the second output unit includes a second transistor and a first diode; the gate of the second transistor is connected to the first plate of the bootstrap capacitor, and the input end is connected to the first signal line, which is used to control the output of the cut-off voltage according to the voltage signal on the first plate of the bootstrap capacitor; the positive electrode of the first diode is connected to the output end of the second transistor, and the negative electrode is connected to the output end of the gate driving unit, which is used to control the output of the cut-off voltage.

[0015] To solve the above problem, the present application provides a display panel in a second aspect, wherein the display panel includes the gate driving circuit described in any embodiment of the first aspect.

[0016] The beneficial effect of the present application is that an overvoltage scan signal is provided after a scan pulse through a gate drive circuit, so that the drive transistor in the display panel can quickly return to an off state after the data voltage is charged, thereby reducing the time required to turn off the drive transistor, thereby achieving the purpose of shortening the blanking time H-blanking and avoiding display abnormalities caused by mischarging or erroneous charging. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0018] Figure 1 A schematic diagram of the structure of an embodiment of a gate driving circuit provided in the present application; Figure 2 A schematic structural diagram of a first specific embodiment of a gate driving unit provided in the present application; Figure 3 A schematic structural diagram of a second specific embodiment of a gate driving unit provided in the present application; Figure 4 A schematic structural diagram of a third specific embodiment of a gate driving unit provided in the present application; Figure 5 A schematic structural diagram of a fourth specific embodiment of a gate driving unit provided in the present application; Figure 6 A schematic structural diagram of a fifth specific embodiment of a gate driving unit provided in the present application; Figure 7A schematic diagram of the circuit structure of a specific embodiment of the gate driving unit provided in this application; Figure 8 A driving timing diagram of a specific embodiment of a gate driving unit provided in the present application; Fig. 9 A circuit diagram of the first driving stage of a specific embodiment of a gate driving unit provided in the present application; Fig.10 A circuit diagram of the second driving stage of a specific embodiment of a gate driving unit provided in the present application; Fig.11 A circuit diagram of the third driving stage of a specific embodiment of a gate driving unit provided in the present application; Fig.12 A circuit diagram of a fourth driving stage of a specific embodiment of a gate driving unit provided in the present application; Fig.13 A circuit diagram of a fifth driving stage of a specific embodiment of a gate driving unit provided in the present application; Fig.14 A schematic diagram of the circuit structure of another specific embodiment of the gate driving unit provided in the present application; Fig.15 A schematic structural diagram of an embodiment of a display panel provided in the present application.

[0019] Explanation of symbols: The first cascade unit 11; the first output unit 12; the overvoltage output unit 13; the first control unit 131; the second cascade unit 132; the overvoltage output control unit 133; the third cascade unit 134; the second output unit 14; the N-th gate driving unit GOA(n); the first signal line VGH; the first jump signal line CK; the second jump signal line XCK; the N-th scan signal Pscan(n); the N-1-th scan signal / the previous scan signal Pscan(n-1); the N+1-th scan signal / the next scan signal Pscan(n+1); the first transistor T1; the second transistor T2; the third transistor T3; the fourth transistor T4; the fifth transistor T5; the sixth transistor T6; the seventh transistor T7; the first capacitor C1; the bootstrap capacitor C2; the first diode D1; the display panel 100; the display area 101; the non-display area 102. DETAILED DESCRIPTION

[0020] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0021] The terms used in the embodiments of the present application are only for the purpose of describing specific embodiments, and are not intended to limit the present application. The singular forms of "a", "said", and "the" used in the embodiments of the present application and the appended claims are also intended to include plural forms, unless otherwise clearly indicated above, and "multiple" generally includes at least two, but does not exclude the inclusion of at least one.

[0022] It should be understood that the term "and / or" used in this article is only a description of the association relationship of associated objects, indicating that three relationships may exist. For example, A and / or B can represent: A exists alone, A and B exist at the same time, and B exists alone. In addition, the character " / " in this article generally indicates that the objects associated with each other are in an "or" relationship. The terms "first", "second", etc. in the specification and claims of this application and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence.

[0023] It should be understood that the terms "include", "comprises" or any other variations used herein are intended to cover non-exclusive inclusion, so that a process, method, article or device that includes a series of elements includes not only those elements, but also includes other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of more restrictions, the elements defined by the sentence "includes..." do not exclude the presence of other identical elements in the process, method, article or device that includes the elements.

[0024] It should be noted that if the embodiments of the present application involve directional indications (such as up, down, left, right, front, back...), such directional indications are only used to explain the relative position relationship, movement status, etc. between the components under a certain specific posture (as shown in the accompanying drawings). If the specific posture changes, the directional indication will also change accordingly.

[0025] Reference to "embodiments" herein means that a particular feature, structure, or characteristic described in conjunction with the embodiments may be included in at least one embodiment of the present application. The presence of the phrase at each location in the specification does not necessarily refer to the same embodiment, nor is it an independent or alternative embodiment that is mutually exclusive with other embodiments. It is explicitly and implicitly understood by those skilled in the art that the embodiments described herein may be combined with other embodiments.

[0026] The charging time t across the capacitor voltage = ; t is the charging time; R is the equivalent resistance; C is the equivalent capacitance; V is the charging voltage; Vc is the charging saturation voltage. It can be seen that when The closer it is to 1, the smaller the t value is, the shorter the charging time is, that is, the larger the charging voltage V is, the shorter the charging time is, and the shorter the H-blanking is. However, in the traditional GOA circuit, the recovery charging voltage used for shutdown comes from the high potential voltage, and the high potential voltage provided by ICs such as TDDI (Touch and Display Driver Integration) generally has a low upper limit. In order to enable the driving transistor to quickly return to the off state after the data voltage is charged, the driving transistor is over-charged once, thereby achieving the purpose of shortening H-blanking.

[0027] The present application provides a gate driving circuit, which includes: a plurality of gate driving units connected in cascade to each other, for details, please refer to Figure 1 , Figure 1 This is a schematic diagram of the structure of an embodiment of the gate drive circuit provided by the present application. Figure 1 As shown, each gate driving unit GOA(n) at least includes: a first cascade unit 11 , a first output unit 12 and an overvoltage output unit 13 .

[0028] Specifically, the gate drive unit of this level is taken as an example of the N-th level gate drive unit GOA(n), and n can be a positive integer. Among them, the previous level gate drive unit GOA(n-1) is also called the N-1-th level gate drive unit, and the next level gate drive unit GOA(n+1) is also called the N+1-th level gate drive unit. It should be noted that the scanning signal output by the N-th level gate drive unit GOA(n) is the N-th level scanning signal Pscan(n), and the previous level scanning signal Pscan(n-1) is the scanning signal output by the previous level gate drive unit GOA(n-1), therefore, it is also called the N-1-th level scanning signal, and the next level scanning signal is also called the N+1-th level scanning signal.

[0029] The first cascade unit 11 is connected to the output end of the previous gate driving unit GOA(n-1) to receive the scan signal Pscan(n-1) output by the previous gate driving unit GOA(n-1). Specifically, the input end of the first cascade unit 11 is connected to the output end of the previous gate driving unit GOA(n-1), the output end is connected to the control end of the first output unit 12, and the control end is connected to a jump signal line to transmit the scan signal Pscan(n-1) of the previous stage to the control end of the first output unit 12 to control the on / off of the first output unit 12, thereby controlling the first output unit 12 to output the scan signal Pscan(n).

[0030] The control end of the first output unit 12 is connected to the output end of the first cascade unit 11, and the input end of the first output unit 12 is connected to a jump signal line, which is used to control the output scanning signal Pscan(n) according to the cascade signal transmitted by the first cascade unit 11. The cascade signal is the previous level scanning signal Pscan(n-1). The scanning signal Pscan(n) includes a start voltage and a cut-off voltage.

[0031] The overvoltage output unit 13 is connected to the first cascade unit 11 , and is configured to output an overvoltage scanning signal according to the cascade signal of the first cascade unit 11 after the first output unit outputs the start-up voltage.

[0032] Among them, the cut-off voltage of the scan signal refers to the voltage that can turn off (shut off) the transistor. The scan signal includes a turn-on voltage and a cut-off voltage. The turn-on voltage is transmitted to the gate of the transistor, which can turn on the source and drain of the transistor. The cut-off voltage is transmitted to the gate of the transistor to turn off the source and drain of the transistor. Specifically, when the transistor is a P-type transistor, the transistor is turned on at a low potential voltage and turned off at a high potential voltage. At this time, the overvoltage scan signal is a voltage higher than the high potential voltage. When the transistor is an N-type transistor, the transistor is turned on at a high potential voltage and turned off at a low potential voltage. At this time, the overvoltage scan signal is a voltage lower than the low potential voltage. The overvoltage scan signal is greater than the cut-off voltage of the scan signal, which means that the absolute value of the overvoltage scan signal is greater than the absolute value of the cut-off voltage of the scan signal. The low potential voltage is usually a negative value. In other words, the overvoltage scan signal is higher than the voltage of the high potential scan signal or lower than the voltage of the low potential scan signal. When the transistor is cut off / off at a low potential, the voltage of the overvoltage scan signal is lower than the voltage of the low potential scan signal, and when the transistor is cut off / off at a high potential, the voltage of the overvoltage scan signal is higher than the voltage of the high potential scan signal.

[0033] In this embodiment, the overvoltage output unit 13 outputs the overvoltage scan signal after the first output unit 12 outputs the turn-on voltage, so that the overvoltage scan signal is greater than the cut-off voltage of the scan signal, thereby accelerating the shutdown of the transistors transmitted to the surface and shortening the blank time.

[0034] In some embodiments, the transistors in the plane are P-type transistors, and the scanning signal is a low-potential pulse signal with a normal high potential, and the transistor is turned on when the low-potential pulse is on and turned off when the high potential is on. In other embodiments, the transistors can also be N-type transistors, and the scanning signal is a high-potential pulse signal with a normal low potential. It should be noted that high potential and low potential are relative, and are not limited to positive or negative values.

[0035] The following description is made by taking a P-type transistor as an example. In other embodiments, an N-type transistor may be used, and the corresponding timing of each signal is opposite.

[0036] For further information, please see Figure 2 , Figure 2 This is a schematic diagram of the structure of the first specific embodiment of the gate driving unit provided in this application. Figure 2 As shown, specifically, the first output unit 12 includes a first transistor T1, the gate of the first transistor T1 is connected to the output end of the first cascade unit 11, and the input end of the first transistor T1 is connected to the first jump signal line CK. The first jump signal line CK transmits a high / low level jump pulse. Specifically, the first jump signal line CK outputs a high potential voltage in the sampling phase and outputs a low potential voltage in the output phase. The high potential voltage is the cut-off voltage of the scanning signal, and the low potential voltage is the start-up voltage of the scanning signal.

[0037] The first output unit 12 also includes a first capacitor C1, and the first plate of the first capacitor C1 is connected to the gate of the first transistor T1, and is used to store the gate voltage charged to the first transistor T1, so that the first transistor T1 remains in the on state in both the sampling stage and the output stage. Specifically, the first plate of the first capacitor C1 is also connected to the output end of the first cascade unit 11 and the input end of the overvoltage output unit 13. Among them, the second plate of the first capacitor C1 is connected to the low potential signal line VGL. In other embodiments, the second plate of the first capacitor C1 can also be connected to the ground line or the high potential signal line, which is not limited here.

[0038] See further Figure 3 , Figure 3 This is a schematic diagram of the structure of the second specific embodiment of the gate driving unit provided in this application. Figure 3 As shown, the overvoltage output unit 13 includes: a bootstrap capacitor C2 , a first control unit 131 and a second cascade unit 132 .

[0039] The first plate of the bootstrap capacitor C2 is connected to the output end of the first cascade unit 11 through the first control unit 131, and the second plate of the bootstrap capacitor C2 is connected to the output end of the gate drive unit GOA(n). By increasing the voltage on the first plate of the bootstrap capacitor C2, the voltage on the second plate of the bootstrap capacitor C2 is coupled to the overvoltage scanning signal and output, so that the overvoltage output unit 13 outputs the overvoltage scanning signal.

[0040] The first control unit 131 is disposed between the first plate of the bootstrap capacitor C2 and the first cascade unit 11 , and is used to control the first cascade unit 11 to charge the first voltage V1 into the first plate of the bootstrap capacitor C2 .

[0041] The second cascade unit 132 is connected to the first plate of the bootstrap capacitor C2, and is used to charge the second voltage V2 to the first plate of the bootstrap capacitor C2. The second voltage V2 is greater than the first voltage V1. Specifically, the first control unit 131 conducts control to charge the first voltage V1 to the first plate of the bootstrap capacitor C2 in the output stage, and the second cascade unit 132 charges the second voltage V2 to the first plate of the bootstrap capacitor C2 in the overvoltage stage after the output stage, so that the second plate of the bootstrap capacitor C2 is coupled to the voltage corresponding to the overvoltage scanning signal.

[0042] In a specific embodiment, the control end of the second cascade unit 132 is connected to the output end of the next-stage gate driving unit GOA(n+1), the input end is connected to the first signal line VGH, and the output end is connected to the first plate of the bootstrap capacitor C2, and is used to control the second cascade unit 132 to charge the second voltage V2 to the first plate of the bootstrap capacitor C2 according to the scan signal Pscan(n+1) output by the next-stage gate driving unit GOA(n+1) in the overvoltage stage. In this specific embodiment, the first signal line VGH is a high-potential signal line for transmitting a high-potential voltage. In other embodiments, other constant voltages can also be transmitted on the first signal line VGH, which is not limited here.

[0043] For further information, please see Figure 4 , Figure 4 This is a schematic diagram of the structure of the third specific embodiment of the gate driving unit provided in the present application. In a further embodiment, the overvoltage output unit 13 also includes an overvoltage output control unit 133, which is arranged between the second plate of the bootstrap capacitor C2 and the output end of the gate driving unit GOA(n) to control the output of the overvoltage output unit 13. Specifically, the overvoltage output unit 13 is turned on in the overvoltage stage and is not turned on in other stages.

[0044] In a preferred embodiment, the control end of the overvoltage output control unit 133 and the control end of the second cascade unit 132 are connected to the same control signal line, that is, they are both connected to the output end of the next-stage gate driving unit GOA(n+1), and the output of the overvoltage output unit 13 is controlled according to the next-stage scan signal Pscan(n+1). Specifically, the overvoltage output control unit 133 is turned on when the next-stage scan signal Pscan(n+1) outputs a low-potential pulse, thereby outputting an overvoltage scan signal in the overvoltage stage (that is, after the output stage). In other embodiments, the control end of the overvoltage output control unit 133 can also be controlled by other control signal lines, which is not limited here. In this specific embodiment, the transistor in the overvoltage output control unit 133 is a P-type transistor.

[0045] The transistors in the second cascade unit 132 are also P-type transistors.

[0046] The specific driving stage in the above embodiment includes a sampling stage, an output stage and an overvoltage stage. Wherein, in the sampling stage, the first cascade unit 11 controls the first output unit 12 to output a high potential voltage. In the output stage, the first cascade unit 11 controls the first output unit 12 to output a low potential voltage. In the output stage, the first control unit 131 transmits the cascade signal stored on the first capacitor C1 to the first plate of the bootstrap capacitor C2, at which time the cascade signal is a low potential voltage, and the first voltage V1 stored on the first plate of the bootstrap capacitor C2 is a low potential voltage. In the overvoltage stage, the second cascade unit 132 charges the first plate of the bootstrap capacitor C2 with a second voltage V2, and the second voltage V2 is a high potential voltage. At the same time, the overvoltage output control unit 133 transmits the voltage on the second plate of the bootstrap capacitor C2 to the output terminal.

[0047] For further information, please see Figure 5 , Figure 5 This is a schematic diagram of the structure of the fourth specific embodiment of the gate driving unit provided in this application. Figure 5 As shown, the overvoltage output unit 13 also includes a third cascade unit 134. The control end of the third cascade unit 134 is connected to the output end of the next-stage gate driving unit GOA (n+1), the input end is connected to the first signal line VGH, and the output end is connected to the second plate of the bootstrap capacitor C2, and is used to charge the second voltage V2 to the second plate of the bootstrap capacitor C2 in the output stage, and the second voltage V2 is a high potential voltage, that is, the starting voltage is charged to the second plate of the bootstrap capacitor C2, so that it is coupled to the overvoltage voltage in the overvoltage stage. In other embodiments, the overvoltage output control unit 133 can also charge the second plate of the bootstrap capacitor C2 with a high potential voltage in the sampling stage, and preferably, the first control unit 131 is used to charge the first plate of the bootstrap capacitor C2 with a low potential voltage at the same time. That is, the first control unit 131 and the overvoltage output control unit 133 are turned on in the sampling stage, so that the voltage is charged to the first plate and the second plate of the bootstrap capacitor C2 respectively. In the output stage, the first control unit 131 and the overvoltage output control unit 133 are turned off, so that the first plate and the second plate of the bootstrap capacitor C2 are suspended, thereby maintaining the voltage stored on the bootstrap capacitor C2.

[0048] The transistors in the third cascade unit 134, the second cascade unit 132 and the overvoltage output control unit 133 are a group of transistors with opposite driving characteristics. Specifically, the transistors in the third cascade unit 134 are N-type transistors, and the transistors in the second cascade unit 132 and the overvoltage output control unit 133 are P-type transistors.

[0049] Furthermore, the gate driving unit further includes a second output unit 14, which is arranged between the first signal line and the output terminal of the gate driving unit GOA(n) and is used to output a high potential voltage (that is, a cut-off voltage) after the overvoltage stage to keep the transistors in the plane in the cut-off state. Figure 6 , Figure 6 This is a schematic diagram of the structure of the fifth specific embodiment of the gate driving unit provided in this application. Figure 6 As shown, the second output unit 14 includes a second transistor T2 and a first diode D1.

[0050] The gate of the second transistor T2 is connected to the first plate of the bootstrap capacitor C2, the input end is connected to the first signal line VGH, and the output end is connected to the output end of the gate driving unit GOA(n), and is used to control the conduction of the second transistor T2 according to the voltage signal on the first plate of the bootstrap capacitor C2, thereby controlling its output cut-off voltage (high potential voltage).

[0051] The anode of the first diode D1 is connected to the output end of the second transistor T2 , and the cathode is connected to the output end of the gate driving unit GOA(n) for controlling the output cut-off voltage thereof.

[0052] Specifically, the second transistor T2 is turned on in the overvoltage stage and after the overvoltage stage to output a high potential voltage. It should be noted that in the overvoltage stage, since the voltage output by the overvoltage output unit 13 is greater than the high potential voltage output by the second transistor T2, the first diode D1 has a cutoff effect.

[0053] In a specific embodiment, the control end of the first cascade unit 11 is connected to the second jump signal line XCK. The second jump signal line XCK and the first jump signal line CK are a set of high / low level jump signals with the same frequency and opposite phases.

[0054] This application provides a circuit structure of a gate drive unit. Figure 7 , Figure 7 This is a schematic diagram of the circuit structure of a specific embodiment of the gate drive unit provided in this application. Figure 7 shown.

[0055] The first output unit 12 includes a first transistor T1 and a first capacitor C1. The second output unit 14 includes a second transistor T2 and a first diode D1. The first cascade unit 11 includes a third transistor T3. The first control unit 131 includes a fourth transistor T4. The second cascade unit 132 includes a fifth transistor T5. The overvoltage output control unit 133 includes a sixth transistor T6. The third cascade unit 134 includes a seventh transistor T7.

[0056] The second transistor T2 and the seventh transistor T7 are N-type transistors, and the remaining transistors are P-type transistors.

[0057] This application also provides a driving timing diagram of a specific embodiment of a gate driving unit. Figure 8 , Figure 8 This is a driving timing diagram of a specific embodiment of the gate driving unit provided in this application. The driving stage includes a sampling stage (first stage), an output stage (second stage), an overvoltage stage (third stage) and a holding stage (fourth stage and fifth stage). For further details, please refer to Figure 9~Figure 13 . Fig. 9 This is a circuit diagram of the first driving stage of a specific embodiment of the gate driving unit provided in the present application. Fig.10 This is a circuit diagram of the second driving stage of a specific embodiment of the gate driving unit provided in the present application. Fig.11 This is a circuit diagram of the third driving stage of a specific embodiment of the gate driving unit provided in this application. Fig.12 This is a circuit diagram of the fourth driving stage of a specific embodiment of the gate driving unit provided in this application. Fig.13 This is a circuit diagram of the fifth driving stage of a specific embodiment of the gate driving unit provided in the present application.

[0058] In the sampling stage, the previous scanning signal Pscan(n-1) transmits a low potential signal, the next scanning signal Pscan(n+1) transmits a high potential signal, the first jump signal line CK transmits a high potential signal, the second jump signal line XCK transmits a low potential signal, and the first signal line VGH transmits a high potential signal. The third transistor T3 is turned on, the fourth transistor T4 is turned off, and the previous scanning signal Pscan(n-1) transmits a low potential signal to the gate of the first transistor T1 and the first plate of the first capacitor C1 through the third transistor T3. The first transistor T1 is turned on, and the first jump signal line CK outputs a high potential signal to the output end of the gate driving unit GOA(n) through the first transistor T1. At the same time, the high potential signal of the next level scanning signal Pscan(n+1) controls the seventh transistor T7 to turn on, and charges the high potential signal to the second plate of the bootstrap capacitor C2. The first plate of the bootstrap capacitor C2 stores a high potential signal in the previous stage, and transmits the high potential signal to the gate of the second transistor T2. The second transistor T2 is turned on, and the first signal line VGH outputs a high potential signal to the output end of the gate drive unit GOA(n) through the second transistor T2 and the first diode D1. It should be noted that whether a high potential is stored on the first plate of the bootstrap capacitor C2, the output end of the gate drive unit GOA(n) outputs a high potential signal. For details, please refer to Fig. 9 , Fig. 9 The solid line in the middle represents signal transmission, the dotted line represents no signal transmission, the red line represents high-potential signal transmission, and the blue line represents low-potential signal transmission.

[0059] In the output stage, the previous level scan signal Pscan(n-1) transmits a high potential signal, the next level scan signal Pscan(n+1) transmits a high potential signal, the first jump signal line CK transmits a low potential signal, the second jump signal line XCK transmits a high potential signal, and the first signal line VGH transmits a high potential signal. The gate of the first transistor T1 remains turned on under the action of the first capacitor C1, and the first jump signal line CK outputs a low potential signal to the output end of the gate drive unit GOA(n) through the first transistor T1. The third transistor T3 is turned off, the fourth transistor T4 is turned on, and the low potential signal stored in the first capacitor C1 in the previous stage is transmitted to the first plate of the bootstrap capacitor C2 through the fourth transistor T4. At the same time, the high potential signal of the next level scan signal Pscan(n+1) controls the seventh transistor T7 to turn on, and charges the high potential signal to the second plate of the bootstrap capacitor C2. At this time, the potential difference between the first plate and the second plate of the bootstrap capacitor C2 is Pscan(n-1)L-VGH. For details, please refer to Fig.10 , Fig.10 The solid line in the middle represents signal transmission, the dotted line represents no signal transmission, the red line represents high-potential signal transmission, and the blue line represents low-potential signal transmission.

[0060] In the overvoltage stage, the previous scanning signal Pscan(n-1) transmits a high potential signal, the next scanning signal Pscan(n+1) transmits a low potential signal, the first jump signal line CK transmits a high potential signal, the second jump signal line XCK transmits a low potential signal, and the first signal line VGH transmits a high potential signal. The third transistor T3 is turned on, the fourth transistor T4 is turned off, and the high potential signal of the previous scanning signal Pscan(n-1) is transmitted to the gate of the first transistor T1 and the first plate of the first capacitor C1 through the third transistor T3. The first transistor T1 is turned off. At the same time, the low potential signal of the next scanning signal Pscan(n+1) controls the seventh transistor T7 to be turned off, controls the fifth transistor T5 and the sixth transistor T6 to be turned on, and the first signal line VGH charges the high potential signal to the first plate of the bootstrap capacitor C2 through the fifth transistor T5. According to the KVL law, at this time, the voltage on the second plate of the bootstrap capacitor C2 is coupled to VGH-Pscan(n-1)L+VGL=2VGH-Pscan(n-1)L>VGH. At this time, Pscan(n-1)L is the low potential signal (low potential voltage) of the previous level scan signal Pscan(n-1), which is a negative value. Further, Pscan(n-1)L is the low potential pulse transmitted on the first jump signal line CK, which is Vck(L). The voltage on the second plate of the bootstrap capacitor C2 is transmitted to the output end of the gate drive unit GOA(n) through the sixth transistor T6, thereby outputting an overvoltage scan signal higher than the high potential scan signal to the output end of the gate drive unit GOA(n). At the same time, the high potential signal on the first plate of the bootstrap capacitor C2 is transmitted to the gate of the second transistor T2, and the second transistor T2 is turned on. At this time, the voltage of the overvoltage scan signal output by the second plate of the bootstrap capacitor C2 is greater than the positive electrode of the first diode D1, and the first diode D1 is turned off. For details, please refer to Fig.11 , Fig.11 The solid line in the middle represents signal transmission, the dotted line represents no signal transmission, the red line represents high-potential signal transmission, and the blue line represents low-potential signal transmission.

[0061] In the first holding stage of the holding stage, the previous level scanning signal Pscan(n-1) transmits a high potential signal, the next level scanning signal Pscan(n+1) transmits a high potential signal, the first jump signal line CK transmits a low potential signal, the second jump signal line XCK transmits a high potential signal, and the first signal line VGH transmits a high potential signal. The third transistor T3 is turned off, the fourth transistor T4 is turned on, and the high potential signal stored on the first plate of the first capacitor C1 is transmitted to the first plate of the bootstrap capacitor C2 through the fourth transistor T4, and is transmitted to the gate of the second transistor T2, controlling the second transistor T2 to turn on, and the first signal line VGH outputs a high potential scanning signal to the output end of the gate driving unit GOA(n) through the second transistor T2. The high potential signal of the next level scanning signal Pscan(n+1) controls the seventh transistor T7 to turn on, the fifth transistor T5, and the sixth transistor T6 to turn off, and the first signal line VGH charges the second plate of the bootstrap capacitor C2 with a high potential signal through the seventh transistor T7, so that the bootstrap capacitor C2 maintains the storage function. For details, please refer to Fig.12 , Fig.12 The solid line in the middle represents signal transmission, the dotted line represents no signal transmission, the red line represents high-potential signal transmission, and the blue line represents low-potential signal transmission.

[0062] In the second holding stage of the holding stage, the previous level scanning signal Pscan(n-1) transmits a high potential signal, the next level scanning signal Pscan(n+1) transmits a high potential signal, the first jump signal line CK transmits a high potential signal, the second jump signal line XCK transmits a low potential signal, and the first signal line VGH transmits a high potential signal. The high potential signal of the next level scanning signal Pscan(n+1) controls the seventh transistor T7 to turn on, the fifth transistor T5, and the sixth transistor T6 to turn off, and the first signal line VGH charges the second plate of the bootstrap capacitor C2 with a high potential signal through the seventh transistor T7, so that the bootstrap capacitor C2 maintains the storage function, so that the high potential signal stored on the first plate of the bootstrap capacitor C2 can be maintained, and then transmitted to the gate of the second transistor T2, controlling the second transistor T2 to remain turned on. The first signal line VGH outputs a high potential scanning signal to the output end of the gate drive unit GOA(n) through the second transistor T2. For details, please refer to Fig.13 , Fig.13 The solid line in the middle represents signal transmission, the dotted line represents no signal transmission, the red line represents high-potential signal transmission, and the blue line represents low-potential signal transmission.

[0063] Before the current frame is completely refreshed, the gate driving unit will continue to work alternately according to the first hold phase h1 and the second hold phase h2 according to the signals on the first jump signal line CK and the second jump signal line XCK, and the scanning signal Pscan(n) will continue to output a high potential signal Vgh, thereby achieving the design purpose.

[0064] This application also provides another circuit structure of the gate drive unit. For details, please refer to Fig.14 , Fig.14 This is a schematic diagram of the circuit structure of another specific embodiment of the gate driving unit provided in this application. Fig.14 As shown, each gate driving unit further includes a third capacitor C3 and an eighth transistor T8, and a first plate of the third capacitor C3 is connected to the output end of the first cascade unit 11 (third transistor T3) and the input end of the overvoltage output unit 13 (fourth transistor T4).

[0065] It should be noted that the third capacitor C3 can improve the stability of the first capacitor C1. In the output stage (second stage), if there is only one first capacitor C1, the first capacitor C1 must drive the first transistor T1 and charge the bootstrap capacitor C2, which may cause the voltage on the first capacitor C1 to jump, and then the gate voltage of the first transistor T1 may jump. In addition, by setting the third capacitor C3, the charging path of the bootstrap capacitor C2 can be greatly reduced and the driving thrust can be increased, thereby improving the response efficiency.

[0066] The input end of the eighth transistor T8 is connected to the first signal line VGH, the output end is connected to the second plate of the bootstrap capacitor C2, and the control end is connected to the first jump signal line CK. The eighth transistor T8 is turned on in the second stage (output stage) and the fourth stage (first holding stage). The eighth transistor T8 is a backup transistor for the seventh transistor T7. Sometimes, for image quality considerations, the gate drive unit GOA (n) usually has a "pre-charge", which is generally more common in LCD display panels. At this time, the rising / falling edges of the waveforms on the second jump signal line XCK and the first jump signal line CK do not completely overlap, that is, when the Nth level gate drive unit GOA (n) is at a low potential, the N+1th level gate drive unit GOA (n+1) may also be at a low potential. The seventh transistor T7 may be weakly turned on or have a low response rate at this time. Therefore, when the Nth level gate drive unit GOA (n) outputs, for the consideration of output stability, an additional eighth transistor T8 branch is added as a backup charging path.

[0067] It should be noted that, in an ideal (standard) cycle, the eighth transistor T8 can be omitted.

[0068] The present application also provides a display panel. Fig.15 , Fig.15 This is a schematic diagram of the structure of an embodiment of a display panel provided by the present application. Fig.15As shown, the display panel 100 includes a display area 101 and a non-display area 102, and the non-display area 102 on one side or opposite sides of the display panel 100 is provided with a gate drive circuit as described in any of the above embodiments, and the gate drive circuit includes a plurality of cascaded gate drive units. The gate drive circuit transmits a scan signal Pscan(n) to each row of pixel units in the display area 101 in sequence. Among them, the scan signal Pscan(n) includes a high potential scan signal, a low potential scan signal and an overvoltage scan signal. In this specific embodiment, the overvoltage scan signal is higher than the high potential scan signal.

[0069] In the above embodiment, all transistors in the above gate drive circuit are P-type transistors. In other embodiments, they may also be N-type transistors, which is not limited here.

[0070] The present application uses the above-mentioned gate drive circuit to provide an overvoltage scan signal after the scan pulse (a low-voltage signal for turning on the transistor), so that the driving transistor in the display panel can quickly return to the off state after the data voltage charging is completed, thereby reducing the time required to turn off the driving transistor, thereby achieving the purpose of shortening the blanking time H-blanking and avoiding display abnormalities caused by incorrect charging or erroneous charging.

[0071] The above are merely embodiments of the present application and are not intended to limit the patent scope of the present application. Any equivalent structure or equivalent process transformation made using the contents of the present application specification and drawings, or directly or indirectly applied in other related technical fields, are also included in the patent protection scope of the present application.

Claims

1. A gate drive circuit, characterized in that: include: A plurality of cascaded gate drive units, each of the gate drive units at least comprising: A first cascade unit connected to the gate driving unit of the previous stage; A first output unit, connected to the first cascade unit, for controlling an output scan signal according to a cascade signal of the first cascade unit; the scan signal includes a start voltage and a cut-off voltage; An overvoltage output unit is connected to the first cascade unit, and is used to output an overvoltage scanning signal according to the cascade signal of the first cascade unit after the first output unit outputs the start-up voltage; wherein the overvoltage scanning signal is greater than the cut-off voltage of the scanning signal.

2. The gate driving circuit according to claim 1, characterized in that: The first output unit includes a first transistor; The gate of the first transistor is connected to the output end of the first cascade unit, and the input end of the first transistor is connected to the first jump signal line; wherein the first jump signal line transmits a high / low level jump signal.

3. The gate driving circuit according to claim 2, characterized in that: The first output unit also includes a first capacitor, a first plate of which is connected to the gate of the first transistor, the output end of the first cascade unit and the input end of the overvoltage output unit, and is used to store the gate voltage charged to the first transistor.

4. The gate driving circuit according to claim 1, characterized in that: The overvoltage output unit comprises: Bootstrap capacitor; A first control unit, disposed between the first electrode plate of the bootstrap capacitor and the first cascade unit, and configured to control the first cascade unit to charge a first voltage into the first electrode plate of the bootstrap capacitor; A second cascade unit, a control end connected to the gate driving unit of the next stage, an input end connected to the first signal line, an output end connected to the first plate of the bootstrap capacitor, and used to charge the first plate of the bootstrap capacitor with a second voltage; Wherein, the second voltage is greater than the first voltage.

5. The gate driving circuit according to claim 4, characterized in that: The overvoltage output unit comprises: An overvoltage output control unit is connected to the second electrode plate of the bootstrap capacitor and is used to control the output of the overvoltage scanning signal.

6. The gate driving circuit according to claim 5, characterized in that: The overvoltage output unit further includes: A third cascade unit, wherein the control end of the third cascade unit is connected to the gate driving unit of the next stage, the input end is connected to the first signal line, and the output end is connected to the second plate of the bootstrap capacitor, and is used to charge the second voltage to the second plate of the bootstrap capacitor.

7. The gate driving circuit according to claim 6, characterized in that: The third cascade unit and the overvoltage output control unit include a group of transistors with opposite driving characteristics; The third cascade unit and the second cascade unit include a group of transistors with opposite driving characteristics; Wherein, the third cascade unit includes an N-type transistor.

8. The gate driving circuit according to claim 4, characterized in that: The gate driving unit further includes: The second output unit is connected to the first signal line and is used to output a cut-off voltage of the scanning signal.

9. The gate driving circuit according to claim 8, characterized in that: The second output unit includes a second transistor and a first diode; The gate of the second transistor is connected to the first plate of the bootstrap capacitor, and the input end is connected to the first signal line, and is used to control the output of the cut-off voltage according to the voltage signal on the first plate of the bootstrap capacitor; The anode of the first diode is connected to the output end of the second transistor, and the cathode is connected to the output end of the gate driving unit, and is used to control the output of the cut-off voltage.

10. A display panel, characterized in that: The display panel comprises the gate driving circuit according to any one of claims 1 to 9.

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