Gate driving circuit and display panel

Abstract

The application discloses a gate driving circuit and a display panel. The gate driving circuit comprises a plurality of shift registers. An Nth stage shift register comprises a stage transmission signal selection module, a pull-up control module, a first filtering module, a second filtering module, a first output module, a first inversion module, an isolation module and a second output module. By connecting a voltage signal smaller than the top gate potential of a second transistor to the bottom gate of the second transistor, the threshold voltage of the second transistor is adjusted to be positively offset. This not only makes the threshold voltage of the second transistor have a larger positive range, but also eliminates the limited range of the threshold voltage of the second transistor. Moreover, the on-state current of the second transistor in the cut-off state is reduced, and the high potential of the second gate driving signal output by the second output module is improved and stabilized.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of display, in particular to a gate drive circuit and a display panel. BACKGROUND

[0002] In a display panel, a gate drive circuit usually provides a required gate drive signal for a transistor corresponding to a pixel circuit.

[0003] However, the threshold voltage drift of some transistors in the gate drive circuit not only limits the range of the threshold voltage of these transistors, but also causes the stability of the pulse amplitude of the gate drive signal provided by the gate drive circuit to decrease. Therefore, this becomes one of the reasons for improving the gate drive circuit. SUMMARY

[0004] The present application provides a gate drive circuit and a display panel to alleviate the technical problem that the threshold voltage drift of a transistor limits the range of the threshold voltage and reduces the stability of the pulse amplitude of the gate drive signal.

[0005] In a first aspect, the present application provides a gate drive circuit, which comprises a plurality of shift registers, and each shift register comprises a stage transmission signal selection module, a pull-up control module, a first filter module, a second filter module, a first output module, a first inverting module, an isolation module, and a second output module. The stage transmission signal selection module is electrically connected between a first node and a first wiring. The pull-up control module controls the potential of a second node according to the potential of the first node and the potential of a first clock signal. The first filter module is electrically connected between the second node and a third node, and the control end of the first filter module is connected to a reset signal. The second filter module is electrically connected between the first filter module and the third node, and the control end of the second filter module is connected to a filter control signal. The first output module outputs a corresponding first gate drive signal according to the potential of the third node and the potential of a fourth node. The first inverting module is electrically connected between the second node and the fourth node. The isolation module is connected in series between the second node and a fifth node, and the control end of the isolation module is connected to the first clock signal. The second output module comprises a first transistor and a second transistor. The first electrode of the first transistor is electrically connected to a high potential line, the gate of the first transistor is electrically connected to the fifth node, the second electrode of the first transistor outputs a corresponding second gate drive signal, and the first transistor is a P-channel transistor. The second transistor is an N-channel transistor, the first electrode of the second transistor is electrically connected to the second electrode of the first transistor, the second electrode of the second transistor is electrically connected to a low potential line, the top gate of the second transistor is electrically connected to the fifth node, and the bottom gate of the second transistor is connected to a voltage signal less than the potential of the fifth node.

[0006] In a second aspect, the present application provides a display panel, which includes a pixel circuit and a gate driving circuit in at least one of the above-mentioned embodiments, the pixel circuit includes a write transistor for controlling the input of a data signal and a compensation transistor for controlling the input of the data signal to the gate of the driving transistor; the output end of the first output module is electrically connected to the gate of the write transistor, and the output end of the second output module is electrically connected to the gate of the compensation transistor.

[0007] The gate drive circuit and display panel provided in the present application can adjust the threshold voltage of the second transistor to shift toward the positive direction by connecting a voltage signal that is less than the top gate potential of the second transistor to the bottom gate of the second transistor. This not only allows the threshold voltage of the second transistor to obtain a larger positive range, but also removes the restriction range on the threshold voltage of the second transistor, and reduces the on-state current of the second transistor in the off state, thereby improving and stabilizing the high potential of the second gate drive signal output by the second output module. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] The following detailed description of the specific embodiments of the present application in conjunction with the accompanying drawings will make the technical solutions and other beneficial effects of the present application apparent.

[0009] Figure 1 Schematic diagram of the structure of a pixel circuit in related technology.

[0010] Figure 2 for Figure 1 A timing diagram of the pixel circuit.

[0011] Figure 3 This is a schematic diagram of the first structure of a gate drive circuit in the related art.

[0012] Figure 4 for Figure 3 The timing diagram of the gate drive circuit shown is shown.

[0013] Figure 5 This is a second structural diagram of a gate drive circuit in the related art.

[0014] Figure 6 for Figure 5 The timing diagram of the gate drive circuit shown is shown.

[0015] Figure 7 A timing diagram of the generation of the Nth level negative pulse gate drive signal provided in an embodiment of the present application.

[0016] Figure 8 for Figure 5 Schematic diagram of the potentials of some nodes in the gate drive circuit shown.

[0017] Figure 9 for Figure 5A schematic diagram of the influence of threshold voltage drift of the second transistor in the illustrated gate driving circuit on output.

[0018] Figure 10 A schematic diagram of the relationship between electrical parameters of a transistor provided for an embodiment of the present application.

[0019] Figure 11 A schematic diagram of the structure of a gate driving circuit provided for an embodiment of the present application.

[0020] Figure 12 A schematic diagram of the structure of a display panel provided for an embodiment of the present application. Figure 3 Or Figure 5 A schematic diagram of the cascade structure between shift registers in the illustrated gate driving circuit.

[0021] Figure 13 A schematic diagram of the structure of a display panel provided for an embodiment of the present application.

[0022] Figure 14 A schematic diagram of the structure of a pixel circuit provided for an embodiment of the present application.

[0023] Figure 15 A schematic diagram of the structure of a display panel provided for an embodiment of the present application. Figure 14 A timing schematic diagram of the pixel circuit. DETAILED DESCRIPTION

[0024] The technical solutions in the embodiments of the present application will be described clearly and completely below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only some of the embodiments of the present application, but not all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative work fall within the scope of protection of the present application.

[0025] In addition, the terms "first", "second" are only used for descriptive purposes, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features, so that the features with "first", "second" can explicitly or implicitly include one or more of the features, and in the description of the present application, the meaning of "multiple" is two or more, unless otherwise explicitly and specifically limited.

[0026] In the gate drive circuit in the invention application with application number 202310191137.9, the N-level negative pulse gate drive signal Pout[N] has one negative pulse in one frame. The N-level positive pulse gate drive signal Nout[N] has two positive pulses in one frame, and the pulse widths of the two positive pulses must be equal and both have a width of 2H. This restricts the width of the positive pulse of the N-level positive pulse gate drive signal Nout[N] to remain consistent and cannot be changed, so that when the width of the positive pulse of the N-level positive pulse gate drive signal Nout[N] is greater than 2H, the number of negative pulses of the N-level negative pulse gate drive signal Pout[N] in one frame will increase.

[0027] Therefore, this will limit Figure 1 The pixel circuit shown is in accordance with Figure 2 Specifically, Figure 1 The pixel circuit shown may include a write transistor T2P, a drive transistor T1P, a first light emission control transistor T5P, a second light emission control transistor T6P, a first initialization transistor T4P, a second initialization transistor T7P, a third initialization transistor T8P, a compensation transistor T3P, a light emitting device D1, a storage capacitor Cst, and at least one of a bootstrap capacitor CbOst.

[0028] The first power line is electrically connected to the first electrode of the first light-emitting control transistor T5P and one end of the storage capacitor Cst, the second electrode of the first light-emitting control transistor T5P is electrically connected to the first electrode of the driving transistor T1P and the first electrode of the writing transistor T2P, the second electrode of the driving transistor T1P is electrically connected to the first electrode of the compensation transistor T3P and the first electrode of the second light-emitting control transistor T6P, the second electrode of the second light-emitting control transistor T6P is electrically connected to the first electrode of the second initialization transistor T7P and the anode of the light-emitting device D1, and the cathode of the light-emitting device D1 is electrically connected to the second power line.

[0029] The light emission control line is electrically connected to the gate of the first light emission control transistor T5P and the gate of the second light emission control transistor T6P.

[0030] The second electrode of the write transistor T2P is electrically connected to the data line, and the gate of the write transistor T2P is electrically connected to one end of the bootstrap capacitor CbOst and receives the Nth-level negative pulse gate drive signal Pout[N]. The second electrode of the second initialization transistor T7P is electrically connected to the second initialization line, and the gate of the second initialization transistor T7P receives the gate drive signal Pscan2.

[0031] The second electrode of the compensation transistor T3P is electrically connected to the gate of the driving transistor T1P, and the gate of the compensation transistor T3P is connected to the N-th stage positive pulse gate driving signal Nout[N].

[0032] The gate of the driving transistor T1P is electrically connected with the other end of the storage capacitor Cst, the other end of the bootstrap capacitor CbOst and the first pole of the first initialization transistor T4P.

[0033] The second pole of the first initialization transistor T4P is electrically connected with the first initialization line, and the gate of the first initialization transistor T4P is inputted with the N-1th positive pulse gate driving signal Nout[N-1].

[0034] The first pole of the third initialization transistor T8P is electrically connected with the first pole of the driving transistor T1P, the second pole of the third initialization transistor T8P is electrically connected with the third initialization line, and the gate of the third initialization transistor T8P shares the gate driving signal Pscan2 with the gate of the second initialization transistor T7P.

[0035] It should be noted that the second initialization line can also be replaced by the first initialization line, so that one wire required by the pixel circuit can be reduced, which is conducive to increasing the density of the pixel circuit in the display panel.

[0036] In the present application, the first pole can be one of the source or the drain, and the second pole can be the other one of the source or the drain. For example, when the first pole is the source, the second pole is the drain; or, when the first pole is the drain, the second pole is the source.

[0037] The first power line is used for transmitting a positive power signal VDD, the second power line is used for transmitting a negative power signal VSS, the potential of the positive power signal VDD is higher than the potential of the negative power signal VSS. The data line is used for transmitting a data signal Data. The light-emitting control line is used for transmitting a light-emitting control signal EM. The first initialization line is used for transmitting a first initialization signal Vi1. The second initialization line is used for transmitting a second initialization signal. The third initialization line is used for transmitting a third initialization signal Vi3. The first gate driving line is used for transmitting the Nth negative pulse gate driving signal Pout[N]. The second gate driving lines connected with different stages of shift registers are respectively used for transmitting the N-1th positive pulse gate driving signal Nout[N-1] and the Nth positive pulse gate driving signal Nout[N].

[0038] As can be seen from the above, in the gate driving circuit shown in the invention application with the application number 202310191137.9, the principle that the Nth negative pulse gate driving signal Pout[N] has one negative pulse in a frame is formed by filtering out the first pulse of the starting control signal STV or the N-Yth positive pulse gate driving signal Nout

N-Y

N-Y

[0039] exist Figure 1 In the pixel circuit shown, in order to realize synchronous conduction of the compensation transistor T3P and the first initialization transistor T4P, the pulse of the N-1th level positive pulse gate drive signal Nout[N-1] and the pulse of the Nth level positive pulse gate drive signal Nout[N] need to partially overlap, which is also Figure 1 The reason why the first initialization transistor T4P in the pixel circuit shown must be connected to the N-1th stage positive pulse gate driving signal Nout[N-1].

[0040] In addition, in order to complete the transmission of the third initialization signal Vi3 through node A and node B to node Q in sequence to reset the potentials of node A, node B, and node Q, the third initialization transistor T8P and the compensation transistor T3P need to be turned on synchronously, which requires the pulse of the gate drive signal Pscan2 to partially overlap with the pulse of the Nth level positive pulse gate drive signal Nout[N].

[0041] And for Figure 1 The pixel circuit shown can continue to use the gate drive signal Pscan2 with a pulse width of only 1H, which requires adjustment Figure 2 The driving timing of the pixel circuit shown in FIG. Figure 1 The gate drive circuit shown is improved.

[0042] In this context, in order to alleviate the technical problem that the gate drive signal pulse is difficult to meet the requirements in terms of time and width, the Figure 3 The gate drive circuit shown in FIG. Figure 4 The gate drive circuit works in the timing shown. The gate drive circuit is described in detail in the invention application with application number 202310922942.4, which can be referenced.

[0043] However, in order to overcome Figure 3 The gate drive circuit shown in the figure is affected by the coupling of the N-level negative pulse gate drive signal Pout[N] during the period when the N-level positive pulse gate drive signal Nout[N] outputs a high potential. Figure 5 The gate drive circuit shown in FIG. Figure 6 The gate drive circuit works in the timing shown. The gate drive circuit is also described in detail in the invention application with application number 202310922942.4, which can be referenced.

[0044] Based on the record of the invention application number 202310922942.4, Figure 7The figure shows the negative pulse generation process of the Nth-level negative pulse gate drive signal Pout[N]. For clarity, the two pulses from right to left in the same signal are referred to as the first pulse and the second pulse, respectively. The second node K transmits the first pulse and the second pulse in a frame. The high voltage of the first portion of the two pulses of the N-2th-level positive pulse gate drive signal Nout[N-2] controls the second filter module 80 to filter out the latter portions of the first pulse and the second pulse output from the second node K. The high voltage of the latter portion of the first pulse of the reset signal RST controls the first filter module 30 to filter out the former portion of the second pulse output from the second node K. At this point, the width of the second pulse at node W is also narrowed. The second pulse output from the second node K is completely filtered out, leaving only the former portion of the first pulse output from the second node K, forming a negative pulse at the third node Q. This negative pulse at the third node Q activates the pull-up module 40, forming a negative pulse of the Nth-level negative pulse gate drive signal Pout[N] with a fixed width.

[0045] Figure 8 Shown Figure 5 Schematic diagram of the waveform of the fifth node N and the second gate drive signal, i.e., the Nth-level positive pulse gate drive signal Nout[N]. For example, when the low potential signal VGL is set to -8V and the voltage of the fifth node N is -3.15V, the gate-source voltage difference of the second transistor T10, which is an indium gallium zinc oxide, is Vgs=4.85V. At this time, the second transistor T10 is in the on state and there will be a relatively small leakage current output. Among them, the high level output by the Nth-level positive pulse gate drive signal Nout[N] is determined by the high potential signal VGH and the low potential signal VGL. Therefore, after the threshold voltage Vth of the second transistor T10 shifts negatively, the leakage current of the second transistor T10 will increase, and the high potential of the Nth-level positive pulse gate drive signal Nout[N] will drop to 7.04V. The threshold voltage of the second transistor T10 drifts negatively, resulting in the threshold voltage of the second transistor T10 being unable to obtain a larger positive threshold voltage, which not only severely limits the operating range of the threshold voltage of the second transistor T10, but also leads to the abnormal high-voltage output of the N-th level positive pulse gate drive signal Nout[N].

[0046] Specific as Figure 9 As shown, during the high-potential output of the N-th level positive pulse gate drive signal Nout[N], as the threshold voltage of the second transistor T10 changes more and more negatively, that is, from △Vth=6V to △Vth=0V, the leakage current or on-state current flowing through the second transistor T10, that is, I-T10, also becomes larger and larger, and the decrease amplitude of the high potential of the N-th level positive pulse gate drive signal Nout[N] also becomes larger and larger, while the influence on the stability of the high potential of the N-th level negative pulse gate drive signal Pout[N] becomes smaller and smaller.

[0047] The research on the electrical property of the double-gate indium gallium zinc oxide (IGZO) thin film transistor shows that, as shown in Figure 10 the threshold voltage Vth is positively biased, the drain-source current Ids will decrease under the same gate-source voltage Vgs; the more negative the Bottom voltage applied by the bottom gate is, the more positive the Vth is, and the mobility changes little.

[0048] Based on the above analysis, the embodiment provides a gate drive circuit, as shown in Figure 11 the gate drive circuit includes a plurality of shift registers, and the shift register includes at least one of a stage transmission signal selection module 10, a pull-up control module 20, a first filter module 30, a second filter module 80, a first output module 46, a first inverting module 50, an isolation module 75, and a second output module 70.

[0049] The stage transmission signal selection module 10 is electrically connected between the first node O[N] and the first wire. The first wire can be between the start control line or the N-Y level positive pulse gate drive line, and Y is an integer greater than or equal to 1.

[0050] The pull-up control module 20 controls the potential of the second node K according to the potential of the first node O[N] and the potential of the first clock signal XCK.

[0051] The first filter module 30 is electrically connected between the second node K and the third node Q, and the control end of the first filter module 30 is connected to the reset signal RST. The reset signal RST can be the N-X level positive pulse gate drive signal Nout[N-X] or other suitable positive pulse signal, and the N-X level positive pulse gate drive signal Nout[N-X] can be transmitted through the N-X level positive pulse gate drive line, and X is an integer greater than or equal to 2.

[0052] The second filter module 80 is electrically connected between the first filter module 30 and the third node Q, and the control end of the second filter module 80 is connected to the filter control signal RST2. The filter control signal RST2 can be a positive pulse gate drive signal of another level, for example, the N-2 level positive pulse gate drive signal Nout[N-2] or the N-3 level positive pulse gate drive signal Nout[N-3].

[0053] The first output module 46 outputs the corresponding first gate drive signal according to the potential of the third node Q and the potential of the fourth node P.

[0054] The first inverting module 50 is electrically connected between the second node K and the fourth node P.

[0055] The isolation module 75 is connected in series between the second node K and the fifth node N, and a control end of the isolation module 75 is connected to the first clock signal XCK.

[0056] The second output module 70 comprises a first transistor T9 and a second transistor T10. The first transistor T9 has a first electrode electrically connected to the high potential line, a gate electrically connected to the fifth node N, and a second electrode outputting a corresponding second gate drive signal. The first transistor T9 is a P-channel transistor.

[0057] The second transistor T10 is an N-channel transistor. The second transistor T10 has a first electrode electrically connected to the second electrode of the first transistor T9, a second electrode electrically connected to the low potential line, a top gate electrically connected to the fifth node N, and a bottom gate connected to a voltage signal smaller than the potential of the fifth node N.

[0058] It can be understood that the gate drive circuit provided by the embodiment can adjust the threshold voltage of the second transistor T10 to be positively offset by connecting the voltage signal smaller than the potential of the top gate of the second transistor T10 to the bottom gate of the second transistor T10. This not only makes the threshold voltage of the second transistor T10 have a larger positive range, but also eliminates the limitation range of the threshold voltage of the second transistor T10. Moreover, the on-state current of the second transistor T10 in the off state is reduced, and the high potential of the second gate drive signal output by the second output module 70 is improved and stabilized.

[0059] It should be noted that, compared with the gate drive circuit shown in Figure 5 , the gate drive circuit shown in Figure 11 does not connect the bottom gate of the second transistor T10 to the top gate of the second transistor T10, but separately connects the voltage signal lower than the potential of the top gate of the second transistor T10 to the bottom gate of the second transistor T10.

[0060] In one of the embodiments, the voltage signal is used to adjust the threshold voltage of the second transistor T10 to be positively offset. This not only can reduce the leakage current, but also can improve and stabilize the high potential output by the second output module 70.

[0061] In one of the embodiments, the voltage signal is also used to adjust the threshold voltage of the second transistor T10 to be greater than 0V. This can further limit the positive offset range of the threshold voltage of the second transistor T10, so as to further reduce the leakage current, and further improve and stabilize the high potential output by the second output module 70.

[0062] In one of the embodiments, the voltage signal is a constant voltage signal, or the voltage signal has two negative pulses in a frame.

[0063] It needs to be explained that in the case that the second transistor T10 is in the off state, the potential of the fifth node N is a negative potential, so that the potential of the voltage signal of the embodiment is more negative than the negative potential of the fifth node N, the threshold voltage of the second transistor T10 can be adjusted to be positively offset, which can not only reduce the leakage current, but also improve and stabilize the high potential output by the second output module 70.

[0064] In one of the embodiments, when the voltage signal is a constant voltage signal, the voltage signal is derived from the low potential line.

[0065] It needs to be explained that the low potential signal VGL of the fixed voltage in the low potential line can also reduce the leakage current, and can also improve and stabilize the high potential output by the second output module 70; at the same time, the low potential line can also be shared, which can reduce the number of lines of the gate drive circuit.

[0066] In one of the embodiments, when the voltage signal has two negative pulses in a frame, the voltage signal is derived from the second node K or the first node O[N+1] in the next stage of the shift register.

[0067] It needs to be explained that under the control of the potential of the second node K or the first node O[N+1] in the next stage of the shift register with two negative pulses, the leakage current can also be reduced, and the high potential output by the second output module 70 can also be improved and stabilized; at the same time, the second node K or the first node O[N+1] in the next stage of the shift register can also be shared, which can reduce the number of lines connected to the gate drive circuit.

[0068] In one of the embodiments, the first inverting module 50 includes a third transistor T3 and a fourth transistor T1, the first electrode of the third transistor T3 is electrically connected with the high potential line, the gate of the third transistor T3 is electrically connected with the second node K, the second electrode of the third transistor T3 is electrically connected with the fourth node P, and the third transistor T3 is a P-channel transistor; the fourth transistor T1 is an N-channel transistor, the first electrode of the fourth transistor T1 is electrically connected with the second electrode of the third transistor T3, the second electrode of the fourth transistor T1 is electrically connected with the low potential line, the top gate of the fourth transistor T1 is electrically connected with the second node K, and the bottom gate of the fourth transistor T1 is connected with a voltage signal smaller than the potential of the second node K.

[0069] It needs to be explained that by connecting the voltage signal smaller than the potential of the top gate of the fourth transistor T1 to the bottom gate of the fourth transistor T1, the threshold voltage of the fourth transistor T1 can be adjusted to be positively offset, which not only makes the threshold voltage of the fourth transistor T1 have a larger positive range, but also eliminates the limited range of the threshold voltage of the fourth transistor T1, and makes the on-state current of the fourth transistor T1 in the off state smaller, improves and stabilizes the high potential of the fourth node P.

[0070] In one of the embodiments, when the fourth transistor T1 is in the off state, the potential of the second node K is a negative potential, so that the potential of the voltage signal which is a constant voltage or has two negative pulses in a frame is more negative than the negative potential of the second node K, the threshold voltage of the fourth transistor T1 can be adjusted to be positively offset, which not only can reduce the leakage current, but also can improve and stabilize the high potential of the fourth node P.

[0071] In one of the embodiments, the low potential line transmits a low potential signal VGL, and when the voltage signal is a constant voltage signal, the voltage signal is the low potential signal VGL. The low potential signal VGL of the fixed voltage in the low potential line can also reduce the leakage current of the fourth transistor T1, and can also improve and stabilize the high potential of the fourth node P; meanwhile, the low potential line can be shared, which can reduce the number of lines of the gate drive circuit.

[0072] In one of the embodiments, when the voltage signal has two negative pulses in a frame, the voltage signal is derived from the second node K or the first node O[N+1] in the next stage of the shift register.

[0073] It should be noted that under the control of the potential of the second node K or the first node O[N+1] in the next stage of the shift register which has two negative pulses, the leakage current of the fourth transistor T1 can also be reduced, and the high potential of the fourth node P can also be improved and stabilized; meanwhile, the second node K or the first node O[N+1] in the next stage of the shift register can be shared, which can reduce the number of lines of the gate drive circuit.

[0074] In one of the embodiments, the voltage signal is also used to adjust the threshold voltage of the fourth transistor T1 to be positively offset and greater than 0V. This can further limit the positive offset range of the threshold voltage of the fourth transistor T1, so as to further reduce the leakage current, and can further improve and stabilize the high potential of the fourth node P.

[0075] In one of the embodiments, the voltage transmission line for transmitting the voltage signal is electrically connected with the first node O[N+1] in the next stage of the shift register.

[0076] It should be noted that the advantage of such arrangement is that the signal frequency of the fifth node N and the first node O[N+1] in the next stage of the shift register is not only the same, but also the voltage of O[N+1] can be more negative due to the absence of the voltage division effect of the pull-up control transistor T2, so as to further reduce the leakage current, and can further improve and stabilize the high potential of the fourth node P or the Nth stage positive pulse gate drive signal Nout[N].

[0077] In summary, when the potential of the fifth node N is -3V, the voltage of O[n+1] is -8V, at this time, the bottom gate of the second transistor T10 and / or the fourth transistor T1 is biased by a voltage of about -8V, and the Vth of the second transistor T10 and / or the fourth transistor T1 is positively biased to 2.5V, compared with Figure 5 The structure design shown can increase the positive range of the threshold voltage of 2V, thereby increasing the reliability of the gate drive circuit.

[0078] It should be noted that, Figure 11 The other descriptions of the gate drive circuit shown can refer to the detailed description of the gate drive circuit shown in the application No. 202310922942.4 Figure 3 The detailed description of the gate drive circuit shown in the application No. 202310922942.4 Figure 5 The detailed description of the gate drive circuit shown in the application No. 202310922942.4.

[0079] Figure 12 For Figure 3 , Figure 5 or or Figure 11 The structure diagram of the cascade structure between different shift registers in the gate drive circuit shown, wherein the first-level shift register, the second-level shift register, the third-level shift register, the N-level shift register, and the N+1-level shift register are arranged from top to bottom. Each shift register works according to the first clock signal XCK and the second clock signal CK.

[0080] The control end of the first filter module 30 and the control end of the second filter module 80 in the first-level shift register are connected to the low potential signal VGL, and the input end (IN) of the first-level shift register connected to the start control line is connected to the start control signal STV. The first-level shift register outputs the corresponding first-level negative pulse gate drive signal Pout[1] and the first-level positive pulse gate drive signal Nout[1]. The first-level negative pulse gate drive signal Pout[1] and the first-level positive pulse gate drive signal Nout[1] are used to drive the dummy pixel (Dummy) or be suspended.

[0081] The control end of the first filter module 30 and the control end of the second filter module 80 in the second-level shift register are connected to the low potential signal VGL, and the start control line connected to the second-level shift register is connected to the cascade signal, i.e., the first-level positive pulse gate drive signal Nout[1]. The second-level shift register outputs the corresponding second-level negative pulse gate drive signal Pout[2] and the second-level positive pulse gate drive signal Nout[2]. The second-level negative pulse gate drive signal Pout[2] and the second-level positive pulse gate drive signal Nout[2] are used to drive the dummy pixel (Dummy) or be suspended.

[0082] The control end of the first filter module 30 and the control end of the second filter module 80 in the third-stage shift register are connected to a low potential signal VGL, and the start control line connected to the third-stage shift register is connected to a cascade signal, that is, a second-stage positive pulse gate drive signal Nout[2]. The third-stage shift register outputs a corresponding third-stage negative pulse gate drive signal Pout[3] and a third-stage positive pulse gate drive signal Nout[3]. The third-stage negative pulse gate drive signal Pout[3] and the third-stage positive pulse gate drive signal Nout[3] are used to drive dummy pixels.

[0083] Other can be analogized in turn, until the control end of the first filter module 30 and the control end of the second filter module 80 in the Nth-stage shift register are connected to an N-Xth-stage positive pulse gate drive signal Nout[N-X] and an N-2th-stage positive pulse gate drive signal Nout[N-2] in turn, respectively, and the start control line connected to the Nth-stage shift register is connected to a cascade signal, that is, an N-1th-stage positive pulse gate drive signal Nout[N-1]. The Nth-stage shift register outputs a corresponding Nth-stage negative pulse gate drive signal Pout[N] and an Nth-stage positive pulse gate drive signal Nout[N]. The Nth-stage negative pulse gate drive signal Pout[N] and the Nth-stage positive pulse gate drive signal Nout[N] are used to drive the first row of pixel circuits (Pixel).

[0084] The control end of the first filter module 30 and the control end of the second filter module 80 in the Nth-stage shift register are connected to an N-Xth-stage positive pulse gate drive signal Nout[N-X] and an N-2th-stage positive pulse gate drive signal Nout[N-2] in turn, respectively, and the start control line connected to the Nth-stage shift register is connected to a cascade signal, that is, an N-1th-stage positive pulse gate drive signal Nout[N-1]. The Nth-stage shift register outputs a corresponding Nth-stage negative pulse gate drive signal Pout[N] and an Nth-stage positive pulse gate drive signal Nout[N]. The Nth-stage negative pulse gate drive signal Pout[N] and the Nth-stage positive pulse gate drive signal Nout[N] are used to drive the first row of pixel circuits (Pixel).

[0085] The other shift registers can be sequentially deduced. It should be noted that since the output terminals of some shift registers are connected with virtual pixels or are suspended, the output terminals of the Nth shift register are not connected with the pixel circuits in the Nth row, but the row number of the pixel circuits connected with the output terminals of the Nth shift register needs to be determined according to the number of the shift registers connected with virtual pixels or suspended.

[0086] Figure 13 The display panel shown includes pixel circuits (Pixel) arranged in an array in the display area, a first gate drive circuit 151 providing an emission control signal EM, a fourth gate drive circuit 154 providing a gate drive signal Pscan2, a second gate drive circuit 152 providing an Nth negative pulse gate drive signal Pout[N] and a gate drive signal Nscan, and a third gate drive circuit 153 providing an Nth negative pulse gate drive signal Pout[N] and a gate drive signal Nscan.

[0087] The first gate drive circuit 151 can be located on the left side of the display area. The output terminal of each shift register in the first gate drive circuit 151 provides an emission control signal EM to two adjacent rows of pixel circuits through a corresponding emission control line, which belongs to single-side driving.

[0088] The fourth gate drive circuit 154 can be located on the right side of the display area. The output terminal of each shift register in the fourth gate drive circuit 154 provides a gate drive signal Pscan2 to one row of pixel circuits through a corresponding gate drive line, which belongs to single-side driving.

[0089] The second gate drive circuit 152 is located between the first gate drive circuit 151 and the display area. The third gate drive circuit 153 is located between the fourth gate drive circuit 154 and the display area. A gate drive line transmitting an Nth negative pulse gate drive signal Pout[N] is electrically connected with the output terminal of a shift register in the second gate drive circuit 152, the output terminal of a shift register in the third gate drive circuit 153, and one row of pixel circuits. A gate drive line transmitting a gate drive signal Nscan is electrically connected with the output terminal of a shift register in the second gate drive circuit 152, the output terminal of a shift register in the third gate drive circuit 153, and one row of pixel circuits, which belongs to double-side driving.

[0090] The second gate drive circuit 152 and the third gate drive circuit 153 can each adopt Figure 3 , Figure 5 or Figure 11The gate drive circuit is shown. The gate drive signal Nscan can include the Nth stage positive pulse gate drive signal Nout[N] and the N-3th stage positive pulse gate drive signal Nout[N-3].

[0091] Because Figure 1 In the pixel circuit shown, the gate of the first initialization transistor T4P needs to access the N-1th stage positive pulse gate drive signal Nout[N-1], Figure 14 In the pixel circuit shown, after the gate of the write transistor T2P accesses the Nth stage negative pulse gate drive signal Pout[N] and the gate of the compensation transistor T3P accesses the Nth stage positive pulse gate drive signal Nout[N], not only can the gate of the third initialization transistor T8P continue to use the existing gate drive signal Pscan2 (no improvement is needed for the fourth gate drive circuit 154), but also the gate of the first initialization transistor T4P can be replaced by the N-3th stage positive pulse gate drive signal Nout[N-3].

[0092] After that, Figure 14 The pixel circuit shown can not only work in the existing stage P12 in a frame, Figure 15 but also can additionally increase a stage P11, in which the three-terminal (Q, A, B) potential of the driving transistor T1P can be reset through the simultaneous conduction of the first initialization transistor T4P and the compensation transistor T3P, so as to reduce the threshold voltage drift of the driving transistor T1P and improve the flicker under different refresh frequencies.

[0093] In one of the embodiments, the embodiment provides a display panel, which includes the gate drive circuit and the pixel circuit in the at least one embodiment.

[0094] It can be understood that, since the display panel provided by the embodiment includes the gate drive circuit in the at least one embodiment, by accessing a voltage signal smaller than the potential of the top gate of the second transistor T10 to the bottom gate of the second transistor T10, the threshold voltage of the second transistor T10 can be adjusted to offset to the positive direction, not only making the threshold voltage of the second transistor T10 have a larger positive range, but also eliminating the limitation range of the threshold voltage of the second transistor T10, and making the on-state current of the second transistor T10 in the off state smaller, and improving and stabilizing the high potential of the second gate drive signal output by the second output module 70.

[0095] In the above embodiments, the description of each embodiment has its own focus, and the parts not described in detail in a certain embodiment can be referred to the related description of other embodiments.

[0096] The above describes the gate drive circuit and the display panel provided by the embodiments of the present application in detail. The principles and implementation manners of the present application are described by using specific examples. The above description of the embodiments is only used to help understand the technical solutions of the present application and the core ideas thereof. Those skilled in the art should understand that the technical solutions recorded in the foregoing embodiments can be modified, or some technical features thereof can be replaced equivalently, and the modification or replacement does not make the essence of the corresponding technical solutions deviate from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A gate drive circuit, characterized in that: The gate driving circuit includes a plurality of shift registers, and the Nth stage shift register includes: a level transmission signal selection module, the level transmission signal selection module being electrically connected between the first node and the first wiring; a pull-up control module, configured to control the potential of the second node according to the potential of the first node and the potential of the first clock signal; a first filtering module, the first filtering module being electrically connected between the second node and the third node, and a control terminal of the first filtering module being connected to a reset signal; a second filtering module, the second filtering module being electrically connected between the first filtering module and the third node, and a control terminal of the second filtering module being connected to a filtering control signal; a first output module, wherein the first output module outputs a corresponding first gate driving signal according to the potential of the third node and the potential of the fourth node; a first inverting module electrically connected between the second node and the fourth node; an isolation module, the isolation module being connected in series between the second node and the fifth node, and a control end of the isolation module being connected to the first clock signal; and A second output module, wherein the second output module includes: a first transistor, wherein a first electrode of the first transistor is electrically connected to the high potential line, a gate of the first transistor is electrically connected to the fifth node, a second electrode of the first transistor outputs a corresponding second gate drive signal, and the first transistor is a P-channel transistor; A second transistor, wherein the second transistor is an N-channel transistor, the first electrode of the second transistor is electrically connected to the second electrode of the first transistor, the second electrode of the second transistor is electrically connected to the low potential line, the top gate of the second transistor is electrically connected to the fifth node, and the bottom gate of the second transistor is connected to a voltage signal that is less than the potential of the fifth node.

2. The gate drive circuit according to claim 1, wherein: The voltage signal is a constant voltage signal, or the voltage signal has two negative pulses in one frame.

3. The gate drive circuit according to claim 2, wherein: When the voltage signal is a constant voltage signal, the voltage signal is derived from the low potential line.

4. The gate drive circuit according to claim 2, wherein: When the voltage signal has two negative pulses in one frame, the voltage signal originates from the second node or the first node in the shift register of the next stage.

5. The gate driving circuit according to claim 1, wherein: The voltage signal is used to adjust the threshold voltage of the second transistor to shift toward a positive direction.

6. The gate driving circuit according to claim 5, wherein: The voltage signal is further used to adjust the threshold voltage of the second transistor to be greater than 0V.

7. The gate driving circuit according to claim 1, wherein: The first inversion module includes: a third transistor, wherein a first electrode of the third transistor is electrically connected to the high potential line, a gate of the third transistor is electrically connected to the second node, a second electrode of the third transistor is electrically connected to the fourth node, and the third transistor is a P-channel transistor; A fourth transistor, wherein the fourth transistor is an N-channel transistor, wherein a first electrode of the fourth transistor is electrically connected to a second electrode of the third transistor, a second electrode of the fourth transistor is electrically connected to the low potential line, a top gate of the fourth transistor is electrically connected to the second node, and a bottom gate of the fourth transistor is connected to the voltage signal having a potential less than that of the second node.

8. The gate driving circuit according to claim 7, wherein: The voltage signal is a constant voltage signal, or the voltage signal has two negative pulses in one frame.

9. The gate driving circuit according to claim 8, wherein: The low-potential line transmits a low-potential signal. When the voltage signal is a constant-voltage signal, the voltage signal is the low-potential signal.

10. The gate driving circuit according to claim 8, wherein: When the voltage signal has two negative pulses in one frame, the potential of the voltage signal is the potential of the second node or the potential of the first node in the shift register of the next stage.

11. The gate driving circuit according to claim 7, wherein: The voltage signal is further used to adjust the threshold voltage of the fourth transistor to shift toward a positive direction and be greater than 0V.

12. A display panel, characterized in that: The display panel includes: a pixel circuit including a write transistor for controlling input of a data signal and a compensation transistor for controlling input of the data signal to a gate of a drive transistor; and The gate drive circuit according to any one of claims 1 to 11, wherein the output end of the first output module is electrically connected to the gate of the write transistor, and the output end of the second output module is electrically connected to the gate of the compensation transistor.

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