Display panel, driving method and display device

Abstract

The embodiment of the invention discloses a display panel, a driving method and a display device. The display panel comprises a pixel circuit and a light-emitting element. The pixel circuit comprises a driving module, a node voltage adjusting module and a first node, and the first node is connected with a driving transistor or a light-emitting element. The node voltage regulation module is configured to write a first voltage regulation signal into a first node in a node voltage regulation stage of a refresh frame; writing a second voltage regulation signal into the first node in a node voltage regulation stage of the holding frame; wherein the first voltage regulation signal and the second voltage regulation signal are both used for regulating the voltage state of the first node, and the voltage of the first voltage regulation signal is different from that of the second voltage regulation signal. According to the embodiment of the invention, the problems that the brightness of the light-emitting element is different and the low-frequency refresh area flickers due to different bias time of the driving transistor between the refresh frame and the holding frame are solved, the display uniformity is ensured, and the display quality is improved.

Description

Technical Field

[0001] Embodiments of the present invention relate to the field of display technology, and in particular to a display panel, a driving method, and a display device. Background Art

[0002] With the development of display technology, new display panels such as Organic Light Emitting Diode (OLED) display panels and Micro Light Emitting Diode (Micro LED) display panels have emerged in an endless stream and are widely favored by consumers.

[0003] Electronic products will use different refresh rates for display in different application scenarios. For example, a higher refresh rate driving method is used to drive the display of dynamic images (such as game scenes) to ensure the smoothness of the displayed images; a lower refresh rate driving method is used to drive the display of slow-motion images or static images to reduce power consumption.

[0004] In some application scenarios, the display screen can also be set to perform dynamic partition refresh, that is, the display screen is divided into several partitions, and different partitions have independent refresh frequencies, thereby achieving the effect of reducing the display screen drive power consumption. However, this dynamic partition refresh method may cause the partition flickering problem, resulting in uneven display and poor display quality. Summary of the invention

[0005] The present invention provides a display panel, a driving method and a display device to improve the flickering problem during dynamic partition refresh, improve display uniformity and enhance display quality.

[0006] In a first aspect, an embodiment of the present invention provides a display panel, including:

[0007] Pixel circuit and light emitting element;

[0008] The pixel circuit includes a driving module and a node voltage regulating module;

[0009] The driving module is configured to provide a driving current for the light emitting element, and the driving module includes a driving transistor;

[0010] The pixel circuit further comprises a first node, the first node being connected to the driving transistor or the light emitting element; the node voltage regulating module being connected to the first node;

[0011] The picture display process of the display panel includes a plurality of display frames, the display panel includes a first partition, the plurality of display frames of the first partition include a refresh frame and a hold frame, and the refresh frame and the hold frame both include a node voltage adjustment stage;

[0012] The node voltage regulation module is configured as follows:

[0013] In the node voltage adjustment phase of the refresh frame, writing a first voltage adjustment signal to the first node;

[0014] In the node voltage adjustment phase of the holding frame, writing a second voltage adjustment signal to the first node;

[0015] The first voltage regulating signal and the second voltage regulating signal are both used to regulate the voltage state of the first node, and the voltage of the first voltage regulating signal is different from the voltage of the second voltage regulating signal.

[0016] In a second aspect, an embodiment of the present invention further provides a method for driving a display panel.

[0017] The display panel includes a pixel circuit and a light-emitting element;

[0018] The pixel circuit includes a driving module and a node voltage regulating module;

[0019] The driving module is configured to provide a driving current for the light emitting element, and the driving module includes a driving transistor;

[0020] The pixel circuit further comprises a first node, the first node being connected to the driving transistor or the light emitting element; the node voltage regulating module being connected to the first node;

[0021] The picture display process of the display panel includes a plurality of display frames, the display panel includes a first partition, the plurality of display frames of the first partition include a refresh frame and a hold frame, and the refresh frame and the hold frame both include a node voltage adjustment stage;

[0022] The driving method comprises:

[0023] In the node voltage regulation phase of the refresh frame, controlling the node voltage regulation module to write a first voltage regulation signal to the first node;

[0024] In the node voltage adjustment phase of the holding frame, controlling the node voltage adjustment module to write a second voltage adjustment signal to the first node;

[0025] The first voltage regulating signal and the second voltage regulating signal are both used to regulate the voltage state of the first node, and the voltage of the first voltage regulating signal is different from the voltage of the second voltage regulating signal.

[0026] In a third aspect, an embodiment of the present invention further provides a display device, comprising any display panel provided by an embodiment of the present invention.

[0027] In the technical solution of the embodiment of the present invention, two different voltage adjustment signals, namely the first voltage adjustment signal and the second voltage adjustment signal, are written respectively in the node voltage adjustment stage of the refresh frame and the hold frame through the node voltage adjustment module, which can respectively meet the differentiated bias adjustment requirements of the driving transistor in the refresh frame and the hold frame, and compensate for the drift of the characteristic curve caused by the forward bias of the driving transistor in the hold frame and the refresh frame, or, the difference in the voltage state of the first node in the refresh frame and the hold frame can be weakened or eliminated, thereby ensuring that the pixel circuit has the same driving process for the light-emitting element in the light-emitting stage, providing the same driving current, and achieving the same light-emitting brightness, solving the problem of difference in the light-emitting brightness of the light-emitting element caused by the different bias time of the driving transistor between the refresh frame and the hold frame, and flickering in the low-frequency refresh area, ensuring display uniformity, and improving display quality. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] Figure 1 is a schematic structural diagram of a display panel provided by an embodiment of the present invention;

[0029] Figure 2 and Figure 3 yes Figure 1 Two schematic diagrams of circuit structures of pixel circuits and light-emitting elements in the display panel are shown;

[0030] Figure 4 is a driving timing diagram of a first subarea pixel circuit provided by an embodiment of the present invention;

[0031] Figure 5 is a flow chart of a driving method of a pixel circuit provided by an embodiment of the present invention;

[0032] Figure 6 is a circuit structure schematic diagram of another pixel circuit and a light-emitting element provided by an embodiment of the present invention;

[0033] Figure 7 and Figure 8 Schematic diagrams of circuit structures of two more pixel circuits and light-emitting elements provided in embodiments of the present invention;

[0034] Fig. 9 is another driving timing diagram of a first subarea pixel circuit provided by an embodiment of the present invention;

[0035] Fig.10 and Fig.11 Schematic diagrams of circuit structures of two more pixel circuits and light-emitting elements provided in embodiments of the present invention;

[0036] Fig.12is a driving timing diagram of a second partition pixel circuit provided by an embodiment of the present invention;

[0037] Fig.13 A schematic structural diagram of a display device provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0038] The present invention will be further described in detail below in conjunction with the accompanying drawings and embodiments. It is to be understood that the specific embodiments described herein are only used to explain the present invention, rather than to limit the present invention. It should also be noted that, for ease of description, only parts related to the present invention, rather than all structures, are shown in the accompanying drawings.

[0039] The terms used in the embodiments of the present invention are only for the purpose of describing specific embodiments, and are not intended to limit the present invention. It should be noted that the directional words such as "upper", "lower", "left", "right" and the like described in the embodiments of the present invention are described at the angles shown in the accompanying drawings and should not be understood as limitations on the embodiments of the present invention. In addition, in the context, it is also necessary to understand that when it is mentioned that an element is formed "on" or "under" another element, it can not only be directly formed "on" or "under" another element, but also indirectly formed "on" or "under" another element through an intermediate element. The terms "first", "second", etc. are only used for descriptive purposes and do not represent any order, quantity or importance, but are only used to distinguish different components. For those of ordinary skill in the art, the specific meanings of the above terms in the present invention can be understood in specific circumstances.

[0040] The term “including” and its variations used in the present invention are open inclusions, that is, “including but not limited to.” The term “based on” means “based at least in part on.” The term “one embodiment” means “at least one embodiment.”

[0041] It should be noted that the concepts such as "first" and "second" mentioned in the present invention are only used to distinguish the corresponding contents, and are not used to limit the order or interdependence.

[0042] It should be noted that the modifications of "one" and "plurality" mentioned in the present invention are illustrative rather than restrictive, and those skilled in the art should understand that, unless otherwise clearly indicated in the context, it should be understood as "one or more".

[0043] As described in the background technology section, the existing display panel drives the light-emitting element to emit light through the pixel circuit to achieve the display function. During display, the driving transistor in the pixel circuit will be in a forward biased state. Long-term forward bias will cause the characteristic curve of the driving transistor to shift and the threshold voltage to change, resulting in the display brightness of the light-emitting element failing to reach the target brightness. Therefore, it is usually necessary to bias the driving transistor during the light-emitting interval of the light-emitting element, that is, to reverse bias the driving transistor to compensate for the influence of long-term forward bias on the characteristics of the driving transistor, avoid changes in the threshold voltage, and ensure the accurate brightness of the light-emitting element.

[0044] However, when reverse bias is performed, a reverse bias signal is usually uniformly provided to each pixel circuit to achieve reverse bias adjustment. For the low-frequency refresh area, the data signal is written in the refresh frame, and the data signal is no longer written in the holding frame, but the display brightness of the refresh frame is maintained. In addition, when the data signal is written, the bias state of the driving transistor will change through the driving transistor, which results in a difference in the time when the driving transistor is in the forward bias state in the refresh frame and the holding frame. Therefore, when a unified reverse bias signal is provided in the refresh frame and the holding frame for bias adjustment, the different bias adjustment requirements of the low-frequency refresh area in each display frame cannot be met, causing differences in the characteristic curves of the driving transistor in the low-frequency refresh area in different display frames, resulting in differences in display brightness between different display frames, and the display of the low-frequency refresh area will change from light to dark, resulting in flickering, which affects the display quality.

[0045] In response to the above technical problems, an embodiment of the present invention provides a display panel, which includes: a pixel circuit and a light-emitting element; the pixel circuit includes a driving module and a node voltage regulation module; the driving module is configured to provide a driving current for the light-emitting element, and the driving module includes a driving transistor; the pixel circuit also includes a first node, and the first node is connected to the driving transistor or the light-emitting element; the node voltage regulation module is connected to the first node; the picture display process of the display panel includes multiple display frames, the display panel includes a first partition, and the multiple display frames of the first partition include refresh frames and hold frames, and the refresh frames and the hold frames both include a node voltage regulation stage.

[0046] The node voltage regulation module is configured to: write a first voltage regulation signal to the first node in the node voltage regulation stage of the refresh frame; write a second voltage regulation signal to the first node in the node voltage regulation stage of the hold frame; wherein the first voltage regulation signal and the second voltage regulation signal are both used to adjust the voltage state of the first node, and the voltage of the first voltage regulation signal is different from the voltage of the second voltage regulation signal.

[0047] In the above technical solution, the display panel has a first partition, and during the picture display process of the display panel, the multiple display frames of the first partition include refresh frames and hold frames, indicating that not all display frames of the first partition are refresh frames, but by setting some display frames as hold frames, the number of refresh frames is limited, so as to control the refresh frequency of the first partition and reduce the power consumption of the panel. Among them, considering the difference in bias time of the driving transistor in the refresh frame and the hold frame, and the influence on the display brightness of the light-emitting element in the two display frames, the embodiment of the present invention determines a node in the pixel circuit that can adjust the bias state of the driving transistor, or a node that will be affected by the bias state of the driving transistor and thus affect the brightness of the light-emitting element, defines it as a first node, and sets a node voltage adjustment module for the first node, and sets a node voltage adjustment stage in both the refresh frame and the hold frame, and writes two different voltage adjustment signals, namely the first voltage adjustment signal and the node voltage adjustment stage in the refresh frame and the hold frame respectively through the node voltage adjustment module. The second voltage regulation signal is used to meet the differentiated bias regulation requirements of the driving transistor in the refresh frame and the hold frame, respectively, to compensate for the drift of the characteristic curve caused by the forward bias of the driving transistor in the hold frame and the refresh frame, or to weaken or eliminate the difference in the voltage state of the first node in the refresh frame and the hold frame, thereby ensuring that the pixel circuit has the same driving process for the light-emitting element in the light-emitting stage, providing the same driving current, and achieving the same light-emitting brightness, solving the problem of difference in the light-emitting brightness of the light-emitting element caused by the different bias time of the driving transistor between the refresh frame and the hold frame, and the flickering problem in the low-frequency refresh area, ensuring display uniformity, and improving display quality.

[0048] The above is the core idea of ​​the present invention. The technical scheme in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0049] Figure 1 is a schematic structural diagram of a display panel provided by an embodiment of the present invention, Figure 2 and Figure 3 yes Figure 1 The following are schematic diagrams of two circuit structures of pixel circuits and light-emitting elements in a display panel. Figure 4 is a driving timing diagram of a first partition pixel circuit provided by an embodiment of the present invention, referring to Figure 1-Figure 4The display panel in the embodiment of the present invention includes a pixel circuit 10 and a light emitting element 20; the pixel circuit 10 includes a driving module 11 and a node voltage regulating module 12; the driving module 11 is configured to provide a driving current for the light emitting element 20, and the driving module 11 includes a driving transistor M1. The pixel circuit 10 also includes a first node N1, the first node N1 is connected to the driving transistor M1 or the light emitting element 20; the node voltage regulating module 12 is connected to the first node N1.

[0050] The picture display process of the display panel includes multiple display frames T, the display panel includes a first partition AA1, and the multiple display frames T of the first partition AA1 include a refresh frame Trefersh and a hold frame Thold, and the refresh frame Trefersh and the hold frame Thold both include a node voltage adjustment stage td; the node voltage adjustment module 12 is configured to: write a first voltage adjustment signal V1 to the first node N1 in the node voltage adjustment stage td of the refresh frame Trefersh; write a second voltage adjustment signal V2 to the first node N1 in the node voltage adjustment stage td of the hold frame Thold; wherein the first voltage adjustment signal V1 and the second voltage adjustment signal V2 are both used to adjust the voltage state of the first node N1, and the voltage of the first voltage adjustment signal V1 is different from the voltage of the second voltage adjustment signal V2.

[0051] First, it can be understood by those skilled in the art that the pixel circuit 10 is electrically connected to the light-emitting element 20, and a driving current is provided to the light-emitting element 20 to drive the light-emitting element 20 to emit light. Several light-emitting elements 20 of different colors can form a pixel unit, and the pixel unit can present different colors by matching the colors of several light-emitting elements 20, and then a display picture can be formed macroscopically by the cooperation of a certain number of pixel units. The time for the display panel to sequentially drive the corresponding light-emitting element 20 to emit light using each pixel circuit 10 to display a display picture is called a display frame T, and multiple display frames T are displayed continuously to form an animation. It should be noted that each light-emitting element 20 in the display panel does not emit light at the same time, but is driven to emit light in sequence by scanning, and a picture is displayed through the visual persistence effect of a person. At the same time, different data signals Vdata are written to the pixel circuit 10 in different display frames, and the pixel circuit 10 provides different driving currents to the light-emitting element 20, so that the pixel unit emits light in different colors, thereby displaying different pictures in each display frame, and realizing a continuous dynamic picture through the visual persistence effect of a person.

[0052] refer to Figure 4On the basis of ensuring that a continuous picture is achieved through the visual persistence effect of a person, the pixel circuits 10 in different areas of the display panel can be designed to have independent data signal writing frequencies. In other words, the pixel circuits 10 in some areas, such as the first partition AA1, can be designed to write data signals Vdata only in some display frames to refresh the luminous brightness of the light-emitting element 20. For the pixel circuits 10 in this area, this display frame is the refresh frame Trefresh. In a part of the display frames T after the refresh frame Trefresh, the data signal Vdata written in the refresh frame Trefresh is maintained, and the brightness of the light-emitting element 20 in the refresh frame Trefresh is maintained to continue to emit light, so that the area continues to display the same picture. For the pixel circuits 10 in this area, the display frame at this time is the hold frame Thold. It can be seen from this that by controlling the frequency of writing the data signal Vdata to the pixel circuit 10, that is, changing the number and ratio of the refresh frame Trefresh and the hold frame Thold, the frequency of the refresh frame Trefresh in the area can be adjusted to achieve control of the picture refresh frequency.

[0053] For the process of driving the light emitting element 20 by writing the data signal Vdata into the pixel circuit, refer to Figure 2-Figure 4 First, to ensure the normal driving of the pixel circuit 10, illustratively, the pixel circuit 10 in the display panel may include a data writing module 13, a compensation module 14, a gate reset module 15 and a light emitting control module 16 in addition to the driving module 11 and the node voltage regulating module 12;

[0054] The refresh frame also includes a gate reset phase ta, a data writing phase tb and a light emitting phase tc, wherein the data writing phase tb is located between the gate reset phase ta and the light emitting phase tc; the hold frame Thold also includes a light emitting phase tc;

[0055] The data writing module 13 is connected between the data signal terminal Vdata and the first electrode of the driving transistor M1, and is configured to be controlled by the data writing control signal SP, and write the data signal Vdata to the gate of the driving transistor M1 during the data writing phase tb of the refresh frame Trefresh;

[0056] The compensation module 14 is connected between the gate and the second electrode of the driving transistor M1 and is configured to be controlled by the threshold compensation control signal S2N to compensate the threshold voltage of the driving transistor M1 during the data writing phase tb of the refresh frame Trefresh;

[0057] The gate reset module 15 is connected to the gate reset signal terminal Vref1 and the gate of the driving transistor M1, and is configured to be controlled by the gate reset control signal S1N, and reset the potential of the gate of the driving transistor M1 in the gate reset phase Ta of the refresh frame Trefresh;

[0058] The light-emitting control module 16 is connected to the driving module 11 and the light-emitting element 20 at the first power signal terminal PVDD and the second power signal terminal PVEE respectively, and is configured to be controlled by the light-emitting control signal Emit, and control the light-emitting element 20 to light up during the light-emitting phase tc of the refresh frame Trefresh and the light-emitting phase tc of the hold frame Thold.

[0059] Further, the light control module 16 includes a first light control unit 161 and a second light control unit 162. The first light control unit 161, the driving module 11, the second light control unit 162, and the light emitting element 20 are sequentially connected in series between the first power signal terminal PVDD and the second power signal terminal PVEE. The pixel circuit 10 may also include a storage capacitor Cst, which is connected between the first power signal terminal PVDD and the gate of the driving transistor M1.

[0060] The above-mentioned circuit modules can be specifically composed of transistors, and the channel type of the transistor can be N-type or P-type. Figure 2 and Figure 3 Except for the compensation module 14 and the gate reset module 15 which are N-type channel transistors, the other circuit modules can all use P-type channel transistors. The storage capacitor Cst is used to store the data signal Vdata written into the gate of the driving transistor M1.

[0061] Below Figure 2 and Figure 3 Taking the pixel circuit shown in the figure as an example, the driving process and principle of the pixel circuit are introduced. Figure 2-Figure 4 In the refresh frame Trefresh, the pixel circuit 10 includes a gate resetting phase ta, a data writing phase tb and a light emitting phase tc.

[0062] In the gate reset stage ta, the gate reset control signal S1N received by the gate of the gate reset transistor M5 in the gate reset module 15 is at a high level, which is a valid pulse signal. The gate reset module 15 is turned on, and the gate reset signal Vref1 is input to the gate of the driving transistor M1 to reset the gate of the driving transistor M1.

[0063] In the data writing phase tb, the data writing control signal SP received by the gate of the data writing transistor M3 in the data writing module 13 is at a low level, which is a valid pulse signal, and the data writing module 13 is turned on; at the same time, the threshold compensation control signal S2N received by the gate of the compensation transistor M4 in the compensation module 14 is at a high level, which is a valid pulse signal, and the compensation module 14 is turned on. The data signal Vdata is input to the gate of the driving transistor M1 through the data writing module 13, the driving module 11, and the compensation module 14, and is stored by the storage capacitor Cst.

[0064] In the light-emitting stage tc, the gates of the first light-emitting control transistor M61 in the first light-emitting control unit 161 and the second light-emitting control transistor M62 in the second light-emitting control unit 162 both receive the light-emitting control signal Emit, which is at a low level and a valid pulse. The first light-emitting control unit 161 and the second light-emitting control unit 162 are turned on, and the driving transistor M1 provides a corresponding driving current to the light-emitting element 20 according to the data signal Vdata stored in the gate, so that the light-emitting element 20 emits light at the target brightness.

[0065] As can be seen from the above, the light emitting element 20 can be controlled by the data signal Vdata to display the target brightness corresponding to the data signal Vdata in the current display frame, namely the refresh frame Trefresh. Figure 4 It can be seen from the refresh frame Trefersh and the hold frame Thold that in the hold frame Thold of the first partition AA1, the gate reset control signal S1N received by the gate of the gate reset transistor M5, the threshold compensation control signal S2N received by the gate of the compensation transistor M4, and the data write control signal SP received by the gate of the data write transistor M3 all have no valid pulses, that is, there is no gate reset stage ta and data write stage tb. However, the light emitting control signal Emit received by the gates of the first light emitting control transistor M61 and the second light emitting control transistor M62 has a valid pulse, that is, there is a light emitting stage tc. It can be seen that in the hold frame Thold, the pixel circuit 10 includes a light emitting stage tc, but does not set the gate reset stage ta and the data write stage tb, and only maintains the target brightness in the refresh frame Trefresh for display.

[0066] Further, as mentioned above, for the first partition AA1, there is a light-emitting phase tc in both the refresh frame Trefresh and the hold frame Thold, which will cause the driving transistor M1 to be in a forward biased state for a long time, causing the electrical characteristic curve to drift. And because the refresh frame Trefresh and the hold frame Thold differ in whether there is a data writing phase tb, the degree of drift of the electrical characteristic curve of the driving transistor M1 will be different. In view of this, in the embodiment of the present invention, reference Figure 2 and Figure 3 A node voltage adjustment module 12 is provided in the pixel circuit to adjust the node in the pixel circuit that is affected by the difference in the drift of the electrical characteristic curve of the driving transistor M1, so as to reduce or avoid the difference in the brightness of the light emitting element 20 caused by the difference. Specifically, an embodiment of the present invention also provides a driving method for a pixel circuit. Figure 5 is a flowchart of a driving method of a pixel circuit provided by an embodiment of the present invention, with reference to Figure 2-Figure 5 Specifically, the driving method includes:

[0067] S110 . In a node voltage regulation phase of a refresh frame, control a node voltage regulation module to write a first voltage regulation signal to a first node.

[0068] S120 . In the node voltage regulation phase of the maintenance frame, control the node voltage regulation module to write a second voltage regulation signal to the first node.

[0069] refer to Figure 2-Figure 4 , the refresh frame Trefresh and the hold frame Thold are also provided with a node voltage adjustment stage td, which does not overlap with the light-emitting stage ta, that is, it is set in the non-light-emitting stage of the pixel circuit, so that when the voltage state of the node in the pixel circuit 10 is adjusted, the light-emitting process of the light-emitting element 20 will not be disturbed. In addition, the node voltage adjustment stage td is substantially set before the light-emitting stage ta, so that in the node voltage adjustment stage td, by controlling the node voltage adjustment module 12 to write a voltage adjustment signal to the first node N1, the node in the pixel circuit affected by the difference in the drift of the electrical characteristic curve of the driving transistor M1 can be adjusted in advance, and the pixel circuit 10 in the current display frame T is adjusted, so as to unify the light-emitting brightness of the light-emitting element 20 in the light-emitting stage ta. Among them, the first voltage adjustment signal V1 is written in the node voltage adjustment stage td of the refresh frame Trefresh, and the second voltage adjustment signal V2 is written in the node voltage adjustment stage td of the hold frame Thold, the purpose of which is to specifically adjust the voltages of the nodes in the refresh frame Trefresh and the hold frame Thold, respectively, to meet the demand for unified light-emitting brightness.

[0070] Specifically, the present invention provides examples of nodes that need to be adjusted in the pixel circuit. Figure 2 and Figure 3 First, it should be noted that, for ease of understanding, the embodiment of the present invention uses the same symbol to represent the signal terminal and the signal connected to the pixel circuit, and no distinction is made.

[0071] like Figure 2As shown, in a specific embodiment, the first end of the node voltage regulation module 12 is connected to the first voltage regulation signal end V1 and the second voltage regulation signal end V2, and the first electrode of the driving transistor M1 is connected to the second end of the node voltage regulation module 12 as the first node N1; the first voltage regulation signal end V1 receives the first voltage regulation signal V1, and the second voltage regulation signal end V2 receives the second voltage regulation signal V2; in the node voltage regulation phase td of the refresh frame Trefresh, the node voltage regulation module 12 turns on the first voltage regulation signal end V1 and the first electrode of the driving transistor M1 to write the first voltage regulation signal V1 to the first electrode of the driving transistor M1; in the node voltage regulation phase td of the hold frame Thold, the node voltage regulation module 12 turns on the second voltage regulation signal end V2 and the first electrode of the driving transistor M1 to write the second voltage regulation signal V2 to the first electrode of the driving transistor M1; wherein, the first voltage regulation signal V1 and the second voltage regulation signal V2 are both used to adjust the voltage state of the driving transistor M1.

[0072] In this embodiment, the first node N1 is substantially the first pole of the driving transistor M1, and the node voltage regulating module 12 regulates the voltage state of the first pole of the driving transistor M1, which is substantially regulating the bias state of the driving transistor M1, and the node voltage regulating stage td is substantially the bias regulating stage. It can be understood that in the light-emitting stage ta of the refresh frame Trefresh and the holding frame Thold, the voltage of the first pole of the driving transistor M1 is greater than the voltage of the second pole, and is in a forward biased state, which will cause the driving transistor M1 to be in a forward biased state for a long time, resulting in a drift of the electrical characteristic curve. In this embodiment, the node voltage regulating stage td, i.e., the bias regulating stage, is set in both the refresh frame Trefresh and the holding frame Thold, and the bias state of the driving transistor M1 can be adjusted before the light-emitting stage ta, that is, the voltage regulating signal, i.e., the bias regulating signal, can be written to the first pole of the driving transistor M1 in this bias regulating stage, so that the voltage of the first pole is less than the voltage of the second pole, and is in a reverse biased state, thereby compensating for the drift of the electrical characteristic curve caused by the forward bias, and ensuring the electrical stability of the driving transistor M1. At the same time, the present embodiment writes different voltage adjustment signals in the bias adjustment stages of the refresh frame Trefresh and the hold frame Thold, namely, the first voltage adjustment signal V1 and the second voltage adjustment signal V2. The two bias adjustment signals are differentiated to compensate for the difference in the forward bias state between the refresh frame Trefresh and the hold frame Thold due to the presence or absence of the data writing stage tb, thereby meeting their respective requirements for bias state adjustment, so that the driving transistor M1 has the same and stable electrical state, ensuring that the light-emitting element 20 has the same luminous brightness in the light-emitting stage ta.

[0073] It should be noted that in Figure 2In the pixel circuit shown, the node voltage adjustment module 12 is substantially a bias adjustment module for adjusting the bias state of the driving transistor M1. In addition, the pixel circuit also includes an anode reset module 17 connected between the anode of the light emitting element 20 and the anode reset signal terminal Vref2.

[0074] I would also like to add that, as for the magnitude relationship of the two voltage adjustment signals, it can be understood that, since the data writing stage tb is added to the refresh frame Trefresh, the driving transistor M1 will be in a reverse bias state during the data writing stage tb, which will compensate the forward bias of the driving transistor M1 during the light-emitting stage to a certain extent, thereby making the driving transistor M1 relatively weaker in the refresh frame Trefresh than in the holding frame Thold. Therefore, the bias adjustments performed in the node voltage adjustment stage td in the refresh frame Trefresh and the node voltage adjustment stage td in the holding frame Thold should be different, and the first node voltage adjustment signal V1 and the second node voltage adjustment signal V2, i.e., the two bias adjustment signals, respectively input in the two voltage adjustment stages should be different. In actual use, through the verification of the flicker adjustment of the display panel, generally, the second node voltage adjustment signal V2 provided to the holding frame Thold will be greater than the first node voltage adjustment signal V1 provided to the refresh frame Trefresh. Of course, due to the complexity of the circuit structure, when providing the first node voltage adjustment signal V1 and the second node voltage adjustment signal V2, the degree to which the driving transistor M1 is affected by the forward bias state in the hold frame Thold and the refresh frame Trefresh can be determined based on simulation or actual measurement, so as to determine the specific values ​​and sizes of the first node voltage adjustment signal V1 and the second node voltage adjustment signal V2. The embodiments of the present invention do not impose too many restrictions on this.

[0075] like Figure 3As shown, in another specific embodiment, the first end of the node voltage regulation module 12 is connected to the first voltage regulation signal end V1 and the second voltage regulation signal end V2, and the anode of the light-emitting element 20 is connected to the second end of the node voltage regulation module 12 as the first node N1; the first voltage regulation signal end V1 receives the first voltage regulation signal V1, and the second voltage regulation signal end V2 receives the second voltage regulation signal V2; in the node voltage regulation phase td of the refresh frame Trefresh, the node voltage regulation module 12 turns on the first voltage regulation signal end V1 and the anode of the light-emitting element 20 to write the first voltage regulation signal V1 to the anode of the light-emitting element 20; in the node voltage regulation phase td of the hold frame Thold, the node voltage regulation module 12 turns on the second voltage regulation signal end V2 and the anode of the light-emitting element 20 to write the second voltage regulation signal V2 to the anode of the light-emitting element 20; wherein, the first voltage regulation signal V1 and the second voltage regulation signal V2 are both used to reset the potential of the anode of the light-emitting element 20.

[0076] In this embodiment, the first node N1 is actually the anode of the light emitting element 20, and the node voltage regulating module 12 regulates the voltage state of the anode of the light emitting element 20, which is actually resetting the anode of the light emitting element 20, and the node voltage regulating stage td is actually the anode resetting stage. It can be understood that in the light emitting stage ta of the refresh frame Trefresh and the hold frame Thold, the path between the first power signal terminal PVDD and the second power signal terminal PVEE is turned on, and the voltage of the anode of the light emitting element 20 directly determines the current passing through the light emitting element 20, that is, determines the brightness of the light emitting element 20. In each display frame T, in order to avoid the influence of the charge stored in the anode of the light emitting element 20 in the previous display frame T on the light emitting brightness of the current display frame T, it is necessary to reset the anode voltage of the light emitting element 20 before the light emitting stage ta. In this embodiment, the node voltage adjustment stage td, i.e., the anode reset stage, is set in both the refresh frame Trefresh and the hold frame Thold. The anode voltage of the light-emitting element 20 can be reset before the light-emitting stage ta. That is, the voltage adjustment signal, i.e., the anode reset signal, can be written to the first electrode of the driving transistor M1 in this anode reset stage to avoid the charge stored in the anode of the light-emitting element 20 from affecting the light emission. At the same time, because there is a difference in the bias state of the driving transistor M1 between the refresh frame Trefresh and the hold frame Thold, which will affect the difference in the anode voltage of the light-emitting element 20, therefore, in this embodiment, different voltage adjustment signals, i.e., the first voltage adjustment signal V1 and the second voltage adjustment signal V2, are written in the anode reset stage of the refresh frame Trefresh and the hold frame Thold, respectively. The two bias adjustment signals are differentiated to compensate for the difference in the anode voltage of the light-emitting element 20 in the refresh frame Trefresh and the hold frame Thold, thereby satisfying their respective requirements for anode reset, so that the anode of the light-emitting element 20 has the same initialization state, and ensures that the light-emitting element 20 has the same light-emitting brightness in the light-emitting stage ta.

[0077] It should be noted that in Figure 3 In the pixel circuit shown, the node voltage adjustment module 12 is substantially an anode reset module for resetting the anode potential of the light emitting element 20. In addition, the pixel circuit also includes a bias adjustment module 18 connected between the first electrode of the driving transistor M1 and the bias adjustment signal terminal DVH.

[0078] It is also necessary to add that, due to the complexity of the circuit structure, when providing the first node voltage adjustment signal V1 and the second node voltage adjustment signal V2, the difference in the influence of the bias state difference of the driving transistor M1 on the anode of the light-emitting element 20 can be determined based on simulation or actual measurement, so as to determine the specific values ​​and sizes of the first node voltage adjustment signal V1 and the second node voltage adjustment signal V2. The embodiments of the present invention do not impose too many restrictions on this.

[0079] Figure 6 is a circuit structure diagram of another pixel circuit and a light-emitting element provided by an embodiment of the present invention, with reference to Figure 6 In the embodiment of the present invention, two node voltage adjustment modules 12 may be provided at the same time, namely, a bias adjustment module 18 and an anode reset module 17 .

[0080] Specifically, the first end of the bias adjustment module 18 is connected to the first bias adjustment signal end DVHA and the second bias adjustment signal end DVHB, and the first electrode of the driving transistor M1 is connected to the second end of the node voltage adjustment module 12 as the first node N1'; the first bias adjustment signal end DVHA receives the first bias adjustment signal DVHA, and the second bias adjustment signal end DVHB receives the second bias adjustment signal DVHB; in the node voltage adjustment phase td of the refresh frame Trefresh, the bias adjustment module 18 turns on the first bias adjustment signal end DVHA and the first electrode of the driving transistor M1 to write the first bias adjustment signal DVHA to the first electrode of the driving transistor M1; in the node voltage adjustment phase td of the hold frame Thold, the bias adjustment module 18 turns on the second bias adjustment signal end DVHB and the first electrode of the driving transistor M1 to write the second bias adjustment signal DVHB to the first electrode of the driving transistor M1; wherein the first bias adjustment signal DVHA and the second bias adjustment signal DVHB are both used to adjust the voltage state of the driving transistor M1.

[0081] The first end of the anode reset module 17 is connected to the first anode reset signal end Vref1 and the second anode reset signal end Vref2, and the anode of the light-emitting element 20 is connected to the second end of the anode reset module 17 as the first node N1″; the first anode reset signal end Vref1 receives the first anode reset signal Vref1, and the second anode reset signal end Vref2 receives the second anode reset signal Vref2; in the node voltage adjustment phase td of the refresh frame Trefresh, the anode reset module 17 turns on the first anode reset signal end Vref1 and the anode of the light-emitting element 20 to write the first anode reset signal Vref1 to the anode of the light-emitting element 20; in the node voltage adjustment phase td of the hold frame Thold, the anode reset module 17 turns on the second anode reset signal end Vref2 and the anode of the light-emitting element 20 to write the second anode reset signal Vref2 to the anode of the light-emitting element 20; wherein, the first anode reset signal Vref1 and the second anode reset signal Vref2 are both used to reset the potential of the anode of the light-emitting element 20.

[0082] Continue to refer to Figure 2 and Figure 3 , the specific structure and driving principle of the node voltage regulation module in the embodiment of the present invention are introduced. Specifically, the node voltage regulation module 12 may include a first transistor M21 and a second transistor M22, the first ends of the first transistor M21 and the second transistor M22 are both connected to the first node N1, the second end of the first transistor M21 is connected to the first voltage regulation signal end V1, and the second end of the second transistor M22 is connected to the second voltage regulation signal end V2; the first transistor M21 is configured to be turned on in the node voltage regulation phase td of the refresh frame Trefresh; the second transistor M22 is configured to be turned on in the node voltage regulation phase td of the hold frame Thold.

[0083] In an optional embodiment, the gates of the first transistor M21 and the second transistor M22 can be connected to corresponding control signals for on-off control. For the first transistor M21, a corresponding control signal is used to provide a valid pulse at least in the node voltage adjustment phase td of the refresh frame Trefresh to control the first transistor M21 to be turned on; for the second transistor M22, a corresponding control signal is used to provide a valid pulse at least in the node voltage adjustment phase td of the hold frame Thold to control the second transistor M22 to be turned on.

[0084] Based on this, in the driving method provided by the present invention, step S110 can be specifically refined as follows:

[0085] The first transistor M21 is controlled to be turned on in the node voltage adjustment phase td of the refresh frame Trefresh.

[0086] Step S120 can be specifically broken down into:

[0087] The second transistor M22 is controlled to be turned on during the node voltage adjustment phase td of the hold frame Thold.

[0088] refer to Figure 4 In a specific embodiment of the present invention, the channel types of the first transistor M21 and the second transistor M22 are opposite, and the gates of the first transistor M21 and the second transistor M22 receive the same first voltage regulating control signal SW.

[0089] More specifically, continue to refer to Figure 4 , the first transistor M21 can be optionally a P-type channel transistor, and the second transistor M22 can be optionally an N-type channel transistor; the first voltage regulation control signal SW is configured to be a first voltage V1_SW at least in the node voltage regulation phase td of the refresh frame Trefresh; the first voltage regulation control signal SW is configured to be a second voltage V2_SW at least in the node voltage regulation phase td of the hold frame Thold; wherein, V1_SW<V2_SW.

[0090] In the node voltage regulation stage td of the refresh frame Trefresh, for the P-type first transistor M21, the first voltage regulation control signal SW at the first voltage V1_SW is at a valid level, thereby controlling the first transistor M21 to be turned on; for the N-type second transistor M22, the first voltage regulation control signal SW at the first voltage V1_SW is at an invalid level, thereby controlling the second transistor M22 to be turned off, thereby controlling the first transistor M21 to be turned on, so that the node voltage regulation module 12 writes the first node voltage regulation signal V1 to the first node N1.

[0091] In the node voltage regulation stage td of the holding frame Thold, for the P-type first transistor M21, the first voltage regulation control signal SW at the second voltage V2_SW is an invalid level, so that the first transistor M21 can be controlled to be turned off, and for the N-type second transistor M22, the first voltage regulation control signal SW at the second voltage V2_SW is an invalid level, so that the second transistor M22 can be controlled to be turned on, thereby, the second transistor M22 can be controlled to be turned on, so that the node voltage regulation module 12 writes the second node voltage regulation signal V2 to the first node N1.

[0092] Of course, in another embodiment of the present invention, the first transistor M21 can be selected as an N-type channel transistor, and the second transistor M22 can be selected as a P-type channel transistor; the first voltage regulation control signal SW is configured as the first voltage V1_SW at least in the node voltage regulation phase td of the refresh frame Trefresh; the first voltage regulation control signal SW is configured as the second voltage V2_SW at least in the node voltage regulation phase td of the hold frame Thold; wherein, V1_SW>V2_SW.

[0093] Those skilled in the art will appreciate that since the channels of the first transistor M21 and the second transistor M22 are opposite to those in the previous embodiment, and the voltage of the first voltage regulation control signal SW is also opposite to that in the previous embodiment, their on and off states remain consistent with those in the previous embodiment, and the same node voltage regulation signal input control can be achieved, which will not be repeated here.

[0094] Further, continue to refer to Figure 2 and Figure 3 The node voltage regulation module 12 also includes a third transistor M23, a first end of the third transistor M23 is connected to the first end of the first transistor M21 and the second transistor M22, and a second end of the third transistor M23 is connected to the first node N1; the third transistor M23 is configured to be turned on in both the node voltage regulation phase td of the refresh frame Trefresh and the node voltage regulation phase td of the hold frame Thold.

[0095] First, if Figure 2 In the pixel circuit shown, the anode reset module 17 may specifically include an anode reset transistor M7, and the gate of the anode reset transistor M7 receives the scanning signal SPX as an anode reset control signal. Figure 3 In the pixel circuit shown in FIG. 1 , the bias adjustment module 18 may specifically include a bias adjustment transistor M8, and the gate of the bias adjustment transistor M8 receives the scanning signal SPX as a bias adjustment control signal. Figure 2 and Figure 3 In the pixel circuit shown, the third transistor M23 is also configured to be controlled by the scan signal SPX, thereby avoiding the need to set control signal lines for the anode reset and bias adjustment in the pixel circuit respectively, reducing the number of signal lines in the pixel circuit, helping to reduce the area of ​​the pixel circuit and improve the resolution of the panel. Based on the fact that the anode reset and bias adjustment share the same scan signal SPX for control, it can be understood that the node voltage adjustment in the embodiment of the present invention is not only controlled by the first voltage adjustment control signal SW, but also by the scan signal SPX. Figure 2 and Figure 4, the node voltage regulation phase td in this embodiment substantially completes the anode reset synchronously, that is, the node voltage regulation phase td is also the anode reset phase. Figure 3 and Figure 4 The node voltage regulation stage td in this embodiment substantially completes the bias regulation synchronously, that is, the node voltage regulation stage td is also a bias regulation stage.

[0096] Figure 7 and Figure 8 is a schematic diagram of the circuit structure of two pixel circuits and light-emitting elements provided in an embodiment of the present invention, with reference to Figure 7 and Figure 8 In other optional embodiments, the node voltage regulating module 12 may include a first transistor M21, a second transistor M22 and a third transistor M23, the first ends of the first transistor M21 and the second transistor M22 are both connected to the second node N2, the second end of the first transistor M21 is connected to the first voltage regulating signal end V1, the second end of the second transistor M22 is connected to the second voltage regulating signal end V2, the first end of the third transistor M23 is connected to the second node N2, and the second end of the third transistor M23 is connected to the first node N1; the first transistor M21 is configured to be turned on before the node voltage regulating phase td of the refresh frame Trefresh to write the first voltage regulation signal V1; the second transistor M22 is configured to be turned on before the node voltage regulation phase td of the holding frame Thold to write the second voltage regulation signal V2 to the second node N2; the third transistor M23 is configured to be turned on both in the node voltage regulation phase td of the refresh frame Trefresh and in the node voltage regulation phase td of the holding frame Thold, so as to write the first voltage regulation signal V1 stored in the second node N2 to the first node N1 in the node voltage regulation phase td of the refresh frame Trefresh, and write the second voltage regulation signal V2 stored in the second node N2 to the first node N1 in the node voltage regulation phase td of the holding frame Thold.

[0097] In this embodiment, the node voltage regulating module 12 is also provided with a first transistor M21, a second transistor M22 and a third transistor M23, the difference being that the switching timings of the three transistors, especially the first transistor M21 and the second transistor M22, are different. Figure 2-Figure 4In the illustrated embodiment, the first transistor M21 and the second transistor M22 are both turned on in the node voltage adjustment phase td corresponding to the display frame T, and at the same time, cooperate with the turned-on third transistor M23, so as to directly write the first node voltage adjustment signal V1 or the second node voltage adjustment signal V2 to the first node N1 through the turned-on first transistor M21 or the second transistor M22. However, in this embodiment, the first transistor M21 and the second transistor M22 are turned on before the node voltage adjustment phase td corresponding to the display frame T, that is, before the third transistor M23 is turned on, and the first node voltage adjustment signal V1 or the second node voltage adjustment signal V2 is pre-written to the node connected to the third transistor M23, that is, the second node N2, and stored in the node. When the third transistor M23 is turned on, the first node voltage adjustment signal V1 or the second node voltage adjustment signal V2 is stored and written to the first node N1, so as to implement node voltage adjustment for the first node N1.

[0098] Based on this, in the driving method provided by the present invention, step S110 can be specifically refined as follows:

[0099] Controlling the first transistor M21 to be turned on before the node voltage adjustment phase td of the refresh frame Trefresh, so as to write the first voltage adjustment signal V1 to the second node N2;

[0100] The third transistor M23 is controlled to be turned on in the node voltage adjustment phase td of the refresh frame Trefresh, so as to write the first voltage adjustment signal V1 stored in the second node N2 into the first node N1 in the node voltage adjustment phase td of the refresh frame Trefresh.

[0101] Step S120 can be specifically broken down into:

[0102] Controlling the second transistor M22 to be turned on before the node voltage adjustment phase td of the holding frame Thold, so as to write the second voltage adjustment signal V2 to the second node N2;

[0103] The third transistor M23 is controlled to be turned on during the node voltage regulation phase td of the holding frame Thold, so as to write the second voltage regulation signal V2 stored in the second node N2 into the first node N1 during the node voltage regulation phase td of the holding frame Thold.

[0104] Fig. 9 is another driving timing diagram of the first partition pixel circuit provided by an embodiment of the present invention, referring to Figure 7-Figure 9 Specifically, the gate of the first transistor M21 receives the second voltage regulation control signal SW2, the gate of the second transistor M22 receives the third voltage regulation control signal SW3, and the second voltage regulation control signal SW2 is different from the third voltage regulation control signal SW3.

[0105] Continue to refer Figure 8-Figure 10 Optionally, any one of the gate reset control signal S1N, the threshold compensation control signal S2N and the data write control signal SP is multiplexed into the second voltage adjustment control signal SW2, and the figure takes the multiplexing with the threshold compensation control signal S2N as an example; the light-emitting control signal Emit is multiplexed into the third voltage adjustment control signal SW3.

[0106] In an optional embodiment, the channel types of the first transistor M21 and the second transistor M22 are opposite, and the gate reset control signal S1N or the threshold compensation control signal S2N is multiplexed as the second voltage adjustment control signal SW2.

[0107] Reference below Figure 7-Figure 9 , the node voltage adjustment process of this embodiment is described in detail. First, Figure 7 and Figure 8 As shown, the first transistor M21 is an N-type channel transistor, and the gate of the first transistor M21 receives the threshold compensation control signal S2N as the second voltage adjustment control signal SW2. The second transistor M22 is a P-type channel transistor, and the gate of the second transistor M22 receives the light emission control signal Emit as the third voltage adjustment control signal SW3.

[0108] For the refresh frame Trefresh: in the light-emitting stage tc of the previous display frame T, the light-emitting control signal Emit is at a low level, which is an effective level for the second transistor M22. At this time, the second transistor M22 is turned on, and the second node voltage adjustment signal V2 can be written to the second node N2 through the second transistor M22; before the node voltage adjustment stage td, there is a high-level pulse in the threshold compensation control transistor S2N, which is an effective pulse for the first transistor M21. At this time, the first transistor M21 is turned on, and the first node voltage adjustment signal V1 is written to the second node N2 through the first transistor M21. Therefore, before the node voltage adjustment stage td, the second node N2 is sequentially written with the second node voltage adjustment signal V2 and the first node voltage adjustment signal V1, and remains as the first node voltage adjustment signal V1. In the node voltage adjustment stage td, that is, the low-level stage of the scan signal SPX, the third transistor M23 is turned on, and the first node voltage adjustment signal V1 of the second node N2 is written into the first node N1.

[0109] For the hold frame Thold: Similarly, in the light-emitting stage tc of the previous display frame T, the light-emitting control signal Emit is at a low level, which is an effective level for the second transistor M22. At this time, the second transistor M22 is turned on, and the second node voltage adjustment signal V2 can be written to the second node N2 through the second transistor M22; and before the node voltage adjustment stage td, there is no high-level pulse in the threshold compensation control transistor S2N, and the first transistor M21 is continuously in the off state. Therefore, before the node voltage adjustment stage td, the second node N2 only writes the second node voltage adjustment signal V2 and maintains it. In the node voltage adjustment stage td, which is also the low-level stage of the scanning signal SPX, the third transistor M23 is turned on, and the second node voltage adjustment signal V2 of the second node N2 is written into the first node N1.

[0110] Fig.10 and Fig.11 is a schematic diagram of the circuit structure of two pixel circuits and light-emitting elements provided in an embodiment of the present invention, with reference to Figure 10-12 In another optional embodiment of the present invention, the first transistor M21 and the second transistor M22 have the same channel type, and the data writing control signal SP is multiplexed into the second voltage regulating control signal SW2.

[0111] It should be noted that if Fig. 9 The pixel circuit driving timing shown also applies Fig.10 and Fig.11 The pixel circuit shown below Figure 9-11 , the node voltage adjustment process of this embodiment is also described in detail. First, Fig.10 and Fig.11 As shown, the first transistor M21 and the second transistor M22 are both P-type transistors, the gate of the first transistor M21 receives the data writing control signal SP as the second voltage regulating control signal SW2, and the gate of the second transistor M22 receives the light emitting control signal Emit as the third voltage regulating control signal SW3.

[0112] For the refresh frame Trefresh: in the light-emitting stage tc of the previous display frame T, the light-emitting control signal Emit is at a low level, which is an effective level for the second transistor M22. At this time, the second transistor M22 is turned on, and the second node voltage adjustment signal V2 can be written to the second node N2 through the second transistor M22; before the node voltage adjustment stage td, there is a low-level pulse in the data writing control signal SP, which is an effective pulse for the first transistor M21. At this time, the first transistor M21 is turned on, and the first node voltage adjustment signal V1 is written to the second node N2 through the first transistor M21. Therefore, before the node voltage adjustment stage td, the second node N2 is sequentially written with the second node voltage adjustment signal V2 and the first node voltage adjustment signal V1, and remains as the first node voltage adjustment signal V1. In the node voltage adjustment stage td, that is, the low-level stage of the scanning signal SPX, the third transistor M23 is turned on, and the first node voltage adjustment signal V1 of the second node N2 is written into the first node N1.

[0113] For the hold frame Thold: Similarly, in the light-emitting stage tc of the previous display frame T, the light-emitting control signal Emit is at a low level, which is an effective level for the second transistor M22. At this time, the second transistor M22 is turned on, and the second node voltage adjustment signal V2 can be written to the second node N2 through the second transistor M22; and before the node voltage adjustment stage td, there is no low-level pulse in the data writing control signal SP, and the first transistor M21 is continuously in the off state. Therefore, before the node voltage adjustment stage td, the second node N2 only writes the second node voltage adjustment signal V2 and maintains it. In the node voltage adjustment stage td, which is also the low-level stage of the scanning signal SPX, the third transistor M23 is turned on, and the second node voltage adjustment signal V2 of the second node N2 is written into the first node N1.

[0114] Further, in order to ensure that the second node N2 can continue to maintain the voltage state of the node voltage adjustment signal written, continue to refer to Figure 7 , Figure 8 , Fig.10 and Fig.11 The node voltage regulating module 12 may further include a storage unit 120, which is connected between the fixed potential signal terminal and the second node N2; the storage unit 120 is used to store the first voltage regulating signal V1 written by the first transistor M21 or the second voltage regulating signal V2 written by the second transistor M22.

[0115] Specifically, the storage unit 120 includes a first capacitor C1 , a first plate of the first capacitor C1 is electrically connected to the power signal terminal PVDD or PVEE, and a second plate of the first capacitor C1 is electrically connected to the second node N2 .

[0116] Thus, when the first transistor M21 or the second transistor M22 is turned on, the node voltage adjustment signal written into the second node N2 can be stored through the first capacitor C2, so that when the third transistor M23 is turned on, the node voltage adjustment signal V of the second node N2 is written into the first node N1.

[0117] Fig.12 is a driving timing diagram of a second partition pixel circuit provided by an embodiment of the present invention, with reference to Figure 1-Figure 3 and Fig.12 The display panel of the embodiment of the present invention may further include a second partition AA2, the first partition AA1 and the second partition AA2 do not overlap; the multiple display frames T of the second partition AA2 are all refresh frames Trefresh; the node voltage regulation module in the pixel circuit of the second partition is configured as: in the node voltage regulation phase td of the refresh frame Trefresh, writing the first voltage regulation signal V1 to the first node N1.

[0118] The display panel is set to the first partition AA1 and the second partition AA2, and the driving process of the first partition AA1 includes a refresh frame Trefresh and a hold frame Thold, while the second partition AA2 only has a refresh frame Trefresh, which means that the display panel adopts a dynamic partition refresh driving mode, that is, the first partition AA1 adopts a low-frequency refresh drive display, and the second partition AA2 adopts a high-frequency refresh drive display. As mentioned above, due to the difference between the refresh frame Trefresh and the hold frame Thold in whether the data writing stage tb is set, the degree of drift of the electrical characteristic curve of the driving transistor M1 will be different. Therefore, for the first partition AA1 with the hold frame Thold and the second partition AA2 without the hold frame Thold, the degree of drift of the electrical characteristic curve of the driving transistor M1 in the pixel circuit will also be different, and the display brightness of the two areas will be different, resulting in a brightness split screen phenomenon. In the embodiment of the present invention, the refresh frame Trefresh and the hold frame Thold of the first partition AA1 are respectively adjusted by the first voltage adjustment signal V1 and the second voltage adjustment signal V2 for node voltage adjustment, and the refresh frame Trefresh of the second partition AA2 is also adjusted by the first voltage adjustment signal V1, which can respectively compensate for the drift of the characteristic curve caused by the forward bias of the driving transistor in the hold frame and the refresh frame, or can weaken or eliminate the difference in the voltage state of the first node in the refresh frame and the hold frame, thereby ensuring that the pixel circuits in all areas of the display panel have the same driving process for the light-emitting elements in the light-emitting stage, provide the same driving current, and achieve the same light-emitting brightness, thereby solving the problem of differences in the light-emitting brightness of the light-emitting elements due to different bias times of the driving transistors between different partitions and the brightness split screen phenomenon in the partitions, ensuring display uniformity and improving display quality.

[0119] Based on the same inventive concept, an embodiment of the present invention further provides a display device. Fig.13 A schematic diagram of a display device according to an embodiment of the present invention is provided. Fig.13 , the display device includes the display panel 1 provided by any embodiment of the present invention, therefore, the display device provided by the embodiment of the present invention has the corresponding beneficial effects of the display panel provided by the embodiment of the present invention, which will not be repeated here. Exemplarily, the display device can be an electronic device such as a mobile phone, a computer, a smart wearable device (for example, a smart watch), and a vehicle-mounted display device, which is not limited by the embodiment of the present invention.

[0120] Note that the above are only preferred embodiments of the present invention and the technical principles used. Those skilled in the art will understand that the present invention is not limited to the specific embodiments described herein, and that various obvious changes, readjustments, combinations and substitutions can be made by those skilled in the art without departing from the scope of protection of the present invention. Therefore, although the present invention has been described in more detail through the above embodiments, the present invention is not limited to the above embodiments, and may include more other equivalent embodiments without departing from the concept of the present invention, and the scope of the present invention is determined by the scope of the appended claims.

Claims

1. A display panel, characterized in that: include: Pixel circuit and light emitting element; The pixel circuit includes a driving module and a node voltage regulating module; The driving module is configured to provide a driving current for the light emitting element, and the driving module includes a driving transistor; The pixel circuit further comprises a first node, the first node being connected to the driving transistor or the light emitting element; the node voltage regulating module being connected to the first node; The picture display process of the display panel includes a plurality of display frames, the display panel includes a first partition, the plurality of display frames of the first partition include a refresh frame and a hold frame, and the refresh frame and the hold frame both include a node voltage adjustment stage; The node voltage regulation module is configured as follows: In the node voltage adjustment phase of the refresh frame, writing a first voltage adjustment signal to the first node; In the node voltage adjustment phase of the holding frame, writing a second voltage adjustment signal to the first node; The first voltage regulating signal and the second voltage regulating signal are both used to regulate the voltage state of the first node, and the voltage of the first voltage regulating signal is different from the voltage of the second voltage regulating signal.

2. The display panel according to claim 1, characterized in that: The first end of the node voltage regulating module is connected to the first voltage regulating signal end and the second voltage regulating signal end, and the first electrode of the driving transistor is connected to the second end of the node voltage regulating module as the first node; The first voltage regulation signal terminal receives the first voltage regulation signal, and the second voltage regulation signal terminal receives the second voltage regulation signal; In the node voltage regulation phase of the refresh frame, the node voltage regulation module conducts the first voltage regulation signal terminal and the first electrode of the driving transistor to write the first voltage regulation signal into the first electrode of the driving transistor; In the node voltage regulation phase of the holding frame, the node voltage regulation module conducts the second voltage regulation signal terminal and the first electrode of the driving transistor to write the second voltage regulation signal into the first electrode of the driving transistor; The first voltage regulating signal and the second voltage regulating signal are both used to regulate the voltage state of the driving transistor.

3. The display panel according to claim 1, characterized in that: The first end of the node voltage regulating module is connected to the first voltage regulating signal end and the second voltage regulating signal end, and the anode of the light emitting element is connected to the second end of the node voltage regulating module as the first node; The first voltage regulation signal terminal receives the first voltage regulation signal, and the second voltage regulation signal terminal receives the second voltage regulation signal; In the node voltage regulation phase of the refresh frame, the node voltage regulation module conducts the first voltage regulation signal terminal and the anode of the light emitting element to write the first voltage regulation signal to the anode of the light emitting element; In the node voltage regulation phase of the holding frame, the node voltage regulation module conducts the second voltage regulation signal terminal and the anode of the light emitting element to write the second voltage regulation signal to the anode of the light emitting element; The first voltage regulating signal and the second voltage regulating signal are both used to reset the potential of the anode of the light emitting element.

4. The display panel according to claim 1, characterized in that: The node voltage regulating module comprises a first transistor and a second transistor, wherein the first ends of the first transistor and the second transistor are both connected to the first node, the second end of the first transistor is connected to the first voltage regulating signal end, and the second end of the second transistor is connected to the second voltage regulating signal end; The first transistor is configured to be turned on during the node voltage regulation phase of the refresh frame; The second transistor is configured to be turned on during the node voltage regulation phase of the hold frame.

5. The display panel according to claim 4, characterized in that: The channel types of the first transistor and the second transistor are opposite, and gates of the first transistor and the second transistor receive the same first voltage regulating control signal.

6. The display panel according to claim 5, characterized in that: The first transistor is a P-type channel transistor, and the second transistor is an N-type channel transistor; the first voltage regulation control signal is configured as a first voltage V1_SW at least in the node voltage regulation phase of the refresh frame; the first voltage regulation control signal is configured as a second voltage V2_SW at least in the node voltage regulation phase of the hold frame; wherein V1_SW<V2_SW; or, The first transistor is an N-type channel transistor, and the second transistor is a P-type channel transistor; the first voltage regulation control signal is configured as a first voltage V1_SW at least in the node voltage regulation phase of the refresh frame; the first voltage regulation control signal is configured as a second voltage V2_SW at least in the node voltage regulation phase of the hold frame; wherein V1_SW>V2_SW.

7. The display panel according to claim 4, characterized in that: The node voltage regulating module further includes a third transistor, a first end of the third transistor is connected to the first end of the first transistor and the first end of the second transistor, and a second end of the third transistor is connected to the first node; The third transistor is configured to be turned on during both the node voltage regulation phase of the refresh frame and the node voltage regulation phase of the hold frame.

8. The display panel according to claim 1, characterized in that: The node voltage regulating module comprises a first transistor, a second transistor and a third transistor, wherein the first ends of the first transistor and the second transistor are both connected to the second node, the second end of the first transistor is connected to the first voltage regulating signal end, the second end of the second transistor is connected to the second voltage regulating signal end, the first end of the third transistor is connected to the second node, and the second end of the third transistor is connected to the first node; The first transistor is configured to be turned on before the node voltage regulation phase of the refresh frame to write the first voltage regulation signal to the second node; The second transistor is configured to be turned on before the node voltage adjustment phase of the hold frame to write the second voltage adjustment signal to the second node; The third transistor is configured to be turned on both in the node voltage regulation phase of the refresh frame and in the node voltage regulation phase of the hold frame, so as to write the first voltage regulation signal stored in the second node to the first node in the node voltage regulation phase of the refresh frame, and to write the second voltage regulation signal stored in the second node to the first node in the node voltage regulation phase of the hold frame.

9. The display panel according to claim 8, characterized in that: The gate of the first transistor receives a second voltage regulation control signal, the gate of the second transistor receives a third voltage regulation control signal, and the second voltage regulation control signal is different from the third voltage regulation control signal.

10. The display panel according to claim 9, characterized in that: The pixel circuit also includes a data writing module, a compensation module, a gate resetting module and a light emitting control module; The refresh frame further includes a gate reset phase, a data writing phase and a light emitting phase, wherein the data writing phase is located between the gate reset phase and the light emitting phase; the hold frame further includes a light emitting phase; The data writing module is connected between the data signal terminal and the first electrode of the driving transistor, and is configured to be controlled by a data writing control signal, and to write a data signal to the gate of the driving transistor during the data writing phase of the refresh frame; The compensation module is connected between the gate and the second electrode of the driving transistor, and is configured to be controlled by a threshold compensation control signal, and to compensate the threshold voltage of the driving transistor during the data writing phase of the refresh frame; The gate reset module is connected to the gate reset signal terminal and the gate of the driving transistor, and is configured to be controlled by a gate reset control signal, and reset the potential of the gate of the driving transistor in the gate reset phase of the refresh frame; The light-emitting control module is connected to the driving module and the light-emitting element at a first power signal terminal and a second power signal terminal respectively, and is configured to be controlled by a light-emitting control signal, and to control the light-emitting element to light up during the light-emitting phase of the refresh frame and the light-emitting phase of the hold frame; Any one of the gate reset control signal, the threshold compensation control signal and the data write control signal is multiplexed as the second voltage adjustment control signal; The light emitting control signal is multiplexed into the third voltage regulating control signal.

11. The display panel according to claim 10, characterized in that: The channel types of the first transistor and the second transistor are opposite, and the gate reset control signal or the threshold compensation control signal is multiplexed as the second voltage adjustment control signal; Alternatively, the channel type of the first transistor and the second transistor is the same, and the data writing control signal is multiplexed into the second voltage regulating control signal.

12. The display panel according to claim 8, characterized in that: The node voltage regulating module further includes a storage unit connected between the fixed potential signal terminal and the second node; The storage unit is used to store the first voltage regulating signal written by the first transistor or the second voltage regulating signal written by the second transistor.

13. The display panel according to claim 12, characterized in that: The storage unit includes a first capacitor, a first plate of the first capacitor is electrically connected to the power signal terminal, and a second plate of the first capacitor is electrically connected to the second node.

14. The display panel according to claim 1, characterized in that: The display panel further includes a second partition, wherein the first partition and the second partition do not overlap; The multiple display frames of the second partition are all refresh frames; The node voltage regulating module in the pixel circuit of the second partition is configured as follows: During the node voltage adjustment phase of the refresh frame, the first voltage adjustment signal is written to the first node.

15. A method for driving a display panel, characterized in that: The display panel includes a pixel circuit and a light-emitting element; The pixel circuit includes a driving module and a node voltage regulating module; The driving module is configured to provide a driving current for the light emitting element, and the driving module includes a driving transistor; The pixel circuit further comprises a first node, the first node being connected to the driving transistor or the light emitting element; the node voltage regulating module being connected to the first node; The picture display process of the display panel includes a plurality of display frames, the display panel includes a first partition, the plurality of display frames of the first partition include a refresh frame and a hold frame, and the refresh frame and the hold frame both include a node voltage adjustment stage; The driving method comprises: In the node voltage regulation phase of the refresh frame, controlling the node voltage regulation module to write a first voltage regulation signal to the first node; In the node voltage adjustment phase of the holding frame, controlling the node voltage adjustment module to write a second voltage adjustment signal to the first node; The first voltage regulating signal and the second voltage regulating signal are both used to regulate the voltage state of the first node, and the voltage of the first voltage regulating signal is different from the voltage of the second voltage regulating signal.

16. The driving method according to claim 15, characterized in that: The node voltage regulating module comprises a first transistor and a second transistor, wherein the first ends of the first transistor and the second transistor are both connected to the first node, the second end of the first transistor is connected to the first voltage regulating signal end, and the second end of the second transistor is connected to the second voltage regulating signal end; In the node voltage regulation phase of the refresh frame, controlling the node voltage regulation module to write a first voltage regulation signal to the first node includes: Controlling the first transistor to turn on during the node voltage regulation phase of the refresh frame; In the node voltage adjustment phase of the holding frame, controlling the node voltage adjustment module to write a second voltage adjustment signal to the first node includes: The second transistor is controlled to be turned on during the node voltage regulation phase of the holding frame.

17. The driving method according to claim 15, characterized in that: The node voltage regulating module comprises a first transistor, a second transistor and a third transistor, wherein the first ends of the first transistor and the second transistor are both connected to the second node, the second end of the first transistor is connected to the first voltage regulating signal end, the second end of the second transistor is connected to the second voltage regulating signal end, the first end of the third transistor is connected to the second node, and the second end of the third transistor is connected to the first node; In the node voltage regulation phase of the refresh frame, controlling the node voltage regulation module to write a first voltage regulation signal to the first node includes: controlling the first transistor to be configured to be turned on before the node voltage regulation phase of the refresh frame to write the first voltage regulation signal to the second node; controlling the third transistor to turn on during the node voltage regulation phase of the refresh frame, so as to write the first voltage regulation signal stored in the second node into the first node during the node voltage regulation phase of the refresh frame; In the node voltage regulation phase of the refresh frame, controlling the node voltage regulation module to write a first voltage regulation signal to the first node includes: controlling the second transistor to be turned on before the node voltage adjustment phase of the holding frame to write the second voltage adjustment signal to the second node; The node voltage regulation phase of the holding frame is controlled to start the third transistor, so as to write the second voltage regulation signal stored in the second node into the first node during the node voltage regulation phase of the holding frame.

18. A display device, characterized in that: Comprising a display panel as described in any one of claims 1-14.

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