Shift registers, gate drive circuits, and display devices

Abstract

This invention provides a shift register, a gate driving circuit, and a display device, relating to the field of display technology, for better narrowing the bezel width of display products. The shift register includes an output circuit, which includes a first output transistor, which is a dual-gate transistor. The top gate of the first output transistor is coupled to a cascaded signal output terminal, and the bottom gate of the first output transistor is coupled to a control terminal. The first electrode of the first output transistor is coupled to a first-level signal input terminal, and the second electrode of the first output transistor is coupled to a gate driving signal output terminal. The cascaded signal output terminal is used to control the first output transistor to be turned on or off, and the control terminal is used to control the characteristic parameters of the first output transistor.

Description

Technical Field

[0001] This invention relates to the field of display technology, and more particularly to a shift register, a gate driving circuit, and a display device. Background Technology

[0002] With the continuous development of display technology, the application fields of display products are becoming increasingly widespread, and people's requirements for the display quality of display products are getting higher and higher. In order to better realize narrow bezel display products, GOA (Gate On Array) technology is adopted in display products. This means that the gate driving circuit is directly fabricated on the array substrate, and the sub-pixel rows of the display area are driven by the shift registers of each stage included in the gate driving circuit, thereby realizing the display function of the display product. However, the existing shift register structure is complex, includes a large number of transistors, and still occupies a large layout space, which is not conducive to further narrowing the bezel of display products. Summary of the Invention

[0003] The purpose of this invention is to provide a shift register, a gate driving circuit, and a display device for better narrowing the bezel width of display products.

[0004] To achieve the above objectives, the present invention provides the following technical solution:

[0005] A first aspect of the present invention provides a shift register, comprising: an output circuit; the output circuit includes a first output transistor, the first output transistor including a dual-gate transistor, the top gate of the first output transistor being coupled to a cascaded signal output terminal, the bottom gate of the first output transistor being coupled to a control terminal, the first electrode of the first output transistor being coupled to a first level signal input terminal, and the second electrode of the first output transistor being coupled to a gate drive signal output terminal.

[0006] The cascaded signal output terminal is used to control the first output transistor to be turned on or off, and the modulation terminal is used to control the characteristic parameters of the first output transistor.

[0007] Optionally, the output circuit further includes a second output transistor; the first output transistor includes an oxide transistor, and the second output transistor includes a low-temperature polycrystalline silicon transistor.

[0008] The gate of the second output transistor is coupled to the cascaded signal output terminal, the first terminal of the second output transistor is coupled to the second level signal input terminal, and the second terminal of the second output transistor is coupled to the gate drive signal output terminal.

[0009] Optionally, the shift register includes a first first-level signal input terminal and a third first-level signal input terminal; the voltage value of the first-level signal input to the third first-level signal input terminal is less than the voltage value of the first first-level signal input to the first first-level signal input terminal.

[0010] The control terminal is coupled to the third first level signal input terminal, and the first terminal of the first output transistor is coupled to the first first level signal input terminal.

[0011] Optionally, the shift register includes a second first-level signal input terminal;

[0012] The control terminal is coupled to the cascaded signal output terminal, and the first electrode of the first output transistor is coupled to the second first level signal input terminal.

[0013] Optionally, the shift register includes a first first-level signal input terminal and a second first-level signal input terminal; the voltage value of the first-level signal input at the first first-level signal input terminal is less than the voltage value of the first-level signal input at the second first-level signal input terminal;

[0014] The output circuit further includes a tenth transistor, which is a dual-gate oxide transistor; the top gate of the tenth transistor is coupled to the cascaded signal output terminal, the bottom gate of the tenth transistor is coupled to the cascaded signal output terminal, the first terminal of the tenth transistor is coupled to the first first level signal input terminal or the second first level signal input terminal, and the second terminal of the tenth transistor is coupled to the first terminal of the first output transistor.

[0015] The shift register also includes:

[0016] The leakage current control circuit is coupled to the gate drive signal output terminal, the first voltage signal input terminal, and the second terminal of the tenth transistor, respectively, and is used to control the electrical connection between the first voltage signal input terminal and the second terminal of the tenth transistor to be turned on or off under the control of the gate drive signal output from the gate drive signal output terminal.

[0017] Optionally, the shift register includes a first second-level signal input terminal and a second second-level signal input terminal, wherein the voltage value of the second-level signal input at the second second-level signal input terminal is less than or equal to the voltage value of the second-level signal input at the first second-level signal input terminal; the first terminal of the second output transistor is coupled to either the first second-level signal input terminal or the second second-level signal input terminal.

[0018] The shift register also includes:

[0019] The first cascade control circuit is coupled to the first node, the cascade signal output terminal, and the second clock signal input terminal, respectively, and is used to control the electrical connection between the cascade signal output terminal and the second clock signal input terminal to be turned on or off under the control of the potential of the first node.

[0020] The second cascade control circuit is coupled to the second node, the cascade signal output terminal, and the first second-level signal input terminal, respectively, and is used to control the electrical connection between the cascade signal output terminal and the first second-level signal input terminal to be turned on or off under the control of the potential of the second node.

[0021] Optionally, the shift register further includes:

[0022] The first node control circuit is coupled to the first node, the first first level signal input terminal and the third node respectively, and is used to control the electrical connection between the first node and the third node to be turned on or off under the control of the first second level signal input terminal.

[0023] The third node control circuit is coupled to the third node, the start signal input terminal and the first clock signal input terminal respectively, and is used to control the electrical connection between the third node and the start signal input terminal to be turned on or off under the control of the first clock signal input at the first clock signal input terminal.

[0024] Optionally, the shift register further includes:

[0025] The second node control circuit is coupled to the second node, the first clock signal input terminal and the fourth node respectively, and is used to control the electrical connection between the second node and the fourth node to be turned on or off under the control of the first clock signal input terminal.

[0026] The fourth node control circuit is coupled to the fourth node, the start signal input terminal, the first level signal input terminal, and the first second level signal input terminal, respectively. It is used to control the electrical connection between the fourth node and the first level signal input terminal, and to control the electrical connection between the fourth node and the first second level signal input terminal, under the control of the start signal input at the start signal input terminal.

[0027] Optionally, the shift register includes a first first-level signal input terminal and a third first-level signal input terminal, wherein the level value of the first-level signal input at the first first-level signal input terminal is greater than the level value of the first-level signal input at the third first-level signal input terminal;

[0028] The fourth node control circuit includes a fifth transistor and a sixth transistor;

[0029] The fifth transistor includes a dual-gate oxide transistor, the top gate of the fifth transistor is coupled to the start signal input terminal, the bottom gate of the fifth transistor is coupled to the third first level signal input terminal, the first electrode of the fifth transistor is coupled to the first first level signal input terminal, and the second electrode of the fifth transistor is coupled to the fourth node.

[0030] The gate of the sixth transistor is coupled to the start signal input terminal, the first terminal of the sixth transistor is coupled to the first second level signal input terminal, and the second terminal of the sixth transistor is coupled to the fourth node.

[0031] Optionally, the shift register includes a first first-level signal input terminal and a second first-level signal input terminal, wherein the level value of the first-level signal input at the first first-level signal input terminal is less than the level value of the first-level signal input at the second first-level signal input terminal;

[0032] The fourth node control circuit includes a fifth transistor and a sixth transistor;

[0033] The fifth transistor includes a dual-gate oxide transistor, the top gate of the fifth transistor is coupled to the start signal input terminal, the bottom gate of the fifth transistor is coupled to the first first level signal input terminal, the first electrode of the fifth transistor is coupled to the second first level signal input terminal, and the second electrode of the fifth transistor is coupled to the fourth node.

[0034] The gate of the sixth transistor is coupled to the start signal input terminal, the first terminal of the sixth transistor is coupled to the first second level signal input terminal, and the second terminal of the sixth transistor is coupled to the fourth node.

[0035] Optionally, the shift register further includes:

[0036] The noise reduction control circuit is coupled to the second clock signal input terminal, the second node, the first second level signal input terminal, and the third node, respectively, and is used to control the electrical connection between the first second level signal input terminal and the third node to be turned on or off under the joint control of the second clock signal input terminal and the potential of the second node.

[0037] Optionally, the first cascade control circuit includes a second transistor and a first capacitor; the gate of the second transistor is coupled to the first node, the first terminal of the second transistor is coupled to the second clock signal input terminal, and the second terminal of the second transistor is coupled to the cascade signal output terminal; the first terminal of the first capacitor is coupled to the first node, and the second terminal of the first capacitor is coupled to the cascade signal output terminal.

[0038] The second cascaded control circuit includes a first transistor and a second capacitor; the gate of the first transistor is coupled to the second node, the first terminal of the first transistor is coupled to the first second-level signal input terminal, and the second terminal of the first transistor is coupled to the cascaded signal output terminal; the first terminal of the second capacitor is coupled to the second node, and the second terminal of the second capacitor is coupled to the first second-level signal input terminal.

[0039] The first node control circuit includes a fourth transistor, the gate of which is coupled to the first first level signal input terminal, the first terminal of which is coupled to the third node, and the second terminal of which is coupled to the first node;

[0040] The third node control circuit includes a third transistor, the gate of which is coupled to the first clock signal input terminal, the first terminal of which is coupled to the start signal input terminal, and the second terminal of which is coupled to the third node.

[0041] The second node control circuit includes a seventh transistor, the gate of which is coupled to the first clock signal input terminal, the first terminal of which is coupled to the fourth node, and the second terminal of which is coupled to the second node;

[0042] In the case where the shift register includes a leakage control circuit, the leakage control circuit includes an eleventh transistor, the gate of the eleventh transistor is coupled to the gate drive signal output terminal, the first terminal of the eleventh transistor is coupled to the first voltage signal input terminal, and the second terminal of the eleventh transistor is coupled to the second terminal of the tenth transistor.

[0043] The noise reduction control circuit includes a twelfth transistor and a thirteenth transistor;

[0044] The gate of the twelfth transistor is coupled to the second node, the first terminal of the twelfth transistor is coupled to the first second-level signal input terminal, the second terminal of the twelfth transistor is coupled to the first terminal of the thirteenth transistor, the gate of the thirteenth transistor is coupled to the second clock signal input terminal, and the second terminal of the thirteenth transistor is coupled to the third node.

[0045] Based on the above-described shift register technical solution, a second aspect of the present invention provides a gate driving circuit comprising a plurality of cascaded shift registers.

[0046] Optionally, the cascade signal output of the nth stage shift register is coupled to the start signal input of the (n+m)th stage shift register, where n is an integer greater than or equal to 1 and m is an integer greater than or equal to 1.

[0047] Based on the above-described gate driving circuit, a third aspect of the present invention provides a display device including the above-described gate driving circuit.

[0048] In the technical solution provided by this invention, the cascaded signal output from the cascaded signal output terminal in the shift register is coupled to the top gate of the first output transistor in the output circuit, thereby controlling the conduction state of the first output transistor and thus controlling the gate drive signal output terminal to output the gate drive signal. Therefore, the technical solution provided by this invention does not require an additional control circuit to control the output circuit. By using the existing cascaded signal in the shift register to control the first output transistor in the output circuit, the gate drive signal output terminal can be controlled to output the required gate drive signal. Thus, the technical solution provided by this invention effectively simplifies circuit complexity, and when the shift register is applied to display products, the bezel area of ​​the display product can be further narrowed.

[0049] Moreover, in the shift register provided by the present invention, the control terminal is coupled to the bottom gate of the first output transistor, and the control signal output by the control terminal can control the characteristic parameters of the first output transistor. These characteristic parameters may specifically include the magnitude of the conduction current and the degree of threshold voltage offset, thereby ensuring that the first output transistor can achieve better operating characteristics. Attached Figure Description

[0050] The accompanying drawings, which are included to provide a further understanding of the invention and form part of this invention, illustrate exemplary embodiments of the invention and are used to explain the invention, but do not constitute an undue limitation of the invention. In the drawings:

[0051] Figure 1 This is a schematic diagram of the first module of the shift register provided in an embodiment of the present invention;

[0052] Figure 2 This is a schematic diagram of the second module of the shift register provided in an embodiment of the present invention;

[0053] Figure 3 A schematic diagram of the third module of the shift register provided in an embodiment of the present invention;

[0054] Figure 4 This is a schematic diagram of the fourth module of the shift register provided in an embodiment of the present invention;

[0055] Figure 5 This is a schematic diagram of the first circuit structure of the shift register provided in an embodiment of the present invention;

[0056] Figure 6 This is a schematic diagram of the second circuit structure of the shift register provided in an embodiment of the present invention;

[0057] Figure 7 This is a schematic diagram of the third circuit structure of the shift register provided in an embodiment of the present invention;

[0058] Figure 8 This is a schematic diagram of the fourth circuit structure of the shift register provided in an embodiment of the present invention;

[0059] Figure 9 This is a schematic diagram of the fifth circuit structure of the shift register provided in an embodiment of the present invention;

[0060] Figure 10 A schematic diagram illustrating the effect of the bottom gate voltage on the threshold voltage of a transistor, provided in an embodiment of the present invention;

[0061] Figure 11 This is a timing diagram of the shift register provided in an embodiment of the present invention;

[0062] Figure 12 This is a schematic diagram of a cascaded multi-stage shift register provided in an embodiment of the present invention;

[0063] Figure 13 The following timing diagrams are provided for the output of multi-stage shift registers in embodiments of the present invention;

[0064] Figure 14 This is another cascaded diagram of a multi-stage shift register provided in an embodiment of the present invention; Detailed Implementation

[0065] To further illustrate the shift register, gate driving circuit, and display device provided in the embodiments of the present invention, a detailed description is provided below with reference to the accompanying drawings.

[0066] Please see Figure 1 , Figures 5 to 9This invention provides a shift register, including an output circuit 10; the output circuit 10 includes a first output transistor T8, the first output transistor T8 includes a dual-gate transistor, the top gate of the first output transistor T8 is coupled to the cascaded signal output terminal CR, the bottom gate of the first output transistor T8 is coupled to the control terminal TK, the first electrode of the first output transistor T8 is coupled to the first level signal input terminal VGL, and the second electrode of the first output transistor T8 is coupled to the gate drive signal output terminal OUT;

[0067] The cascaded signal output terminal CR is used to control the first output transistor T8 to be turned on or off, and the modulation terminal TK is used to control the characteristic parameters of the first output transistor T8.

[0068] For example, the control terminal TK is coupled to the cascaded signal output terminal CR or the third first-level signal input terminal VGL3, but is not limited to this.

[0069] For example, the characteristic parameters include the magnitude of the conduction current and the degree of deviation of the threshold voltage, but are not limited to these.

[0070] For example, the output circuit 10 is coupled to the cascaded signal output terminal CR, the gate drive signal output terminal OUT, the first level signal input terminal VGL, and the second level signal input terminal VGH, respectively. It is used to control the electrical connection between the gate drive signal output terminal OUT and the first level signal input terminal VGL, and to control the electrical connection between the gate drive signal output terminal OUT and the second level signal input terminal VGH, under the control of the cascaded signal output from the cascaded signal output terminal CR.

[0071] For example, the shift register can be applied to LTPO or LTPS OLED display products. For instance, the shift register can be applied to LTPO, where the transistor in the pixel circuit that controls the gate of the driving transistor to write data signals is an oxide transistor. It needs to be driven by a high-voltage pulse with a pulse width of less than 1H or about 1.5H as the control signal for the oxide transistor. The shift register that outputs this signal can be called NGateGOA.

[0072] For example, the first level signal input terminal is used to output a first level signal of negative voltage, and the second level signal input terminal is used to output a second level signal of positive voltage.

[0073] For example, when the gate drive signal output at the gate drive signal output terminal OUT is at a low level, the output circuit 10 is used to control the electrical connection between the gate drive signal output terminal OUT and the first level signal input terminal to be turned on, and to control the electrical connection between the gate drive signal output terminal OUT and the second level signal input terminal to be turned off, under the control of the cascade signal output at the cascade signal output terminal CR; when the gate drive signal output at the gate drive signal output terminal OUT is at a high level, the output circuit 10 is used to control the electrical connection between the gate drive signal output terminal OUT and the first level signal input terminal to be turned off, and to control the electrical connection between the gate drive signal output terminal OUT and the second level signal input terminal to be turned on, under the control of the cascade signal output at the cascade signal output terminal CR.

[0074] As can be seen from the specific structure of the shift register described above, the cascaded signal output from the cascaded signal output terminal CR in the shift register provided in this embodiment of the invention is coupled to the top gate of the first output transistor T8 in the output circuit 10, which can control the conduction state of the first output transistor T8, thereby controlling the gate drive signal output terminal OUT to output the gate drive signal. Therefore, in the shift register provided in this embodiment of the invention, there is no need to introduce an additional control circuit to control the output circuit 10. By using the existing cascaded signal in the shift register to control the first output transistor T8 in the output circuit 10, the gate drive signal output terminal OUT can be controlled to output the gate drive signal that meets the requirements. Therefore, the shift register provided in this embodiment of the invention effectively simplifies the circuit complexity, and when the shift register is applied to a display product, the bezel area of ​​the display product can be further narrowed.

[0075] Furthermore, in the shift register provided in this embodiment of the invention, the control terminal is coupled to the bottom gate of the first output transistor T8, and the control signal output by the control terminal can control the characteristic parameters of the first output transistor. These characteristic parameters may specifically include the magnitude of the conduction current and the degree of threshold voltage offset, thereby ensuring that the first output transistor can achieve better operating characteristics.

[0076] like Figures 5 to 9 As shown, in some embodiments, the output circuit 10 further includes a second output transistor T9; the first output transistor T8 includes an oxide transistor, and the second output transistor T9 includes a low-temperature polysilicon transistor.

[0077] The gate of the second output transistor T9 is coupled to the cascaded signal output terminal CR, the first terminal of the second output transistor T9 is coupled to the second level signal input terminal, and the second terminal of the second output transistor T9 is coupled to the gate drive signal output terminal OUT.

[0078] For example, the first output transistor T8 includes an NMOS transistor, and the second output transistor T9 includes a PMOS transistor.

[0079] The output circuit 10 of the above structure adopts a CMOS circuit structure, which effectively reduces the number of transistors used in the shift register while realizing the output of a gate drive signal with a positive pulse. When the shift register is applied to a display product, the bezel area of ​​the display product can be further narrowed.

[0080] like Figure 5 As shown, in some embodiments, the shift register includes a first first-level signal input terminal VGL1 and a third first-level signal input terminal VGL3; the voltage value of the first-level signal input to the third first-level signal input terminal VGL3 is less than the voltage value of the first-level signal input to the first first-level signal input terminal VGL1;

[0081] The control terminal TK is coupled to the third first level signal input terminal VGL3, and the first terminal of the first output transistor T8 is coupled to the first first level signal input terminal VGL1.

[0082] For example, both the first first-level signal input terminal VGL1 and the third first-level signal input terminal VGL3 are used to output a negative voltage first-level signal. The negative voltage value of the first-level signal input at the first first-level signal input terminal VGL1 is greater than the negative voltage value of the first-level signal input at the third first-level signal input terminal VGL3.

[0083] More specifically, such as Figure 10 The figure illustrates the Id-Vg curves of an oxide transistor under different bottom-gate voltages (-6V, -4V, -2V, 0V, 2V, 4V, 6V). Id represents the drive current when the transistor is operating, and Vg represents the top-gate voltage of the transistor. The horizontal axis represents Vg in volts (V), and the vertical axis represents Id in amperes (A). The figure shows that the more negative the bottom-gate voltage, the more positive the threshold voltage Vth of the transistor. Therefore, increasing the bottom-gate voltage ensures that Vth of the oxide transistor is positive and prevents negative bias.

[0084] In the shift register provided in the above embodiment, the bottom gate of the first output transistor T8 is coupled to the third first level signal input terminal VGL3, which can better ensure that the threshold voltage of the first output transistor T8 does not become negatively biased; at the same time, the first terminal of the first output transistor T8 is coupled to the first first level signal input terminal VGL1, so that the gate drive signal can have a low level that meets the requirements.

[0085] like Figure 6 As shown, in some embodiments, the shift register includes a second first-level signal input terminal VGL2; the control terminal is coupled to the cascaded signal output terminal CR, and the first terminal of the first output transistor T8 is coupled to the second first-level signal input terminal VGL2.

[0086] For example, the first first-level signal input terminal VGL1, the second first-level signal input terminal VGL2, and the third first-level signal input terminal VGL3 are all used to output a negative voltage first-level signal. The negative voltage value of the first-level signal input at the first first-level signal input terminal VGL1 is greater than the negative voltage value of the first-level signal input at the third first-level signal input terminal VGL3, and the negative voltage value of the first-level signal input at the second first-level signal input terminal VGL2 is greater than the negative voltage value of the first first-level signal input at the first first-level signal input terminal VGL1.

[0087] The above configuration couples both the top and bottom gates of the first output transistor T8 to the cascaded signal output terminal CR, allowing the first output transistor T8 to have a larger conduction current when it is turned on. This makes it less prone to loss of the low-voltage first-level signal when it is written to the gate drive signal output terminal OUT through the first output transistor T8. At the same time, it can reduce the size of the first output transistor T8, thereby further reducing the layout space occupied by the shift register and helping to reduce the bezel size of the display products in which it is applied.

[0088] like Figure 8 As shown, in some embodiments, the shift register includes a first first-level signal input terminal VGL1 and a second first-level signal input terminal VGL2; the voltage value of the first-level signal input to the first first-level signal input terminal VGL1 is less than the voltage value of the first-level signal input to the second first-level signal input terminal VGL2;

[0089] The output circuit 10 further includes a tenth transistor T10, which is a dual-gate oxide transistor. The top gate of the tenth transistor T10 is coupled to the cascaded signal output terminal CR, the bottom gate of the tenth transistor T10 is coupled to the cascaded signal output terminal CR, the first terminal of the tenth transistor T10 is coupled to the first first level signal input terminal VGL1 or the second first level signal input terminal VGL2, and the second terminal of the tenth transistor T10 is coupled to the first terminal of the first output transistor T8.

[0090] The shift register also includes:

[0091] The leakage current control circuit 50 is coupled to the gate drive signal output terminal OUT, the first voltage signal input terminal GVDD, and the second terminal of the tenth transistor T10, respectively. It is used to control the electrical connection between the first voltage signal input terminal and the second terminal of the tenth transistor T10 to be turned on or off under the control of the gate drive signal output by the gate drive signal output terminal OUT.

[0092] For example, in the above embodiment, the shift register includes a first second-level signal input terminal VGH1 and a second second-level signal input terminal VGH2, wherein the voltage value of the second-level signal input at the second second-level signal input terminal VGH2 is less than the voltage value of the second-level signal input at the first second-level signal input terminal VGH1. The first terminal of the second output transistor T9 is coupled to either the first second-level signal input terminal VGH1 or the second second-level signal input terminal VGH2.

[0093] For example, the leakage current control circuit 50 includes an eleventh transistor T11. The gate of the eleventh transistor T11 is coupled to the gate drive signal output terminal OUT. The first terminal of the eleventh transistor T11 is coupled to the first voltage signal input terminal, and the second terminal of the eleventh transistor T11 is coupled to the second terminal of the tenth transistor T10. For example, the first voltage signal input terminal is an independent high voltage source. The voltage value of the first voltage signal input can be set to be less than or equal to the voltage value of the second level signal input at the first second level signal input terminal VGH1, or the voltage value of the first voltage signal input can be set to be less than or equal to the voltage value of the second level signal input at the second second level signal input terminal VGH2.

[0094] The shift register described above includes the first output transistor T8, the tenth transistor T10, and the eleventh transistor T11. This configuration ensures that when the second output transistor T9 is turned on at the cascaded signal output terminal CR, and the gate drive signal output at the gate drive signal output terminal OUT is at a high level, the eleventh transistor T11 is turned on. This causes the first electrode of the first output transistor T8 to be written with a first voltage signal, thereby controlling the first output transistor T8 to turn off more completely. This avoids leakage problems in the first output transistor T8 and ensures a more stable gate drive signal output at the gate drive signal output terminal OUT.

[0095] like Figure 2As shown, in some embodiments, the shift register includes a first second-level signal input terminal VGH1 and a second second-level signal input terminal VGH2, wherein the voltage value of the second-level signal input at the second second-level signal input terminal VGH2 is less than or equal to the voltage value of the second-level signal input at the first second-level signal input terminal VGH1; the first terminal of the second output transistor T9 is coupled to either the first second-level signal input terminal VGH1 or the second second-level signal input terminal VGH2.

[0096] The shift register also includes:

[0097] The first cascade control circuit 20 is coupled to the first node Q1, the cascade signal output terminal CR, and the second clock signal input terminal CB, respectively, and is used to control the electrical connection between the cascade signal output terminal CR and the second clock signal input terminal CB to be turned on or off under the control of the potential of the first node Q1.

[0098] The second cascade control circuit 30 is coupled to the second node QB, the cascade signal output terminal CR, and the first second-level signal input terminal VGH1, respectively, and is used to control the electrical connection between the cascade signal output terminal CR and the first second-level signal input terminal VGH1 to be turned on or off under the control of the potential of the second node QB.

[0099] It should be noted that the low voltage of the first clock signal input at the first clock signal input terminal CK is the same as the voltage of the first level signal input at the first first level signal input terminal VGL1, and the high voltage of the first clock signal input at the first clock signal input terminal CK is the same as the voltage of the second level signal input at the first second level signal input terminal VGH1. Similarly, the low voltage of the second clock signal input at the second clock signal input terminal CB is the same as the voltage of the first level signal input at the first first level signal input terminal VGL1, and the high voltage of the second clock signal input at the second clock signal input terminal CB is the same as the voltage of the second level signal input at the first second level signal input terminal VGH1.

[0100] like Figure 3 As shown, in some embodiments, the shift register further includes:

[0101] The first node control circuit 41 is coupled to the first node Q1, the first first level signal input terminal VGL1 and the third node Q3 respectively, and is used to control the electrical connection between the first node Q1 and the third node Q3 to be turned on or off under the control of the first second level signal input terminal VGH1.

[0102] The third node control circuit 43 is coupled to the third node Q3, the start signal input terminal STV and the first clock signal input terminal CK respectively, and is used to control the electrical connection between the third node Q3 and the start signal input terminal STV to be turned on or off under the control of the first clock signal input to the first clock signal input terminal CK.

[0103] like Figure 4 As shown, in some embodiments, the shift register further includes:

[0104] The second node control circuit 42 is coupled to the second node QB, the first clock signal input terminal CK and the fourth node QB1 respectively, and is used to control the electrical connection between the second node QB and the fourth node QB1 to be turned on or off under the control of the first clock signal input to the first clock signal input terminal CK.

[0105] The fourth node control circuit 44 is coupled to the fourth node QB1, the start signal input terminal STV, the first level signal input terminal, and the first second level signal input terminal VGH1, respectively. It is used to control the electrical connection between the fourth node QB1 and the first level signal input terminal, and to control the electrical connection between the fourth node QB1 and the first second level signal input terminal VGH1, under the control of the start signal input at the start signal input terminal STV.

[0106] The shift register is configured with the above structure so that the first node control circuit 41 and the third node control circuit 43 can control the potential of the first node Q1, the potential of the first node Q1 can control the conduction of the first cascade control circuit 20, the second node control circuit 42 and the fourth node control circuit 44 can control the potential of the second node QB, and the potential of the second node QB can control the conduction of the second cascade control circuit 30, thereby controlling the cascade signal output by the cascade signal output terminal CR. When the shift register adopts the above structure, the circuit structure is simple, and when it is applied to display products, it is beneficial to achieve narrow bezels in display products.

[0107] like Figure 5 and Figure 6 As shown, in some embodiments, the shift register includes a first first-level signal input terminal VGL1 and a third first-level signal input terminal VGL3, wherein the level value of the first-level signal input at the first first-level signal input terminal VGL1 is greater than the level value of the first-level signal input at the third first-level signal input terminal VGL3;

[0108] The fourth node control circuit 44 includes a fifth transistor T5 and a sixth transistor T6;

[0109] The fifth transistor T5 includes a dual-gate oxide transistor. The top gate of the fifth transistor T5 is coupled to the start signal input terminal STV, the bottom gate of the fifth transistor T5 is coupled to the third first level signal input terminal VGL3, the first terminal of the fifth transistor T5 is coupled to the first first level signal input terminal VGL1, and the second terminal of the fifth transistor T5 is coupled to the fourth node QB1.

[0110] The gate of the sixth transistor T6 is coupled to the start signal input terminal STV, the first terminal of the sixth transistor T6 is coupled to the first second level signal input terminal VGH1, and the second terminal of the sixth transistor T6 is coupled to the fourth node QB1.

[0111] The above configuration couples the bottom gate of the fifth transistor T5 to the third first-level signal input terminal VGL3 and the first terminal of the fifth transistor T5 to the first first-level signal input terminal VGL1. This not only better ensures that the threshold voltage of the fifth transistor T5 does not become negatively biased, but also ensures that the fifth transistor T5 conducts better and writes the first-level signal to the fourth node QB1.

[0112] like Figure 7 and Figure 8 As shown, in some embodiments, the shift register includes a first first-level signal input terminal VGL1 and a second first-level signal input terminal VGL2, wherein the level value of the first-level signal input to the first first-level signal input terminal VGL1 is less than the level value of the first-level signal input to the second first-level signal input terminal VGL2;

[0113] The fourth node control circuit 44 includes a fifth transistor T5 and a sixth transistor T6;

[0114] The fifth transistor T5 includes a dual-gate oxide transistor. The top gate of the fifth transistor T5 is coupled to the start signal input terminal STV, the bottom gate of the fifth transistor T5 is coupled to the first first level signal input terminal VGL1, the first terminal of the fifth transistor T5 is coupled to the second first level signal input terminal VGL2, and the second terminal of the fifth transistor T5 is coupled to the fourth node QB1.

[0115] The gate of the sixth transistor T6 is coupled to the start signal input terminal STV, the first terminal of the sixth transistor T6 is coupled to the first second level signal input terminal VGH1, and the second terminal of the sixth transistor T6 is coupled to the fourth node QB1.

[0116] The above configuration couples the bottom gate of the fifth transistor T5 to the first first-level signal input terminal VGL1 and the first terminal of the fifth transistor T5 to the second first-level signal input terminal VGL2. This not only better ensures that the threshold voltage of the fifth transistor T5 does not become negatively biased, but also ensures that the fifth transistor T5 conducts better and writes the first-level signal to the fourth node QB1.

[0117] In some embodiments, the fifth transistor T5 is an NMOS transistor and the sixth transistor T6 is a PMOS transistor.

[0118] The fourth node control circuit 44 described above includes the fifth transistor T5 and the sixth transistor T6, so that the fourth node control circuit 44 is formed as an inverter structure, so that the start signal input at the start signal input terminal STV can synchronously control the potential of the fourth node QB1.

[0119] like Figure 9 As shown, in some embodiments, the shift register further includes:

[0120] The noise reduction control circuit 60 is coupled to the second clock signal input terminal CB, the second node QB, the first second level signal input terminal VGH1, and the third node Q3, respectively. It is used to control the electrical connection between the first second level signal input terminal VGH1 and the third node Q3 under the joint control of the second clock signal input terminal CB and the potential of the second node QB.

[0121] For example, the noise reduction control circuit 60 includes a twelfth transistor T12 and a thirteenth transistor T13; the gate of the twelfth transistor T12 is coupled to the second node QB, the first terminal of the twelfth transistor T12 is coupled to the first second-level signal input terminal VGH1, the second terminal of the twelfth transistor T12 is coupled to the first terminal of the thirteenth transistor T13, the gate of the thirteenth transistor T13 is coupled to the second clock signal input terminal CB, and the second terminal of the thirteenth transistor T13 is coupled to the third node Q3.

[0122] The shift register described above includes the noise reduction control circuit 60, which enables the noise reduction control circuit 60 to control whether to write the second level signal to the third node Q3 under the control of the second node QB and the second clock signal, thereby better stabilizing the potential of the third node Q3 and improving the overall noise reduction function of the shift register.

[0123] like Figures 5 to 9As shown, in some embodiments, the first cascade control circuit 20 includes a second transistor T2 and a first capacitor C1; the gate of the second transistor T2 is coupled to the first node Q1, the first terminal of the second transistor T2 is coupled to the second clock signal input terminal CB, and the second terminal of the second transistor T2 is coupled to the cascade signal output terminal CR; the first terminal of the first capacitor C1 is coupled to the first node Q1, and the second terminal of the first capacitor C1 is coupled to the cascade signal output terminal CR.

[0124] The second cascaded control circuit 30 includes a first transistor T1 and a second capacitor C2; the gate of the first transistor T1 is coupled to the second node QB, the first terminal of the first transistor T1 is coupled to the first second-level signal input terminal VGH1, and the second terminal of the first transistor T1 is coupled to the cascaded signal output terminal CR; the first terminal of the second capacitor C2 is coupled to the second node QB, and the second terminal of the second capacitor C2 is coupled to the first second-level signal input terminal VGH1;

[0125] The first node control circuit 41 includes a fourth transistor T4, the gate of the fourth transistor T4 is coupled to the first first level signal input terminal VGL1, the first terminal of the fourth transistor T4 is coupled to the third node Q3, and the second terminal of the fourth transistor T4 is coupled to the first node Q1.

[0126] The third node control circuit 43 includes a third transistor T3, the gate of the third transistor T3 is coupled to the first clock signal input terminal CK, the first terminal of the third transistor T3 is coupled to the start signal input terminal STV, and the second terminal of the third transistor T3 is coupled to the third node Q3.

[0127] The second node control circuit 42 includes a seventh transistor T7, the gate of which is coupled to the first clock signal input terminal CK, the first terminal of which is coupled to the fourth node QB1, and the second terminal of which is coupled to the second node QB.

[0128] When the shift register includes a leakage control circuit 50, the leakage control circuit 50 includes an eleventh transistor T11, the gate of the eleventh transistor T11 is coupled to the gate drive signal output terminal OUT, the first terminal of the eleventh transistor T11 is coupled to the first voltage signal input terminal, and the second terminal of the eleventh transistor T11 is coupled to the second terminal of the tenth transistor T10.

[0129] For example, the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the sixth transistor T6, the seventh transistor T7, the second output transistor T9, the twelfth transistor T12, and the thirteenth transistor T13 are all PMOS transistors; the fifth transistor T5, the first output transistor T8, the tenth transistor T10, and the eleventh transistor T11 are all NMOS transistors.

[0130] It should be noted that the PMOS transistor used in the shift register provided in the above embodiments can be a single-gate transistor or a dual-gate transistor. When a dual-gate transistor is used, the top gate and the bottom gate are connected. The selected dual-gate transistor can have a separate metal layer as the bottom gate, which can improve the reliability of the transistor.

[0131] The shift registers provided in the above embodiments are applicable not only to LTPS and LTPO OLED display panels, but also to LTPS PMOS GOA circuits and CMOS GOA circuits used in LCD display panels, as well as BP GOA circuits under integrated circuit technology used in ARVR display panels.

[0132] The shift register described above uses a CMOS circuit structure, which effectively reduces the number of transistors used in the shift register while outputting a gate drive signal with a positive pulse. When the shift register is applied to a display product, the bezel area of ​​the display product can be further narrowed.

[0133] In some embodiments, the first node control circuit 41 can be coupled to a second first-level signal input terminal VGL2, that is, under the control of the second first-level signal input terminal VGL2, it controls the electrical connection between the first node Q1 and the third node Q3 to be turned on or off. It is worth noting that the first node control circuit 41 should be avoided from being coupled to a third first-level signal input terminal VGL3 as much as possible, to prevent the third first-level signal input terminal VGL3 from fully turning on the fourth transistor T4, which would be detrimental to the control of the potential of the first node Q1.

[0134] like Figure 11 As shown, when the shift register adopts the above structure, the specific working process is as follows:

[0135] During the P1 period, when the voltage of the start signal input at the start signal input terminal STV changes from high to low, and the first clock signal input at the first clock signal input terminal CK is at a high voltage, the third node Q3 and the first node Q1 maintain a high voltage, the voltage of the fourth node QB1 changes from low to high, the second node QB maintains a low voltage, the cascade signal output at the cascade signal output terminal CR maintains a high voltage, and the gate drive signal output at the gate drive signal output terminal OUT is at a low voltage.

[0136] During the P2 period, when the start signal input at the start signal input terminal STV is low and the voltage of the first clock signal input at the first clock signal input terminal CK changes from high to low, the fourth node QB1 remains high, the voltage of the second node QB changes from low to high, and the voltages of the third node Q3 and the first node Q1 are pulled low by the start signal input at the start signal input terminal STV. Since the second clock signal input at the second clock signal input terminal CB is high at this time, the cascade signal output at the cascade signal output terminal CR is high, and the gate drive signal output at the gate drive signal output terminal OUT is low.

[0137] During the P3 period, when the start signal input at the start signal input terminal STV is low and the voltage of the first clock signal input at the first clock signal input terminal CK changes from low to high, the fourth node QB1 maintains a high voltage. Due to the voltage stabilization effect of the first capacitor C1 and the second capacitor C2, the third node Q3 and the first node Q1 maintain a low voltage, and the second node QB maintains a high voltage. Since the second clock signal input at the second clock signal input terminal CB is high at this time, the cascade signal output at the cascade signal output terminal CR maintains a high voltage, and the gate drive signal output at the gate drive signal output terminal OUT is low.

[0138] During period P4, when the start signal input at the start signal input terminal STV is low, the first clock signal input at the first clock signal input terminal CK is high, and the second clock signal input at the second clock signal input terminal CB changes from high to low, the fourth node QB1 remains high. Due to the coupling effect of the second capacitor C2, the voltage of the first node Q1 is pulled down due to the voltage change of the cascaded signal output at the cascaded signal output terminal CR. Due to the voltage limiting effect of the fourth transistor T4, the potential of the third node Q3 is pulled down by a much smaller amount than that of the first node Q1. At this time, the voltage of the cascaded signal output at the cascaded signal output terminal CR changes from high to low, and the voltage of the gate drive signal output at the gate drive signal output terminal OUT changes from low to high.

[0139] During the P5 period, when the start signal input at the start signal input terminal STV is low and the first clock signal input at the first clock signal input terminal CK is high, the fourth section remains high, the third node Q3 and the first node Q1 remain low, the cascade signal output at the cascade signal output terminal CR remains consistent with the second clock signal input at the second clock signal input terminal CB, and the gate drive signal output at the gate drive signal output terminal OUT is opposite to the second clock signal input at the second clock signal input terminal CB.

[0140] During period P6, when the start signal input at the start signal input terminal STV is high, and the voltage of the first clock signal input at the first clock signal input terminal CK changes from high to low, the second clock signal input at the second clock signal input terminal CB is high, the voltage of the fourth node QB1 changes from high to low, the voltages of the third node Q3 and the first node Q1 change from low to high, the second transistor T2 is turned off, the first transistor T1 is turned on, the cascade signal output at the cascade signal output terminal CR maintains a high voltage, and the gate drive signal output at the gate drive signal output terminal OUT is low.

[0141] This invention also provides a gate driving circuit, including a plurality of cascaded shift registers.

[0142] By cascading multiple shift registers together, it is possible to shift a gate drive signal with a positive pulse.

[0143] In the shift register provided in the above embodiment, the cascaded signal output from the cascaded signal output terminal CR is coupled to the top gate of the first output transistor T8 in the output circuit 10, which can control the conduction state of the first output transistor T8, thereby controlling the gate drive signal output terminal OUT to output the gate drive signal. Therefore, in the shift register provided in the above embodiment, there is no need to introduce an additional control circuit to control the output circuit 10. By using the existing cascaded signal in the shift register to control the first output transistor T8 in the output circuit 10, the gate drive signal output terminal OUT can be controlled to output the gate drive signal that meets the requirements. Therefore, the shift register provided in the above embodiment effectively simplifies the circuit complexity, and when the shift register is applied to a display product, the bezel area of ​​the display product can be further narrowed.

[0144] Moreover, in the shift register provided in the above embodiment, the control terminal is coupled to the bottom gate of the first output transistor T8, and the control signal output by the control terminal can control the characteristic parameters of the first output transistor. These characteristic parameters may specifically include the magnitude of the conduction current and the degree of threshold voltage offset, thereby ensuring that the first output transistor can achieve better operating characteristics.

[0145] The gate drive circuit provided in this embodiment of the invention, when including the above-mentioned shift register, also has the above-mentioned beneficial effects, which will not be repeated here.

[0146] In some embodiments, the cascaded signal output terminal CR of the nth stage shift register is coupled to the start signal input terminal STV of the (n+m)th stage shift register, where n is an integer greater than or equal to 1 and m is an integer greater than or equal to 1.

[0147] like Figure 12 As shown, for example, m=1, meaning the cascaded signal output terminal CR of the nth stage shift register is coupled to the start signal input terminal STV of the (n+1)th stage shift register. In this case, the gate drive circuit can connect two clock signal lines (e.g., CK1, CK2). For example, the first clock signal input terminal CK in the odd-numbered shift register is coupled to the first clock signal line CK1, and the second clock signal input terminal CB in the odd-numbered shift register is coupled to the second clock signal line CK2; the first clock signal input terminal CK in the even-numbered shift register is coupled to the second clock signal line CK2, and the second clock signal input terminal CB in the even-numbered shift register is coupled to the first clock signal line CK1. Simultaneously, the gate drive circuit can connect a frame start signal line, meaning the start signal input terminal STV of the first stage shift register is coupled to this frame start signal line. It should be noted that, as shown in the diagram, GOA-1 represents the first-stage shift register, GOA-2 represents the second-stage shift register, GOA-3 represents the third-stage shift register, GOA-4 represents the fourth-stage shift register, GOA-5 represents the fifth-stage shift register, and GOA-6 represents the sixth-stage shift register.

[0148] like Figure 13 and Figure 14As shown, for example, m=2, that is, the cascaded signal output terminal CR of the nth stage shift register is coupled to the start signal input terminal STV of the (n+2)th stage shift register. In this case, the gate drive circuit can be connected to four clock signal lines (e.g., CK1, CK2, CK3, CK4), which can divide the multi-stage shift registers included in the gate drive circuit into multiple register groups. Each register group includes two adjacent shift registers. In the odd-numbered group of shift registers, the first clock signal input terminal CK of the first stage shift register in the two-stage shift register is coupled to the first clock signal line CK1, and the second clock signal input terminal CB is coupled to the third clock signal line CK3. In the two-stage shift register, the first clock signal input terminal CK of the first-stage shift register is coupled to the second clock signal line CK2, and the second clock signal input terminal CB is coupled to the fourth clock signal line CK4. In the even-numbered shift registers, the first clock signal input terminal CK of the first-stage shift register is coupled to the third clock signal line CK3, and the second clock signal input terminal CB is coupled to the first clock signal line CK1. The first clock signal input terminal CK of the other-stage shift register is coupled to the fourth clock signal line CK4, and the second clock signal input terminal CB is coupled to the second clock signal line CK2. Simultaneously, the gate drive circuit can be connected to a frame start signal line, meaning that the start signal input terminals STV of both the first-stage and second-stage shift registers are coupled to this frame start signal line.

[0149] It is worth noting that when m=2, the gate drive circuit can also be configured to connect to two frame start signal lines, that is, the start signal input terminal STV of the first-stage shift register is coupled to the first frame start signal line, and the start signal input terminal STV of the second-stage shift register is coupled to the second frame start signal line.

[0150] For example, when m=3, the cascaded signal output terminal CR of the nth-stage shift register is coupled to the start signal input terminal STV of the (n+3)th-stage shift register. In this case, the gate driver circuit can be connected to six clock signal lines. Simultaneously, the gate driver circuit can be connected to one frame start signal line, meaning the start signal input terminals STV of the first, second, and third-stage shift registers are all coupled to this frame start signal line. It is worth noting that when m=3, the gate driver circuit can also be configured to connect to three frame start signal lines: the start signal input terminal STV of the first-stage shift register is coupled to the first frame start signal line, the start signal input terminal STV of the second-stage shift register is coupled to the second frame start signal line, and the start signal input terminal STV of the third-stage shift register is coupled to the third frame start signal line.

[0151] For example, when m=4, the cascaded signal output terminal CR of the nth-stage shift register is coupled to the start signal input terminal STV of the (n+4)th-stage shift register. In this case, the gate driver circuit can be connected to eight clock signal lines. Simultaneously, the gate driver circuit can be connected to one frame start signal line, meaning the start signal input terminals STV of the first, second, third, and fourth-stage shift registers are all coupled to this frame start signal line. It is worth noting that when m=4, the gate driver circuit can also be configured to connect to four frame start signal lines: the start signal input terminal STV of the first-stage shift register is coupled to the first frame start signal line, the start signal input terminal STV of the second-stage shift register is coupled to the second frame start signal line, the start signal input terminal STV of the third-stage shift register is coupled to the third frame start signal line, and the start signal input terminal STV of the fourth-stage shift register is coupled to the fourth frame start signal line.

[0152] This invention also provides a display device, including the gate driving circuit provided in the above embodiments.

[0153] It should be noted that the display device can be any product or component with display function, such as a television, monitor, digital photo frame, mobile phone, or tablet computer. The display device also includes flexible circuit boards, printed circuit boards, and backplanes.

[0154] The gate driving circuit provided in the above embodiments effectively simplifies circuit complexity and ensures that the gate driving circuit can achieve better operating characteristics. Therefore, the display device provided in the embodiments of the present invention, when including the above-mentioned gate driving circuit, can further narrow the bezel area of ​​the display product.

[0155] It should be noted that, in the embodiments of the present invention, "same layer" can refer to film layers located on the same structural layer. Alternatively, for example, film layers located on the same layer can be layer structures formed by using the same film deposition process to form a specific pattern, and then patterning the film layer using the same photomask through a single patterning process. Depending on the specific pattern, the single patterning process may include multiple exposure, development, or etching processes, and the specific pattern in the formed layer structure can be continuous or discontinuous. These specific patterns may also be at different heights or have different thicknesses.

[0156] In the various method embodiments of the present invention, the sequence numbers of each step are not intended to limit the order of the steps. For those skilled in the art, any changes in the order of the steps without creative effort are also within the scope of protection of the present invention.

[0157] It should be noted that the various embodiments in this specification are described in a progressive manner, and the same or similar parts between the various embodiments can be referred to mutually. Each embodiment focuses on describing the differences from other embodiments. In particular, the method embodiments are basically similar to the product embodiments, so the description is relatively simple, and the relevant parts can be referred to the description of the product embodiments.

[0158] Unless otherwise defined, the technical or scientific terms used in this disclosure shall have the ordinary meaning understood by one of ordinary skill in the art to which this invention pertains. The terms “first,” “second,” and similar terms used in this disclosure do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Terms such as “comprising” or “including” mean that the element or object preceding the word encompasses the elements or objects listed following the word and their equivalents, without excluding other elements or objects. Terms such as “connection,” “coupled,” or “linked” are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. Terms such as “upper,” “lower,” “left,” and “right” are used only to indicate relative positional relationships; these relative positional relationships may change accordingly when the absolute position of the described object changes.

[0159] It is understandable that when a component such as a layer, film, region, or substrate is referred to as being "above" or "below" another component, the component may be "directly" located "above" or "below" the other component, or there may be intermediate components present.

[0160] In the description of the above embodiments, specific features, structures, materials, or characteristics may be combined in any suitable manner in one or more embodiments or examples.

[0161] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in the present invention should be included within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.

Claims

1. A shift register, characterized in that, The output circuit comprises a first output transistor, the first output transistor comprises a double-gate transistor, the top gate of the first output transistor is coupled with a cascade signal output end, the bottom gate of the first output transistor is coupled with a control end, the first electrode of the first output transistor is coupled with a first level signal input end, and the second electrode of the first output transistor is coupled with a gate drive signal output end. The cascade signal output end is used for controlling the first output transistor to be turned on or turned off, and the control end is used for controlling the characteristic parameter of the first output transistor. The shift register comprises a first first level signal input end and a second first level signal input end. The voltage value of the first level signal input by the first first level signal input end is less than the voltage value of the first level signal input by the second first level signal input end. The output circuit further comprises a tenth transistor, the tenth transistor comprises an oxide transistor with a double-gate structure. The top gate of the tenth transistor is coupled with the cascade signal output end, the bottom gate of the tenth transistor is coupled with the cascade signal output end, the first electrode of the tenth transistor is coupled with the first first level signal input end or the second first level signal input end, and the second electrode of the tenth transistor is coupled with the first electrode of the first output transistor. The shift register further comprises: A leakage control circuit is coupled with the gate drive signal output end, the first voltage signal input end and the second electrode of the tenth transistor respectively, and is used for controlling the electrical connection between the first voltage signal input end and the second electrode of the tenth transistor to be turned on or turned off under the control of the gate drive signal output by the gate drive signal output end. The output circuit further comprises a second output transistor, the first output transistor comprises an oxide transistor, and the second output transistor comprises a low-temperature polysilicon transistor. The gate of the second output transistor is coupled with the cascade signal output end, the first electrode of the second output transistor is coupled with a second level signal input end, and the second electrode of the second output transistor is coupled with the gate drive signal output end.

2. The shift register of claim 1, wherein, The shift register comprises a first first level signal input end and a third first level signal input end, the voltage value of the first level signal input by the third first level signal input end is less than the voltage value of the first level signal input by the first first level signal input end. The control end is coupled with the third first level signal input end, and the first electrode of the first output transistor is coupled with the first first level signal input end.

3. The shift register of claim 2, wherein, The shift register comprises a second first level signal input end. The control end is coupled with the cascade signal output end, and the first electrode of the first output transistor is coupled with the second first level signal input end.

4. The shift register of claim 2, wherein, The shift register comprises a first second level signal input end and a second second level signal input end, the voltage value of the second level signal input by the second second level signal input end is less than or equal to the voltage value of the second level signal input by the first second level signal input end. ​ 5. The shift register according to any one of claims 2 to 4, characterized in that, ​ The first electrode of the second output transistor is coupled with the first second-level signal input terminal or the second second-level signal input terminal; The shift register further comprises: The first node control circuit is coupled with the first node, the first first-level signal input terminal, and the third node, respectively, and is configured to control the electrical connection between the first node and the third node to be turned on or turned off under the control of the first second-level signal input by the first second-level signal input terminal; The third node control circuit is coupled with the third node, the start signal input terminal, and the first clock signal input terminal, respectively, and is configured to control the electrical connection between the third node and the start signal input terminal to be turned on or turned off under the control of the first clock signal input by the first clock signal input terminal.

6. The shift register of claim 5, wherein, The shift register further comprises: The second node control circuit is coupled with the second node, the first clock signal input terminal, and the fourth node, respectively, and is configured to control the electrical connection between the second node and the fourth node to be turned on or turned off under the control of the first clock signal input by the first clock signal input terminal; The fourth node control circuit is coupled with the fourth node, the start signal input terminal, the first-level signal input terminal, and the first second-level signal input terminal, respectively, and is configured to control the electrical connection between the fourth node and the first-level signal input terminal to be turned on or turned off under the control of the start signal input by the start signal input terminal, and control the electrical connection between the fourth node and the first second-level signal input terminal to be turned on or turned off.

7. The shift register of claim 6, wherein, The shift register comprises a first first-level signal input terminal and a third first-level signal input terminal, and the level of the first-level signal input by the first first-level signal input terminal is greater than the level of the first-level signal input by the third first-level signal input terminal; The fourth node control circuit comprises a fifth transistor and a sixth transistor; The fifth transistor comprises an oxide transistor with a double-gate structure, the top gate of the fifth transistor is coupled with the start signal input terminal, the bottom gate of the fifth transistor is coupled with the third first-level signal input terminal, the first electrode of the fifth transistor is coupled with the first first-level signal input terminal, and the second electrode of the fifth transistor is coupled with the fourth node; 8. The shift register of claim 7, wherein, ​ ​ ​ A gate of the sixth transistor is coupled with the start signal input end, a first electrode of the sixth transistor is coupled with the first second-level signal input end, and a second electrode of the sixth transistor is coupled with the fourth node.

9. The shift register of claim 7, wherein, The shift register comprises a first first-level signal input end and a second first-level signal input end, a first-level signal inputted by the first first-level signal input end has a smaller level value than a first-level signal inputted by the second first-level signal input end; The fourth node control circuit comprises a fifth transistor and a sixth transistor; The fifth transistor comprises an oxide transistor with a double-gate structure, a top gate of the fifth transistor is coupled with the start signal input end, a bottom gate of the fifth transistor is coupled with the first first-level signal input end, a first electrode of the fifth transistor is coupled with the second first-level signal input end, and a second electrode of the fifth transistor is coupled with the fourth node; A gate of the sixth transistor is coupled with the start signal input end, a first electrode of the sixth transistor is coupled with the first second-level signal input end, and a second electrode of the sixth transistor is coupled with the fourth node.

10. The shift register of claim 7, wherein, The shift register further comprises: The anti-noise control circuit is coupled with the second clock signal input end, the second node, the first second-level signal input end and the third node respectively, and is used for controlling the electrical connection between the first second-level signal input end and the third node to be turned on or turned off under the joint control of the second clock signal inputted by the second clock signal input end and the potential of the second node.

11. The shift register according to claim 10, wherein The first cascade control circuit comprises a second transistor and a first capacitor, a gate of the second transistor is coupled with the first node, a first electrode of the second transistor is coupled with the second clock signal input end, and a second electrode of the second transistor is coupled with the cascade signal output end; a first electrode of the first capacitor is coupled with the first node, and a second electrode of the first capacitor is coupled with the cascade signal output end; The second cascade control circuit comprises a first transistor and a second capacitor, a gate of the first transistor is coupled with the second node, a first electrode of the first transistor is coupled with the first second-level signal input end, and a second electrode of the first transistor is coupled with the cascade signal output end; a first electrode of the second capacitor is coupled with the second node, and a second electrode of the second capacitor is coupled with the first second-level signal input end; The first node control circuit comprises a fourth transistor, a gate of the fourth transistor is coupled with the first first-level signal input end, a first electrode of the fourth transistor is coupled with the third node, and a second electrode of the fourth transistor is coupled with the first node; The third node control circuit comprises a third transistor, a gate of the third transistor is coupled with the first clock signal input end, a first pole of the third transistor is coupled with the start signal input end, and a second pole of the third transistor is coupled with the third node. The second node control circuit comprises a seventh transistor, a gate of the seventh transistor is coupled with the first clock signal input end, a first pole of the seventh transistor is coupled with the fourth node, and a second pole of the seventh transistor is coupled with the second node. In the case that the shift register comprises a leakage control circuit, the leakage control circuit comprises an eleventh transistor, a gate of the eleventh transistor is coupled with the gate drive signal output end, a first pole of the eleventh transistor is coupled with a first voltage signal input end, and a second pole of the eleventh transistor is coupled with a second pole of the tenth transistor. The anti-noise control circuit comprises a twelfth transistor and a thirteenth transistor. A gate of the twelfth transistor is coupled with the second node, a first pole of the twelfth transistor is coupled with the first second level signal input end, a second pole of the twelfth transistor is coupled with a first pole of the thirteenth transistor, a gate of the thirteenth transistor is coupled with the second clock signal input end, and a second pole of the thirteenth transistor is coupled with the third node.

12. A gate drive circuit, characterized by A plurality of shift registers as claimed in any one of claims 1-11 are cascaded.

13. The gate drive circuit according to claim 12, characterized by A cascade signal output end of an n-level shift register is coupled with a start signal input end of an n+m-level shift register, n is an integer greater than or equal to 1, and m is an integer greater than or equal to 1.

14. A display device comprising: It comprises: The gate drive circuit as claimed in claim 12 or 13.

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