Memory, memory operation method and memory system

Abstract

The invention provides a memory, a memory operation method and a memory system, and relates to the technical field of memories. The memory includes: a memory cell array; the plurality of bit lines are respectively coupled to different memory strings in the memory cell array; a peripheral circuit includes a page buffer circuit coupled to a memory string through a bit line, in which the page buffer circuit includes: a first sensing latch circuit including a first sensing unit configured to sense data of the memory string and a first latch unit coupled to each other, the first sensing unit configured to sense the data of the memory string, and the first latch unit configured to latch the data of the memory string; the first latch unit is configured to latch data sensed by the first sensing unit; the second sensing latch circuit is configured to control the first switch unit to be switched on or switched off according to data sensed by the second sensing latch circuit; and the first switch unit is configured to open or close the connection between the first sensing unit and the first latch unit under the control of the data sensed by the second sensing latch circuit. The memory realizes reduction of DC current generated in a first sense latch circuit of a page buffer circuit during a read process.

Description

Technical Field

[0001] The present disclosure relates to the field of memory technology, and in particular to a memory, a memory operation method, and a memory system. Background Art

[0002] Flash memory is a widely used non-volatile memory that can be electrically erased and reprogrammed. Flash memory includes NOR flash memory and NAND flash memory. The threshold voltage of a memory cell in the flash memory can be changed to a desired level to perform read, program, and erase operations. For NAND flash memory, an erase operation can be performed at the block level, and a program operation or a read operation can be performed at the page level.

[0003] The memory includes a memory cell array and a peripheral circuit, wherein the peripheral circuit includes a page buffer circuit. The page buffer circuit can perform a sensing operation in a programming operation or a reading operation, for example.

[0004] The above information disclosed in this Background section is only for enhancement of understanding of the background of the present disclosure and therefore it may contain information that does not constitute the prior art that is already known to one of ordinary skill in the art. Summary of the invention

[0005] The purpose of the present disclosure is to provide a memory, a memory operation method and a memory system.

[0006] Other features and advantages of the present disclosure will become apparent from the following detailed description, or may be learned in part by the practice of the present disclosure.

[0007] According to one aspect of the present disclosure, a memory is provided, comprising: a memory cell array; a plurality of bit lines, the plurality of bit lines being respectively coupled to different memory strings in the memory cell array; a peripheral circuit, the peripheral circuit comprising a page buffer circuit, the page buffer circuit being coupled to the memory strings through the bit lines, wherein the page buffer circuit comprises: a first sensing latch circuit, comprising a first sensing unit and a first latch unit coupled to each other, the first sensing unit being configured to sense data of the memory string, the first latch unit being configured to latch the data sensed by the first sensing unit; a second sensing latch circuit being configured to control a first switch unit to be turned on or off according to the data sensed by the second sensing latch circuit; and the first switch unit being configured to control the connection between the first sensing unit and the first latch unit to be turned on or off by the data sensed by the second sensing latch circuit.

[0008] According to one embodiment of the present disclosure, the memory cell array includes a first memory cell in a first programming state and a second memory cell in a second programming state, the threshold voltage of the first memory cell is less than the threshold voltage of the second memory cell, and the first memory cell is coupled to a first word line; the first switch unit is also configured to control shutdown by sensing data of the first memory cell by the second sensing latch circuit when a first read voltage is applied to the first word line, and the first read voltage is greater than the threshold voltage of the first memory cell.

[0009] According to an embodiment of the present disclosure, the second storage unit is coupled to a second word line, and the first switch unit is further configured to be turned on by the second sensing latch circuit sensing data of the second storage unit when the first read voltage is applied to the second word line.

[0010] According to an embodiment of the present disclosure, the first sensing latch circuit further includes a first node disposed at a first end of the first latch unit, and the first node is used to output data sensed by the first sensing unit to the first storage unit.

[0011] According to an embodiment of the present disclosure, the first switch unit includes a first transistor, and the first sensing unit includes a second transistor, wherein: the first terminal of the first transistor is coupled to the first terminal of the second transistor, the second terminal of the first transistor is coupled to the input end of the first latch unit, and the control terminal of the first transistor is coupled to the input end of the second sensing latch circuit; the second terminal of the second transistor is coupled to a ground voltage source, and the control terminal of the second transistor is coupled to a sensing node.

[0012] According to one embodiment of the present disclosure, the second sensing latch circuit includes a second sensing unit and a second latch unit coupled to each other, and the second sensing unit includes a third transistor, wherein: the first terminal of the third transistor is coupled to a ground voltage source, the second terminal of the third transistor is coupled to the input end of the second latch unit, and the control terminal of the third transistor is coupled to the sensing node; the control terminal of the first transistor is coupled to the input end of the second latch unit.

[0013] According to an embodiment of the present disclosure, the second sensing latch circuit also includes a first data reset switch unit, the first data reset switch unit includes a fourth transistor, the first terminal of the fourth transistor is coupled to the second terminal of the third transistor, and the second terminal of the fourth transistor is coupled to the input end of the second latch unit.

[0014] According to one embodiment of the present disclosure, the second sensing latch circuit also includes a first data input switch unit, the first data input switch unit includes a fifth transistor, the first terminal of the fifth transistor is coupled to the second terminal of the third transistor, and the second terminal of the fifth transistor is coupled to the output end of the second latch unit.

[0015] According to one embodiment of the present disclosure, the first sensing latch circuit also includes a second data input switch unit, the second data input switch unit includes a sixth transistor, the first terminal of the sixth transistor is coupled to the second terminal of the first transistor, and the second terminal of the sixth transistor is coupled to the input end of the first latch unit.

[0016] According to an embodiment of the present disclosure, the page buffer circuit further includes a second switch unit connected in parallel with the first switch unit and configured to disconnect the first sensing unit and the first latch unit under the control of a first signal.

[0017] According to an embodiment of the present disclosure, the second switching unit includes a seventh transistor, a first terminal of the seventh transistor is coupled to the first terminal of the first transistor, a second terminal of the seventh transistor is coupled to the second terminal of the first transistor, and a control terminal of the seventh transistor inputs the first signal.

[0018] According to another aspect of the present disclosure, a memory operation method is provided, wherein a page buffer circuit of the memory includes a first sensing latch circuit, a second sensing latch circuit and a first switch unit, wherein the first sensing latch circuit includes a first sensing unit and a first latch unit, wherein the first switch unit is coupled between the first sensing unit and the first latch unit, wherein an input end of the second sensing latch circuit is coupled to a control end of the first switch unit, wherein the second sensing latch circuit includes a first data input switch unit, and wherein the method includes: in a sensing stage, controlling the first data input switch unit to be turned on.

[0019] According to one embodiment of the present disclosure, the memory includes a first storage cell in a first programming state and a second storage cell in a second programming state, the threshold voltage of the first storage cell is less than the threshold voltage of the second storage cell, and the first storage cell is coupled to a first word line; the first switch unit is configured to be turned off by controlling the data of the first storage cell input into the second sensing latch circuit when a first read voltage is applied to the first word line during the sensing phase, and the first read voltage is greater than the threshold voltage of the first storage cell; the method also includes: in the sensing phase, applying the first read voltage to the first word line.

[0020] According to an embodiment of the present disclosure, the first sensing latch circuit further includes a second data input switch unit; the method further includes: in a data storage phase after the sensing phase, controlling the second data input switch unit to turn on.

[0021] According to an embodiment of the present disclosure, the second sensing latch circuit further includes a first data reset switch unit; the method further includes: in a pre-charging phase before the sensing phase, controlling the first data reset switch unit to be turned on.

[0022] According to an embodiment of the present disclosure, the first sensing latch circuit further includes a second data reset switch unit; the method further includes: in the pre-charging stage, controlling the second data reset switch unit to turn on.

[0023] According to one embodiment of the present disclosure, the second programming state includes a third programming state and a fourth programming state, the second storage cell includes a third storage cell in the third programming state and a fourth storage cell in the fourth programming state, the threshold voltage of the third storage cell is less than the threshold voltage of the fourth storage cell; the first read voltage is greater than the threshold voltage of the third storage cell and less than the threshold voltage of the fourth storage cell.

[0024] According to an embodiment of the present disclosure, the page buffer circuit further includes a second switch unit connected in parallel with the first switch unit; and the method further includes: in the sensing phase, controlling the second switch unit to be turned off.

[0025] According to yet another aspect of the present disclosure, a storage system is provided, comprising: any one of the above-mentioned memories and a controller coupled to the memory.

[0026] It is to be understood that the foregoing general description and the following detailed description are exemplary only and are not restrictive of the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] The above and other objects, features and advantages of the present disclosure will become more apparent by describing in detail example embodiments thereof with reference to the attached drawings.

[0028] Figure 1 A block diagram showing an exemplary system with a memory according to an embodiment of the present disclosure is shown.

[0029] Figure 2A A block diagram of a memory system is shown as an example.

[0030] Figure 2B A block diagram of another memory system is shown as an example.

[0031] Figure 3A schematic circuit diagram of a memory 300 including peripheral circuits provided in an embodiment of the present disclosure.

[0032] Figure 4 A schematic diagram of a peripheral circuit provided in an embodiment of the present disclosure.

[0033] Figure 5 A block diagram of a page buffer circuit is exemplarily shown.

[0034] Figure 6 An exemplary implementation of reading a TLC memory cell is schematically illustrated.

[0035] Figure 7 According to an embodiment of the present disclosure, a schematic block diagram of a sensing latch circuit in a page buffer circuit is shown.

[0036] Fig. 8A An exemplary implementation of applying the page buffer circuit provided by the embodiment of the present disclosure to the reading of TLC is schematically shown.

[0037] Figure 8B Another exemplary implementation of applying the page buffer circuit provided by the embodiment of the present disclosure to the reading of TLC is schematically shown.

[0038] Fig. 9 A schematic block diagram of a sensing latch circuit in another page buffer circuit is shown according to an embodiment of the present disclosure.

[0039] Fig. 10A According to an embodiment of the present disclosure, a circuit diagram of a sensing latch circuit in a page buffer circuit is shown.

[0040] Fig. 10B A circuit diagram of a sensing latch circuit in another page buffer circuit is shown according to an embodiment of the present disclosure.

[0041] Fig.11 A flow chart of a memory operation method in an embodiment of the present disclosure is shown.

[0042] Fig.12 A flow chart showing another memory operation method in an embodiment of the present disclosure.

[0043] Fig.13 A flowchart of another memory operation method in an embodiment of the present disclosure is shown.

[0044] Fig.14 according to Figures 11 to 13 A signal waveform diagram of a memory operation method is shown. DETAILED DESCRIPTION

[0045] Example embodiments will now be described more fully with reference to the accompanying drawings. However, example embodiments can be implemented in a variety of forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided so that the disclosure will be more comprehensive and complete and will fully convey the concepts of the example embodiments to those skilled in the art. The accompanying drawings are only schematic illustrations of the disclosure and are not necessarily drawn to scale. The same reference numerals in the figures represent the same or similar parts, and thus their repeated description will be omitted.

[0046] In addition, the described features, structures or characteristics may be combined in one or more embodiments in any suitable manner. In the following description, many specific details are provided to provide a full understanding of the embodiments of the present disclosure. However, those skilled in the art will appreciate that the technical solutions of the present disclosure may be practiced while omitting one or more of the specific details, or other methods, devices, steps, etc. may be adopted. In other cases, well-known structures, methods, devices, implementations or operations are not shown or described in detail to avoid obscuring various aspects of the present disclosure.

[0047] In addition, the terms "first", "second", etc. are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of the present disclosure, the meaning of "plurality" is at least two, such as two, three, etc., unless otherwise clearly and specifically defined. The symbol " / " generally indicates that the objects associated with each other are in an "or" relationship.

[0048] In this disclosure, unless otherwise clearly specified and limited, terms such as "connection" should be understood in a broad sense, for example, it can be an electrical connection or can communicate with each other; it can be directly connected or indirectly connected through an intermediate medium. For ordinary technicians in this field, the specific meanings of the above terms in this disclosure can be understood according to specific circumstances.

[0049] Figure 1 A block diagram of an exemplary system with a memory in an embodiment of the present disclosure is shown. System 100 may be a mobile phone, a desktop computer, a laptop computer, a tablet computer, a vehicle computer, a game console, a printer, a positioning device, a wearable electronic device, a smart sensor, a virtual reality device, an augmented reality device, or any other suitable electronic device having a memory therein.

[0050] like Figure 1As shown, the system 100 may include a host 108 and a memory system 102, the memory system 102 having one or more memories 104 and a memory controller 106. The host 108 may be a processor (e.g., a central processing unit (CPU)) or a system on chip (SoC) (e.g., an application processor) of an electronic device. The host 108 may be configured to send data to the memory 104 or receive data from the memory 104.

[0051] The memory 104 may be any memory in the present disclosure, for example, a non-volatile memory. The non-volatile memory may be a NAND flash memory (eg, a three-dimensional (3D) NAND flash memory).

[0052] In some embodiments, the memory controller 106 is coupled to the memory 104 and the host 108 and is configured to control the memory 104. The memory controller 106 may manage data stored in the memory 104 and communicate with the host 108.

[0053] In some embodiments, the memory controller 106 is configured to send a command to the memory 104 so that the memory 104 executes the memory operation method provided by the embodiments of the present disclosure.

[0054] In some embodiments, the memory controller 106 is designed to operate in a low duty cycle environment, such as a secure digital (SD) card, a compact flash (CF) card, a universal serial bus (USB) flash drive, or other media for use in electronic devices such as personal computers, digital cameras, mobile phones, etc.

[0055] In some embodiments, the memory controller 106 is designed to operate in a high duty cycle environment, such as a solid state drive (SSD) or an embedded multimedia card (eMMC), which can be used as data storage for mobile devices such as smartphones, tablet computers, laptop computers, etc., as well as enterprise storage arrays. The memory controller 106 can be configured to send commands to the memory 104 to cause the memory 104 to perform operations, such as read, erase, and program operations.

[0056] The memory controller 106 may also be configured to manage various functions regarding data stored or to be stored in the memory 104 , including, but not limited to, bad block management, garbage collection, logical to physical address translation, wear leveling, and the like.

[0057] In some embodiments, the memory controller 106 is further configured to process error correction codes (ECC) on data read from or written to the memory 104. The memory controller 106 may also perform any other suitable functions, such as formatting the memory 104. The memory controller 106 may communicate with an external device (e.g., the host 108) according to a specific communication protocol. For example, the memory controller 106 may communicate with the external device through at least one of various interface protocols, such as a USB protocol, an MMC protocol, a peripheral component interconnect (PCI) protocol, a PCI Express (PCI-E) protocol, an Advanced Technology Attachment (ATA) protocol, a serial ATA protocol, a parallel ATA protocol, a small computer mini interface (SCSI) protocol, an enhanced small disk interface (ESDI) protocol, an integrated drive electronics (IDE) protocol, a Firewire protocol, etc.

[0058] The memory controller 106 and the one or more memories 104 may be integrated into various types of storage devices, for example, included in the same package (eg, a universal flash storage (UFS) package or an eMMC package). That is, the memory system 102 may be implemented and packaged into different types of terminal electronic products.

[0059] Figure 2A A block diagram of a memory system is shown as an example. Figure 2A As shown, the memory controller 106 and the single memory 104 may be integrated into a memory card 202. The memory card 202 may include a PC card (also known as a PCMCIA card, a Personal Computer Memory Card International Association card), a CF card, a Smart Media (SM) card, a memory stick, a multimedia card (e.g., an MMC card, an RS-MMC card, an MMCmicro card, etc.), an SD card (e.g., an SD card, a miniSD card, a microSD card, an SDHC card, etc.), a UFS card, etc. The memory card 202 may also include a computer that connects the memory card 202 to a host (e.g., Figure 1 A memory card connector 204 is coupled to the host 108 in the memory card connector.

[0060] Figure 2B FIG. 1 is a block diagram of another memory system. Figure 2B As shown, the memory controller 106 and the plurality of memories 104 may be integrated into the SSD 206. The SSD 206 may also include a processor that connects the SSD 206 to a host (e.g., Figure 1 In some embodiments, the storage capacity and / or operating speed of the SSD 206 is greater than the storage capacity and / or operating speed of the memory card 202.

[0061] Figure 3A schematic circuit diagram of a memory 300 including a peripheral circuit provided in an embodiment of the present disclosure. The memory 300 may be Figure 1 300 may include a memory cell array 301 and a peripheral circuit 302 coupled to the memory cell array 301. The memory cell array 301 may be a NAND flash memory cell array, wherein the memory cells 306 are provided in the form of an array of memory strings 308 of the NAND flash memory, each memory string 308 extending vertically above a substrate (not shown).

[0062] In some embodiments, the peripheral circuit 302 is configured to execute the operation method provided by the embodiment of the present disclosure. It is understood that the peripheral circuit 302 can be configured to execute the operation method provided by the embodiment of the present disclosure according to the instruction received from the memory controller 106.

[0063] In some embodiments, each memory string 308 includes a plurality of memory cells 306 coupled in series and stacked vertically. Each memory cell 306 can hold a continuous analog value, such as a voltage or charge, which depends on the number of electrons trapped in the region of the memory cell 306. Each memory cell 306 can be a floating gate type memory cell including a floating gate transistor, or a charge trapping type memory cell including a charge trapping transistor.

[0064] In some embodiments, each storage cell 306 can store 1 bit of data or 2 bits of data or more bits of data, that is, it can be a single-level cell (SLC) type, a multi-level cell (MLC) type, a triple-level cell (TLC) type, a quad-level cell (QLC) type or a higher level type.

[0065] like Figure 3 As shown, each memory string 308 may include a source select gate (SSG) 310 at its source terminal and a drain select gate (DSG) 312 at its drain terminal. SSG 310 and DSG 312 may be configured to activate the selected memory string 308 during read and program operations.

[0066] In some embodiments, the sources of the memory strings 308 in the same block 304 are coupled through the same source line (Source Line, SL) 314 (e.g., a common SL). For example, all memory strings 308 in the same block 304 have an array common source (Array Common Source, ACS). Figure 3 As shown, the memory string 308 can be organized into a plurality of blocks 304, each of which can have a common source line 314 (e.g., coupled to ground). In some embodiments, each block 304 is a basic data unit for an erase operation, i.e., all memory cells 306 on the same block 304 are erased at the same time.

[0067] In some embodiments, the transistors of the DSG 312 of each memory string 308 are coupled to a corresponding bit line (BL) 316, and data can be read from or written to the bit line 316 via an output bus (not shown). Each memory string 308 can be configured to be selected or deselected by applying a selection voltage (e.g., higher than the threshold voltage of the transistors having the DSG 312) or a deselection voltage (e.g., 0V) to the corresponding DSG 312 via one or more DSG lines 313 and / or by applying a selection voltage (e.g., higher than the threshold voltage of the transistors having the SSG 310) or a deselection voltage (e.g., 0V) to the corresponding SSG 310 via one or more SSG lines 315.

[0068] like Figure 3 As shown, the memory cells 306 of the memory string 308 may be coupled via a word line (WL) 318, which selects which row of memory cells 306 are affected by read and program operations. The peripheral circuit 302 may be coupled to the memory cell array 301 via a bit line 316, a word line 318, a source line 314, an SSG line 315, and a DSG line 313. The peripheral circuit 302 may include any suitable analog, digital, and mixed signal circuits for facilitating the operation of the memory cell array 301 by applying a voltage signal and / or a current signal to each memory cell 306 that is the target of the operation and sensing a voltage signal and / or a current signal from each memory cell 306 that is the target of the operation via the bit line 316, the word line 318, the source line 314, the SSG line 315, and the DSG line 313. The peripheral circuit 302 may include various types of peripheral circuits formed using Metal-Oxide-Semiconductor (MOS) technology.

[0069] Figure 4 Schematic diagram of a peripheral circuit provided by an embodiment of the present disclosure. Figure 4 As shown, the peripheral circuit 302 may include a page buffer circuit / sense amplifier 404, a column decoder / BL driver 406, a row decoder / WL driver 408, a voltage generator 410, a control logic unit 412, a register 414, an input / output (I / O) circuit 416, and a data bus 418. It should be understood that in some examples, the peripheral circuit 302 may also include Figure 4Additional peripheral circuits not shown.

[0070] In some embodiments, the page buffer circuit / sense amplifier 404 can be configured to read data from the memory cell array 301 and program (write) data to the memory cell array 301 according to a control signal from the control logic unit 412. For example, the page buffer circuit / sense amplifier 404 can store a page of programming data (write data) to be programmed into the memory cell array 301. For another example, the page buffer circuit / sense amplifier 404 can also sense a low-power signal from the bit line 316 representing a data bit stored in the memory cell 306, and amplify a small voltage swing to a recognizable logic level in a read operation. The column decoder / BL driver 406 can be configured to be controlled by the control logic unit 412, and select one or more memory strings 308 by applying a bit line voltage generated from the voltage generator 410.

[0071] The row decoder / WL driver 408 may be configured to be controlled by the control logic unit 412, and select / deselect the block 304 of the memory cell array 301 and select / deselect the word line 318 of the block 304. The row decoder / WL driver 408 may also be configured to drive the word line 318 using the word line voltage generated from the voltage generator 410. In some embodiments, the row decoder / WL driver 408 may also select / deselect and drive the SSG line 314 and the DSG line 313. The voltage generator 410 may be configured to be controlled by the control logic unit 412, and generate a word line voltage (e.g., a read voltage, a program voltage, a pass voltage, a local voltage, a verification voltage, etc.), a bit line voltage, a source line voltage, etc. to be supplied to the memory cell array 301.

[0072] The control logic unit 412 may be coupled to each portion of the peripheral circuit 302 and configured to control the operation of each portion. The register 414 may be coupled to the control logic unit 412 and may include a status register, a command register, and an address register for storing status information, a command operation code (OP code), and a command address for controlling the operation of each peripheral circuit. The input / output circuit 416 may be coupled to the control logic unit 412 and act as a control buffer to buffer the input / output information from the host ( Figure 4 The input / output circuit 416 may also be coupled to the column decoder / bit line driver 406 via the data bus 418 and act as a data I / O interface and data buffer to buffer data and relay it to or from the memory cell array 301.

[0073] Figure 5 A block diagram of a page buffer circuit is exemplarily shown. Figure 5 Can be Figure 4 An example of a page buffer circuit / sense amplifier 404 in FIG. Figure 5 As shown, the page buffer circuit / sense amplifier 404 may include a plurality of page buffer circuits 500, each of which is coupled to a corresponding one of the bit lines 316, i.e., each page buffer circuit 500 may be coupled to a corresponding storage string 308 via a corresponding bit line 316, and is configured to temporarily store data read from a corresponding selected storage cell (coupled to a selected word line 318 and a bit line 316 coupled to the selected storage cell) during a read operation.

[0074] Each page buffer circuit 500 may include a bias circuit 501, which is coupled to the corresponding bit line 316 and is, for example, configured to be controlled by the control logic unit 412 to apply a bit line voltage to a corresponding selected storage cell coupled to the corresponding bit line 316 in a programming operation, and is, for example, configured to be controlled by the control logic unit 412 to pass the current on the bit line 316 to the sensing node SO in a read operation.

[0075] Each page buffer circuit 500 may also include a plurality of latch circuits for storing non-data page information (ie, any information other than the data bits in the data page). Figure 5 As shown in , in some embodiments, the page buffer circuit 500 may include latched circuits A 502, B 504, C 506, and D 508, one or more of which may be a sensing latch circuit configured to latch data based on a current flowing through a bit line, and the remaining one or more latch circuits may be a data latch circuit configured to latch the data sensed by the sensing latch circuit in a read operation, and may also be configured to latch the data to be programmed to a selected memory cell in a programming operation. It should be understood that Figure 5 The number of latch circuits can be adjusted according to actual needs.

[0076] Figure 6 An exemplary embodiment of reading a TLC storage cell is schematically shown. Figure 5 The page buffer circuit shown reads TLC memory cells, wherein latch circuits B 504, C 506 and D 508 store the read data of the upper page, middle page and lower page respectively.

[0077] like Figure 6As shown, the TLC memory cell has 8 states, L0, L1, L2...L7, including one erased state L0 and 7 programmed states L1, L2...L7. The upper limit of the threshold voltage distribution interval of the memory cell in the erased state L0 is E0, the lower limit of the threshold voltage distribution interval of the memory cell in the programmed state L1 is E2 and the upper limit is E3, and so on. Figure 6 It is exemplified that the midpoint of the threshold voltage distribution range of the memory cell in the erased state L0 is -3V, the upper limit of the threshold voltage distribution range of the memory cell in the programmed state L7 is 5V, and the threshold voltage distribution ranges of the memory cells in the remaining programmed states L1, L2 ... L6 are arranged in sequence between -3V and 5V.

[0078] according to Figure 6 In the example in , in some embodiments, when reading a TLC memory cell, read voltages RD1 and RD5 may be applied to the corresponding word lines to read the data of the upper page, wherein the read voltage RD1 is between E0 and E1, and the read voltage RD5 is between E8 and E9. Then, read voltages RD2, RD4, and RD6 are applied to the corresponding word lines to read the data of the middle page, wherein the read voltage RD2 is between E2 and E3, the read voltage RD4 is between E6 and E7, and the read voltage RD6 is between E10 and E11. Then, read voltages RD3 and RD7 are applied to the corresponding word lines to read the data of the lower page, wherein the read voltage RD3 is between E4 and E5, and the read voltage RD7 is between E12 and E13.

[0079] In other embodiments, when reading the TLC memory cell, read voltages RD3 and RD7 may be applied to the corresponding word lines to read the data of the lower page, and then read voltages RD2, RD4 and RD6 may be applied to the corresponding word lines to read the data of the middle page, and then read voltages RD1 and RD5 may be applied to the corresponding word lines to read the data of the upper page.

[0080] When a higher read voltage is used to read the data stored in the target memory cell, if the threshold voltage of the target memory cell is so low that the gap with the read voltage is large, a larger voltage difference will be generated between the gate and the channel of the target memory cell, that is, a larger current (DC current) will be generated in the channel, and the DC current can be transmitted to the sensing unit in the sensing latch circuit in the page buffer circuit through the sensing node SO, thereby generating a larger DC current in the sensing latch circuit. When a read operation is performed simultaneously on multiple layers of a three-dimensional memory stacked by multiple layers of planes, a larger instantaneous current peak will be generated due to the DC current, and the increase in the number of layers of the three-dimensional memory stack is therefore limited. In some embodiments, additional metal wiring is used as a power output channel to avoid the larger instantaneous current peak affecting the stability of the power supply voltage (vdd) and the ground voltage (vss), but some performance will be sacrificed, such as increasing the reading time / programming time. In addition, additional metal wiring will also increase the processing cost.

[0081] Figure 7 According to an embodiment of the present disclosure, a schematic block diagram of a sensing latch circuit in a page buffer circuit is shown. Figure 7 A partial page buffer circuit is shown, including a first sensing latch circuit 502 and a second sensing latch circuit 504. The first sensing latch circuit 502 may include a first sensing unit 7024 and a first latch unit 7022 coupled to each other, and the second sensing latch circuit 504 may include a second sensing unit 7044 and a second latch unit 7042 coupled to each other. The first sensing unit 7024 and the second sensing unit 7044 are coupled to a sensing node SO and are configured to sense data of a storage string. The output terminal Ao of the first latch unit 7022 (corresponding to the first node of the first terminal) and the output terminal Bo of the second latch unit 7042 are coupled to the sensing node SO and are configured to output the latched data through the sensing node SO.

[0082] In some embodiments, the page buffer circuit may further include a first switch unit 706 , which may be configured to control opening or disconnecting the connection between the first sensing unit 7024 and the first latch unit 7022 according to the data sensed by the second sensing latch circuit 504 . Figure 7 An exemplary connection method between the first switch unit 706 and the second sensing latch circuit 504 is shown. Figure 7 As shown, the first end (for example, the control end) of the first switch unit 706 can be coupled to the input end Bi of the second latch unit 7042, the second end of the first switch unit 706 is coupled to the first end of the first sensing unit 7024, and the third end of the first switch unit 706 is coupled to the input end Ai of the first latch unit 7022. Then, the second sensing latch circuit 504 is configured to control the first switch unit to be turned on or off according to the data sensed by it.

[0083] The following takes the first read voltage to read the memory cell with three threshold voltages as an example. Figure 7 The sensing process of the sensing latch circuit shown in the figure in the reading operation is described. Among them, the first storage cell is in the first programming state, the second storage cell is in the second programming state, the threshold voltage of the first storage cell is less than the threshold voltage of the second storage cell, and the first reading voltage is greater than the threshold voltage of the first storage cell; the second programming state includes the third programming state and the fourth programming state, the second storage cell includes the third storage cell in the third programming state and the fourth storage cell in the fourth programming state, the threshold voltage of the third storage cell is less than the threshold voltage of the fourth storage cell, and the first reading voltage is greater than the threshold voltage of the third storage cell and less than the threshold voltage of the fourth storage cell.

[0084] For example, it can be configured that the time when the second sensing latch circuit 504 starts to sense the data on the SO node is earlier than the time when the first sensing latch circuit 502 starts to sense the data on the SO node. Then, when the first read voltage is applied to the first word line connected to the first storage unit to be read, when the threshold voltage of the first storage unit to be read is less than the first read voltage and the voltage difference is large, when the second sensing latch circuit 504 performs sensing, the voltage drop on the SO node is large enough to make the current voltage on the SO node low enough to keep the second sensing unit 7044 turned off, so that the input terminal Bi of the second sensing unit 7044 (which has been reset to 0 in the pre-charging stage) is maintained at a low level, and then the first switch unit 706 is controlled to be turned off, disconnecting the connection between the first sensing unit 7024 and the first latch unit 7022, and the DC current generated due to the large difference between the first read voltage and the threshold voltage of the first storage unit will not be transmitted to the first sensing latch circuit 502. Furthermore, when the first sensing latch circuit 502 senses, the data sensed by the first sensing unit 7024 will not be transmitted to the first latch unit 7022, and the output terminal Ao of the first latch unit 7022 (which has been reset to 0 in the pre-charging stage) is still at a low level, thereby ensuring that the data output by the first sensing latch circuit 502 is correct and avoiding the DC current from being transmitted to the first sensing latch circuit 502.

[0085] For another example, when the first read voltage is applied to the second word line connected to the second storage unit to be read, when the threshold voltage of the second storage unit is greater than the first read voltage (i.e., the fourth storage unit mentioned above), when the second sensing latch circuit 504 performs sensing, the voltage drop on the SO node is small, and the current voltage of the SO node is sufficient to control the second sensing unit 7044 to turn on, so that the input terminal Bi of the second sensing unit 7044 is flipped to a high level, thereby controlling the first switch unit 706 to turn on, and the first sensing unit 7024 is connected to the first latch unit 7022; then the first sensing latch circuit 502 performs sensing, and the voltage drop on the SO node is small, thereby controlling the first sensing unit 7024 to turn on (i.e., the current SO node voltage Vso is greater than the flip voltage Vtrip), and the input terminal Ai of the first latch unit 7022 is flipped to a low level, and the output terminal Ao is flipped to a high level.

[0086] For another example, when the first read voltage is applied to the second word line connected to the second storage unit to be read, when the threshold voltage of the second storage unit is less than the first read voltage and the voltage difference is small (for example, the third storage unit mentioned above), when the second sensing latch circuit 504 performs sensing, the voltage drop on the SO node is small, and the current voltage of the SO node is sufficient to control the second sensing unit 7044 to turn on, so that the input terminal Bi of the second sensing unit 7044 is flipped to a high level, thereby controlling the first switch unit 706 to turn on, and the first sensing unit 7024 is connected to the first latch unit 7022; then the first sensing latch circuit 502 performs sensing, and the voltage on the SO node continues to drop so as to control the first sensing unit 7024 to turn off (that is, the current SO node voltage Vso is less than the flip voltage Vtrip), and the input terminal Ai of the first latch unit 7022 is still at a high level, and the output terminal Ao is still at a high level. In this case, because the difference between the first read voltage and the threshold voltage of the first storage unit is small, the generated current is transmitted to the first sensing latch circuit 502, but the impact on it is small and can be ignored.

[0087] According to the memory provided by the embodiment of the present disclosure, by setting a first switch unit coupled between the first sensing latch circuit and the second sensing latch circuit in the page buffer circuit, the first switch unit is configured to control the opening or disconnection of the connection between the first sensing unit and the first latch unit of the first sensing latch circuit by the data sensed by the second sensing latch circuit, so that the DC current generated by the large gap between the read voltage and the threshold voltage of the storage unit can be avoided from being transmitted to the first sensing latch circuit while ensuring that the data output by the first sensing latch circuit is correct, thereby reducing the instantaneous current peak, reducing the reading time / programming time, improving the performance of the memory, and reducing the processing cost. At the same time, it can also break through the limitation of the increase in the number of layers of the three-dimensional memory stack due to the DC current.

[0088] Fig. 8A An exemplary implementation of applying the page buffer circuit provided by the embodiment of the present disclosure to TLC reading is schematically shown. Fig. 8A , the memory cells with programming states L0 to L5 may be, for example, the first memory cell mentioned above, the memory cells with programming states L6 and L7 may be, for example, the second memory cell mentioned above, wherein the memory cell with programming state L6 may be the third memory cell mentioned above, and the memory cell with programming state L7 may be the fourth memory cell mentioned above, then RD7 may be the first reading voltage, and RD7 is between the upper limit E12 of the threshold voltage of the memory cell with programming state L6 and the lower limit E13 of the threshold voltage of the memory cell with programming state L7. Referring to the above Figure 7 In the sensing process of the sensing latch circuit in the reading operation shown, when RD7 is applied to the corresponding word line for reading, for the memory cells in the programming state L0 to L5, the data sensed by the second sensing latch circuit 504 controls the first switch unit 706 to be turned off, disconnecting the connection between the first sensing unit 7024 and the first latch unit 7022, and the DC current generated by the large difference between RD7 and the threshold voltage of the memory cells in the programming state L0 to L5 will not be transmitted to the first sensing latch circuit 502, and the first sensing latch circuit 502 outputs data 0. For the memory cells in the programming state L6 and L7, the data sensed by the second sensing latch circuit 504 controls the first switch unit 706 to be turned on, and the data stored in the memory cells sensed by the first sensing latch circuit 502 is 0 (L6) or 1 (L7).

[0089] Figure 8B Another exemplary implementation of applying the page buffer circuit provided by the embodiment of the present disclosure to TLC reading is schematically shown. Figure 8B , the memory cells with programming states L0 to L3 may be, for example, the first memory cells mentioned above, the memory cells with programming states L4 to L7 may be, for example, the second memory cells mentioned above, wherein the memory cells with programming state L4 may be the third memory cells mentioned above, and the memory cells with programming states L5 to L7 may be the fourth memory cells mentioned above, then RD5 may be the first reading voltage, and RD5 is between the upper limit E8 of the threshold voltage of the memory cells with programming state L4 and the lower limit E9 of the threshold voltage of the memory cells with programming state L5. Referring to the above Figure 7In the sensing process of the sensing latch circuit in the reading operation shown, when RD5 is applied to the corresponding word line for reading, for the memory cells in the programming state L0 to L3, the data sensed by the second sensing latch circuit 504 controls the first switch unit 706 to be turned off, disconnecting the connection between the first sensing unit 7024 and the first latch unit 7022, and the DC current generated by the large difference between RD5 and the threshold voltage of the memory cells in the programming state L0 to L3 will not be transmitted to the first sensing latch circuit 502, and the first sensing latch circuit 502 outputs data 0. For the memory cells in the programming state L4 to L7, the data sensed by the second sensing latch circuit 504 controls the first switch unit 706 to be turned on, and the data stored in the memory cells sensed by the first sensing latch circuit 502 is 0 (L4) or 1 (L5 to L7).

[0090] Fig. 9 A schematic block diagram of a sensing latch circuit in another page buffer circuit is shown according to an embodiment of the present disclosure. Fig. 9 exist Figure 7 Based on the invention, it also includes a second switch unit for configuring whether to use the data sensed by the second sensing latch circuit to control the on-off between the first sensing unit and the first latch unit. Fig. 9 As shown, the page buffer circuit may further include a second switch unit 902 connected in parallel with the first switch unit 706, and configured to control the first signal com to open or disconnect the connection between the first sensing unit 7024 and the first latch unit 7022. Figure 7 As shown, the first end of the second switch unit 902 (for example, it can be a control end) can input the first signal com, the second end of the second switch unit 902 is coupled to the first end of the first sensing unit 7024, and the third end of the second switch unit 902 is coupled to the input end Ai of the first latch unit 7022.

[0091] In the case where the input first signal com controls the disconnection between the first sensing unit 7024 and the first latch unit 7022, the on-off between the first sensing unit 7024 and the first latch unit 7022 can be controlled by the data sensed by the second sensing latch circuit 504 via the first switch unit 706 during the sensing process; in the case where the input first signal com controls the opening of the connection between the first sensing unit 7024 and the first latch unit 7022, the on-off between the first sensing unit 7024 and the first latch unit 7022 is not controlled by the data sensed by the second sensing latch circuit 504 during the sensing process, that is, all storage cells in the programmed state have data sensed by the first sensing unit 7024 in the first sensing latch circuit 502.

[0092] According to the memory provided by the embodiment of the present disclosure, by setting a first switch unit coupled between the first sensing latch circuit and the second sensing latch circuit and a second switch unit connected in parallel with the first switch unit in the page buffer circuit, the first switch unit is configured to be controlled by the data sensed by the second sensing latch circuit to turn on or off the connection between the first sensing unit and the first latch unit of the first sensing latch circuit, and the second switch unit is configured to be controlled by the second signal to turn on or off the connection between the first sensing unit and the first latch unit of the first sensing latch circuit, so that the sensing process can select whether the data sensed by the second sensing latch circuit controls the connection and disconnection between the first sensing unit and the first latch unit, thereby making the memory operation mode more flexible.

[0093] Fig. 10A According to an embodiment of the present disclosure, a circuit diagram of a sensing latch circuit in a page buffer circuit is shown. Fig. 10A Shows Fig. 9 An example of a circuit implementation of Fig. 9 ,like Fig. 10A As shown, the first switch unit 706 may include a first transistor M1, the first sensing unit 7024 may include a second transistor M2, the second sensing unit 7044 may include a third transistor M3, the first latch unit 7022 may include a latch A 1002, and the second latch unit 7042 may include a latch B 1004. The page buffer circuit may further include a voltage control circuit 1006, which may be configured to precharge the sensing node SO.

[0094] like Fig. 10A As shown, the first terminal (for example, it can be a source) of the first transistor M1 is coupled to the first terminal (for example, it can be a drain) of the second transistor M2, the second terminal (for example, it can be a drain) of the first transistor M1 is coupled to the input terminal of the latch A 1002, and the control terminal of the first transistor M1 is coupled to the input terminal Bi of the latch B 1004 (i.e., the input terminal of the second sensing latch circuit 504) to receive the signal d_B. The second terminal (for example, it can be a source) of the second transistor M2 is coupled to the ground voltage source GND1, and the control terminal of the second transistor M2 is coupled to the sensing node SO. The first terminal (for example, it can be a source) of the third transistor M3 is coupled to the ground voltage source GND2, the second terminal (for example, it can be a drain) of the third transistor M3 is coupled to the input terminal Bi of the latch B 1004, and the control terminal of the third transistor M3 is coupled to the sensing node SO.

[0095] In some embodiments, reference Fig. 9 and Fig. 10AThe second sensing latch circuit 504 may further include a first data reset switch unit and a first data input switch unit. The first data reset switch unit may include a fourth transistor M4. The control terminal of the fourth transistor M4 inputs a signal rst_B. The first terminal (for example, a source) of the fourth transistor M4 is coupled to the second terminal of the third transistor M2. The second terminal (for example, a drain) of the fourth transistor M4 is coupled to the input terminal Bi of the latch B1004. The first data input switch unit may include a fifth transistor M5. The control terminal of the fifth transistor M5 inputs a signal set_B. The first terminal (for example, a source) of the fifth transistor M5 is coupled to the second terminal of the third transistor M3. The second terminal (for example, a drain) of the fifth transistor M5 is coupled to the output terminal Bo of the latch B1004.

[0096] In some embodiments, reference Fig. 9 and Fig. 10A , the first sensing latch circuit 502 may further include a second data input switch unit and a second data reset switch unit. The second data input switch unit may include a sixth transistor M6, the control terminal of the sixth transistor M6 inputs a signal set_A, the first terminal (for example, a source) of the sixth transistor M6 is coupled to the second terminal of the first transistor M1, and the second terminal (for example, a drain) of the sixth transistor M6 is coupled to the input terminal Ai of the latch A1002. The second data reset switch unit may include an eighth transistor M8, the control terminal of the eighth transistor M8 inputs a signal rst_A, the first terminal (for example, a source) of the eighth transistor M8 is coupled to the second terminal of the first transistor M1, and the second terminal (for example, a drain) of the eighth transistor M8 is coupled to the output terminal Ao of the latch A1002.

[0097] In some embodiments, reference Fig. 9 and Fig. 10A The second switch unit 902 may include a seventh transistor M7, a first terminal (for example, a source) of the seventh transistor M7 is coupled to the first terminal of the first transistor M1, a second terminal (for example, a drain) of the seventh transistor M7 is coupled to the second terminal of the first transistor M1, and a control terminal of the seventh transistor M7 inputs the first signal com.

[0098] In some other embodiments, the fourth transistor M4 and the fifth transistor M5 may be connected at interchangeable positions. In this case, the control terminal of the first transistor M1 is coupled to the output terminal of the second sensing latch circuit 504 . Fig. 10B A circuit diagram of a sensing latch circuit in another page buffer circuit is shown according to an embodiment of the present disclosure. Fig. 10B and Fig. 10AThe only difference is the connection of the fourth transistor M4 and the fifth transistor M5 and the connection of the control terminal of the first transistor M1. Fig. 10B In the embodiment, the control terminal of the first transistor M1 is coupled to the output terminal Bo of the latch B 1004 to receive the signal d_B', the second terminal (for example, the drain) of the fourth transistor M4 is coupled to the output terminal Bo of the latch B1004, and the second terminal (for example, the drain) of the fifth transistor M5 is coupled to the input terminal Bi of the latch B 1004.

[0099] Fig. 10A and Fig. 10B The transistor shown in the figure may be, for example, an NMOS transistor or a PMOS transistor, etc. Fig. 10A and Fig. 10B In the description, an example is given in which all transistors are NMOS transistors, but the invention is not limited thereto.

[0100] According to the memory provided by the embodiment of the present disclosure, by only adding two transistors, the first transistor and the seventh transistor (for example, two NMOS tubes), in each page buffer circuit, that is, by slightly increasing the thickness of each layer of the page buffer circuit, it is possible to avoid the DC current generated by the large gap between the read voltage and the threshold voltage of the storage unit from being transmitted to the first sensing latch circuit while ensuring that the data output by the first sensing latch circuit is correct, thereby reducing the metal wiring processing cost, reducing the power bounce noise, and thus reducing the sensing bounce noise.

[0101] Figures 11 to 13 An example of a reading process of a memory including a page buffer circuit provided by an embodiment of the present disclosure is shown. Figures 11 to 13 In the description, the target storage unit to be read is taken as the first storage unit as an example, but the present invention is not limited thereto.

[0102] Fig.11 FIG. 1 is a flow chart of a memory operation method according to an exemplary embodiment. Fig.11 The method shown can be applied to, for example, Fig. 9 Or the memory of the page buffer circuit in Figure 10.

[0103] refer to Fig.11 , the method 110 provided in the embodiment of the present disclosure may include the following steps S1102 to S1106.

[0104] In step S1102 , in a sensing phase, a first read voltage is applied to a first word line.

[0105] Fig. 8A and Figure 8B An exemplary implementation of a first read voltage is shown.

[0106] In some embodiments, a corresponding bit line voltage may be applied to a bit line coupled to the memory string where the first memory cell is located during the sensing phase.

[0107] In step S1104 , during the sensing phase, the second switch unit is controlled to be turned off.

[0108] In some embodiments, the second switch unit may be turned off by inputting a low level signal to the control terminal thereof during the sensing phase.

[0109] In some other embodiments, the second switch unit may be controlled to be turned off in the pre-charging phase before the sensing phase, and the second switch unit may be kept turned off in the sensing phase.

[0110] In step S1106 , in the sensing phase, the first data input switch unit is controlled to be turned on.

[0111] In some embodiments, the first data input switch unit can be controlled to be turned on during a sensing phase before a data storage phase, and the data of the first storage unit can be sensed using a second sensing latch circuit to control the opening or disconnection of the first sensing latch circuit and the connection between the first sensing unit and the first latch unit during the data storage phase.

[0112] According to the memory operation method provided by the embodiment of the present disclosure, a first read voltage greater than the threshold voltage of the first memory cell is applied to the first word line coupled to the first memory cell in the sensing stage, and the second switch unit connected in parallel with the first switch unit is controlled to be turned off, thereby controlling the first data input switch unit to be turned on in the sensing stage before the data storage stage, and using the second sensing latch circuit to sense the data of the first memory cell, so as to control the opening or disconnection of the connection between the first sensing unit and the first latch unit of the first sensing latch circuit in the data storage stage, so as to ensure that the data output by the first sensing latch circuit is correct, and avoid the DC current generated by the large gap between the read voltage and the threshold voltage of the memory cell from being transmitted to the first sensing latch circuit.

[0113] Fig.12 FIG. 1 is a flow chart showing another memory operation method according to an exemplary embodiment. Fig.12 The method shown can be applied to a memory including the page buffer circuit in FIG. 10 , for example.

[0114] refer to Fig.12 The method 120 provided in the embodiment of the present disclosure may include the following steps S1202 and S1204, for example, Fig.11 Executed before.

[0115] In step S1202 , in a pre-charging phase before a sensing phase, a first data reset switch unit is controlled to be turned on.

[0116] In some embodiments, a high level signal may be input to the control terminal of the first data reset switch unit to turn it on during the pre-charging phase, so as to reset the input terminal of the second sensing latch circuit to data “0”.

[0117] In step S1204 , in the pre-charging stage, the second data reset switch unit is controlled to be turned on.

[0118] In some embodiments, a high level signal may be input to the control terminal of the second data reset switch unit to turn it on during the pre-charging phase, so as to reset the output terminal of the first sensing latch circuit to data “0”.

[0119] According to the memory operation method provided by the embodiment of the present disclosure, by controlling the first data reset switch unit to be turned on in the pre-charging stage before the sensing stage, the input end of the second sensing latch circuit is reset to data "0", so that no matter whether the data sensed by the second sensing latch circuit controls the connection between the first sensing unit and the first latch unit of the first sensing latch circuit to be turned on or off, the data output by the first sensing latch circuit can be guaranteed to be correct.

[0120] Fig.13 FIG. 1 is a flow chart of another memory operation method according to an exemplary embodiment. Fig.13 The method shown can be applied to a memory including the page buffer circuit in FIG. 10 described above, for example.

[0121] refer to Fig.13 , the method 130 provided in the embodiment of the present disclosure may include the following steps S1302 to S1306.

[0122] In step S1302 , in a sensing phase, a first read voltage is applied to a first word line.

[0123] In step S1304, in the sensing phase, the first data input switch unit is controlled to be turned on.

[0124] The implementation of step S1302 and step S1304 can refer to Fig.11 Steps S1102 and S1106 in .

[0125] In step S1306 , in the data storage phase after the sensing phase, the second data input switch unit is controlled to be turned on.

[0126] In some embodiments, the data of the first storage unit can be sensed by using the first sensing latch circuit by controlling the second data input switch unit to be turned on during the data storage phase.

[0127] According to the memory operation method provided by the embodiment of the present disclosure, a first read voltage greater than the threshold voltage of the first memory cell is applied to the first word line coupled to the first memory cell in the sensing stage, and the second switch unit connected in parallel with the first switch unit is controlled to be turned off, thereby controlling the first data input switch unit to be turned on in the sensing stage before the data storage stage, and using the second sensing latch circuit to sense the data of the first memory cell, so as to control the opening or disconnection of the connection between the first sensing unit and the first latch unit of the first sensing latch circuit in the data storage stage, so that when the first sensing latch circuit senses the data of the first memory cell, the current in the first memory cell will not be transmitted to the first sensing latch circuit, thereby avoiding the DC current generated by the large gap between the read voltage and the threshold voltage of the memory cell from being transmitted to the first sensing latch circuit.

[0128] Fig.14 according to Figures 11 to 13 A signal waveform diagram of a memory operation method is shown. Fig.14 by Fig. 10A Taking the circuit diagram shown in as an example, the pre-charging stage t1, the sensing stage t2, the data storage stage t3 in the reading process, the voltage changes of the control terminal signals of M8, M6, M4, and M5, the sensing node SO, the selected WL, and the selected BL are described. Fig.14 The case in which the gate input signal com of the transistor M7 is a low level signal or the transistor M7 is not included.

[0129] Reference Fig. 10A and Fig.14 During the precharge phase t1, the SO node voltage Vso is precharged to a high level (for example, by a voltage control circuit), a first read voltage Vrd (for example, the above-mentioned RD7, RD5, or other read voltages) is applied to the selected WL coupled to the gate of the target memory cell (for example, the first memory cell, the second memory cell, the third memory cell, and the fourth memory cell), and a bit line voltage Vbl is applied to the selected BL coupled to the memory string where the target memory cell is located. In addition, by raising the gate of the transistor M8 to send a signal rst_A (for example, vdd) to turn it on, the latch A 1002 is reset, and the output signal of its output terminal Ao is set to 0; and by raising the gate of the transistor M4 to send a signal rst_B (for example, vdd) to turn it on, the latch B 1004 is reset, and the output signal d_B of its input terminal Bi is set to 0.

[0130] In the sensing phase t2, the voltage on the sensing node SO starts to drop. In the latter part of the sensing phase t2 (e.g., the latter 50%, the latter 40%, the latter 30%, etc.), the gate of the transistor M5 is raised to send a signal set_B (e.g., vdd) to turn it on, so as to sense the voltage on the current SO node through the transistor M3. In the case where the target memory cell is the first memory cell, the voltage drop waveform on the sensing node SO can be Fig.14 In 1402, that is, when the transistor M5 is turned on, the gate input voltage Vso of the transistor M3 is less than the flip voltage Vtrip, the transistor M3 is turned off, the input terminal Bi signal d_B of the latch B 1004 remains at a low level, and the transistor M1 is turned off; when the target memory cell is the third memory cell, the voltage drop waveform on the sensing node SO can be Fig.14 In 1404, that is, when the transistor M5 is turned on, the gate input voltage Vso of the transistor M3 is greater than the flip voltage Vtrip, the transistor M3 is turned on, the output terminal Bo signal of the latch B1004 is low level, the input terminal Bi signal d_B is high level, and the transistor M1 is turned on; when the target memory cell is the fourth memory cell, the voltage drop waveform on the sensing node SO can be Fig.14 1406 (the decrease is small), that is, when the transistor M5 is turned on, the gate input voltage Vso of the transistor M3 is greater than the flip voltage Vtrip, the transistor M3 is turned on, the output terminal Bo signal of the latch B 1004 is low level, the input terminal Bi signal d_B is high level, and the transistor M1 is turned on.

[0131] During the data storage phase t3, a signal set_A (for example, vdd) is sent by raising the gate of transistor M6 to turn it on. When the target memory cell is the first memory cell, transistor M1 is turned off, the output terminal Ao of latch A 1002 is still at a low level, and latch A 1002 latches data "0"; when the target memory cell is the third memory cell, transistor M1 is turned on, and the voltage Vso on the sensing node SO drops to less than the flip voltage Vtrip, transistor M2 remains turned off, the output terminal Ao of latch A 1002 is still at a low level, and latch A 1002 latches data "0"; when the target memory cell is the fourth memory cell, transistor M1 is turned on, and the voltage Vso on the sensing node SO is still higher than the flip voltage Vtrip, transistor M2 is turned on, the input terminal Ai of latch A 1002 flips to a low level, the output terminal Ao of latch A 1002 flips to a high level, and latch A 1002 latches data "1".

[0132] The exemplary embodiments of the present disclosure are specifically shown and described above. It should be understood that the present disclosure is not limited to the detailed structures, configurations or implementations described herein; on the contrary, the present disclosure is intended to cover various modifications and equivalent configurations included in the spirit and scope of the appended claims.

Claims

1. A memory, characterized in that: include: A memory cell array; A plurality of bit lines, the plurality of bit lines are respectively coupled to different storage strings in the memory cell array; A peripheral circuit, the peripheral circuit comprising a page buffer circuit, the page buffer circuit is coupled to the memory string through the bit line, wherein the page buffer circuit comprises: A first sensing latch circuit comprises a first sensing unit and a first latch unit coupled to each other, wherein the first sensing unit is configured to sense data of the storage string, and the first latch unit is configured to latch the data sensed by the first sensing unit; A second sensing latch circuit is configured to control the first switch unit to be turned on or off according to the data sensed by the second sensing latch circuit; The first switch unit is configured to control opening or disconnecting the connection between the first sensing unit and the first latch unit according to the data sensed by the second sensing latch circuit.

2. The memory according to claim 1, characterized in that: The memory cell array includes a first memory cell in a first programming state and a second memory cell in a second programming state, a threshold voltage of the first memory cell is lower than a threshold voltage of the second memory cell, and the first memory cell is coupled to a first word line; The first switch unit is further configured to be turned off by sensing data of the first memory cell by the second sense latch circuit when a first read voltage is applied to the first word line, and the first read voltage is greater than a threshold voltage of the first memory cell.

3. The memory according to claim 2, characterized in that: The second memory cell is coupled to a second word line, and the first switch unit is further configured to be turned on by sensing data of the second memory cell by the second sense latch circuit when the first read voltage is applied to the second word line.

4. The memory according to claim 2 or 3, characterized in that: The first sensing latch circuit further includes a first node disposed at a first end of the first latch unit, and the first node is used to output data sensed by the first sensing unit to the first storage unit.

5. The memory according to any one of claims 1 to 3, characterized in that: The first switch unit includes a first transistor, and the first sensing unit includes a second transistor, wherein: The first terminal of the first transistor is coupled to the first terminal of the second transistor, the second terminal of the first transistor is coupled to the input terminal of the first latch unit, and the control terminal of the first transistor is coupled to the input terminal of the second sensing latch circuit; A second terminal of the second transistor is coupled to a ground voltage source, and a control terminal of the second transistor is coupled to a sensing node.

6. The memory according to claim 5, characterized in that: The second sensing latch circuit comprises a second sensing unit and a second latch unit coupled to each other, and the second sensing unit comprises a third transistor, wherein: A first terminal of the third transistor is coupled to a ground voltage source, a second terminal of the third transistor is coupled to an input terminal of the second latch unit, and a control terminal of the third transistor is coupled to the sensing node; A control terminal of the first transistor is coupled to an input terminal of the second latch unit.

7. The memory according to claim 6, characterized in that: The second sensing latch circuit further includes a first data reset switch unit including a fourth transistor, a first terminal of the fourth transistor being coupled to a second terminal of the third transistor, and a second terminal of the fourth transistor being coupled to an input end of the second latch unit.

8. The memory according to claim 6 or 7, characterized in that: The second sensing latch circuit also includes a first data input switch unit, which includes a fifth transistor, a first terminal of the fifth transistor is coupled to the second terminal of the third transistor, and a second terminal of the fifth transistor is coupled to the output end of the second latch unit.

9. The memory according to any one of claims 5 to 7, characterized in that: The first sensing latch circuit also includes a second data input switch unit, the second data input switch unit includes a sixth transistor, a first terminal of the sixth transistor is coupled to the second terminal of the first transistor, and the second terminal of the sixth transistor is coupled to the input end of the first latch unit.

10. The memory according to any one of claims 4 to 7, characterized in that: The page buffer circuit further includes a second switch unit connected in parallel with the first switch unit and configured to disconnect the first sensing unit and the first latch unit under the control of a first signal.

11. The memory according to claim 10, characterized in that: The second switch unit includes a seventh transistor, a first terminal of the seventh transistor is coupled to the first terminal of the first transistor, a second terminal of the seventh transistor is coupled to the second terminal of the first transistor, and a control terminal of the seventh transistor inputs the first signal.

12. A memory operation method, characterized in that: The page buffer circuit of the memory includes a first sensing latch circuit, a second sensing latch circuit and a first switch unit, the first sensing latch circuit includes a first sensing unit and a first latch unit, the first switch unit is coupled between the first sensing unit and the first latch unit, an input end of the second sensing latch circuit is coupled to a control end of the first switch unit, the second sensing latch circuit includes a first data input switch unit, and the method includes: In the sensing phase, the first data input switch unit is controlled to be turned on.

13. The method according to claim 12, characterized in that The memory includes a first memory cell in a first programming state and a second memory cell in a second programming state, a threshold voltage of the first memory cell is lower than a threshold voltage of the second memory cell, and the first memory cell is coupled to a first word line; The first switch unit is configured to be turned off by the data inputted into the second sensing latch circuit by the first storage unit when a first reading voltage is applied to the first word line during the sensing phase, and the first reading voltage is greater than a threshold voltage of the first storage unit; The method further comprises: During the sensing phase, the first read voltage is applied to the first word line.

14. The method according to claim 12 or 13, characterized in that The first sensing latch circuit further includes a second data input switch unit; The method further comprises: In a data storage phase after the sensing phase, the second data input switch unit is controlled to be turned on.

15. The method according to claim 14, characterized in that The second sensing latch circuit further includes a first data reset switch unit; The method further comprises: In a precharge phase before the sensing phase, the first data reset switch unit is controlled to be turned on.

16. The method according to claim 15, characterized in that The first sensing latch circuit further includes a second data reset switch unit; The method further comprises: In the pre-charging stage, the second data reset switch unit is controlled to be turned on.

17. The method according to claim 13, characterized in that The second programming state includes a third programming state and a fourth programming state, the second storage cell includes a third storage cell in the third programming state and a fourth storage cell in the fourth programming state, and a threshold voltage of the third storage cell is lower than a threshold voltage of the fourth storage cell; The first read voltage is greater than a threshold voltage of the third memory cell and less than a threshold voltage of the fourth memory cell.

18. The method according to any one of claims 12 to 17, characterized in that The page buffer circuit further includes a second switch unit connected in parallel with the first switch unit; The method further comprises: During the sensing phase, the second switch unit is controlled to be turned off.

19. A storage system, characterized in that: The invention comprises the memory as claimed in any one of claims 1 to 11 and a controller coupled to the memory.

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