Memory device and operating method of memory device

Abstract

The invention discloses a memory device and an operating method of the memory device. The memory device includes a memory cell array, control logic to control a read operation to read hard decision data and soft decision data from each page, and a page buffer including a first latch related to sensing of the hard decision data and a second latch related to sensing of the soft decision data. The control logic controls execution of a first sensing operation in which a value determined based on a first offset level is stored in a second latch at a first sensing timing, and a second sensing operation in which a value determined based on a second offset level is stored in the second latch at a second sensing timing, and perform a control operation to provide the setting signal SET to the second latch in the first sensing operation, and to provide the reset signal RST to the second latch in the second sensing operation.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the priority of Korean Patent Application No. 10-2023-0105135 filed on August 10, 2023, and Korean Patent Application No. 10-2023-0137038 filed on October 13, 2023, in the Korean Intellectual Property Office, the disclosures of which are incorporated herein by reference in their entirety. Technical Field

[0003] The present disclosure relates to a memory device and a method of operating the memory device. Background Art

[0004] A nonvolatile memory device includes a plurality of memory cells that store data nonvolatilely. As an example of a nonvolatile memory device, a flash memory device can be used in mobile phones, digital cameras, portable digital assistants (PDAs), portable computer devices, fixed computer devices, and various other types of devices.

[0005] The memory device may write or read data in various ways. As an example, in response to a read request from a memory controller, the memory device may generate hard decision data and soft decision data and output the hard decision data and the soft decision data. The hard decision data may be data read using a normal read level having a specific voltage level, and the soft decision data may be data read using an offset level having a specific offset compared to the normal read level. The memory controller may perform soft decision error correction to correct data errors by using the hard decision data and the soft decision data from the memory device together.

[0006] To generate soft decision data, multiple latches are used to sense data based on different offset levels, and operations are performed on values ​​determined based on the different offset levels. The time and resources used to generate soft decision data may be high. Summary of the invention

[0007] Some aspects of the present disclosure provide a memory device (and a corresponding operating method) that can reduce resources required to generate soft decision data while improving data read speed in a system using hard decision data and soft decision data.

[0008] According to some embodiments of the present disclosure, a memory device is provided. The memory device includes: a memory cell array including a plurality of pages, each of which includes a plurality of memory cells; a control logic that controls a read operation to read hard decision data based on a normal read level and soft decision data based on a first offset level and a second offset level from each page; and a page buffer including buffer units corresponding to the plurality of memory cells of the page, each buffer unit including a first latch related to sensing of hard decision data and a second latch related to sensing of soft decision data. The control logic controls to perform a first sensing operation in which a value determined based on a first offset level is stored in a second latch at a first sensing timing and a second sensing operation in which a value determined based on a second offset level is stored in a second latch at a second sensing timing during a sensing duration of the page, and performs a control operation to provide any one of a set signal (SET) and a reset signal (RST) to the second latch in the first sensing operation, and to provide the other of the set signal (SET) and the reset signal (RST) to the second latch in the second sensing operation.

[0009] According to some embodiments of the present disclosure, a method for operating a memory device is provided, wherein the memory device includes a page buffer, the page buffer includes buffer units corresponding to a plurality of memory cells, and each buffer unit includes a first latch related to sensing of hard decision data based on a normal read level and a second latch related to sensing of soft decision data based on a first offset level and a second offset level, the method including: initializing the second latch to a first value; changing the value of the second latch to a second value in response to any one of a set signal (SET) and a reset signal (RST) at a first sensing timing of a sensing duration for any one page, the second latch being connected to a memory cell corresponding to a turn-off cell based on the first offset level; and changing the value of the second latch to the first value in response to the other of the set signal (SET) and the reset signal (RST) at a second sensing timing of the sensing duration, the second latch being connected to a memory cell corresponding to a turn-off cell based on a second offset level, and after performing a second sensing operation, outputting soft decision data having a logic state corresponding to a value stored in the second latch or an inverted value of the value stored in the second latch.

[0010] According to some embodiments of the present disclosure, a method for operating a memory device is provided, wherein the memory device includes a page buffer, the page buffer includes buffer units corresponding to a plurality of memory cells, and each buffer unit includes a first latch related to sensing of hard decision data based on a normal read level and a second latch related to sensing of soft decision data based on a first offset level and a second offset level, the method comprising: in response to a first read command for a first page of the memory device, performing a first precharge on a sense node of the buffer unit; during a first sensing duration after the first precharge, storing a value determined based on the normal read level in the first latch; and in a second precharge, storing a value determined based on the normal read level in the first latch; After a sensing duration ends, a second precharge is performed on the sensing node of the buffer unit; in response to any one of a set signal (SET) and a reset signal (RST), a sensing result corresponding to the first value is stored in a second latch in a first sensing timing of a second sensing duration after the second precharge, and the second latch is connected to a memory unit corresponding to the shutdown unit based on the first offset level; and in response to the other of the set signal (SET) and the reset signal (RST) at a second sensing timing of the second sensing duration, a sensing result corresponding to the second value is stored in the second latch, and the second latch is connected to the memory unit corresponding to the shutdown unit based on the second offset level. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Embodiments will be understood from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0012] Figure 1 is a block diagram illustrating a memory system according to some embodiments of the present disclosure.

[0013] Figure 2 is a diagram illustrating an example of generating hard decision data and soft decision data.

[0014] Figure 3 is a block diagram illustrating an example of a memory device according to some embodiments of the present disclosure.

[0015] Figure 4 It is shown Figure 3 A diagram of an example of a buffer unit of a page buffer.

[0016] Figure 5 It is shown Figure 4 A circuit diagram of an example of any one of the latches shown in .

[0017] Fig. 6A and Figure 6B is a diagram illustrating an example of the operation of a buffer unit related to soft decision data.

[0018] Figure 7is a flowchart illustrating an operating method of a memory device according to some embodiments of the present disclosure.

[0019] Figures 8 to 10A , Fig. 10B , Fig. 10C and Fig. 10D is a diagram illustrating an example of the operation of a page buffer according to some embodiments of the present disclosure.

[0020] Fig.11A and Fig. 11B as well as Fig. 12A and Fig. 12B is a diagram illustrating an example of reading soft decision data according to some embodiments of the present disclosure.

[0021] Fig.13 is a perspective view showing a memory block according to some embodiments of the present disclosure.

[0022] Fig.14 is a block diagram illustrating an example of applying a memory device to a solid state drive (SSD) system according to some embodiments of the present disclosure. DETAILED DESCRIPTION

[0023] Hereinafter, embodiments according to the present disclosure will be described in detail with reference to the accompanying drawings.

[0024] Figure 1 is a block diagram illustrating a memory system 10 according to some embodiments.

[0025] Reference Figure 1 , the memory system 10 may include a memory controller 100 and a memory device 200. The memory controller 100 may include a command generator 110 and an error correction code (ECC) circuit 120. The memory device 200 may include a memory cell array 210, a page buffer 220, and a control logic 230. The memory controller 100 may provide a command (CMD), an address (ADD), and a control signal (CTRL) to the memory device 200, and the memory controller 100 may communicate data (DATA) with the memory device 200.

[0026] The memory system 10 can communicate with the host (HOST) through various interfaces. As some examples, the memory system 10 can communicate with the HOST through interfaces such as universal serial bus (USB), multimedia card (MMC), embedded MMC (eMMC), peripheral component interconnect (PCI), PCI Express (PCI-E), advanced technology attachment (ATA), serial ATA, parallel ATA, small computer interface (SCSI), enhanced small disk interface (ESDI), integrated drive electronics (IDE), FireWire, universal flash storage (UFS), non-volatile memory express (NVMe), etc.

[0027] The memory device 200 may include a non-volatile memory device such as a flash memory. In some embodiments, the memory system 10 is implemented by a memory embedded in an electronic device or attachable to / detachable from an electronic device. For example, the memory system 10 may be implemented in various forms such as an embedded universal flash storage (UFS) memory device, an embedded multimedia card (eMMC), a solid-state drive (SSD), a UFS memory card, a compact flash (CF), a secure digital (SD), a micro secure digital (micro SD), a mini secure digital (mini SD), an extreme digital (xD), a memory stick, etc. In addition, the memory system 10 may also be referred to as a storage device because the memory system 10 stores data non-volatilely.

[0028] In response to a write / read request from the HOST, the memory controller 100 may control the memory device 200 to read data stored in the memory device 200 or write (or program) data to the memory device 200. As an example, the memory controller 100 may have a processor (not shown), and the processor may control the overall operation within the memory controller 100 and may also control memory operations for the memory device 200.

[0029] The memory cell array 210 may include a plurality of pages, and each page may include a plurality of memory cells corresponding to the cells to be programmed and read. For example, each page may include a flash memory cell. The following will describe the embodiments by way of an example in which the memory cells are NAND flash memory cells. However, the scope of the present disclosure is not limited to NAND flash memory cells, and in some embodiments, the plurality of memory cells may be resistive memory cells, such as resistive RAM (ReRAM), phase change RAM (PRAM), or magnetic RAM (MRAM).

[0030] In some embodiments, the memory cell array 210 may include a three-dimensional memory cell array, and the three-dimensional memory cell array may include a plurality of NAND strings, and each NAND string may include memory cells respectively connected to word lines stacked vertically on a substrate. However, the scope of the present disclosure is not limited thereto, and in some embodiments, the memory cell array 210 may include a two-dimensional memory cell array, and the two-dimensional memory cell array may include a plurality of NAND strings arranged along row directions and column directions.

[0031] Based on the read command provided from the memory controller 100 to the memory device 200, a read operation may be performed under the control of the control logic 230. The page buffer 220 may store data read from the memory device 200 in units of pages, and may include a plurality of buffer units arranged to correspond to the memory cells. Each of the buffer units may include one or more latches. As an example, each buffer unit may include a cache latch for transmitting data with an external controller, a sense latch for sensing data according to a voltage of a sense node, and one or more data latches for storing data.

[0032] As an operation example, when reading page data, hard decision data HD and soft decision data SD may be read from each memory cell. The hard decision data may correspond to data determined based on a normal read level corresponding to a normal read operation, and the soft decision data may correspond to data determined based on an offset level having a specific offset compared to the normal read level. As an example, the offset level may include a first offset level having a negative (-) offset and a second offset level having a positive (+) offset compared to the normal read level, and the soft decision data may be generated based on a combination of values ​​determined based on the first offset level and the second offset level. The memory controller 100 may receive the hard decision data and the soft decision data, and perform an ECC decoding process by using the received hard decision data and the soft decision data. As an example, the ECC circuit 120 may perform an error correction operation such as a low-density parity check (LDPC).

[0033] The above-mentioned hard decision data and soft decision data may be provided to the memory controller 100 according to various strategies. As an example, when an error occurs in normal data (e.g., hard decision data) read from the memory device 200, the memory device 200 may generate soft decision data under the control of the memory controller 100. In some embodiments, regardless of the result of normal data error detection, the memory device 200 may also generate hard decision data and soft decision data under the control of the memory controller 100, and provide the generated hard decision data and soft decision data to the memory controller 100.

[0034] In addition, regarding the command for generating soft decision data, the command generator 110 may generate a read command (e.g., a first read command) requesting the provision of normal data, and may also further generate a command (e.g., a second read command) defined separately from the first read command. In response to the first read command from the command generator 110, the memory device 200 may generate hard decision data and output the hard decision data to the memory controller 100. Conversely, in response to the second read command from the command generator 110, the memory device 200 may generate hard decision data and soft decision data together, and output the generated hard decision data and soft decision data to the memory controller 100.

[0035] As described above, hard decision data and soft decision data may be generated and output according to various strategies. In the following embodiments, it will be described that, regardless of the result of error detection of normal data, the memory device 200 generates hard decision data and soft decision data together in response to a read command from the memory controller 100, and provides the generated hard decision data and soft decision data to the memory controller 100.

[0036] Specific operation examples according to some embodiments will be described as follows.

[0037] In order to improve the reading speed of soft decision data and reduce resource consumption, a latch can be used to perform a sensing operation based on multiple offset levels according to some embodiments. In addition, the reading operation may include a precharge duration for precharging the voltage of the sensing node, a development duration for developing the voltage of the sensing node, and a sensing duration for determining the value of the data according to the voltage of the sensing node. Sensing operations based on multiple offset levels can be performed during the same sensing duration (for example, without performing precharging between sensing operations). As an example, after performing a sensing operation based on any one offset level, without performing a precharge operation on the sensing node again, multiple sensing operations can be performed at different sensing timings of the same sensing duration, and soft decision data can be generated based on the value determined by the sensing operation.

[0038] In some embodiments, the control logic 230 may include a sensing controller 231. The sensing controller 231 may perform various control operations for generating hard decision data and soft decision data. As an example, the sensing controller 231 may control the control operation to perform a sensing operation based on multiple offset levels by using one latch, and generate soft decision data according to the result of the sensing operation, for example, as described above.

[0039] In addition, as described below, according to some embodiments, soft decision data can be generated based on various sensing methods. The control logic 230 may also include a sensing mode setter 232. The sensing mode setter 232 may select any of the various sensing methods by which soft decision data can be generated, and may set the selected method as a sensing mode. However, some embodiments may perform a sensing operation for generating soft decision data according to a preset method without including the sensing mode setter 232.

[0040] In an embodiment, assuming that the first latch among the plurality of latches included in each buffer unit senses the soft decision data, the first latch may determine the value of the data based on the first offset level at the first sensing timing, and may also determine the value of the data based on the second offset level at the second sensing timing. At this time, regarding the sensing of the data, a set signal SET or a reset signal RST may be provided to the first latch, and the value stored in the first latch from the memory cell having the same threshold voltage according to the signal applied to the first latch may have a complementary level. For example, when the set signal SET is provided to the first latch, a value "1" corresponding to a logic high level may be stored in the first latch from a memory cell having a threshold voltage greater than the first offset level, and when the reset signal RST is provided to the first latch, a value "0" corresponding to a logic low level may be stored in the first latch.

[0041] According to some embodiments, assuming that the set signal SET is provided to the first latch at the first sensing timing, the reset signal RST may be provided to the first latch at the second sensing timing. According to the above process, assuming that the second offset level is greater than the first offset level, a value "0" corresponding to a logic low level may be stored in the first latch from a memory cell having a threshold voltage less than the first offset level and greater than the second offset level. Conversely, a value "1" corresponding to a logic high level may be stored in the first latch from a memory cell having a threshold voltage between the first offset level and the second offset level.

[0042] Therefore, the reading time of the soft decision data can be reduced because the sensing operations based on different offset levels can be performed during the same sensing duration to facilitate the generation of the soft decision data. In addition, the signal provided to the first latch is controlled as described above, so that the sensing operations based on multiple offset levels can be performed by one latch, and the result corresponding to the soft decision data can be generated without performing a separate operation such as an exclusive OR (XOR) operation, so that the resource consumption related to the generation of the soft decision data can be reduced.

[0043] In some embodiments, the soft decision data may be dumped to a cache latch included in each buffer unit and then provided to the memory controller 100. The memory device 200 may include a compressor (not shown). The compressor may perform a compression operation on the soft decision data stored in the cache latch, and the compressed soft decision data may be output to the memory controller 100. The compression operation may be performed by various types of compression algorithms such as lossy compression and lossless compression. When compression is performed, the soft decision data of any one page may be smaller in size than the hard decision data.

[0044] Figure 2 is a diagram illustrating an example of generating hard decision data and soft decision data.

[0045] In response to a read command from a memory controller, the memory device may generate hard decision data and soft decision data together. As an example, the memory device may read the hard decision data by using a word line voltage having a normal read level, and may read the soft decision data by using a word line voltage having a first offset level and a second offset level.

[0046] According to some embodiments, the memory device can read the soft decision data by performing the sensing operation at different sensing timings of any one sensing duration. As an example, when the sensing timing of any one sensing duration is relatively early, the value of the data can be determined based on a relatively low threshold voltage level, and when the sensing timing is relatively late, the value of the data can be determined based on a relatively high threshold voltage level. According to some embodiments, a selection signal (e.g., a set signal SET and a reset signal RST) having complementary levels is provided to the latch at at least two sensing timings, so that the soft decision data can be read using one latch.

[0047] Reference Figure 1 and Figure 2 , the memory device 200 may output data determined based on the normal read level as hard decision data HD, and output data determined based on the offset level as soft decision data SD. The offset level may include a first offset level Offset 1 having a level as small as the first offset compared to the normal read level and a second offset level Offset 2 having a level as large as the second offset compared to the normal read level. The memory device 200 may generate the soft decision data SD based on a value determined using the first offset level Offset 1 and the second offset level Offset 2. The first offset and the second offset may be the same or may be different.

[0048] As an example, the hard decision data HD of a memory cell having a threshold voltage less than a normal read level may have a value of "1", and the hard decision data HD of a memory cell having a threshold voltage greater than the normal read level may have a value of "0". In addition, the soft decision data SD of a memory cell having a threshold voltage less than a first offset level Offset 1 or greater than a second offset level Offset 2 has a value of "0", and the soft decision data SD of a memory cell having a threshold voltage between the first offset level Offset 1 and the second offset level Offset 2 may have a value of "1". The soft decision data SD may include information indicating whether the memory cell has a strong error or a weak error. Various parameters (such as coefficients) for an error correction operation may be calculated based on the hard decision data HD and the soft decision data SD.

[0049] The read operation performed in response to the read command may include multiple durations, and as an example, may include a precharge duration, a development duration, and a sensing duration. During the precharge duration, the sensing node may be precharged with a voltage of a specific level. In addition, during the development duration, the voltage level of the sensing node may change according to the data stored in the memory cell. As an example, there may be a characteristic that the voltage level of the sensing node drops rapidly when data is programmed with a relatively low threshold voltage corresponding to the on-cell with its memory cell, while the voltage level of the sensing node gradually decreases when data is programmed with a relatively high threshold voltage corresponding to the off-cell with its memory cell.

[0050] In some embodiments, Figure 2 As shown in , by performing the sensing operations at different timings of any one sensing duration, hard decision data HD and soft decision data SD may be generated together. As an example, the value of the data may be determined based on the first offset level Offset 1 according to the sensing operation performed at the earliest sensing timing of the sensing duration, and the value of the data may be determined based on the normal read level according to the sensing operation performed at the subsequent sensing timing, and the value of the data may be determined based on the second offset level Offset 2 according to the sensing operation performed at the last sensing timing. In addition, the soft decision data SD may be generated based on the value of the data determined based on the first offset level Offset 1 and the second offset level Offset 2.

[0051] exist Figure 2In the example of , it has been described that the soft decision data SD of the memory cell having a threshold voltage less than the first offset level Offset 1 or greater than the second offset level Offset 2 has a value of "0", but the embodiment does not need to be limited thereto. As an example, the soft decision data SD of the memory cell having a threshold voltage less than the first offset level Offset 1 or greater than the second offset level Offset 2 may be defined as having a value of "1".

[0052] Assuming that the soft decision data SD of the memory cell having a threshold voltage less than the first offset level Offset 1 or greater than the second offset level Offset 2 corresponds to "0", the value "1" may also be stored in the latch according to the sensing result for the memory cell. At this time, by inverting the value "1" and dumping the soft decision data SD to the cache latch, the soft decision data SD having a value of "0" may be output from the cache latch to the memory controller.

[0053] Figure 3 is a block diagram illustrating an example of a memory device according to some embodiments. Figure 3 , the memory device 300 may include a memory cell array 310, a page buffer 320, a control logic 330, a voltage generator 340, a row decoder 350, and an input and output (I / O) buffer 360. In addition, the control logic 330 may include a sensing controller 331, a sensing mode setter 332, a set / reset controller 333, and a compressor 334. The memory device 300 may be Figure 1 A memory device 200 is provided.

[0054] The memory cell array 310 may include a plurality of pages, and the memory cell array 310 may be connected to word lines WL, string selection lines SSL, ground selection lines GSL, and bit lines BL. For example, the memory cell array 310 may be connected to the row decoder 350 through the word lines WL, string selection lines SSL, and ground selection lines GSL, and may be connected to the page buffer 320 through the bit lines BL.

[0055] The page buffer 320 may be connected to the bit line BL and temporarily store write data or temporarily store read data. The page buffer 320 may include a plurality of buffer units corresponding to a plurality of memory cells of a page (e.g., the 1st buffer unit PBU 1 to the kth buffer unit PBU K). Each buffer unit may be connected to the corresponding bit line BL through a sensing node and may include a plurality of latches.

[0056] The control logic 330 may program data to the memory cell array 310 or read data from the memory cell array 310 based on the command CMD, the address ADD, and the control signal CTRL received from the memory controller. Various internal control signals output from the control logic 330 may be provided to the page buffer 320, the voltage generator 340, and the row decoder 350. For example, the control logic 330 may provide the voltage control signal CTRL_vol to the voltage generator 340. With respect to the program / read / erase operation, the voltage generator 340 may provide various levels of word line voltages VWL to the row decoder 350. In addition, the control logic 330 may provide the row address X_ADD to the row decoder 350, and may provide the column address Y_ADD to the page buffer 320. In addition, with respect to the data sensing operation, the control logic 330 may output the sensing control signal Ctrl_S and the set / reset signal SET / RST to the page buffer 320.

[0057] In some embodiments, the control logic 330 may control the read operation by performing a control operation on a plurality of latches included in each buffer unit of the page buffer 320. For example, the sensing controller 331 may control the sensing timing for performing the sensing operation to determine the value of the data based on the normal read level and / or the offset level. In addition, the control of the sensing timing for any one of the above sensing durations may be performed by various methods, and the sensing mode setter 332 may set the sensing mode according to any one of the methods to perform the sensing operation. In addition, according to the above example, the set / reset controller 333 may output a set signal SET and a reset signal RST to the latch for sensing the hard decision data HD and / or the soft decision data SD. The compressor 334 may perform a compression operation on the hard decision data HD and / or the soft decision data SD. As an example, the compressor 334 may perform a compression operation on the soft decision data SD dumped to the cache latch.

[0058] Figure 4 It is shown Figure 3 FIG. 1 is a diagram of an example of a buffer unit of a page buffer. Figure 4 1 shows a schematic configuration of a latch included in the first buffer unit PBU 1 connected to any one bit line BL. In this example, it is assumed that each memory cell can store at least two bits of data and the first buffer unit PBU 1 includes five latches. In addition, the sensing node SO of the first buffer unit PBU 1 can be connected to the bit line BL through the turn-off transistor T_SHF, and the turn-off transistor T_SHF can be controlled by the turn-off control signal BLSHF.

[0059] The first buffer unit PBU 1 may include a first latch (e.g., a sense latch S_LAT), a second latch (e.g., a force latch F_LAT), a third latch (e.g., a first data latch M_LAT), a fourth latch (e.g., a second data latch L_LAT), and a fifth latch (e.g., a cache latch C_LAT). As an example, the sense latch S_LAT may be a latch that senses hard decision data HD. In addition, in some embodiments, the soft decision data SD may be defined to be sensed by the force latch F_LAT. In addition, the force latch F_LAT may also be used to store force information that is used to finely change the distribution of threshold voltages during data programming. In addition, the first data latch M_LAT and the second data latch L_LAT may be used to temporarily store data to be written and data to be read.

[0060] The read operation may include a precharge duration, a development duration, and a sensing duration. When the turn-off transistor T_SHF is turned on during the development duration, the sensing node SO may be connected to the memory cell through the bit line BL, and the voltage level of the sensing node SO may change according to the data stored in the memory cell. In addition, the turn-off transistor T_SHF may be turned off during the sensing duration for sensing the value of the data. However, according to some embodiments of the present disclosure, when multiple sensing operations are performed during any one sensing duration, at least some of the sensing operations may be performed with the turn-off transistor T_SHF turned on.

[0061] The cache latch C_LAT may store data received from the outside or may output data to the outside, and data (DATA) may be dumped between the cache latch C_LAT and other latches within the first buffer unit PBU 1. As an example, hard decision data HD stored in the sense latch S_LAT may be dumped to the cache latch C_LAT and then output to the memory controller, and soft decision data SD stored in the forcing latch F_LAT may be dumped to the cache latch C_LAT and then output to the memory controller.

[0062] As an operation example, the soft decision data SD may have a value corresponding to a result of performing a specific operation (e.g., an exclusive OR operation) on a value determined by two offset levels (a first offset level and a second offset level). According to some embodiments, any one of the set signal SET and the reset signal RST may be provided to the forcing latch F_LAT at a first sensing timing of any one sensing duration, and the other of the set signal SET and the reset signal RST may be provided to the forcing latch F_LAT at a second sensing timing.

[0063] Any one of the hard decision data HD and the soft decision data SD may be controlled to be output first to the memory controller according to the setting of the memory system. As an example, the hard decision data HD or the soft decision data SD may be set to be output first by the initial setting of the memory device, or the hard decision data HD or the soft decision data SD may also be set to be output first according to the type of command from the memory controller.

[0064] Figure 5 It is shown Figure 4 A circuit diagram of an example of any of the latches shown in FIG. As an example, a circuit diagram of any of the latches shown in FIG. Figure 5 The latch is a forced latch F_LAT for sensing soft decision data SD, but other latches can also be used with Figure 5 is implemented in the same manner as the circuit shown in FIG.

[0065] Reference Figure 5 , the forced latch F_LAT may include a latch circuit LC in which inverters are implemented to be coupled to each other, and one or more transistors. The logic states of the first node A and the second node B of the latch circuit LC may have complementary levels. Assuming that the first node A corresponds to the output terminal in the forced latch F_LAT, the second node B may correspond to the inverted output terminal.

[0066] The logic state of the data stored in the latch circuit LC may be flipped by the voltage level supplied to any one of the first node A and the second node B. For example, when the first node A is connected to the ground voltage through the first transistor T1, the logic state of the data may be flipped as the voltage level of the first node A drops to the ground voltage level, and when the first node A is not connected to the ground voltage, the voltage level of the first node A may be maintained.

[0067] In addition, the gate of the first transistor T1 may be connected to the sensing node SO. The first transistor T1 may be turned on or off according to the voltage level of the sensing node SO. When data is programmed with a relatively low threshold voltage in a memory cell connected to the sensing node SO corresponding to the on-cell, the first transistor T1 may maintain an off state as the voltage level of the sensing node SO rapidly decreases during the development duration. On the contrary, when data is programmed with a relatively high threshold voltage in a memory cell connected to the sensing node SO corresponding to the off-cell, the first transistor T1 may be changed to an on state as the voltage level of the sensing node SO gradually decreases during the development duration. In addition, the forced latch F_LAT may further include a set transistor TS and a reset transistor TR arranged between the latch circuit LC and the first transistor T1. A set signal SET may be provided to the gate of the set transistor TS, and a reset signal RST may be provided to the gate of the reset transistor TR.

[0068] Assuming that the voltage of the first node A is provided as the output signal of the forcing latch F_LAT, the voltage level of the first node A may have a value "1" corresponding to a logic high level or a value "0" corresponding to a logic low level through the initialization process of the forcing latch F_LAT. If the first transistor T1 is turned on as the memory cell connected to the sensing node SO corresponds to the off cell based on the sensing level, the voltage level of the first node A may have a value "1" when the set signal SET is provided to the forcing latch F_LAT in the sensing operation. On the contrary, in a state where the first transistor T1 is turned on, the voltage level of the first node A may have a value "0" when the reset signal RST is provided to the forcing latch F_LAT in the sensing operation. Therefore, in the first sensing operation based on the first offset level, any one of the set signal SET and the reset signal RST may be provided to the forcing latch F_LAT, and in the second sensing operation based on the second offset level, the other of the set signal SET and the reset signal RST may be provided to the forcing latch F_LAT.

[0069] Fig. 6A and Figure 6B is a diagram illustrating an example of the operation of a buffer unit related to soft decision data. Fig. 6A An example of the operation of a buffer unit using separate latches for sensing two values ​​of soft decision data SD is shown, and Figure 6B An example of the operation of a buffer unit using one latch for transmitting two values ​​of soft decision data SD during the same sensing duration is shown.

[0070] Reference Fig. 6A, a sensing operation based on the first offset level may be performed by the forcing latch F_LAT, and a sensing operation based on the second offset level may be performed by the first data latch M_LAT. According to the above sensing operation, the first sensing value SD1 may be stored in the forcing latch F_LAT, and the second sensing value SD2 may be stored in the first data latch M_LAT. Soft decision data SD may be generated by performing an operation on the first sensing value SD1 and the second sensing value SD2. As an example, the result of performing an XOR operation on the first sensing value SD1 and the second sensing value SD2 may be stored in the second data latch L_LAT as soft decision data SD.

[0071] Reference Figure 6B According to some embodiments, a first sensing operation may be performed at a first sensing timing of the sensing duration, and a first sensing value SD1 based on a first offset level Offset 1 may be stored in the forcing latch F_LAT. In addition, at the first sensing timing, a set signal SET may be provided to the forcing latch F_LAT.

[0072] Afterwards, a second sensing operation based on the second offset level Offset 2 may be performed at a second sensing timing of the sensing duration. The reset signal RST may be provided to the forcing latch F_LAT at the second sensing timing. According to the above operation, a value corresponding to the soft decision data SD may be stored in the forcing latch F_LAT. As an example, soft decision data SD having the same value (e.g., value "0") may be read from a memory cell having a threshold voltage less than the first offset level Offset 1 or greater than the second offset level Offset 2. In addition, soft decision data SD having the same value (e.g., value "1") may be read from a memory cell having a threshold voltage between the first offset level Offset 1 and the second offset level Offset 2.

[0073] Figure 7 is a flow chart illustrating a method of operating a memory device according to some embodiments. Figure 7 In the example of , a first latch among a plurality of latches included in a buffer unit generates soft decision data through a sensing operation at a first sensing timing and a second sensing timing. In addition, the page buffer includes a plurality of buffer units, and the soft decision data read from a plurality of memory cells can be stored in a plurality of first latches included in the plurality of buffer units.

[0074] Reference Figure 7 Before performing the read operation, the value of the first latch may be initialized to a first value (S11). As an example, it is assumed that the first value stored in the first latch according to the initialization operation corresponds to a value "0" corresponding to a logic low level.

[0075] The first latch may perform a first sensing operation based on a first offset level at a first sensing timing (S12), and a set signal SET may be provided to the first latch in the first sensing operation (S13). In this case, a value of a first latch connected to a shutoff unit based on the first offset level among a plurality of first latches may be changed to a second value (S14). The second value may correspond to "1" corresponding to a logic high level.

[0076] Afterwards, the first latch may perform a second sensing operation based on the second offset level at the second sensing timing (S15), and a reset signal RST may be provided to the first latch in the second sensing operation (S16). In this case, the value of the first latch connected to the shut-off unit based on the second offset level among the plurality of first latches may be changed to a first value (S17). The first value may correspond to "0" corresponding to the logic low level as described above.

[0077] Through the above process, the reading result of the soft decision data can be stored in the first latch, and the soft decision data stored in the first latch can be dumped to the cache latch and then output to the memory controller (S18). As an example, when the soft decision data of the first latch is dumped to the cache latch, an inversion operation may be applied or may not be applied. Therefore, the value stored in the first latch can be dumped to the cache latch, or the value stored in the first latch can be inverted and then dumped to the cache latch.

[0078] Figures 8 to 10A , Fig. 10B , Fig. 10C and Fig. 10D is a diagram illustrating a specific example of an operation of a page buffer according to some embodiments.

[0079] Each buffer unit may include a plurality of latches, and it is assumed that the hard decision data HD is sensed by the first latch, and the soft decision data SD is sensed by the second latch. In addition, each buffer unit is connected to the corresponding bit line through a turn-off transistor, and it is assumed that the turn-off transistor is turned on during the duration that the turn-off control signal BLSHF is logic high. In addition, in these examples, it is assumed that Figures 8 to 10A , Fig. 10B , Fig. 10C and Fig. 10D The sensing duration described in the example includes the development duration and the sensing duration of the above-described embodiment, because the sensing operation can be performed while the voltage of the sensing node is developed in a state where the turn-off transistor is turned on.

[0080] Reference Figure 8, regarding the read operation, a word line voltage corresponding to a normal read level may be provided, and the normal read level may correspond to a standard for determining hard decision data HD. In addition, Figure 8 It is shown that hard decision data HD and soft decision data SD are sensed during separate sensing durations. As an example, after the sensing node SO is precharged to the precharge level VSO, the hard decision data HD may be sensed during a first sensing duration. Thereafter, a precharge operation may be performed again on the sensing node SO, and the soft decision data SD may be sensed during a subsequent second sensing duration. For example, at a first sensing timing of the second sensing duration, data may be determined based on a first offset level Offset 1, and at a second sensing timing, data may be determined based on a second offset level Offset 2.

[0081] In an operation example, the first latch may be initialized to have a value of "1", and a reset signal RST may be provided to the first latch related to a sensing operation for hard decision data HD during a first sensing duration. In response to the reset signal RST, a value stored in the first latch connected to the turn-off unit based on a normal read level may be changed from a value of "1" to a value of "0". Therefore, hard decision data HD having a value of "1" may be read from a memory cell having a threshold voltage less than the normal read level, and hard decision data HD having a value of "0" may be read from a memory cell having a threshold voltage greater than the normal read level.

[0082] In addition, the second latch may be initialized to have a value of “0”, and the set signal SET may be provided to the second latch at a first sensing timing of a second sensing duration, and the value of the second latch connected to the turn-off unit based on the first offset level Offset 1 may be changed from a value of “0” to a value of “1”. Thereafter, the reset signal RST may be provided to the second latch at a second sensing timing of the second sensing duration, and the value of the second latch connected to the turn-off unit based on the second offset level Offset 2 may be changed from a value of “1” to a value of “0”. According to the above process, soft decision data SD having a value of “0” may be read from a memory cell having a threshold voltage less than the first offset level Offset 1 or greater than the second offset level Offset 2, and soft decision data SD having a value of “1” may be read from a memory cell having a threshold voltage between the first offset level Offset 1 and the second offset level Offset 2.

[0083] Fig. 9A , Fig. 9B , Fig. 9C and Fig.9DAn operation of changing a value stored in a second latch through a first sensing operation and a second sensing operation according to a threshold voltage of a memory cell is shown. In the following example, a sensing operation for soft decision data is described.

[0084] Fig. 9A 1 shows a sensing operation for a first memory cell whose threshold voltage level is less than the first offset level Offset 1. The second latch may have a value of "0" through an initialization process. When the threshold voltage of the first memory cell is small, the voltage level of the sensing node SO connected to the first memory cell may decrease rapidly during the development process. Fig. 9A In the development process shown in , the voltage level shown by the dotted line represents an example of the change of the voltage level when the memory cell has a threshold voltage level corresponding to the normal read level.

[0085] When the first memory cell corresponds to an on-cell based on the first offset level Offset 1, Figure 5 The first transistor T1 shown in can be turned off, and the value of the second latch can be maintained as a value of "0" without being changed at the first sensing timing. In addition, when the first memory cell corresponds to an on-cell based on the second offset level Offset 2, the value of the second latch can be maintained as a value of "0" without being changed at the second sensing timing. Therefore, assuming Figure 5 The first node A of the above example shown in corresponds to the output terminal of the second latch, and soft decision data SD corresponding to a value of “0” can be read from the first memory cell.

[0086] Fig. 9B 2 shows a sensing operation for a second memory cell whose threshold voltage level has a value between the first offset level Offset 1 and the second offset level Offset 2. Fig. 9B , when the threshold voltage level of the second memory cell is higher than the threshold voltage level of the first memory cell, the voltage level of the sensing node SO connected to the second memory cell may be gradually lowered during development compared to the voltage level of the sensing node SO connected to the first memory cell.

[0087] When the second memory cell corresponds to a turn-off cell based on the first offset level Offset 1, Figure 5 The first transistor T1 shown in FIG. 1 may be turned on, and in response to the set signal SET, the value of the second latch may be changed from "0" to "1" at the first sensing timing. In addition, when the second memory cell corresponds to the on-cell based on the second offset level Offset 2, the value of the second latch may be maintained as the value "1" without being changed at the second sensing timing. Therefore, the soft decision data SD corresponding to the value "1" may be read from the second memory cell.

[0088] Fig. 9C 2 shows a sensing operation for a third memory cell whose threshold voltage level is greater than the second offset level Offset 2. Fig. 9C , when the third memory cell has a threshold voltage level higher than those of the first memory cell and the second memory cell, the voltage level of the sensing node SO connected to the third memory cell may be more gradually lowered during development compared to the voltage level of the sensing node SO connected to the first memory cell and the second memory cell.

[0089] When the third memory cell corresponds to the off cell based on the first offset level Offset 1, the value of the second latch may be changed from "0" to "1" at the first sensing timing in response to the set signal SET. In addition, when the third memory cell corresponds to the off cell based on the second offset level Offset2, the value of the second latch may be changed from "1" to "0" at the second sensing timing in response to the reset signal RST. Therefore, the soft decision data SD corresponding to the value "0" may be read from the third memory cell.

[0090] Fig.9D An example related to sensing timing is shown. Fig. 9A , Fig. 9B and Fig. 9C In the above example, the sensing timing of the first latch and the first sensing timing and the second sensing timing of the second latch are all performed when the turn-off transistor is turned on. However, the implementation does not need to be limited to this. As an example, Fig.9D As shown in , the sensing timing of the first latch can also be performed when the turn-off transistor is turned off, the first sensing timing of the second latch can be performed when the turn-off transistor is turned on, and the second sensing timing can be performed when the turn-off transistor is turned off.

[0091] Fig. 10A , Fig. 10B , Fig. 10C and Fig. 10D Shown with Fig. 9A , Fig. 9B , Fig. 9C and Fig.9DAn example of a method of providing a set signal SET and a reset signal RST is changed compared to the example of . The first latch storing the hard decision data HD may have a value of "0" through an initialization process. In response to the set signal SET, the value of the first latch connected to the shutdown unit having a threshold voltage greater than the normal read level may be changed to a value of "1". In addition, an inversion operation may be performed when the hard decision data HD stored in the first latch is dumped to the cache latch. Therefore, the hard decision data HD corresponding to the value "1" may be read from the shutdown unit having a threshold voltage greater than the normal read level.

[0092] The second latch may have a value of "1" through an initialization process. Fig. 10A As shown in , a first memory cell whose threshold voltage level is less than the first offset level Offset 1 may correspond to an on-cell based on the first offset level Offset 1. Therefore, the value of the second latch may be maintained as a value "1" without being changed at the first sensing timing. In addition, when the first memory cell corresponds to an on-cell based on the second offset level Offset 2, the value of the second latch may be maintained as a value "1" without being changed at the second sensing timing. In addition, an inversion operation may be performed when dumping the soft decision data SD stored in the second latch to the cache latch. Therefore, the soft decision data SD corresponding to the value "0" may be read from the first memory cell.

[0093] Fig. 10B A sensing operation for a second memory cell whose threshold voltage level has a value between a first offset level Offset 1 and a second offset level Offset 2 is shown. When the second memory cell corresponds to an off cell based on the first offset level Offset 1, the value of the second latch may be changed from "1" to "0" at the first sensing timing in response to the reset signal RST. When the second memory cell corresponds to an on cell based on the second offset level Offset 2, the value of the second latch may be maintained as a value "0" without being changed at the second sensing timing. In addition, an inversion operation may be performed when dumping the soft decision data SD stored in the second latch to the cache latch. Therefore, the soft decision data SD corresponding to the value "1" may be read from the second memory cell.

[0094] Fig. 10CA sensing operation for a third memory cell whose threshold voltage level is greater than the second offset level Offset 2 is shown. When the third memory cell corresponds to a turn-off cell based on the first offset level Offset 1, the value of the second latch may be changed from "1" to "0" at the first sensing timing in response to the reset signal RST. In addition, when the third memory cell corresponds to a turn-off cell based on the second offset level Offset 2, the value of the second latch may be changed from "0" to "1" at the second sensing timing in response to the set signal SET. In addition, an inversion operation may be performed when dumping the soft decision data SD stored in the second latch to the cache latch. Therefore, the soft decision data SD corresponding to the value "0" may be read from the second memory cell.

[0095] With the above Fig.9D Similar to the example, Fig. 10D It is shown that at least one sensing operation can be performed when the turn-off transistor is turned off. As an example, the sensing timing of the first latch can be performed when the turn-off transistor is turned off, and the first sensing timing of the second latch can be performed when the turn-off transistor is turned on, and the second sensing timing of the second latch can be performed when the turn-off transistor is turned off.

[0096] According to the above-described embodiments, an operation of performing a sensing operation based on a plurality of offset levels by using any one latch and generating soft decision data SD by a result of the sensing operation is performed through initialization operations and set / reset control of various methods for latches.

[0097] Fig.11A and Fig. 11B as well as Fig. 12A and Fig. 12B is a diagram illustrating an example of reading soft decision data according to some embodiments.

[0098] Reference Fig.11A and Fig. 11B , a word line voltage corresponding to a normal read level related to the generation of hard decision data HD may be provided to the word line of the memory cell performing the read operation, and hard decision data HD and soft decision data SD may be generated together during any one sensing duration. For example, at the first sensing timing of the sensing duration, the value of the data may be determined based on the first offset level Offset 1, at the second sensing timing, the value of the data may be determined based on the normal read level, and at the third sensing timing, the value of the data may be determined based on the second offset level Offset 2. At this time, the value determined based on the normal read level at the second sensing timing may correspond to the hard decision data HD. Fig.11A and Fig. 11BIn the example of FIG. 1 , it is shown that the first sensing sequence and the second sensing sequence are performed when the turn-off transistor is turned on and the third sensing sequence is performed when the turn-off transistor is turned off, but the implementation does not need to be limited thereto, and the sensing operation can be performed at various time points. For example, the third sensing sequence can also be performed when the turn-off transistor is turned on.

[0099] Reference Fig.11A , the first latch may be initialized to a value of "1" through an initialization process. In response to the reset signal RST, the value of the first latch connected to the memory cell corresponding to the off cell based on the normal read level may be changed to a value of "0" at the second sensing timing. Therefore, hard decision data HD having a value of "1" may be read from the on cell, and hard decision data HD having a value of "0" may be read from the off cell.

[0100] The second latch sensing the soft decision data SD may be initialized to a value of "0", and the set signal SET may be provided to the second latch at the first sensing timing. At this time, the second latch connected to the memory cell corresponding to the on cell based on the first offset level Offset 1 may maintain the value of "0". On the contrary, the value of the second latch connected to the memory cell corresponding to the off cell based on the first offset level Offset 1 may be changed to a value of "1".

[0101] Afterwards, the reset signal RST may be provided to the second latch at the third sensing timing. At this time, the second latch connected to the memory cell corresponding to the on cell based on the second offset level Offset 2 maintains the value "1", and the value of the second latch connected to the memory cell corresponding to the off cell based on the second offset level Offset 2 may be changed to "0". Therefore, the soft decision data SD corresponding to the value "0" may be read from the memory cell having a threshold voltage level less than the first offset level Offset 1 or greater than the second offset level Offset 2.

[0102] Fig. 11B 1 shows a value stored in the second latch when the threshold voltage of the memory cell has a level between the first offset level Offset 1 and the second offset level Offset 2. Fig. 11B , the second latch sensing the soft decision data SD may be initialized to a value of “0”. When the memory cell corresponds to a turn-off cell based on the first offset level Offset 1 at the first sensing timing, the value of the second latch may be changed to a value of “1” in response to the set signal SET.

[0103] Thereafter, at the third sensing timing, the reset signal RST may be provided to the second latch. At this time, when the memory cell corresponds to the on-cell based on the second offset level Offset 2 at the third sensing timing, the value of the second latch may be maintained as the value "1". Therefore, the soft decision data SD corresponding to the value "1" may be read from the memory cell having the threshold voltage level between the first offset level Offset 1 and the second offset level Offset 2.

[0104] According to the above Fig.11A and Fig. 11B In the example shown in , there is an influence of noise because the sensing operation for the hard decision data HD is performed with the bit line and the sensing node electrically connected, and the reading speed can be improved because the hard decision data HD and the soft decision data SD can be read together during one sensing duration.

[0105] exist Fig. 12A and Fig. 12B , a description is provided of an example in which a sensing operation for hard decision data HD is performed with a bit line and a sensing node electrically disconnected, and the amount of information of soft decision data SD is reduced.

[0106] Reference Fig. 12A and Fig. 12B , a word line voltage higher by a certain level than the normal read level of the above example may be provided to the word line of the memory cell that performs the read operation. Therefore, the criterion for determining the threshold voltage level of the value of the hard decision data HD may be increased. Assuming that the criterion for determining the value of the hard decision data HD is the first threshold voltage level, hard decision data HD having a value of "0" may be read from a memory cell having a threshold voltage greater than the first threshold voltage level. The first threshold voltage level may have any level. In some embodiments, the first threshold voltage level may have a level corresponding to the second offset level Offset 2 of the above example.

[0107] In addition, Fig. 12A In the example of , the hard decision data HD and the soft decision data SD may be generated together during the same sensing duration. For example, with respect to reading the soft decision data SD, the value of the data may be determined based on the first offset level Offset 1 at the first sensing timing of the sensing duration, and the value of the data may be determined based on the second offset level Offset 2 at the second sensing timing. As an example, the second sensing timing may correspond to the timing after the turn-off transistor is turned off. Fig. 12AIn the example of , it is shown that the sensing operation through the first latch and the sensing operation through the second latch are performed at the same time at the second sensing timing, but the embodiment does not need to be limited to this. For example, the sensing operation through the first latch and the sensing operation through the second latch can also be performed at different timings after the turn-off transistor is turned off.

[0108] The first latch may be initialized to a value of "1" through an initialization process. In response to a reset signal RST, a value of the first latch connected to a memory cell corresponding to an off cell based on a first threshold voltage level may be changed to a value of "0" at a second sensing timing. Therefore, hard decision data HD having a value of "1" may be read from the on cell, and hard decision data HD having a value of "0" may be read from the off cell.

[0109] The second latch sensing the soft decision data SD may be initialized to a value of "0", and a set signal SET may be provided to the second latch at the first sensing timing. At this time, the value of the second latch connected to the memory cell corresponding to the off cell based on the first offset level Offset 1 may be changed to a value of "1".

[0110] Afterwards, the reset signal RST may be provided to the second latch at the second sensing timing. The value of the second latch connected to the memory cell corresponding to the off cell based on the second offset level Offset 2 among the second latches whose values ​​have been previously changed to the value "1" may be changed to "0". Therefore, the soft decision data SD corresponding to the value "0" may be read from the memory cell having a threshold voltage level less than the first offset level Offset 1 or greater than the second offset level Offset 2.

[0111] Fig. 12B 1 shows a value stored in the second latch when the threshold voltage of the memory cell has a level between the first offset level Offset 1 and the second offset level Offset 2. Fig. 12B , the second latch sensing the soft decision data SD may be initialized to a value of "0". When the memory cell corresponds to an off cell based on the first offset level Offset 1 at the first sensing timing, the value of the second latch may be changed to a value of "1" in response to the set signal SET. Thereafter, at the second sensing timing, a reset signal RST may be provided to the second latch. When the memory cell corresponds to an on cell based on the second offset level Offset 2 at the second sensing timing, the value of the second latch may be maintained as a value of "1".

[0112] according to Fig. 12A and Fig. 12BIn the example shown in , the influence of noise can be reduced in the sensing of the hard decision data HD because the sensing operation for the hard decision data HD is performed with the bit line and the sensing node electrically disconnected, and the reading speed can also be improved because the hard decision data HD and the soft decision data SD can be read together during one sensing duration.

[0113] Fig.13 is a stereoscopic diagram showing a memory block BLKa according to some embodiments.

[0114] Reference Fig.13 , the memory block BLKa can be connected with Figure 1 Corresponding to any one of the multiple memory blocks included in the memory cell array 210. The memory block BLKa is formed in the vertical direction VD relative to the substrate SUB having a first conductivity type (e.g., p-type). In some embodiments, a common source line CSL doped with impurities of a second conductivity type (e.g., n-type) may be disposed on the substrate SUB. In some embodiments, the substrate SUB may be implemented by polycrystalline silicon, and a plate-shaped common source line CSL may also be arranged on the substrate SUB. A plurality of insulating films IL extending along the second direction H2 are sequentially disposed on the substrate SUB along the vertical direction VD, and the plurality of insulating films IL are spaced apart by a specific distance along the vertical direction VD. For example, the plurality of insulating films IL may include an insulating material such as silicon oxide.

[0115] A plurality of pillars P sequentially arranged along a first direction H1 and penetrating a plurality of insulating films IL along a vertical direction VD are provided on a substrate SUB. For example, a plurality of pillars P may penetrate a plurality of insulating films IL and contact the substrate SUB. Specifically, a surface layer S of each pillar P may include a first type of silicon material and may be used as a channel region. Therefore, the pillars P may be referred to as a vertical channel structure. An inner layer I of each pillar P may include an insulating material such as silicon oxide or an air gap.

[0116] The charge storage layer CS is arranged along the exposed surfaces of the insulating film IL, the pillars P and the substrate SUB. The charge storage layer CS may include a gate insulating layer, a charge trapping layer and a blocking insulating layer. For example, the charge storage layer CS may have an oxide-nitride-oxide (ONO) structure. In addition, gate electrodes GE such as ground selection lines GSL, string selection lines SSL and word lines WL0 to WL7 are arranged on the exposed surface of the charge storage layer CS. The drains DR are respectively arranged on the plurality of pillars P. For example, the drain DR may include a silicon material doped with impurities of a second conductivity type. Bit lines BL0 to BL2 arranged to extend in the first direction H1 and spaced apart by a specific distance along the second direction H2 are arranged on the drain DR.

[0117] Fig.14is a block diagram illustrating an example of applying a memory device to an SSD system 400 according to some embodiments.

[0118] Reference Fig.14 , the SSD system 400 may include a host 410 and an SSD 420. The SSD 420 exchanges a signal SIG with the host 410 through a signal connector, and receives power PWR through a power connector. The SSD 420 may include an SSD controller 421, an auxiliary power supply 422, and memory devices 423_1 to 423_3. The memory devices 423_1 to 423_3 may each use the above reference Figures 1 to 13 The described embodiments are implemented.

[0119] That is, the SSD controller 421 may correspond to the memory controller described in the above embodiment, and the memory devices 423_1 to 423_3 may correspond to the memory devices of the above embodiment, and hard decision data and soft decision data may be transmitted and received between the SSD controller 421 and the memory devices 423_1 to 423_3 through channels Ch1 to Chn. The memory devices 4231 to 4233 may each include a sensing controller, and the sensing controller may sense the soft decision data by using any one latch according to the above embodiment, and the selection signals (e.g., the setting signal and the reset signal) provided to the latch at a plurality of sensing timings may have mutually complementary levels.

[0120] Although this specification contains many specific implementation details, these should not be interpreted as limitations on the scope of any invention or on the scope that can be claimed, but rather as descriptions of features that can be specific to a particular implementation of a particular invention. Specific features described in this specification in the context of separate implementations may also be implemented in combination in a single implementation. Conversely, various features described in the context of a single implementation may also be implemented in multiple implementations individually or in any suitable sub-combination. In addition, although features may be described above as working in a particular combination, one or more features from a combination may be removed from the combination in some cases, and a combination may be directed to a sub-combination or a variation of a sub-combination.

[0121] While some embodiments have been particularly shown and described with reference to examples of some embodiments, it will be understood that various changes in form and details may be made therein without departing from the spirit and scope of the appended claims.

Claims

1. A memory device, comprising: a memory cell array comprising a plurality of pages, each of the plurality of pages comprising a plurality of memory cells; a control logic configured to control a read operation to read hard decision data based on a normal read level and soft decision data based on a first offset level and a second offset level from the plurality of pages; as well as a page buffer comprising buffer units for the plurality of pages, each buffer unit comprising a first latch for sensing the hard decision data and a second latch for sensing the soft decision data, The control logic is configured to control the read operation to read the soft decision data from a first page of the plurality of pages by: controlling a first sensing operation at a first sensing timing during a sensing duration for the first page, and controlling a second sensing operation at a second sensing timing during the sensing duration, Wherein, controlling the first sensing operation includes: providing one of a set signal and a reset signal to a second latch of a buffer unit in the buffer unit to store a value based on the first offset level in the second latch, and Wherein, controlling the second sensing operation includes: The other of the set signal and the reset signal is provided to a second latch of the buffer unit to store a value based on the second offset level in the second latch.

2. The memory device according to claim 1, wherein: The control logic is configured to, after performing the second sensing operation, cause a value stored in the second latch or an inverted value of the value stored in the second latch as the soft decision data to be output to a memory controller.

3. The memory device according to claim 2, in, A first logic state of the soft decision data corresponds to a memory cell having a threshold voltage less than the first offset level or greater than the second offset level, and a second logic state of the soft decision data corresponds to a memory cell having a threshold voltage between the first offset level and the second offset level.

4. The memory device according to claim 1, in, The control logic is configured to control a third sensing operation at a third sensing timing during the sensing duration, wherein the third sensing operation includes storing a value based on the normal read level in a first latch of the buffer unit, and The third sensing timing is later than the first sensing timing and earlier than the second sensing timing.

5. The memory device according to claim 1, in, The control logic is configured to control a third sensing operation at the same time as the second sensing timing, wherein the third sensing operation includes storing a value based on the normal read level in a first latch of the buffer unit, and Wherein, the normal read level and the second offset level are equal to each other.

6. The memory device according to claim 1, in, The sensing duration for the first page is a second sensing duration, wherein the first sensing duration is after a first precharge of a voltage of a sensing node of the buffer unit, and wherein the second sensing duration is after a second precharge of the voltage of the sensing node, the second precharge being after the first sensing duration, and Wherein, the control logic is configured as follows: A third sensing operation is controlled during the first sensing duration, the third sensing operation including storing a value based on the normal read level in a first latch of the buffer unit.

7. The memory device according to claim 6, in, The buffer unit is connected to the corresponding bit line through a turn-off transistor, wherein the third sensing operation is performed when the turn-off transistor is turned off, and Wherein, at least one of the first sensing operation and the second sensing operation is performed when the turn-off transistor is turned on.

8. The memory device according to claim 1, wherein: The second latch of the buffer unit comprises: a first transistor including a gate connected to a sensing node of the buffer unit; a setting transistor connected between the first transistor and an output terminal of the second latch, the setting transistor being controlled by the setting signal; and a reset transistor connected between the first transistor and an inverting output terminal of the second latch, the reset transistor being controlled by the reset signal, When the first transistor is turned on, a voltage level of the output terminal changes in response to at least one of the setting signal and the reset signal.

9. The memory device according to claim 8, in, The second latch is configured such that the value of the second latch changes to a second value in response to the set signal in the first sensing operation in a state where the value of the second latch is initialized to a first value and the second latch is connected to a turned-off memory cell based on the first offset level.

10. The memory device according to claim 9, in, The second latch is configured such that the value of the second latch is changed to the first value in response to the reset signal in the second sensing operation in a state where the second latch is connected to a turned-off memory cell based on the second offset level.

11. A method of operating a memory device, in, The memory device includes a page buffer, the page buffer including buffer units for a plurality of memory cells, each buffer unit of the buffer unit including a first latch for sensing hard decision data based on a normal read level and a second latch for sensing soft decision data based on a first offset level and a second offset level, Wherein, the method comprises: initializing a value stored in a second latch of a buffer unit in the buffer unit to a first value; changing the value stored in the second latch to a second value in response to one of a set signal and a reset signal at a first sensing timing of a sensing duration for a page of the memory device, wherein the second latch is connected to a turned-off memory cell based on the first offset level; changing the value stored in the second latch to the first value in response to the other of the set signal and the reset signal at a second sensing timing of the sensing duration, wherein the second latch is connected to turn off a memory cell based on the second offset level; and After the value stored in the second latch is changed to the first value, the soft decision data having a logic state corresponding to the value stored in the second latch or an inverted value of the value stored in the second latch is output.

12. The method according to claim 11, in, A first logic state of the soft decision data corresponds to a memory cell having a threshold voltage less than the first offset level or greater than the second offset level, and a second logic state of the soft decision data corresponds to a memory cell having a threshold voltage between the first offset level and the second offset level.

13. The method according to claim 11, comprising: At a third sensing timing of the sensing duration, a value based on the normal read level is stored in the first latch, wherein the hard decision data includes the value based on the normal read level, and The third sensing timing is later than the first sensing timing and earlier than the second sensing timing.

14. The method according to claim 11, comprising: storing a value determined based on the normal read level in the first latch at the same time as the second sensing timing, wherein the hard decision data includes the value based on the normal read level, and Wherein, the normal read level and the second offset level are equal to each other.

15. The method according to claim 11, in, The sensing duration for the page is a second sensing duration, wherein the first sensing duration is after a first precharge of a voltage of a sensing node of the buffer unit, and wherein the second sensing duration is after a second precharge of the voltage of the sensing node, the second precharge being after the first sensing duration, and Therein, the method includes storing a value determined based on the normal read level in the first latch during the first sensing duration.

16. The method according to claim 15, in, The buffer unit is connected to the corresponding bit line through a turn-off transistor, wherein storing the value determined based on the normal read level in the first latch is performed when the turn-off transistor is turned off, and Wherein, at least one of changing the value stored in the second latch at the first sensing timing and the second sensing timing is performed when the turn-off transistor is turned on.

17. The method according to claim 11, comprising: dumping the value stored in the second latch or the inverted value of the value stored in the second latch to a cache latch of the buffer unit, wherein the value stored in the second latch or the inverted value of the value stored in the second latch comprises the soft decision data; and Compression is performed on the soft decision data stored in the cache latch.

18. A method of operating a memory device, in, The memory device includes a page buffer including buffer units for a plurality of memory cells, wherein each buffer unit includes a first latch for sensing hard decision data based on a normal read level and a second latch for sensing soft decision data based on a first offset level and a second offset level, and Wherein, the operation method includes: performing a first precharge on a sense node of a buffer cell in the buffer cells in response to a first read command for a first page of the memory device; storing a value determined based on the normal read level in a first latch of the buffer unit during a first sensing duration after the first precharge; performing a second precharge on a sensing node of the buffer unit after the first sensing duration; storing a first sensing result in a second latch of the buffer unit, wherein the second latch is connected to a turned-off memory unit based on the first offset level, wherein storing the first sensing result is performed at a first sensing timing of a second sensing duration in response to one of a set signal and a reset signal, the second sensing duration being after the second precharge; and A second sensing result is stored in a second latch of the buffer unit, wherein the second latch is connected to a turned-off memory unit based on the second offset level, wherein storing the second sensing result is performed at a second sensing timing of the second sensing duration in response to the other of the set signal and the reset signal.

19. The operating method according to claim 18, further comprising: dumping the value stored in the second latch or an inverted value of the value stored in the second latch to a cache latch of the buffer unit; as well as The soft decision data is output to a memory controller, wherein a logic state of the soft decision data is based on a value stored in the cache latch.

20. The operating method according to claim 19, in, A first logic state of the soft decision data corresponds to a memory cell having a threshold voltage less than the first offset level or greater than the second offset level, and wherein a second logic state of the soft decision data corresponds to a memory cell having a threshold voltage between the first offset level and the second offset level.

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