Memory device and operating method of memory device

Abstract

The invention relates to a memory device and an operating method thereof. The memory device may include: a memory bank including memory blocks; a data compression circuit connected to the memory bank; a first merging circuit; a second merging circuit receiving an output from the first merging circuit; a delay detection circuit that generates a delay control signal by comparing the output control signals; a compensation circuit calibrating the output control signal based on the delay control signal; and an output buffer circuit that latches the second merged data and outputs the second merged data based on at least a portion of the output control signal.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the priority of Korean Patent Application No. 10-2023-0104014 filed on August 9, 2023 in the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] The present disclosure generally relates to a memory device and a method of operating the memory device. Background Art

[0004] Data read from the memory device can be transmitted to the input / output pad via the data line. The number of data lines in the memory device may be limited by the physical limitations of the memory device. Typically, multiple memory regions (memory banks) included in multiple memory devices or within a single memory device can share and use the same fixed number of data lines.

[0005] Generally, sharing data lines may require an operation in which a plurality of memory devices or a plurality of memory regions included in one memory device exclusively use a fixed number of data lines in a set order within or during a set time period using time division.

[0006] However, in a specific operation mode, for example, in a compression read operation, data read from each of a plurality of memory areas included in a plurality of memory devices or in one memory device can be compressed and output. Each of a plurality of memory areas included in a plurality of memory devices or in one memory device can use a certain number of data lines, which are determined by assigning or allocating a fixed number of data lines to each of the plurality of memory areas. Therefore, a plurality of memory devices or a plurality of memory areas included in one memory device can be used simultaneously.

[0007] For example, when data read in each of four memory devices is compressed four times or 1 / 4 and then the compressed data is output, each of the four memory devices uses only two data lines that are determined or assigned by dividing eight data lines between each of the four memory devices. Four memory devices can be used simultaneously. Summary of the invention

[0008] The embodiments provide a memory device and a method for operating the memory device, which can reduce or prevent a merge failure that may occur during a data merge process when performing a compression read operation.

[0009] According to one aspect of the present disclosure, a memory device is provided, comprising: a plurality of memory banks, each memory bank comprising a plurality of memory blocks; a plurality of compression circuits, each compression circuit being connected to at least one memory bank, each compression circuit outputting compressed data by compressing data obtained from the memory bank; a first merging circuit receiving an output control signal from the memory bank, and providing a first merged data stream by merging compressed data output from at least two different compression circuits into a single compressed data stream in response to the output control signal; a second merging circuit receiving at least two first merged data streams output from different first merging circuits, and outputting a second merged data stream by merging at least two first merged data streams; a delay detection circuit receiving an output control signal, and generating a delay control signal by comparing the output control signal; a compensation circuit calibrating the output control signal based on the delay control signal; and an output buffer circuit configured to latch the second merged data, and output the second merged data based on at least a portion of the output control signal.

[0010] According to another aspect of the present disclosure, a method for operating a memory device is provided, the method comprising: generating a delay control signal based on an output control signal output from at least a portion of a plurality of memory bodies; calibrating the output control signal based on the delay control signal; compressing data read from the plurality of memory bodies; performing a first merge on compressed data corresponding to different memory bodies in a plurality of first merge circuits based on the calibrated output control signal; performing a second merge on first merged data on which the first merge has been performed in a second merge circuit; and outputting second merged data on which the second merge has been performed based on the calibrated output control signal. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Example embodiments will now be described more fully hereinafter with reference to the accompanying drawings; however, the embodiments may be implemented in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the example embodiments to those skilled in the art.

[0012] In the accompanying drawings, dimensions may be exaggerated for clarity of illustration. It will be understood that when an element is referred to as being "between" two elements, it can be the only element between the two elements, or one or more intermediate elements may also be present. Throughout the specification, the same reference numerals refer to the same elements.

[0013] Figure 1 is a block diagram illustrating a memory device according to an embodiment of the present disclosure.

[0014] Figure 2 yes Figure 1 A diagram of a first combining circuit is shown.

[0015] Figure 3 It is shown Figure 1 A diagram of a second merging circuit and an output buffer circuit is shown.

[0016] Figure 4 It is shown Figure 1 Schematic diagram of the delay detection circuit shown.

[0017] Figures 5 to 7 It is shown Figure 4 A timing diagram of the operation of the delay detection circuit is shown.

[0018] Figure 8 is a timing diagram illustrating signals provided to a memory device according to an embodiment of the present disclosure.

[0019] Fig. 9 It is shown Figure 1 A diagram of an example of a compensation circuit is shown.

[0020] Fig.10 It is shown Figure 1 A block diagram of another embodiment of a memory device is shown.

[0021] Fig.11 is a block diagram illustrating a storage device including a memory device according to an embodiment of the present disclosure.

[0022] Fig.12 yes Fig.11 A diagram of another embodiment of a memory controller is shown.

[0023] Fig.13 is a flowchart illustrating an operating method of a memory device according to an embodiment of the present disclosure.

[0024] Fig.14 is a flowchart illustrating in more detail a process of outputting a delay control signal in a method of operating a memory device according to an embodiment of the present disclosure.

[0025] Fig.15 is a flowchart illustrating in more detail a process of generating a delay control signal in a method of operating a memory device according to an embodiment of the present disclosure.

[0026] Fig.16 is a flowchart illustrating an example of correcting an output control signal in a method of operating a memory device according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0027] The specific structural or functional descriptions disclosed herein are merely illustrative and are intended to describe embodiments of the concepts of the present disclosure. Embodiments of the concepts of the present disclosure may be implemented in various forms and should not be construed as being limited to the embodiments set forth herein.

[0028] Figure 1 is a block diagram illustrating a memory device according to an embodiment of the present disclosure.

[0029] Reference Figure 1 , the memory device 1000 may include a plurality of memory banks, each of which has Figure 1 1100. Each memory bank 1100 may include a plurality of memory blocks (not shown). Each memory block may include a plurality of memory cells (not shown).

[0030] In an embodiment, the memory cell may be a nonvolatile memory cell. Memory cells connected to the same word line (not shown) may be defined as a page. Therefore, one memory block BK may include a plurality of pages.

[0031] In an embodiment, the memory bank 1100 may be memory regions respectively included in different memory devices. In another embodiment, the memory bank 1100 may be different memory regions divided in one memory device.

[0032] exist Figure 1 , the memory device 1000 includes eight memory banks 1100 BK0 to BK3 and BK0' to BK3'. However, the number of memory banks 1100 is not limited thereto and is selected according to the design. Therefore, the number of memory banks 1100 may be less than or greater than Figure 1 In another example, the number of memory banks 1100 may be 16 or 32.

[0033] In an embodiment, the memory bank 1100 may be divided into one or more memory planes, and one or more memory banks 1100 may be included in one memory plane. For example, memory banks 0BK0 to 3BK3 may be included in a first memory plane, and memory banks 0'BK0' to 3'BK3' may be included in a second memory plane. Alternatively, memory banks 0BK0 and 1BK1 may be included in a first memory plane, memory banks 2BK2 and 3BK3 may be included in a second memory plane, memory banks 0'BK0' and 1'BK1' may be included in a third memory plane, and memory banks 2'BK2' and 3'BK3' may be included in a fourth memory plane. The number of memory planes and the number of memory banks included in a memory plane are design choices and are not limited to a specific number thereof.

[0034] The compression circuit 1200 may be connected to each memory bank 1100. The compression circuit 1200 may be enabled when the memory device 1000 performs a "compression read" operation, in response to the memory device 1000 receiving a datagram from a device ( Figure 1 In another embodiment, the memory device 1000 may perform the compressed read operation autonomously, ie, determined by its own control logic.

[0035] When performing a compressed read operation, in a first step, read data R.DATA may be output from each memory bank 1100. Read data R.DATA may be output from each memory bank 1100 in response to an output control signal OUTPUT_CTR. The output control signal OUTPUT_CTR may be generated in response to a clock signal provided from outside the memory device 1000 or provided by a clock signal source in the memory device 1000. Figure 1 Only control signals OUTPUT_CTR0, OUTPUT_CTR1, OUTPUT_CTR0' and OUTPUT_CTR1' outputted from banks 0BK0, 1BK1, 0'BK0' and 1'BK1' are shown, but the present disclosure is not limited thereto. Other banks 1100 not shown may output corresponding other control signals OUTPUT_CTR, respectively.

[0036] After the compression read operation, read data R.DATA read from each memory bank 1100 may be compressed in the compression circuit 1200 connected to each memory bank 1100. After being compressed by the compression circuit 1200, the compressed data C.DATA may be output from the compression circuit 1200 in response to the output control signal OUTPUT_CTR.

[0037] The compression circuit 1200 may compress the read data R.DATA at a compression ratio or compression factor of 1:N, thereby generating corresponding compressed data C.DATA. N may be an integer greater than or equal to two (2). For example, when N is 4, the compression circuit 1200 may compress the read data R.DATA at a compression ratio of 1:4, i.e., reduce the "amount" or "size" of the data before compression by 4 times. Therefore, the size of the compressed data is 25% of the size of the same data before compression, thereby generating compressed data C.DATA. For example, if the read data R.DATA before compression is 16 bits, 4 bits of compressed data C.DATA may be output from the compression circuit 1200.

[0038] The compressed data C.DATA outputted from the plurality of different compression circuits 1200 may be merged in the first merge circuit 1300. The first merge circuit 1300 may merge the compressed data C.DATA corresponding to the different memory banks 1100. Figure 1 As shown, compressed data C.DATA0 from bank 0BK0 and compressed data C.DATA2 from bank 2BK2 may be merged in first merge circuit 1300 that receives C.DATA0 and C.DATA2. The number and location or position of memory banks 1100 that may generate compressed data C.DATA merged in first merge circuit 1300 is a matter of design choice.

[0039] Each first merging circuit 1300 may receive the compressed data C.DATA from two or more compression circuits 1200 , and an output control signal OUTPUT_CTR corresponding to the compressed data C.DATA from corresponding different memory banks 1100 .

[0040] In an embodiment, the first merge circuit 1300 may latch the compressed data C.DATA corresponding to the different memory banks 1100 and output the latched compressed data C.DATA in response to the output control signal OUTPUT_CTR. Then, the compressed data C.DATA corresponding to the different memory banks 1100 may be output from the first merge circuit 1300 as the first merge data 1 st M. DATA.

[0041] The first merging circuit 1300 may select and use any one of the output control signals OUTPUT_CTR received by the first merging circuit 1300 from the memory bank 1100 coupled to the first merging circuit 1300, each received OUTPUT_CTR signal corresponding to the corresponding compressed data C.DATA. For example, when C.DATA0 and C.DATA2 are merged by the first merging circuit 1300, the first merging circuit 1300 may select and generate the output control signal OUTPUT_CTR0 output from the memory bank 0BK0, and may select and generate the output control signal OUTPUT_CTR2 (not shown) output from the memory bank 2BK2. Therefore, the first merged data 1 may be output in response to the output control signal OUTPUT_CTR0. st M.DATA0. A method of selecting the output control signal OUTPUT_CTR is not limited to a specific example.

[0042] The first merged data 1 outputted from the first merge circuit 1300 stM.DATA0 may be coupled to the second merging circuit 1400 and merged in the second merging circuit 1400. The second merging circuit 1400 may merge the first merged data 1 outputted from different first merging circuits 1300. st M.DATA1,1 st M.DATA2 and 1 st M.DATA3.

[0043] For example, the first merged data 1 st M.DATA0 and first merged data 1 st M.DATA1 can be merged in the second merge circuit 1400. In another example, the first merged data 1 st M.DATA0 and first merged data 1 st M.DATA3 may be merged in the second merge circuit 1400. The number and location of the first merge circuits 1300 corresponding to the first merge data merged in the second merge circuit 1400 are design choices and are not limited to the specific examples described herein.

[0044] Therefore, the second merging circuit 1400 can combine the first merged data 1 st M.DATAn is different from the first merged data 1 st M.DATAm merges and outputs the second merged data 2 nd M.DATAn+m. Output second merged data 2 nd M.DATAn+m may be latched in the output buffer circuit 1700. The second merged data 2 latched in the output buffer circuit 1700 nd M.DATAn+m can be output from the buffer circuit 1700 by or in response to the output control signal OUTPUT_CTR, such as Figure 1 The output buffer circuit 1700 can select the second merged data 2 to be output. nd M.DATA corresponds to any one of the output control signals OUTPUT_CTR, thereby outputting the second merged data 2 in response to the selected output control signal OUTPUT_CTR. nd M. DATA.

[0045] For example, when merging the first merged data 1 st M.DATA0 and first merged data 1 st M.DATA1 obtains the second merged data 2 ndWhen M.DATA0 is on, the output buffer circuit 1700 may select and use the output control signal OUTPUT_CTR0 from the output control signal OUTPUT_CTR0 and the output control signal OUTPUT_CTR1. Therefore, the second merged data 2 may be output from the output buffer circuit 1700 in response to the output control signal OUTPUT_CTR0. nd M.DATA0.

[0046] like Figure 1 As shown, the output control signal OUTPUT_CTRn may be provided to the delay detection circuit 1500, and the delay detection circuit 1500 may generate a delay control signal DELAY_CTR by comparing the received output control signal OUTPUT_CTRn. In an embodiment, the delay detection circuit 1500 may compare the output control signal OUTPUT_CTRn with the first merged data 1 st M.DATA and an output control signal OUTPUT_CTR corresponding to the data signal to be merged in the second merging circuit 1400.

[0047] For example, when in the second merging circuit 1400, the first merged data 1 st M.DATA0 and first merged data 1 st M.DATA1 is merged and first merged data 1 st M.DATA2 and first merged data 1 st When M.DATA3 is merged, the delay detection circuit 1500 can compare the output control signal OUTPUT_CTR0 and the output control signal OUTPUT_CTR1 with each other, and compare the output control signal OUTPUT_CTR2 and the output control signal OUTPUT_CTR3 with each other. Then, the delay detection circuit 1500 can compare the phase difference, i.e., the delay difference, between the compared output control signals OUTPUT_CTR. As a result of the comparison, the delay detection circuit 1500 can generate a delay control signal DELAY_CTR, which indicates whether the delay difference between the output control signals OUTPUT_CTR is within or outside the predetermined delay range. In an embodiment, the delay control signal DELAY_CTR can indicate whether each output control signal OUTPUT_CTR needs to be delayed. In addition, in an embodiment, the delay control signal DELAY_CTR may include information about how much each output control signal OUTPUT_CTR will be delayed.

[0048] The delay control signal DELAY_CTR generated in the delay detection circuit 1500 may be provided to the compensation circuit 1600, and the compensation circuit 1600 may calibrate the output control signal OUTPUT_CTR based on the received delay control signal DELAY_CTR. In an embodiment, the compensation circuit 1600 may delay or not delay the output control signal OUTPUT_CTR according to the delay control signal DELAY_CTR.

[0049] The delay-calibrated output control signal OUTPUT_CTR can be used for outputting and merging data in subsequent operations. For example, since the calibrated output control signal OUTPUT_CTR is provided to the first merging circuit 1300, the first merged data 1 can be generated in the first merging circuit 1300. st In addition, since the calibrated output control signal OUTPUT_CTR is provided to the second merging circuit 1400 or the output buffer circuit 1700, the second merged data 2 can be generated and output. nd M.DATA uses the calibrated output control signal OUTPUT_CTR.

[0050] In this way, the delay difference between the control signals OUTPUT_CTR for outputting and merging data is reduced by calibrating or synchronizing the output control signals OUTPUT_CTR with each other, thereby reducing or preventing data merging failure that may occur due to the delay difference between the output control signals OUTPUT_CTR.

[0051] Figure 2 yes Figure 1 A block diagram of a first merging circuit 1100 is shown.

[0052] Reference Figure 2 , the read data R.DATA0 read from the memory bank 0BK0 may be compressed by the “first” compression circuit 1200, such as Figure 2 The compressed form of the read data R.DATA0, named C.DATA0, can be output from the “first” compression circuit 1200.

[0053] like Figure 2 As shown in the lower half of FIG. 1 , read data R.DATA2 read from a different memory bank 2BK2 may be compressed by a different or “second” compression circuit 1200. A compressed form of other data from a different memory bank 2BK2, named C.DATA2, may be output from another compression circuit 1200.

[0054] like Figure 2As shown, corresponding output control signals OUTPUT_CTR0 and OUTPUT_CTR2 may be output from respective memory banks 1100 (BK0 and BK2). Therefore, read data R.DATA may be output from each of memory banks 1100 (BK0 and BK2) in response to output control signals OUTPUT_CTR0 and OUTPUT_CTR2. Therefore, read data R.DATA0 may be output in response to output control signal OUTPUT_CTR0. Read data R.DATA2 may be output in response to output control signal OUTPUT_CTR2.

[0055] The compressed data C.DATA0 and the compressed data C.DATA2 may be merged by the first merge circuit 1300. In an embodiment and as shown in FIG. Figure 2 As shown, the first merging circuit 1300 may include a D flip-flop. The compressed data C.DATA0 and the compressed data C.DATA2 are "bundled" together so that they are both input to the same D input terminal of the D flip-flop to be latched. In an optional embodiment, the first merging circuit 1300 may include a plurality of D flip-flops, the number of which corresponds to the number of data bits read from the memory bank 1100. For example, if 16 bits of data are read from the memory bank 1100, the first merging circuit 1300 may include 16 flip-flops. In a normal read operation, 16 bits of data may be read from the memory bank 1100, and each bit of the data read from the memory bank 1100 is latched into one of the 16 D flip-flops.

[0056] In the compression read operation, when the compression circuit 1200 compresses the read data R.DATA at a compression ratio of 1:2 (i.e., 50%), the 8-bit compressed data C.DATA0 output from the memory bank 0BK0 and the 8-bit compressed data C.DATA2 output from the memory bank 2BK2 may be latched into 16 flip-flops. When the compression circuit 1200 compresses the read data R.DATA at a compression ratio of 1:4 (i.e., 25%), the 4-bit compressed data C.DATA0 output from the memory bank 0BK0 and the 4-bit compressed data C.DATA2 output from the memory bank 2BK2 may be latched into 8 flip-flops among the 16 flip-flops without using the other 8 flip-flops.

[0057] The latched compressed data C.DATA0 and the latched compressed data C.DATA1 can be temporarily aligned, that is, they are simultaneously latched into the D flip-flop and output from the D flip-flop by the output control signal OUTPUT_CTR supplied to the clock input terminal CK, so that the first merged data 1 st M.DATA0 is output from the D flip-flop at the Q output.

[0058] exist Figure 2, the output control signal OUTPUT_CTR0 is used as a clock signal, which causes the data (whether logic 0 or logic 1) at the D input terminal to enter the D flip-flop, thereby being output from the Q output terminal of the flip-flop. However, the present disclosure is not limited to this, and optionally, the clock signal input to the D flip-flop can be the output control signal OUTPUT_CTR2. Therefore, in an optional embodiment, the first merging circuit 1300 may include a clock signal selection circuit, and the clock signal selection circuit may be implemented as, for example, a multiplexer to select which clock signal of a plurality of clock signals will be provided to the clock input terminal of the D flip-flop.

[0059] Figure 3 It is shown Figure 1 A block diagram of a second merging circuit 1400 and an output buffer circuit 1700 is shown.

[0060] Reference Figure 3 The second merging circuit 1400 may include a data merging circuit identified by reference numeral 1410 . The second merging circuit 1400 may further include a signal selecting circuit 1420 .

[0061] The data merging circuit 1410 may receive and merge the first merged data 1 outputted from the plurality of first merging circuits 1300. st M.DATA. For example, the data merge circuit 1410 may be named 1 st The first merged data of M.DATA0 is named 1 st M.DATA1 is merged with the "second" or "different" first merged data and henceforth the output is named 2 nd The second merged data of M.DATA0.

[0062] The same data merging circuit 1410 may be named as 1 st Another first merged data of M.DATA2 and named 1 st Another first merged data of M.DATA3 is merged and the output is named 2 nd Another different “second” merged data of M.DATA1. However, the number and position of the first merge circuits 1300 corresponding to the first merged data merged by the data merge circuit 1410 are not limited to a specific example.

[0063] In an embodiment, the data merging circuit 1410 may include one or more multiplexers. Therefore, all first merged data 1 provided or input to the data merging circuit 1410 are st M.DATA streams can be merged together and output to latch group 1720, such as Figure 3 shown.

[0064] The signal selection circuit 1420 may receive the output control signal OUTPUT_CTR from the memory bank 1100. When the memory device 1000 performs a compression read operation, the signal selection circuit 1420 may select and output at least a portion of the received output control signal OUTPUT_CTR.

[0065] In an embodiment, the signal selection circuit 1420 can select the first merged data 1 merged by the data merging circuit 1410. st One of the output control signals OUTPUT_CTR corresponding to M.DATA. Figure 3 As shown, when the data merging circuit 1410 combines the first merged data 1 st M.DATA0 and first merged data 1 st M.DATA1 is merged together and outputs the second merged data 2 nd M.DATA0, and when the data merging circuit 1420 converts the first merged data 1 st M.DATA2 and first merged data 1 st M.DATA3 are merged together and output as the second merged data 2 nd When M.DATA1 is used, the signal selection circuit 1420 can select and output the output control signal OUTPUT_CTR0 and the output control signal OUTPUT_CTR1, and can select and output the output control signal OUTPUT_CTR0' and the output control signal OUTPUT_CTR1'. Figure 3 In the embodiment, the output control signal OUTPUT_CTR0 is selected from the output control signal OUTPUT_CTR0 and the output control signal OUTPUT_CTR1, and the output control signal OUTPUT_CTR0' is selected from the output control signal OUTPUT_CTR0' and the output control signal OUTPUT_CTR1'.

[0066] When the memory device 1000 performs a normal read operation, the signal selection circuit 1420 does not simultaneously receive the output control signals OUTPUT_CTR0 and OUTPUT_CTR1 or OUTPUT_CTR0 ′ and OUTPUT_CTR1 ′. Therefore, the signal selection circuit 1420 may output the received output control signal OUTPUT_CTR as is.

[0067] The second combined data 2 is combined and output by the data combining circuit 1410 ndM.DATA and the output control signal OUTPUT_CTR selected by the signal selection circuit 1420 may be provided to the output buffer circuit 1700. The output buffer circuit 1700 may include an output control circuit 1710 and a latch group 1720.

[0068] The latch group 1720 may include a plurality of latches, and the second merged data 2 outputted from the second merge circuit 1400 may be nd M.DATA may be latched to a plurality of latches. The output control circuit 1710 may provide a data output control signal DOUT_CTR to the latch group 1720 based on the output control signal OUTPUT_CTR received from the second merging circuit 1400. The second merging data 2 latched to the latch group 1720 may be output to the latch group 1720. nd M.DATA may be output in response to a data output control signal DOUT_CTR.

[0069] Figure 4 yes Figure 1 Schematic diagram of the delay detection circuit shown.

[0070] Reference Figure 4 , the delay detection circuit 1500 may include a delay control signal generator 1510 and a delay control signal output unit 1520 .

[0071] The delay control signal generator 1510 may receive and compare the output control signals OUTPUT_CTR0 and OUTPUT_CTR1. In an embodiment, the delay detection circuit 1500 may compare the first merged data 1 merged by the second merge circuit 1400 with the first merged data 1 merged by the second merge circuit 1400. st M.DATA corresponding to the output control signal. For example, the first merged data 1 st M.DATA0 and first merged data 1 st M.DATA1 may be merged by the second merge circuit 1400. The delay detection circuit 1500 may receive and compare the output control signal OUTPUT_CTR0 and the output control signal OUTPUT_CTR1, which correspond to the first merged data 1 respectively. st M.DATA0 and first merged data 1 st M.DATA1.

[0072] Also, when a compression read operation is performed, the delay detection circuit 1500 may be enabled. In an embodiment, the delay control signal generator 1510 may receive a compression read enable signal ESS_EN.

[0073] In an embodiment, the delay control signal generator 1510 may include two D flip-flops DFF. The D flip-flops DFF of the delay control signal generator 1510 may compare the delay difference between the output control signals OUTPUT_CTR0 and OUTPUT_CTR1 and generate a delay control signal indicating whether the delay difference therebetween exceeds a predetermined range.

[0074] In an embodiment, the delay control signal generator 1510 may include a delay circuit Delay Cell 1. Therefore, the output control signal OUTPUT_CTR1 may be delayed by a predetermined range. Figure 4 In the example, the delay circuit Delay Cell 1 can delay the output control signal OUTPUT_CTR1 and provide the delayed output control signal to Figure 4 The D input terminal of the lower D flip-flop DFF shown is used as an input.

[0075] The delayed output control signal OUTPUT_CTR1_DEL may be input to the D input terminal of the lower D flip-flop in the delay control signal generator 1510. Figure 4 As shown, the output control signal OUTPUT_CTR1 may be input to the clock input terminal of the upper D flip-flop in the delay control signal generator 1510. Therefore, a signal indicating whether the delay difference between the output control signals exceeds a predetermined range may be output from the D flip-flop in the delay control signal generator 1510. More specifically, when the output control signal OUTPUT_CTR0 is compared with the output control signal OUTPUT_CTR1, a signal Q_B0 indicating whether the output control signal OUTPUT_CTR0 is faster than a predetermined range may be output.

[0076] Likewise, the delayed output control signal OUTPUT_CTR1_DEL may be input to a data input terminal of another D flip-flop in the delay control signal generator 1510, and the output control signal OUTPUT_CTR0 may be input to a clock input terminal of another D flip-flop in the delay control signal generator 1510. Therefore, when the output control signal OUTPUT_CTR1 is compared with the output control signal OUTPUT_CTR0, a signal Q_B1 indicating whether the output control signal OUTPUT_CTR1 is faster than a predetermined range may be output.

[0077] In an embodiment, the delay control signal output unit 1520 may include two D flip-flops. The delay control signal generated by the delay control signal generator 1510 may be input to a data input terminal of one D flip-flop in the delay control signal output unit 1520 and latched into the D flip-flop.

[0078] The calibration enable signal CALIB_EN may be provided to (input to) clock input terminals of two D flip-flops in the delay control signal output unit 1520. Therefore, the latched delay control signals B0_FAST, B1_FAST may be output in response to the calibration enable signal CALIB_EN.

[0079] For example, the delay control signal output from the delay control signal output unit 1520 may correspond to a signal B0_FAST, which indicates whether the output control signal OUTPUT_CTR0 is faster than the output control signal OUTPUT_CTR1 by more than a predetermined range when the signal B0_FAST is logic 1. The signal B1_FAST of logic 1 indicates whether the output control signal OUTPUT_CTR1 is faster than the output control signal OUTPUT_CTR0 by more than a predetermined range.

[0080] Although it shows Figure 4 Each of the delay control signal generator 1510 and the delay control signal output unit 1520 shown includes a D flip-flop, but the present disclosure is not limited to the implementation of using the D flip-flop. The delay control signal generator 1510 can be implemented with various types of components capable of generating a delay control signal by receiving the output control signal OUTPUT_CTR and comparing the output control signal OUTPUT_CTR.

[0081] In addition, the delay control signal output unit 1520 may be implemented with various types of components capable of latching the input delay control signal and outputting the latched signal in response to the calibration enable signal CALIB_EN. Figure 4 The delay detection circuit 1500 has been described for the output control signal OUTPUT_CTR0 and the output control signal OUTPUT_CTR1, but the delay detection circuit 1500 may be similarly applied to other output control signals OUTPUT_CTR.

[0082] Figures 5 to 7 It is shown Figure 4 A timing diagram of the operation of the delay detection circuit is shown.

[0083] Reference Figure 4 and Figure 5, the delay control signal generator 1510 may compare the delayed output control signal OUTPUT_CTR0_DEL with the output control signal OUTPUT_CTR1. As a result of the comparison, the delayed output control signal OUTPUT_CTR0_DEL is not faster than the output control signal OUTPUT_CTR1. Therefore, the delay control signal generator 1510 may generate a signal Q_B0 indicating that the output control signal OUTPUT_CTR0 is not faster than the output control signal OUTPUT_CTR1 by more than a predetermined range. For example, a signal having a low value may indicate that the target output control signal is not faster than a predetermined value compared to the comparison output control signal. Therefore, Q_B0 may have a low value.

[0084] The delay control signal generator 1510 may compare the delayed output control signal OUTPUT_CTR1_DEL with the output control signal OUTPUT_CTR0. As a result of the comparison, the delayed output control signal OUTPUT_CTR1_DEL is not faster than the output control signal OUTPUT_CTR0. Therefore, the delay control signal generator 1510 may generate a signal Q_B1 indicating that the output control signal OUTPUT_CTR1 is not faster than the output control signal OUTPUT_CTR0 by more than a predetermined range. Therefore, Q_B1 may have a low value.

[0085] Each of Q_B0 and Q_B1 having these values ​​may be input to the delay control signal output unit 1520 so that the values ​​according to Q_B0 and Q_B1 are latched. When the calibration enable signal CALIB_EN is input, the data latched to the delay control signal output unit 1520 may be output as B0_FAST and B1_FAST as delay control signals. That is, since the value latched to the delay control signal output unit 1520 is a low value, both B0_FAST and B1_FAST may be output as low values.

[0086] Reference Figure 4 and Figure 6 , the delay control signal generator 1510 may compare the delayed output control signal OUTPUT_CTR0_DEL with the output control signal OUTPUT_CTR1. As a result of the comparison, the delayed output control signal OUTPUT_CTR0_DEL is faster than the output control signal OUTPUT_CTR1. Therefore, the delay control signal generator 1510 may generate a signal Q_B0 indicating that the output control signal OUTPUT_CTR0 is faster than the output control signal OUTPUT_CTR1 by more than a predetermined range. For example, a signal having a high value may indicate that the target output control signal is faster than the comparison output control signal by more than a predetermined value. Therefore, Q_B0 may have a high value.

[0087] The delay control signal generator 1510 may compare the delayed output control signal OUTPUT_CTR1_DEL with the output control signal OUTPUT_CTR0. As a result of the comparison, the delayed output control signal OUTPUT_CTR1_DEL is not faster than the output control signal OUTPUT_CTR0. Therefore, the delay control signal generator 1510 may generate a signal Q_B1 indicating that the output control signal OUTPUT_CTR1 is not faster than the output control signal OUTPUT_CTR0 by more than a predetermined range. Therefore, Q_B1 may have a low value.

[0088] Each of Q_B0 and Q_B1 having these values ​​may be input to the delay control signal output unit 1520 so that the values ​​according to Q_B0 and Q_B1 are latched. When the calibration enable signal CALIB_EN is input, the data latched to the delay control signal output unit 1520 may be output as B0_FAST and B1_FAST as delay control signals. That is, since the value latched to the delay control signal output unit 1520 is a high value due to Q_B0, B0_FAST may be output as a high value. In addition, since the value latched to the delay control signal output unit 1520 is a low value due to Q_B1, B1_FAST may be output as a low value.

[0089] Reference Figure 4 and Figure 7 , the delay control signal generator 1510 may compare the delayed output control signal OUTPUT_CTR0_DEL with the output control signal OUTPUT_CTR1. As a result of the comparison, the delayed output control signal OUTPUT_CTR0_DEL is not faster than the output control signal OUTPUT_CTR1. Therefore, the delay control signal generator 1510 may generate a signal Q_B0 indicating that the output control signal OUTPUT_CTR0 is not faster than the output control signal OUTPUT_CTR1 by more than a predetermined range. Therefore, Q_B0 may have a low value.

[0090] The delay control signal generator 1510 may compare the delayed output control signal OUTPUT_CTR1_DEL with the output control signal OUTPUT_CTR0. As a result of the comparison, the delayed output control signal OUTPUT_CTR1_DEL is faster than the output control signal OUTPUT_CTR0, and thus, the delay control signal generator 1510 may generate a signal Q_B1 indicating that the output control signal OUTPUT_CTR1 is faster than the output control signal OUTPUT_CTR0 by more than a predetermined range. Therefore, Q_B1 may have a high value.

[0091] Each of Q_B0 and Q_B1 having these values ​​may be input to the delay control signal output unit 1520 so that the values ​​according to Q_B0 and Q_B1 are latched. When the calibration enable signal CALIB_EN is input, the data latched to the delay control signal output unit 1520 may be output as B0_FAST and B1_FAST as delay control signals. That is, since the value latched to the delay control signal output unit 1520 is a low value due to Q_B0, B0_FAST may be output as a low value. In addition, since the value latched to the delay control signal output unit 1520 is a high value due to Q_B1, B1_FAST may be output as a high value.

[0092] Figure 8 is a timing diagram illustrating signals provided to a memory device according to an embodiment of the present disclosure.

[0093] Reference Figure 1 , Figure 4 and Figure 8 , in the initial stage of the compression read operation, a predetermined number of clocks CKCOL may be generated to load the compression circuit 1200. For example, Figure 8 As shown, when a compression read operation is performed upon receiving a compression read enable signal ESS_EN, 13 initial clocks may correspond to a "dummy period" during which the compression circuit 1200 is loaded. Dummy data may be output during the dummy period. When the dummy period is completed, a prefetch signal ESS_Prefetch indicating that the dummy period has been completed may be provided.

[0094] According to an embodiment of the present disclosure, a virtual period may be used as a training period for calibrating an output control signal OUTPUT_CTR. In addition, during the virtual period, a signal ESS_Prefetch indicating that the virtual period has been completed may be used as a calibration enable signal CALIB_EN. For example, the delay detection circuit 1500 may compare the output control signal OUTPUT_CTR0 and the output control signal OUTPUT_CTR1 received during the virtual period. When the pre-fetch signal ESS_Prefetch is received, a delay control signal DELAY_CTR generated as a result of the comparison may be output. Therefore, starting from the virtual period, data may be output and merged in response to the calibrated output control signals OUTPUT_CTR0 and OUTPUT_CTR1.

[0095] Fig. 9 It is shown Figure 1 A diagram of an example of a compensation circuit is shown.

[0096] Reference Fig. 9, the clock signal CKCOL0 to be provided to the memory bank 0BK0 may be input to the compensation circuit 1600. The clock signal CKCOL0 may be generated by an internal power supply of the memory device 1000 or provided from the outside.

[0097] The compensation circuit 1600 may include a delay circuit Delay Cell 2, and delay the clock signal CKCOL0 input through the delay circuit DelayCell 2. The compensation circuit 1600 may receive the delay control signal DELAY_CTR0 output from the delay detection circuit 1500, and output a calibrated clock signal CKCOL0_CAL1B based on the received delay control signal DELAY_CTR0. In an embodiment, the calibrated clock signal CKCOL0_CAL1B may be a signal obtained by delaying or not delaying the clock signal CKCOL0 input to the compensation circuit 1600 according to the delay control signal DELAY_CTR0.

[0098] Therefore, the output control signal OUTPUT_CTR0 may be output based on the calibrated clock signal CKCOL0_CAL1B in the memory bank 0BK0. That is, the output control signal OUTPUT_CTR0 generated based on the calibrated clock signal CKCOL0_CAL1B may be different from the output control signal generated according to the uncalibrated clock signal CKCOL_B0.

[0099] That is, the clock signal CKCOL provided to the memory bank 1100 is calibrated according to the delay control signal DELAY_CTR, so that the output control signal OUTPUT_CTR generated based on the clock signal can be indirectly calibrated. Therefore, the configuration of the compensation circuit 1600 for indirectly calibrating the output control signal OUTPUT_CTR is not limited to Fig. 9 That is, various components that can input the clock signal CKCOL and the delay control signal DELAY_CTR and change the clock signal CKCOL according to the delay control signal DELAY_CTR can be used as implementation examples. In addition, although it has been Fig. 9 10 is described with respect to the compensation circuit 1600 for the memory bank 0BK0, but the compensation circuit 1600 can be similarly applied to other memory banks 1100.

[0100] Fig.10 It is shown Figure 1 A block diagram of an embodiment of a memory device is shown.

[0101] Reference Fig.10 , the memory device 100 may include a memory cell array 110 , a voltage generator 120 , an address decoder 130 , an input / output circuit 140 , and a control logic 150 .

[0102] The memory cell array 110 may include a plurality of memory blocks BLK1 to BLKz. The plurality of memory blocks BLK1 to BLKz may be connected to the address decoder 130 via row lines RL. The plurality of memory blocks BLK1 to BLKz may be connected to the input / output circuit 140 via column lines CL. In an embodiment, the row lines RL may include word lines, source selection lines, and drain selection lines. In an embodiment, the column lines may include bit lines.

[0103] Each memory block BLK of the plurality of memory blocks BLK1 to BLKz includes a plurality of memory cells MCn. In an embodiment, each memory cell MCn of the plurality of memory cells MCn may be a nonvolatile memory cell.

[0104] In any one of the plurality of memory blocks BLK1 to BLKz, word lines arranged in parallel to each other may be connected between a first selection line and a second selection line. The first selection line may be a source selection line SSL. The second selection line may be a drain selection line DSL. More specifically, the memory block BLKi may include a plurality of strings ST connected between the bit lines BL1 to BLn and the source line SL. The bit lines BL1 to BLn may be connected to the string ST, respectively, and the source line SL may be connected to the string ST in common. The string ST may be configured to be identical to each other, and therefore, the string ST connected to the first bit line BL1 will be described in detail as an example.

[0105] like Fig.10 As shown, the string ST may include a source selection transistor SST, a plurality of memory cells MC1 to MC16 connected in series, and a drain selection transistor DST, all of which are connected in series with each other between a source line SL and a first bit line BL1. A string ST may include at least one source selection transistor SST and at least one drain selection transistor DST, and the number of memory cells included in a string ST may be greater than the number of memory cells MC1 to MC16 shown in the drawings.

[0106] A source of the source selection transistor SST may be connected to a source line SL, and a drain of the drain selection transistor DST may be connected to a first bit line BL1.

[0107] Memory cells MC1 to MC16 may be connected in series between source select transistors SST and drain select transistors DST. Gates of source select transistors SST included in different strings ST may be connected to source select lines SSL. Gates of drain select transistors DST included in different strings ST may be connected to drain select lines DSL.

[0108] A gate of a transistor including one of the memory cells MC1 to MC16 may be connected to a corresponding word line among a plurality of word lines WL1 to WL16 .

[0109] A group of memory cells MC connected to the same word line WL in different strings ST may be referred to as a physical page PPG. Therefore, physical pages PPG corresponding in number to the number of word lines WL1 to WL16 may be included in the memory block BLKi.

[0110] Each memory cell MC may be configured as a single-level cell (SLC) storing one data bit, a multi-level cell (MLC) storing two data bits, a triple-level cell (TLC) storing three data bits, or a quad-level cell (QLC) storing four data bits.

[0111] The SLC can store one bit of data. One physical page PPG of the SLC can store one logical page of data. One logical page of data can include a number of data bits corresponding to the number of cells included in one physical page PPG.

[0112] MLC, TLC and QLC can store two or more bits of data. One physical page PPG can store two or more logical pages of data.

[0113] The memory cell array 110 may be configured with a plurality of memory banks, each memory bank including a plurality of memory blocks. Figure 1 The same as the memory body 1100 described in .

[0114] In an embodiment, the voltage generator 120, the address decoder 130, and the input / output circuit 140 may be collectively designated as a peripheral circuit. The peripheral circuit may drive the memory cell array 110 under the control of the control logic 150. The peripheral circuit may enable the memory cell array 110 to perform a program operation, a read operation, and an erase operation.

[0115] The voltage generator 120 may generate a plurality of operating voltages by using an external power supply voltage provided to the memory device 100. The voltage generator 120 may operate under the control of the control logic 150.

[0116] In an embodiment, the voltage generator 120 may generate an internal power supply voltage by regulating an external power supply voltage. The internal power supply voltage generated by the voltage generator 120 may be used as an operating voltage of the memory device 100.

[0117] In an embodiment, the voltage generator 120 may generate a plurality of operating voltages by using an external power supply voltage or an internal power supply voltage. The voltage generator 120 may generate various voltages required in the memory device 100. For example, the voltage generator 120 may generate a plurality of erase voltages, a plurality of program voltages, a plurality of pass voltages, a plurality of select read voltages, and a plurality of non-select read voltages.

[0118] To generate a plurality of operating voltages having various voltage levels, the voltage generator 120 may include a plurality of pumping capacitors receiving an internal power supply voltage. The voltage generator 120 may generate the plurality of operating voltages by selectively enabling the plurality of pumping capacitors under the control of the control logic 150.

[0119] The plurality of operating voltages generated by the voltage generator 120 may be provided to the memory cell array 110 by the address decoder 130 .

[0120] The address decoder 130 may be connected to the memory cell array 110 through a row line RL. The address decoder 130 may operate under the control of the control logic 150. The address decoder 130 may receive an address ADDR from the control logic 150. The address decoder 130 may decode a block address in the received address ADDR. The address decoder 130 may select at least one memory block among a plurality of memory blocks BLK1 to BLKi according to the decoded block address. The address decoder 130 may decode a row address in the received address ADDR. The address decoder 130 may select at least one word line among the word lines of the selected memory block according to the decoded row address. In an embodiment, the address decoder 130 may decode a column address in the received address ADDR. The address decoder 130 may connect the input / output circuit 140 and the memory cell array 110 to each other according to the decoded column address.

[0121] The address decoder 130 may include components such as a row decoder circuit, a column decoder circuit, and an address decoder circuit.

[0122] The input / output circuit 140 may include a plurality of page buffers. The plurality of page buffers may be connected to the memory cell array 110 through bit lines. In a programming operation, data may need to be stored in a selected memory cell according to data stored in the plurality of page buffers. In a read operation, data stored in a selected memory cell may need to be sensed through a bit line, and the sensed data may need to be stored in a page buffer.

[0123] The input / output circuit 140 may include a plurality of data compression circuits. The data compression circuits may be connected to a plurality of page buffers. More specifically, each of the data compression circuits may be connected to a page buffer connected to a memory bank corresponding to the data compression circuit. The data compression circuits may be connected to a plurality of page buffers. Figure 1 The compression circuit 1200 is the same as the compression circuit 1200 described in . When a compression read operation is performed under the control of the control logic 150 , the compression circuit 1200 may compress and output data read from the memory cell array 110 .

[0124] The input / output circuit 140 may include a plurality of first merging circuits and second merging circuits. The first merging circuit may be connected to two or more compression circuits, and the second merging circuit may be connected to two or more first merging circuits. The first merging circuit and the second merging circuit may be connected to Figure 1 The first merging circuit 1300 and the second merging circuit 1400 described in the embodiment are the same. The first merging circuit may merge and output the data output from the compression circuit, and the second merging circuit may merge and output the data output from the first merging circuit.

[0125] The input / output circuit 140 may include a delay detection circuit and a compensation circuit. The delay detection circuit may be directly / indirectly connected to the memory cell array 110 to receive an output control signal output from the memory cell array 110. In addition, the compensation circuit may be connected to the delay detection circuit and may be directly / indirectly connected to the memory cell array 110 to calibrate the output control signal output from the memory cell array 110. The delay detection circuit and the compensation circuit may be connected to the memory cell array 110. Figure 1 The delay detection circuit 1500 and the compensation circuit 1600 described in are the same. The delay detection circuit may generate and output a delay control signal by comparing an output control signal output from the memory cell array 110, and the compensation circuit may calibrate the output control signal based on the received delay control signal.

[0126] The control logic 150 may control the address decoder 130, the voltage generator 120, and the input / output circuit 140. The control logic 150 may operate in response to a command CMD transmitted from an external device. The control logic 150 may control the peripheral circuit by generating a control signal in response to the command CMD and the address ADDR. The control logic 150 may control the peripheral circuit so that the memory device 100 performs a normal read operation or a compressed read operation.

[0127] Fig.11 is a block diagram illustrating a storage device including a memory device according to an embodiment of the present disclosure.

[0128] Reference Fig.11, the storage device 50 may include a memory device 100 and a memory controller 200. The storage device 50 may be a device that stores data under the control of a host such as a mobile phone, a smart phone, an MP3 player, a laptop computer, a desktop computer, a game console, a television, a tablet PC, or an in-vehicle infotainment system. Alternatively, the storage device 50 may be a device that stores data under the control of a host that stores large amounts of data in one location, such as a server or a data center.

[0129] The memory device 50 may be manufactured as any of various types of memory devices according to a host interface as a communication scheme with a host. In addition, the memory device 50 may be manufactured as any of various package types.

[0130] The memory device 100 may store data and may operate under the control of the memory controller 200. The memory device 100 may be Figure 1 The memory device 1000 shown may alternatively be Fig.10 The memory device 100 is shown. Therefore, the memory device 100 may include: a memory cell array 110 including a plurality of memory cells; an input / output (I / O) circuit 140 connected to the memory cell array 110 and outputting data read from the memory cells; and a control logic 150 controlling peripheral circuits.

[0131] The memory cell array 110 may include a plurality of memory banks, each memory bank including a plurality of memory blocks. Each memory block may include a plurality of pages. In an embodiment, a page may be a unit for storing data in the memory device 100 or a unit for reading data stored in the memory device 100. A memory block may be a unit for erasing data.

[0132] In an embodiment, the memory device 100 may be any one of various types of volatile memory or nonvolatile memory. In this specification, for the convenience of description, it is assumed that the memory device 100 is a NAND flash memory and described.

[0133] The memory device 100 can receive a command and an address from the memory controller 200, and access the area selected by the address in the memory cell array. The memory device 100 can perform operations on the memory area selected or determined by the address portion of the command. For example, the memory device 100 can perform a write operation (programming operation), a read operation, and an erase operation. In a programming operation, the memory device 100 can program data in an area selected by an address provided together with a programming operation command or as part of a programming operation command. In a read operation, the memory device 100 can read data from an area selected by an address. In an erase operation, the memory device 100 can erase data stored in an area selected by an address.

[0134] The memory controller 200 may control the overall operations of the memory device 50 .

[0135] The memory controller 200 may run firmware (FW) when power is applied to the memory device 50. When the memory device 100 is a flash memory device, the memory controller 200 may run FW such as a flash translation layer (FTL) for controlling communication between the host and the memory device 100.

[0136] In an embodiment, the memory controller 200 may receive a logical address (LA) input from a host and convert the LA into a physical address (PA) indicating an address of a memory cell in the memory device 100 where data is to be stored or read.

[0137] The memory controller 200 may control the memory device 100 to perform a write operation, a read operation, an erase operation, etc. in response to a request from the host. In a program operation, the memory controller 200 may provide a write command, a PA, and data to the memory device 100. In a read operation, the memory controller 200 may provide a read command and a PA to the memory device 100. In an erase operation, the memory controller 200 may provide an erase command and a PA to the memory device 100.

[0138] In an embodiment, the memory controller 200 may autonomously generate commands, addresses, and data regardless of any request from the host, and transmit the commands, addresses, and data to the memory device 100. For example, the memory controller 200 may provide the memory device 100 with commands, addresses, and data for performing a program operation, a read operation, and an erase operation accompanied by wear leveling, read recycling, garbage collection, etc.

[0139] In an embodiment, the memory controller 200 may control at least two memory devices 100. The memory controller 200 may control the memory devices according to an interleaving scheme, thereby improving operation performance. The interleaving scheme may be a scheme in which operations of controlling at least two memory devices 100 overlap with each other.

[0140] In an embodiment, the memory controller 200 may include a read operation manager 210. The read operation manager 210 may control the memory device 100 to perform a compressed read operation or a normal read operation. For example, the read operation manager 210 may determine whether the memory device 100 is to perform a compressed read operation or a normal read operation, and provide a compressed read command or a normal read command to the memory device 100 according to whether the memory device 100 is to perform a compressed read operation or a normal read operation. The control logic 150 may control the peripheral circuit including the I / O circuit 140 to perform a compressed read operation or a normal read operation in response to the received command. Therefore, the data read from the memory cell array 110 may be output to the memory controller 200 through the I / O circuit 140. When the memory device 100 receives the compressed read command, the I / O circuit 140 may provide the memory controller 200 with the read data compressed by the compression operation. When the memory device 100 receives the normal read command, the I / O circuit 140 may provide the memory controller 200 with the read data without the compression operation.

[0141] In an embodiment, a compression read operation may be performed using an efficient soft sensing (ESS) scheme. The ESS scheme may be a scheme that combines and outputs compressed data while compressing data of a plurality of regions in the memory cell array 110.

[0142] Fig.12 yes Fig.11 A diagram of another embodiment of a memory controller is shown.

[0143] Reference Fig.12 , the memory controller 2000 may include a processor 2010 , an internal memory 2020 , an error checking and correction (ECC) circuit 2030 , a host interface 2040 , a buffer memory interface 2050 , and a memory interface 2060 .

[0144] The processor 2010 may perform various calculations for controlling the memory device 100 or generate various commands. When the processor 2010 receives a request from the host 400, the processor 2010 may generate a command according to the received request and transmit the generated command to a queue controller (not shown). The processor 2010 may control the next operation of the memory device 100 based on the verification result received by the memory interface 2060 from the memory device 100. In an embodiment, the processor 2010 may generate a normal read command or a compressed read command.

[0145] The internal memory 2020 may store various information required for the operation of the memory controller 2000. For example, the internal memory 2020 may include a logical and physical address mapping table.

[0146] The ECC circuit 2030 is configured to detect and correct an error of data received from the memory device 100 by using an error correction code. The processor 2010 may adjust a read voltage according to an error detection result of the ECC circuit 2030, and control the memory device 100 to perform a re-read. In an exemplary embodiment, the error correction block may be provided as a component of the memory controller 2000.

[0147] The host interface 2040 may exchange commands, addresses, data, etc. between the memory controller 2000 and the host 400. For example, the host interface 2040 may receive a request, an address, data, etc. from the host 400, and output data read from the memory device 100 to the host 400. The host interface 2040 may communicate with the host 400 using various protocols.

[0148] The buffer memory interface 2050 may transfer data between the processor 2010 and the buffer memory (not shown). The buffer memory may be used as a working memory or a cache memory of the memory controller 2000 and stores data used in the storage device. The buffer memory may be used by the processor 2010 as a read buffer, a write buffer, a mapping buffer, etc.

[0149] The memory interface 2060 may exchange commands, addresses, data, etc. between the memory controller 2000 and the memory device 100. For example, the memory interface 2060 may send commands, addresses, data, etc. to the memory device 100 through a channel, and receive data, etc. from the memory device 100. The memory interface 2060 may provide a compressed read command or a normal read command to the memory device 100 according to an instruction of the processor 2010. Therefore, the memory interface 2060 may receive compressed read data or normal read data from the memory device 100.

[0150] Fig.13is a flowchart illustrating an operating method of a memory device according to an embodiment of the present disclosure.

[0151] Reference Figure 1 and Fig.13 In operation S1301, the delay detection circuit 1500 of the memory device 1000 may generate a delay control signal DELAY_CTR based on the output control signals OUTPUT_CTR outputted from the plurality of memory banks 1100. In an embodiment, the delay detection circuit 1500 may compare the output control signals OUTPUT_CTR to generate the delay control signal DELAY_CTR. In an embodiment, the delay control signal DELAY_CTR may be generated in a training operation period of outputting dummy data in a compression read operation, but the present disclosure is not limited to this period.

[0152] In operation S1303, the compensation circuit 1600 of the memory device 1000 may calibrate the output control signal OUTPUT_CTR based on the delay control signal DELAY_CTR. In an embodiment, the compensation circuit 1600 may delay the output control signal OUTPUT_CTR based on the delay control signal DELAY_CTR to calibrate the output control signal OUTPUT_CTR.

[0153] In operation S1305 , the compression circuit 1200 of the memory device 1000 may compress the read data R.DATA provided from the memory bank 1100 , and thus, the compressed data C.DATA may be output from the compression circuit 1200 .

[0154] In operation 1307, the first merge circuit 1300 of the memory device 1000 may merge the compressed data C.DATA based on the output control signal OUTPUT_CTR calibrated in operation S1303, and the merging of the compressed data C.DATA performed by the first merge circuit 1300 may be designated as the first merge. In an embodiment, the compressed data C.DATA output from the compression circuit 1200 may be latched to the first merge circuit 1300, and when the latched data is output from the first merge circuit 1300 in response to the calibrated output control signal OUTPUT_CTR, the first merge data C.DATA may be output. st M. DATA.

[0155] In operation S1309, the second merge circuit 1400 of the memory device 1000 may merge the first merged data 1 st M.DATA, and the merged first merged data 1 performed by the second merge circuit 1400 stM.DATA may be designated as the second merge. The second merge circuit 1400 may output the first merged data 1 to the output buffer circuit 1700. st The second merged data 2 obtained by M.DATA nd M. DATA.

[0156] In operation S1311, the output buffer circuit 1700 of the memory device 1000 may merge the first merged data 1 based on the output control signal OUTPUT_CTR calibrated in operation S1303. st M.DATA. In an embodiment, the second merged data 2 outputted from the second merge circuit 1400 is nd M.DATA may be latched to the output buffer circuit 1700 , and the latched data may be output from the output buffer circuit 1700 in response to a calibrated output control signal OUTPUT_CTR.

[0157] Fig.14 is a flowchart illustrating in more detail a process of outputting a delay control signal in a method of operating a memory device according to an embodiment of the present disclosure. Fig.14 The operations shown may correspond to Fig.13 Operation S1301 is shown.

[0158] Reference Fig.13 and Fig.14 In operation S1401, the delay detection circuit 1500 of the memory device 1000 may compare output control signals output from the plurality of memory banks 1100. In an embodiment, the delay detection circuit 1500 may compare output control signals corresponding to the first merged data for performing the second merge. In an embodiment, the delay detection circuit 1500 may compare delay differences between corresponding output control signals.

[0159] In operation S1403, the delay detection circuit 1500 may generate a delay control signal based on a result obtained by comparing the output control signals. In an embodiment, the delay control signal may indicate whether the delay difference between the output control signals exceeds a predetermined range.

[0160] The generated delay control signal may be latched to the delay detection circuit 1500, and it is checked in operation S1405 whether the calibration enable signal has been received. In an embodiment, when the period of outputting dummy data in the compressed read operation is used for the training operation, a training operation completion signal indicating that the training operation has been completed, i.e., a signal indicating that the dummy data output period has ended, may be used as the calibration enable signal.

[0161] When it is checked in operation S1405 that the calibration enable signal has not been received, in operation S1407 , the delay detection circuit 1500 may maintain the latched delay control signal and repeatedly check whether the calibration enable signal has been received.

[0162] When it is checked in operation S1405 that the calibration enable signal has been received, the delay detection circuit 1500 may output a latched delay control signal in operation S1409 .

[0163] Fig.15 is a flowchart illustrating in more detail a process of generating a delay control signal in a method of operating a memory device according to an embodiment of the present disclosure. Fig.15 The operations shown may correspond to Fig.14 Operations S1401 and S1403 are shown.

[0164] Reference Fig.14 and Fig.15 , in operation S1501 , the delay detection circuit 1500 of the memory device 1000 may check whether a delay difference between a target output control signal and a comparison output control signal exceeds a predetermined range.

[0165] When it is determined in operation S1501 that the delay difference between the output control signals exceeds the predetermined range, in operation S1503, the delay detection circuit 1500 may generate a delay control signal indicating that the target output control signal needs to be delayed. When it is determined in operation S1501 that the delay difference between the output control signals does not exceed the predetermined range, in operation S1505, the delay detection circuit 1500 may generate a delay control signal indicating that the target output control signal does not need to be delayed.

[0166] Fig.16 is a flowchart illustrating an example of correcting an output control signal in a method of operating a memory device according to an embodiment of the present disclosure. Fig.16 The operations shown may correspond to Fig.13 Operation S1303 is shown.

[0167] Reference Fig.13 and Fig.16 , in operation S1601 , the compensation circuit 1600 of the memory device 1000 may receive a delay control signal output from the delay detection circuit 1500 .

[0168] In operation S1603, the compensation circuit 1600 may calibrate the clock signal to be provided to the memory bank 1100 based on the delay control signal. In an embodiment, the compensation circuit 1600 may delay or not delay the clock signal to be provided to the memory bank 1100 according to the delay control signal.

[0169] In operation S1605, the clock signal calibrated by the compensation circuit 1600 may be provided to the memory bank 1100. Therefore, in operation S1607, a calibrated output control signal may be generated based on the calibrated clock signal provided to the memory bank 1100. The calibrated output control signal may be output from the memory bank 1100 together with the read data. The calibrated output control signal may be provided to the first merging circuit 1300, the second merging circuit 1400, and / or the output buffer circuit 1700 for merging and outputting data.

[0170] That is to say, Fig.16 In the illustrated operation method, the compensation circuit 1600 calibrates the clock signal to be provided to the memory bank 1100 and generates a calibrated output control signal according to the calibrated clock signal. Therefore, the compensation circuit 1600 can indirectly calibrate the output control signal.

[0171] According to the present disclosure, a memory device and a method for operating the memory device can be provided, which can reduce or prevent a merge failure that may occur during a merge process of data when performing a compression read operation.

[0172] Although the present disclosure has been shown and described with reference to certain exemplary embodiments of the present disclosure, it will be understood by those skilled in the art that various changes in form and details may be made without departing from the spirit and scope of the present disclosure as defined by the appended claims and their equivalents. Therefore, the scope of the present disclosure should not be limited to the above exemplary embodiments, but should be determined not only by the appended claims, but also by their equivalents.

[0173] In the above-described embodiments, all steps may be selectively performed, or some steps may be omitted. In each embodiment, the steps are not necessarily performed in the order described, but may be rearranged. The embodiments disclosed in this specification and the accompanying drawings are only examples for facilitating understanding of the present disclosure, and the present disclosure is not limited thereto. That is, it is obvious to those skilled in the art that various modifications may be made based on the technical scope of the present disclosure.

[0174] On the other hand, exemplary embodiments of the present disclosure have been described in the drawings and the specification. Although specific terms are used herein, these terms are only for explaining the embodiments of the present disclosure. Therefore, the present disclosure is not limited to the above-described embodiments, but many modifications can be made within the spirit and scope of the present disclosure. It is obvious to those skilled in the art that, in addition to the embodiments disclosed herein, various modifications can also be made based on the technical scope of the present disclosure.

Claims

1. A memory device, comprising: A plurality of storage bodies, each storage body comprising a plurality of storage blocks; a plurality of compression circuits, each compression circuit being connected to at least one memory bank, each compression circuit outputting compressed data by compressing data read from the at least one memory bank; a plurality of first merging circuits, each of which receives an output control signal from at least one compression circuit, and each of which generates first merged data by merging compressed data output from the at least one compression circuit; a second merging circuit that receives the first merged data from different first merging circuits and outputs second merged data by merging the first merged data received from the different first merging circuits; a delay detection circuit receiving the output control signal and generating a delay control signal by comparing the output control signal; a compensation circuit calibrating the output control signal in response to the delay control signal; as well as An output buffer circuit latches the second merged data and outputs the second merged data in response to at least one of the output control signals.

2. The memory device according to claim 1, wherein: The delay detection circuit compares the output control signal when a training operation of outputting dummy data from the memory bank is performed.

3. The memory device according to claim 2, wherein: When the delay detection circuit receives a training operation completion signal indicating that the training operation has been completed, the delay detection circuit outputs the delay control signal.

4. The memory device according to claim 1, wherein: The delay detection circuit comprises: a delay control signal generating unit, receiving the output control signal, and generating the delay control signal based on the output control signal; and The delay control signal output circuit receives a calibration enable signal and outputs the delay control signal based on the calibration enable signal.

5. The memory device according to claim 4, wherein: The delay detection circuit compares a delay difference between output control signals corresponding to the first combined data combined by the second combining circuit.

6. The memory device according to claim 5, wherein: The delay control signal indicates whether a delay difference between the output control signals exceeds a predetermined range.

7. The memory device according to claim 6, wherein: The delay detection circuit receives a first output control signal and a second output control signal among the output control signals, and compares a signal obtained by delaying the first output control signal by the predetermined range with the second output control signal.

8. The memory device according to claim 7, wherein: The delay control signal output unit outputs the delay control signal to the compensation circuit so as to calibrate a first output control signal among the output control signals according to a comparison result.

9. The memory device according to claim 1, wherein: The output control signal is output from the memory bank based on a clock signal input to the memory bank.

10. The memory device according to claim 9, wherein: The compensation circuit delays an input signal in response to the delay control signal.

11. The memory device according to claim 10, wherein: The compensation circuit: receiving a clock signal to be provided to the memory bank, In response to the delay control signal, delaying the clock signal, and A delayed clock signal is provided to the memory bank.

12. A method of operating a memory device, comprising: generating a delay control signal based on an output control signal output from at least a portion of the plurality of memory banks; calibrating the output control signal based on the delay control signal; compressing data read from the plurality of memory banks; performing first merging of compressed data corresponding to different memory banks in a plurality of first merging circuits based on the calibrated output control signal; performing, in a second merging circuit, a second merging on the first merging data on which the first merging has been performed; as well as Based on the calibrated output control signal, second combined data on which the second combination is performed is output.

13. The method according to claim 12, wherein: Generating the delay control signal comprises: comparing the output control signal received by the delay detection circuit; and A delay control signal generated according to a result obtained by comparing the output control signals is supplied to a compensation circuit.

14. The method according to claim 13, wherein: Comparing the output control signal comprises: A delay difference between output control signals corresponding to the first merged data on which the second merge is to be performed is determined.

15. The method according to claim 13, wherein: Providing the delay control signal to the first combining circuit is performed in response to the delay detection circuit receiving a calibration enable signal.

16. The method according to claim 15, wherein: In the case of comparing the output control signals, when a training operation of outputting dummy data from the memory bank is performed, the output control signals output from the memory bank are compared.

17. The method according to claim 16, wherein: The calibration enable signal is a training completion signal indicating that the training operation has ended.

18. The method according to claim 12, wherein: Calibrating the output control signal comprises: calibrating a clock signal in response to the delay control signal and providing the calibrated clock signal to the memory bank; and Based on the calibrated clock signal, a calibrated output control signal is output from the memory bank.

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