Memory device, refresh control circuit and row hammer refresh method
By designing memory devices and refresh control circuits in DRAM, optimizing the refresh cycle, the problem of row hammer refresh interfering with normal refresh is solved, and the effect of reducing power consumption and improving performance is achieved.
Patent Information
- Application Number
- CN202410024588.8
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Priority Date
- 2023-08-08
- Filing Date
- 2024-01-08
- Publication Date
- 2025-02-18
AI Technical Summary
The existing DRAM hammer refresh cycle interferes with the normal refresh cycle, resulting in a decrease in refresh performance and increasing power consumption.
A memory device and refresh control circuit are designed to generate internal refresh commands by receiving external refresh commands, voltage divider signals and line hammer signals, optimize the refresh cycle and reduce the loss of line hammer refresh.
It effectively reduces the interference of hammer refresh on normal refresh, reduces refresh power consumption, and optimizes DRAM performance.
Smart Images
Figure CN119479722A_ABST
Abstract
Description
Technical Field
[0001] The present disclosure relates to memory technology, and in particular, to a memory device, a refresh control circuit, and a row hammer refresh method. Background Art
[0002] Dynamic Random Access Memory (DRAM) is a type of memory that stores each data bit in a separate tiny capacitor within an integrated circuit. The capacitor can be charged or discharged. DRAM requires regular refresh cycles to maintain data integrity because each data bit is stored in a separate capacitor that leaks charge over time.
[0003] Row hammer is a phenomenon in DRAM that can cause bit flips and thus memory errors. This occurs when one row of memory is accessed repeatedly, causing charge leakage in neighboring rows and potentially causing data loss or corruption in those neighboring rows. This is a security vulnerability because it can be exploited to gain unauthorized access to data.
[0004] DRAMs often incorporate row hammer protection. This mechanism involves tracking target cells and periodically refreshing victim cells. However, row hammer refresh cycles can interfere with normal refresh cycles, potentially causing refresh performance to degrade. The more row hammer refresh cycles that occur, the more severe this degradation can become. Since the refresh process consumes power, a mechanism to reduce DRAM refresh losses is needed. Summary of the invention
[0005] Therefore, the present disclosure provides a memory device, a refresh control circuit, and a row hammer refresh method, which mitigate normal refresh degradation caused by row hammer refresh and reduce row hammer refresh loss.
[0006] An embodiment of the present disclosure provides a memory device, comprising: a command decoder, which generates an external refresh command; a refresh skip voltage divider, which is coupled to the command decoder, captures the external refresh command and outputs a voltage divider signal; a row hammer circuit, which generates a row hammer signal; and a refresh control circuit, which is coupled to the command decoder, the refresh skip voltage divider and the row hammer circuit, wherein the refresh control circuit receives the external refresh command, the voltage divider signal and the row hammer signal, and generates an internal refresh command according to the external refresh command, the voltage divider signal and the row hammer signal.
[0007] An embodiment of the present disclosure provides a refresh control circuit, comprising: an AND gate, comprising a first input terminal, a second input terminal and a first output terminal; an OR gate, coupled to the AND gate, comprising a third input terminal, a fourth input terminal and a second output terminal; and an NOR gate, coupled to the OR gate, comprising a fifth input terminal, a sixth input terminal and a third output terminal, wherein the AND gate receives an external refresh command, the OR gate receives a voltage divider signal, the NOR gate receives the voltage divider signal and a row hammer signal, and the AND gate generates an internal refresh command.
[0008] The disclosed embodiment provides a row hammer refresh method, including: receiving an external refresh command, a voltage divider signal and a row hammer signal; and generating an internal refresh command according to the external refresh command, the voltage divider signal and the row hammer signal. BRIEF DESCRIPTION OF THE DRAWINGS
[0009] Figure 1 is a schematic diagram of a memory device in a first embodiment of the present disclosure;
[0010] Figure 2 is a schematic diagram of a memory device in a second embodiment of the present disclosure;
[0011] Figure 3 is a flow chart of a row hammer refresh method according to an embodiment of the present disclosure;
[0012] Figure 4 is an example of a signal timing flow chart showing a row hammer refresh in an embodiment of the present disclosure.
[0013] Description of Figure Numbers
[0014] 10, 20: memory device;
[0015] 101, 201: command decoder;
[0016] 102, 202: refresh skip voltage divider;
[0017] 103, 203: hammer circuit;
[0018] 104, 204: refresh control circuit;
[0019] 41, 42, 43: cycle;
[0020] a1, a2, a3, a4, a5, a6: input terminals;
[0021] b1, b2, b3: output terminals;
[0022] bRowHammer_ENABLE: row hammer signal;
[0023] Divider: voltage divider signal;
[0024] Divider0: voltage divider signal / low voltage divider pulse;
[0025] Divider1: voltage divider signal / high voltage divider pulse;
[0026] G1: AND gate;
[0027] G2: OR gate;
[0028] G3: NOR gate;
[0029] n, n+1, n+2, n+3, n+4: unit;
[0030] REFRESH_FINAL: internal refresh command;
[0031] REFRESH_PRE: external refresh command;
[0032] S301, S302: steps. DETAILED DESCRIPTION
[0033] The following examples are listed and described in detail with reference to the accompanying drawings, but the examples provided are not intended to limit the scope of the present invention. For ease of understanding, the same components will be described with the same symbols in the following description. In addition, the drawings are for illustrative purposes only and are not drawn to their original size. In fact, the size of various features may be increased or decreased arbitrarily for the sake of clarity.
[0034] Figure 1 is a schematic diagram of a memory device in a first embodiment of the present disclosure. Figure 1 , the memory device 10 includes a command decoder 101, a refresh skip voltage divider 102, a row hammer circuit 103, and a refresh control circuit 104. The command decoder 101 generates an external refresh command (REFRESH_PRE). The refresh skip voltage divider 102 is coupled to the command decoder 101. The refresh skip voltage divider 102 captures the external refresh command (REFRESH_PRE) and outputs a voltage divider signal (Divider). The row hammer circuit 103 generates a row hammer signal (bRowHammer_ENABLE). The refresh control circuit 104 is coupled to the command decoder 101, the refresh skip voltage divider 102, and the row hammer circuit 103. The refresh control circuit 104 receives the external refresh command (REFRESH_PRE), the voltage divider signal (Divider), and the row hammer signal (bRowHammer_ENABLE). The refresh control circuit 104 generates an internal refresh command (REFRESH_FINAL) according to the external refresh command (REFRESH_PRE), the voltage divider signal (Divider), and the row hammer signal (bRowHammer_ENABLE).
[0035] Specifically, the command decoder 101 is responsible for receiving and interpreting commands from an external controller or processor. The command decoder 101 decodes the commands and generates signals for various operations in the memory device 10. The refresh skip voltage divider 102 is an element for managing the refresh process in the memory device 10. The refresh skip voltage divider 102 determines the frequency at which the refresh operation needs to be performed based on the specifications and operating conditions of the memory device 10. Row hammer may occur when repeated access to adjacent rows in the memory array causes interference effects that can damage data or endanger system security. The row hammer circuit 103 is designed to detect and prevent such interference in the memory device 10. The refresh control circuit 104 is responsible for managing and coordinating the refresh operations in the memory device 10. The refresh control circuit 104 generates the necessary signals to initiate the refresh process with appropriate intervals, thereby ensuring that the data stored in the memory cells is periodically refreshed to prevent data loss or damage.
[0036] In one embodiment, the voltage divider signal (Divider) includes a high voltage divider pulse and a low voltage divider pulse. In one embodiment, in response to the refresh control circuit 104 receiving the high voltage divider pulse and the row hammer signal (bRowHammer_ENABLE) is not enabled, the refresh control circuit 104 transmits an external refresh command (REFRESH_PRE) to generate an internal refresh command (REFRESH_FINAL). In one embodiment, in response to the refresh control circuit 104 receiving the low voltage divider pulse and the row hammer signal (bRowHammer_ENABLE) is not enabled, the refresh control circuit 104 blocks the external refresh command (REFRESH_PRE) and the refresh control circuit 104 does not generate the internal refresh command (REFRESH_FINAL). In one embodiment, in response to the refresh control circuit 104 receiving the low voltage divider pulse (Divider0) and the row hammer signal (bRowHammer_ENABLE) is enabled, the refresh control circuit 104 transmits the external refresh command (REFRESH_PRE) to generate the internal refresh command (REFRESH_FINAL). In one embodiment, in response to refresh control circuit 104 receiving the high voltage divider pulse and the row hammer signal (bRowHammer_ENABLE) being enabled, refresh control circuit 104 blocks the external refresh command (REFRESH_PRE) and refresh control circuit 104 does not generate an internal refresh command (REFRESH_FINAL).
[0037] Figure 2 is a schematic diagram of a memory device in a second embodiment of the present disclosure. Figure 2, the memory device 20 includes a command decoder 201, a refresh skip voltage divider 202, a row hammer circuit 203, and a refresh control circuit 204. In this embodiment, the command decoder 201, the refresh skip voltage divider 202, and the row hammer circuit 203 are respectively connected to Figure 1 The command decoder 101, refresh skip voltage divider 102 and row hammer circuit 103 are the same.
[0038] exist Figure 2 In one embodiment, the refresh control circuit 204 includes a logic gate G1, a logic gate G2, and a logic gate G3. In one embodiment, the logic gate G1 is an AND gate. The logic gate G1 includes an input terminal a1, an input terminal a2, and an output terminal b1. In one embodiment, the logic gate G2 is an OR gate. The logic gate G2 is coupled to the logic gate G1. The logic gate G2 includes an input terminal a3, an input terminal a4, and an output terminal b2. In one embodiment, the logic gate G3 is an NOR gate. The logic gate G3 is coupled to the logic gate G2. The logic gate includes an input terminal a5, an input terminal a6, and an output terminal b3.
[0039] In one embodiment, logic gate G1 receives an external refresh command (REFRESH_PRE) from command decoder 201. Logic gate G2 receives a voltage divider signal (Divider1) from refresh skip voltage divider 202. Logic gate G3 receives a voltage divider signal (Divider0) from refresh skip voltage divider 202 and a row hammer signal (bRowHammer_ENABLE) from row hammer circuit 203. Logic gate G1 generates an internal refresh command (REFRESH_FINAL).
[0040] In one embodiment, the input terminal a1 of the AND gate G1 receives an external refresh command (REFRESH_PRE), the output terminal b1 of the AND gate G1 outputs an internal refresh command (REFRESH_FINAL), and the input terminal a2 of the AND gate G1 is connected to the output terminal b2 of the OR gate G2.
[0041] In one embodiment, Figure 1 The voltage divider signal referred to as (Divider) in the example includes Figure 2 , the voltage divider signal (Divider1) and the voltage divider signal (Divider0) are shown in FIG. The voltage divider signal (Divider1) is a high voltage divider pulse, and the voltage divider signal (Divider0) is a low voltage divider pulse.
[0042] In one embodiment, input terminal a3 of OR gate G2 receives the high voltage divider pulse (Divider1), and input terminal a4 of OR gate G2 is connected to output terminal b3 of NOR gate G3. In one embodiment, input terminal a5 of NOR gate G3 receives the low voltage divider pulse (Divider0), and input terminal a6 of NOR gate G3 receives the row hammer signal (bRowHammer_ENABLE).
[0043] In one embodiment, in response to the input terminal a3 of the OR gate G2 receiving the high voltage divider pulse (Divider1) and the row hammer signal (bRowHammer_ENABLE) being not enabled, the AND gate G1 passes the external refresh command (REFRESH_PRE) to generate the internal refresh command (REFRESH_FINAL). In one embodiment, in response to the input terminal a5 of the NOR gate G3 receiving the low voltage divider pulse (Divider0) and the row hammer signal (bRowHammer_ENABLE) being not enabled, the AND gate G1 blocks the external refresh command (REFRESH_PRE) and does not generate the internal refresh command (REFRESH_FINAL). In one embodiment, in response to the input terminal a5 of the NOR gate G3 receiving the low voltage divider pulse (Divider0) and the row hammer signal (bRowHammer_ENABLE) being enabled, the AND gate G1 passes the external refresh command (REFRESH_PRE) to generate the internal refresh command (REFRESH_FINAL). In one embodiment, in response to the input a3 of the OR gate G2 receiving the high voltage divider pulse (Divider1) and the row hammer signal (bRowHammer_ENABLE) being enabled, the AND gate G1 blocks the external refresh command (REFRESH_PRE) and does not generate the internal refresh command (REFRESH_FINAL).
[0044] Figure 3 1 is a flow chart of a row hammer refresh method according to an embodiment of the present disclosure. In step S301, an external refresh command, a voltage divider signal, and a row hammer signal are received. In step S302, an internal refresh command is generated according to the external refresh command, the voltage divider signal, and the row hammer signal. In one embodiment, the voltage divider signal includes a high voltage divider pulse and a low voltage divider pulse.
[0045] In one embodiment, in response to receiving a high voltage divider pulse and the row hammer signal is not enabled, an external refresh command is passed to generate an internal refresh command. In one embodiment, in response to receiving a low voltage divider pulse and the row hammer signal is not enabled, an external refresh command is blocked and an internal refresh command is not generated. In one embodiment, in response to receiving a low voltage divider pulse and the row hammer signal is enabled, an external refresh command is passed to generate an internal refresh command. In one embodiment, in response to receiving a high voltage divider pulse and the row hammer signal is enabled, an external refresh command is blocked and an internal refresh command is not generated.
[0046] In view of the above embodiments, the present disclosure optimizes the performance of DRAM cells by reducing the power consumption associated with refresh cycles. When the DRAM cells exhibit minimal leakage current, there is an opportunity to skip external refresh commands and therefore save refresh power. It is worth noting that when refresh skip is implemented, the normal refresh degradation caused by row hammer becomes more severe. The present disclosure alleviates the problem through a row hammer refresh mechanism that operates during the refresh skip cycle. This mechanism ensures that the normal refresh cycle is maintained while eliminating any potential losses caused by row hammer refresh. Specifically, this mechanism is implemented by the refresh control circuit 104 to control the internal refresh commands accordingly.
[0047] During the row hammer not enabled state (ie, the row hammer signal bRowHammer_ENABLE is "1"), when the voltage divider signal is "1" (Divider1), the external refresh command (REFRESH_PRE) is passed to the internal refresh command (REFRESH_FINAL), thereby ensuring that the normal refresh cycle proceeds as expected. On the other hand, when the voltage divider pulse is "0" (Divider0), the external refresh command (REFRESH_PRE) signal is blocked, preventing the generation of the internal refresh command (REFRESH_FINAL).
[0048] During the row hammer enabled state (i.e., the row hammer signal bRowHammer_ENABLE is "0"), the external refresh command is passed to the internal refresh command (REFRESH_FINAL) only when the voltage divider signal is "0" (Divider0). The row hammer refresh is only performed when the voltage divider signal is "1" (Divider1), which means that the normal refresh cycle will not be interfered by the row hammer refresh, thereby reducing loss.
[0049] Figure 4 FIG. 1 is an example of a signal timing flow chart showing a row hammer refresh in an embodiment of the present disclosure. Figure 4The timing flow shown in FIG. 4 provides a detailed description of the row hammer refresh of cell n, cell n+1, cell n+2, cell n+3, and cell n+4 in the embodiments of the present disclosure. Taking cell n+3 as the target cell as an example, the row hammer refresh address (target+1, target-1) is specifically calibrated and executed only during the "refresh skip" cycle (see cycle 42 and cycle 43) when the row hammer is enabled (i.e., the row hammer signal bRowHammer_ENABLE is "0") and the voltage divider output is "0" (Divider0). In addition, during the period when the row hammer is not enabled (i.e., the row hammer signal bRowHammer_ENABLE is "1"), such as cycle 41, only normal refresh is executed, and row hammer refresh is not executed. Therefore, there is no interference with normal refresh during this process, thereby reducing loss.
[0050] The present disclosure optimizes the performance of DRAM cells by reducing refresh power consumption while mitigating degradation caused by row hammer. By implementing a refresh skip mechanism when the leakage current in the DRAM cells is low, external refresh commands can be skipped internally, thereby saving power. To address potential degradation caused by row hammer during a normal refresh cycle, a row hammer refresh is performed during a refresh skip cycle so that the normal refresh cycle remains intact while reducing any losses associated with the row hammer. A refresh control circuit is introduced to control external refresh commands and internal refresh commands based on a voltage divider signal pulse. In addition, during a row hammer enabled state, external refresh commands are allowed only during specific conditions to avoid normal refresh losses and thus effectively reduce refresh power consumption while maintaining data integrity.
[0051] Examples of the memory device 10 or the memory device 20 include random access memory (RAM), such as dynamic RAM (DRAM) or static RAM (SRAM), which is commonly used in computers, laptops, and servers for fast data access; flash memory found in USB flash drives, solid-state drives (SSDs), and memory cards, which provides non-volatile storage for portable devices; read-only memory (ROM), such as firmware in computers and game consoles, which stores permanent pre-recorded data; cache memory, such as L1 cache and L2 cache, which is used in computer systems to store frequently accessed data closer to the processor for faster access; graphics memory (VRAM) in graphics cards and GPUs, which is dedicated to storing graphics data for smooth image rendering; and high-speed disk cache, which acts as a buffer between main memory and the hard disk drive, storing frequently accessed data.
[0052] Examples of command decoders 101 and 201 in a DRAM include dedicated circuitry or logic designed to receive and interpret commands from a memory controller. This circuitry may include multiplexers, decoders, and control logic that analyze incoming command signals and determine the appropriate memory operation to be performed (e.g., read, write, or refresh). The circuitry may also include timing circuits to synchronize the execution of commands with the DRAM's internal clock. Command decoders 101 and 201 enable the DRAM to efficiently process and execute commands from a memory controller, thereby facilitating seamless interaction between a processor or system and a memory subsystem.
[0053] Examples of refresh skip voltage dividers 102 and refresh skip voltage dividers 202 in DRAM include frequency dividers. A frequency divider is a circuit that takes an input clock signal and produces an output clock signal with a reduced frequency. In the case of a refresh skip voltage divider, it is used to determine the frequency at which a refresh operation needs to be performed in the DRAM. By dividing the frequency of the input clock signal, the refresh skip voltage divider can control the rate at which the refresh process occurs, thereby optimizing the rate of the refresh process based on the specifications and operating conditions of the memory.
[0054] An example of row hammer circuit 103 and row hammer circuit 203 comprises a dedicated hardware circuit integrated into a memory controller. This circuit can monitor memory access patterns and detect repeated accesses to adjacent rows within a memory array. Upon identifying such patterns, the row hammer circuit intervenes by dynamically reordering or delaying memory access requests to prevent the row hammer effect. An example of row hammer circuit 103 and row hammer circuit 203 can utilize techniques such as row isolation or forced refresh cycles to mitigate disturbances caused by repeated row accesses. In addition, an example of row hammer circuit 103 and row hammer circuit 203 can work with software-based mitigation techniques to further enhance protection against row hammer vulnerabilities.
[0055] Although the present invention has been disclosed as above by way of embodiments, it is not intended to limit the present invention. Any person skilled in the art may make some changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be determined by the following claims.
Claims
1. A memory device, comprising: Command decoder, generates external refresh commands; a refresh skip voltage divider, coupled to the command decoder, capturing the external refresh command and outputting a voltage divider signal; A hammer circuit generates a hammer signal; as well as A refresh control circuit is coupled to the command decoder, the refresh skip voltage divider and the row hammer circuit, wherein: The refresh control circuit receives the external refresh command, the voltage divider signal and the hammer signal, and The refresh control circuit generates an internal refresh command according to the external refresh command, the voltage divider signal and the hammer signal.
2. The memory device of claim 1, wherein the voltage divider signal comprises a high voltage divider pulse and a low voltage divider pulse.
3. The memory device according to claim 2, wherein In response to the refresh control circuit receiving the high voltage divider pulse and the row hammer signal being inactive, the refresh control circuit passes the external refresh command to generate the internal refresh command.
4. The memory device according to claim 2, wherein In response to the refresh control circuit receiving the low voltage divider pulse and the row hammer signal being inactive, the refresh control circuit blocks the external refresh command and the refresh control circuit does not generate the internal refresh command.
5. The memory device of claim 2, wherein In response to the refresh control circuit receiving the low voltage divider pulse and the row hammer signal being enabled, the refresh control circuit passes the external refresh command to generate the internal refresh command.
6. The memory device of claim 2, wherein In response to the refresh control circuit receiving the high voltage divider pulse and the row hammer signal being enabled, the refresh control circuit blocks the external refresh command and the refresh control circuit does not generate the internal refresh command.
7. A refresh control circuit, comprising: An AND gate, comprising a first input terminal, a second input terminal and a first output terminal; an OR gate, coupled to the AND gate, comprising a third input terminal, a fourth input terminal, and a second output terminal; and A NOR gate, coupled to the OR gate, includes a fifth input terminal, a sixth input terminal and a third output terminal, wherein The AND gate receives an external refresh command, The OR gate receives the voltage divider signal, The NOR gate receives the voltage divider signal and the hammer signal, and The AND gate generates an internal refresh command.
8. The refresh control circuit according to claim 7, wherein The first input terminal of the AND gate receives the external refresh command, The first output terminal of the AND gate outputs the internal refresh command, and The second input terminal of the AND gate is connected to the second output terminal of the OR gate. 9 . The refresh control circuit of claim 8 , wherein the voltage divider signal comprises a high voltage divider pulse and a low voltage divider pulse.
10. The refresh control circuit according to claim 9, wherein The third input terminal of the OR gate receives the high voltage divider pulse, The fourth input terminal of the OR gate is connected to the third output terminal of the NOR gate, The fifth input terminal of the NOR gate receives the low voltage divider pulse, and The sixth input terminal of the NOR gate receives the hammer signal.
11. The refresh control circuit according to claim 10, wherein In response to the third input of the OR gate receiving the high voltage divider pulse and the row hammer signal being inactive, the AND gate passes the external refresh command to generate the internal refresh command.
12. The refresh control circuit according to claim 10, wherein In response to the fifth input of the NOR gate receiving the low voltage divider pulse and the row hammer signal being inactive, the AND gate blocks the external refresh command and does not generate the internal refresh command.
13. The refresh control circuit according to claim 10, wherein In response to the fifth input of the NOR gate receiving the low voltage divider pulse and the row hammer signal being inactive, the AND gate passes the external refresh command to generate the internal refresh command.
14. The refresh control circuit according to claim 10, wherein In response to the third input of the OR gate receiving the high voltage divider pulse and the row hammer signal being inactive, the AND gate blocks the external refresh command and does not generate the internal refresh command.
15. A row hammer refresh method, comprising: Receive external refresh commands, voltage divider signals and hammer signals; as well as An internal refresh command is generated according to the external refresh command, the voltage divider signal and the hammer signal. 16 . The row hammer refresh method of claim 15 , wherein the voltage divider signal comprises a high voltage divider pulse and a low voltage divider pulse.
17. The row hammer refresh method according to claim 16, further comprising: In response to receiving the high voltage divider pulse and the row hammer signal being inactive, the external refresh command is passed to generate the internal refresh command.
18. The row hammer refresh method according to claim 16, further comprising: In response to receiving the low voltage divider pulse and the row hammer signal being inactive, the external refresh command is blocked and the internal refresh command is not generated.
19. The row hammer refresh method according to claim 16, further comprising: In response to receiving the low voltage divider pulse and the row hammer signal being enabled, the external refresh command is passed to generate the internal refresh command.
20. The row hammer refresh method according to claim 16, further comprising: In response to receiving the high voltage divider pulse and the row hammer signal being enabled, the external refresh command is blocked and the internal refresh command is not generated.