An operating method of a nonvolatile ovonic threshold switch memory, and an operating device and a storage system thereof

Abstract

The present application belongs to the technical fields of information storage, and discloses an operating method of a nonvolatile ovonic threshold switch memory, an operating device thereof and a storage system. The method comprises a write operation and a read operation. The write operation comprises: when a reset logic state needs to be rewritten into any set logic state, a positive conduction voltage pulse corresponding to the logic state to be written is applied; when any set logic state needs to be rewritten into a reset logic state, a negative conduction voltage pulse corresponding to the logic state to be written is applied; and when any set logic state needs to be rewritten into another set logic state, a negative conduction voltage pulse is applied first, and then a positive conduction voltage pulse corresponding to the logic state to be written is applied. The read operation comprises: applying the same subthreshold voltage, reading the current or resistance to identify the logic state stored. Based on the above write and read operations, multi-value storage of the memory can be realized, and the number of logic states can be expanded.

Description

TECHNICAL FIELD

[0001] The present application belongs to the technical field related to information storage, and more particularly, to an operating method of a non-volatile ovonic threshold switch memory, and an operating device and a storage system thereof. BACKGROUND

[0002] Dynamic Random Access Memory (DRAM) has been the main memory of computer storage architecture for the past few decades due to its advantages of speed and storage density. However, as the technology node enters 20nm, DRAM is approaching the physical limit of size scaling due to the reduction of capacitance and the increase of transistor leakage current caused by size scaling, and the complex process and high cost required for further scaling of DRAM also cause the cost benefit of scaling to gradually saturate, forming a barrier in physical size and cost and causing a "scaling wall".

[0003] Therefore, it is necessary to design a new type of memory that can achieve smaller process size while matching the access speed of DRAM. The Ovonic Threshold Switch (OTS) has the characteristics of fast switching speed, low process cost, and easy three-dimensional stacking, and as a storage unit, it can match the DRAM application scenario in speed and density. Currently, there are corresponding schemes for non-volatile storage of information based on controllable threshold voltage changes of the Ovonic Threshold Switch. The common approach is to apply a forward conduction voltage and a negative conduction voltage to distinguish between high and low resistance, and high resistance and low resistance can correspond to two different states. However, based on the existing scheme, only two states can be switched, and the limited state storage of each storage unit limits the bit density of the storage array, and it is not easy to apply in the field of large-scale in-memory computing.

[0004] Therefore, it is necessary to provide a multi-value access operation method based on a non-volatile ovonic threshold switch memory, so as to realize a new type of memory array with high bit storage density. SUMMARY

[0005] In view of the above defects or improvement needs of the prior art, the present application provides an operating method of a non-volatile ovonic threshold switch memory, and an operating device and a storage system thereof, which aims to realize three or more multi-value accesses by improving the operating method.

[0006] To achieve the above-mentioned purpose, the present application provides an operating method of a non-volatile ovonic threshold switch memory, which includes a write operation and a read operation.

[0007] The write operation comprises: obtaining a logic state to be written, and applying a turn-on voltage pulse to the corresponding memory according to a mapping relationship; the mapping relationship at least stipulates three different logic states and corresponding turn-on voltage pulses, different logic states correspond to different turn-on voltage pulses, one of which is a reset logic state and corresponds to a negative turn-on voltage pulse, and the remaining logic states are set logic states and different set logic states correspond to positive turn-on voltage pulses of different amplitudes; when it is necessary to rewrite the reset logic state into any set logic state, a positive turn-on voltage pulse corresponding to the logic state to be written is applied to the memory; when it is necessary to rewrite any set logic state into the reset logic state, a negative turn-on voltage pulse corresponding to the logic state to be written is applied to the memory; when it is necessary to rewrite any set logic state into another set logic state, a negative turn-on voltage pulse is first applied to the memory, and then a positive turn-on voltage pulse corresponding to the logic state to be written is applied to the memory;

[0008] The read operation comprises: applying the same sub-threshold voltage to the memory, reading the current or resistance thereof to identify the logic state stored therein; under the same sub-threshold voltage, the memory with a set logic state has a higher resistance than the memory with a reset logic state, and the greater the amplitude of the positive turn-on voltage pulse applied during the write operation, the greater the resistance of the resulting memory under the same sub-threshold voltage; the sub-threshold voltage is less than the threshold voltage of the memory in all set logic states.

[0009] In an optional embodiment, different logic states represent different binary logic values.

[0010] In an optional embodiment, the mapping relationship stipulates four different logic states, divided into one reset logic state and three set logic states.

[0011] In an optional embodiment, the memory in different logic states has different threshold voltages, and the threshold window between adjacent threshold voltages is greater than 0.4V.

[0012] In an optional embodiment, the memory comprises a first metal electrode layer, a threshold switching layer, and a second metal electrode layer stacked in sequence, the threshold switching layer comprises a chalcogenide semiconductor material, and the chalcogenide semiconductor material comprises one or more of Ge, Se, Te, S, and As elements.

[0013] In an optional embodiment, the chalcogenide semiconductor material comprises a doping element, the doping element comprises one or more of C, Si, N, Sb, B, O, Al, Ga, In, and Sn elements, and the doping proportion of the doping element is not more than 60%;

[0014] In an optional embodiment, the threshold switching layer is doped Ge x Se 1-x , x is 0.2≤x≤0.8, the doping element includes one of In element and B element and mixed doping of both, and the doping ratio is between 1% and 20%.

[0015] The application further provides an operating device of the nonvolatile threshold switching memory, comprising a memory and a processor, the memory stores a computer program, wherein the processor executes the computer program to realize the steps of the above method.

[0016] The application further provides a storage system, comprising a storage array and an operating device, the storage array contains the nonvolatile threshold switching memory arranged in an array, and the operating device is the operating device of the nonvolatile threshold switching memory.

[0017] The application further provides a computer readable storage medium, which stores a computer program, and the computer program is executed by a processor to realize the steps of the above method.

[0018] Overall, compared with the prior art, the above technical scheme conceived by the application mainly has the following beneficial effects:

[0019] 1. The application improves the operation method of the memory. In the writing stage, different pulse voltages are applied according to the mapping relationship, and the mapping relationship at least stipulates three different logic states and the corresponding conduction voltage pulses. Different logic states correspond to different conduction voltage pulses. The logic state obtained by applying a negative conduction voltage is called a reset logic state, and the logic state obtained by applying a positive conduction voltage is called a set logic state. The mapping relationship sets a reset logic state and at least two set logic states. The amplitudes of the positive conduction voltage pulses corresponding to different set logic states are different. When performing a write operation, the corresponding conduction voltage pulse is applied according to the logic state to be written, so that the memory is turned on, and the write of the logic state is realized. The applied conduction voltage pulse is different, the conduction threshold voltage of the memory is different, the corresponding logic state is different, and the conduction threshold voltage in the set logic state is greater than the conduction threshold voltage in the reset logic state. The greater the amplitude of the conduction voltage pulse, the greater the conduction threshold voltage of the obtained memory. Therefore, by applying different conduction voltages in the writing stage, the memory can have different conduction threshold voltages corresponding to different logic states. The memory with different conduction threshold voltages has different resistances at the same sub-threshold voltage, which is called sub-threshold resistance, and the sub-threshold resistance and the conduction threshold voltage have a positive correlation. Therefore, the current or resistance of the memory can be read at the same sub-threshold voltage, and the logic state stored therein can be identified. Therefore, based on the above write and read operations, multi-value storage of the memory can be realized, the number of logic states can be expanded, and higher bit density storage can be realized.

[0020] At the same time, for the non-volatile threshold switch memory with multiple logic states, the application adopts a reading method that does not cause threshold conduction. Based on the corresponding relationship between the threshold voltage and the sub-threshold resistance, the reading of the sub-threshold resistance is converted, thereby realizing the non-destructive multi-value reading, and compared with the reading method of the traditional threshold switch memory, the power consumption of the reading operation is reduced.

[0021] 2. In an optional embodiment, the threshold window between adjacent threshold voltages is greater than 0.4V, which can ensure that different logic states have a certain degree of differentiation, so that the data access is more accurate.

[0022] 3. In an optional embodiment, the threshold switch layer of the memory is doped Ge x Se 1-x When the applied voltage is different, the threshold window of the conduction threshold voltage is larger, thereby realizing accurate storage of different logic states. BRIEF DESCRIPTION OF DRAWINGS

[0023] Figure 1is a step flow chart of an operating method of a nonvolatile ovonic threshold switch memory in an embodiment of the present application;

[0024] Figure 2 is a voltage-current curve of a memory in different logic states in an embodiment of the present application;

[0025] Figure 3 is a voltage-current curve of a memory in a certain logic state in an embodiment of the present application;

[0026] Figure 4 is a distribution diagram of a threshold voltage and a subthreshold resistance of a memory in an embodiment of the present application;

[0027] Figure 5 is a current output result of a memory with different logic states at the same threshold voltage in an embodiment of the present application;

[0028] Figure 6 is a structural schematic diagram of a memory in an embodiment of the present application. DETAILED DESCRIPTION

[0029] In order to make the objectives, technical solutions and advantages of the present application clearer, the present application is further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and do not limit the present application. In addition, the technical features involved in each embodiment of the present application described below can be combined with each other as long as they do not conflict with each other.

[0030] Embodiment 1

[0031] As Figure 1 is a step flow chart of an operating method of a nonvolatile ovonic threshold switch memory in an embodiment of the present application, which includes a write operation and a read operation. It can be understood that the specific operation is selected according to the instruction. When a write instruction is received, the write operation is performed, and when a read instruction is received, the read operation is performed. Each operation is described in detail below.

[0032] Step S1: Obtain the logic state to be written, and apply a conduction voltage pulse to the corresponding memory according to the mapping relationship; when it is needed to rewrite the reset logic state to any set logic state, a positive conduction voltage pulse corresponding to the logic state to be written is applied to the memory; when it is needed to rewrite any set logic state to the reset logic state, a negative conduction voltage pulse corresponding to the logic state to be written is applied to the memory; when it is needed to rewrite any set logic state to another set logic state, a negative conduction voltage pulse is first applied to the memory, and then a positive conduction voltage pulse corresponding to the logic state to be written is applied to the memory.

[0033] The mapping relationship stipulates at least three different logic states and corresponding conduction voltage pulses, different logic states correspond to different conduction voltage pulses, one logic state is a reset logic state and corresponds to a negative conduction voltage pulse, and the remaining logic states are set logic states and different set logic states correspond to positive conduction voltage pulses of different amplitudes.

[0034] Step S2: Apply the same subthreshold voltage to the memory, read the current or resistance thereof to identify the logic state stored therein. At the same subthreshold voltage, the memory with a set logic state has a higher resistance than the memory with a reset logic state, and the greater the amplitude of the positive conduction voltage pulse applied during the write operation, the greater the resistance of the resulting memory at the same subthreshold voltage.

[0035] The subthreshold voltage is less than the threshold voltage of the memory in all set logic states.

[0036] In the above operation, step S1 corresponds to a write operation, and step S2 corresponds to a read operation.

[0037] Specifically, before the write operation, the mapping relationship is determined in advance, which determines the conduction voltage to be applied to the memory when writing different logic states. Understandably, the memory has a positive conduction voltage and a negative conduction voltage, and the polarities of the applied voltages are opposite. In the present application, the mapping relationship stipulates at least three different logic states and corresponding conduction voltage pulses, different logic states correspond to different conduction voltage pulses, and different conduction voltage pulses can be different in polarity or amplitude. The logic states can be divided into reset logic states and set logic states according to the difference in polarity of the conduction voltage, wherein the logic state obtained by applying a negative conduction voltage is referred to as a reset logic state, and the logic state obtained by applying a positive conduction voltage is referred to as a set logic state. In the present application, one reset logic state and at least two set logic states are provided, and the amplitudes of the positive conduction voltage pulses corresponding to different set logic states are different.

[0038] In actual writing, operations are performed according to different situations:

[0039] Case one: when the reset logic state needs to be rewritten as any set logic state, a positive conduction voltage pulse corresponding to the logic state to be written is applied to the memory;

[0040] Case two: when any set logic state needs to be rewritten as a reset logic state, a negative conduction voltage pulse corresponding to the logic state to be written is applied to the memory;

[0041] Case three, when any set logic state needs to be rewritten to another set logic state, first apply a negative turn-on voltage pulse to the memory, and then apply a positive turn-on voltage pulse corresponding to the logic state to be written.

[0042] Case one refers to the current state of the memory as a reset logic state, that is, the last time the memory is stored as a negative turn-on voltage pulse, that is, the memory is currently in a negative turn-on state, at this time, if a set logic state is needed to be written, only the positive turn-on voltage pulse corresponding to the logic state to be written is needed to be applied to the memory, so that it is positively turned on.

[0043] Case two refers to the current state of the memory as a set logic state, that is, the last time the memory is stored as a positive turn-on voltage pulse, that is, the memory is currently in a positive turn-on state, at this time, if a reset logic state is needed to be written, only the negative turn-on voltage pulse corresponding to the logic state to be written is needed to be applied to the memory, so that it is negatively turned on.

[0044] Case three refers to the current state of the memory as a set logic state, that is, the last time the memory is stored as one of the positive turn-on voltage pulses, and the memory is in a positive turn-on state, at this time, if another set logic state is needed to be written, a negative turn-on voltage pulse needs to be applied to the memory to make it negatively turned on, and then a positive turn-on voltage pulse corresponding to the logic state to be written is applied to the memory to make it positively turned on again.

[0045] When writing, no matter which logic is written, a turn-on voltage pulse needs to be applied to turn on the memory, and different turn-on voltage pulses are applied to make the memory have different logic states. When the positive and negative turn-on polarities are different, the resistance of the memory at the same sub-threshold voltage will be significantly different, thereby distinguishing the reset logic state and the set logic state; when the amplitudes of the positive turn-on voltage pulses are different, the turn-on threshold voltage of the memory after turn-on will be different, and the voltage-current curve of the memory will also be different. The greater the amplitude of the positive turn-on voltage pulse, the greater the turn-on threshold voltage of the memory after turn-on, and the greater the resistance at the same sub-threshold voltage, thereby distinguishing different set logic states.

[0046] Therefore, before reading, a suitable sub-threshold voltage needs to be determined as the reading voltage, and the application selects a sub-threshold voltage as the reading voltage, which is less than the threshold voltage of the memory in all set logic states. When the same sub-threshold voltage is applied to the memory, the resistances of the memory in different logic states are different. For different polarities of logic states, the resistance of the memory in the set logic state is greater than the resistance of the memory in the reset logic state. For different set logic states, the greater the amplitude of the positive conduction voltage pulse applied during the writing operation, that is, the greater the conduction threshold voltage in the set logic state, the greater the resistance of the memory at the sub-threshold voltage. Therefore, the current or resistance at the same sub-threshold voltage can be read to identify the logic state stored therein. Regarding the specific selection of the positive threshold voltage, the sub-threshold voltage with the largest discrimination can be selected as the positive threshold voltage according to experiments.

[0047] In a specific embodiment, different logic states can be used to represent different binary logic values. For example, for commonly used two-bit binary values 00, 01, 10, and 11, four different logic states can be set, including one reset logic state and three set logic states, each of which corresponds to a binary value. For example, the reset logic state represents 11, the first set logic state represents 10, the second set logic state represents 01, and the third set logic state represents 00. The reset logic state corresponds to a negative conduction voltage pulse, the first logic state corresponds to a first positive conduction voltage pulse, for example, 4V, the second logic state corresponds to a second positive conduction voltage pulse, for example, 6V, and the third logic state corresponds to a third positive conduction voltage pulse, for example, 8V. The operation method of this embodiment is described below:

[0048] When the memory is currently in the reset logic state 11, if the first set logic state 10 needs to be written, the first positive conduction voltage pulse 4V is applied; if the second set logic state 01 needs to be written, the second positive conduction voltage pulse 6V is applied; and if the third set logic state 00 needs to be written, the third positive conduction voltage pulse 8V is applied.

[0049] When the memory is currently in the first set logic state 10, or in the second set logic state 01, or in the third set logic state 00, if the reset logic state 11 needs to be written, a negative conduction voltage is applied, which satisfies the condition of enabling the memory to conduct negatively.

[0050] When the memory is currently in the first set logic state 10, if the second set logic state 01 needs to be written, a negative conduction voltage pulse is first applied to the memory, and then a second positive conduction voltage pulse of 6V is applied to it; if the third set logic state 00 needs to be written, a negative conduction voltage pulse is first applied to the memory, and then a third positive conduction voltage pulse of 8V is applied to it.

[0051] When the memory is currently in the second set logic state 01, if the first set logic state 10 needs to be written, a negative conduction voltage pulse is first applied to the memory, followed by a first positive conduction voltage pulse of 4V; if the third set logic state 00 needs to be written, a negative conduction voltage pulse is first applied to the memory, followed by a third positive conduction voltage pulse of 8V.

[0052] When the memory is currently in the third set logic state 00, if the first set logic state 10 needs to be written, a negative conduction voltage pulse is first applied to the memory, followed by a first positive conduction voltage pulse of 4V; if the second set logic state 01 needs to be written, a negative conduction voltage pulse is first applied to the memory, followed by a second positive conduction voltage pulse of 6V.

[0053] Memory in different logic states has different threshold voltages. In some preferred embodiments, the threshold window between adjacent threshold voltages is greater than 0.4V to ensure that different logic states have a certain degree of distinguishability. Figure 2 The figure shows the voltage-current curves of the memory in one embodiment under different logic states, where V th,11 V is the turn-on threshold voltage in the reset logic state. th,10 V is the turn-on threshold voltage in the first set logic state. th,01 V is the turn-on threshold voltage under the second set logic state. th,00 This refers to the turn-on threshold voltage under the third set logic state. It can be seen that the turn-on threshold voltage of the memory differs somewhat under different logic states. Figure 2 In the middle, V th,11 With V th,10 There is a threshold window of 0.5V between them, V th,10 With V th,01 There is a threshold window of 0.5V between them, V th,01 With V th,00 There is a threshold window of 1.8V between them, which confirms that there are obvious differences between the four threshold states, and can be used as the basis for accessing data in the four logic states.

[0054] like Figure 3Fig. 1 shows a voltage-current curve of a memory in a logic state in an embodiment, in each logic state, the memory corresponds to a voltage-current curve, and the turn-on threshold voltage is V th In the present application, a sub-threshold voltage is taken as the read voltage, which is less than the turn-on threshold voltage, and the resistance at the same sub-threshold voltage has a certain positive correlation with the threshold voltage, such as Figure 4 Fig. 2 shows a relationship distribution diagram of the threshold voltage and the sub-threshold resistance of the memory in an embodiment, from which it can be seen that the memory with a larger threshold voltage has a higher resistance value (referred to as sub-threshold resistance) under the same sub-threshold voltage value, and the sub-threshold resistance also has a clear distinction in the four logic states with a clear distinction in the threshold voltage, further confirming that the sub-threshold resistance reading scheme proposed in the present application can distinguish multiple threshold states.

[0055] As shown in Fig. 3, the memory in an embodiment has different logic states, and the current output results under the same threshold voltage are shown, the read voltage amplitude used is 1V, and the output currents corresponding to the logic states 11, 10, 01 and 00 are 155nA, 10nA, 0.59nA and 0.26nA, respectively, which decrease in turn, and through multiple cycle tests of the sub-threshold voltage difference between different states, it is confirmed that the sub-threshold resistance of different logic states has a relatively stable resistance difference. Figure 5 As shown in Fig. 3, the memory in an embodiment has different logic states, and the current output results under the same threshold voltage are shown, the read voltage amplitude used is 1V, and the output currents corresponding to the logic states 11, 10, 01 and 00 are 155nA, 10nA, 0.59nA and 0.26nA, respectively, which decrease in turn, and through multiple cycle tests of the sub-threshold voltage difference between different states, it is confirmed that the sub-threshold resistance of different logic states has a relatively stable resistance difference.

[0056] Figure 6 Fig. 4 shows a structural schematic diagram of the memory in an embodiment of the present application, which includes a first metal electrode layer 100, a threshold switch layer 200 and a second metal electrode layer 300 stacked in sequence, the threshold switch layer 200 contains a chalcogenide semiconductor material, and the chalcogenide semiconductor material contains one or more of Ge, Se, Te, S and As elements. In some embodiments, the chalcogenide semiconductor material further includes a doping element, and the doping element contains one or more of C, Si, N, Sb, B, O, Al, Ga, In and Sn elements, and the doping ratio of the doping element ranges from 0 to 60%. For example, the threshold switch layer is doped Ge x Se 1-x , and the value of x is 0.2≤x≤0.8, the doping element includes one of In element and B element, and the doping ratio is between 1% and 20%. In some embodiments, the first metal electrode layer and the second metal electrode layer are both inert electrode materials, and the inert electrode material is at least one of W, TiW, Pt, Au, Ru, Al, TiN, Ta, TaN, IrO2, ITO and IZO.

[0057] Embodiment 2

[0058] ​The application also relates to an operating device of a nonvolatile ovonic threshold switch memory, comprising a memory and a processor, the memory storing a computer program, and the processor implementing the steps of the above method when executing the computer program.

[0059] The electronic device can be a desktop computer, a notebook computer, a palm computer, a cloud server and the like, and the processor can be a central processing unit (CPU), and can also be other general-purpose processors, digital signal processors (DSP), application specific integrated circuits (ASIC), field-programmable gate arrays (FPGA) or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components and the like. The memory can be used to store computer programs and / or modules, and the processor can implement various functions of the electronic device by running or executing the computer programs and / or modules stored in the memory, and by calling data stored in the memory.

[0060] Embodiment 3

[0061] The application also relates to a computer readable storage medium, which stores a computer program, and the computer program implements the steps of the above method when executed by a processor.

[0062] Specifically, the memory can include a high-speed random access memory, and can also include a nonvolatile memory, for example, a hard disk, a memory, a plug-in hard disk, a smart media card (SMC), a secure digital (SD) card, a flash card, at least one magnetic disk storage device, a flash memory device or other volatile solid-state memory device.

[0063] Embodiment 4

[0064] The application provides a storage system, which comprises a storage array and an operating device, the storage array contains nonvolatile ovonic threshold switch memories arranged in an array, and the operating device is the operating device of the nonvolatile ovonic threshold switch memory as in Embodiment 2.

[0065] Any combination of the technical features in the above-described embodiments can be made, and for the sake of brevity, not all possible combinations are described, however, as long as there is no conflict, any combination of the technical features should be considered within the scope of the present disclosure. It should be noted that "in an embodiment of the present application", "for example", "for instance", and the like are intended to serve as examples of the present application, and are not intended to limit the present application.

[0066] The above-described embodiments only express several implementation manners of the present application, and the description is relatively specific and detailed, but it should not be understood as a limitation on the patent application scope. It should be noted that for those skilled in the art, without departing from the concept of the present application, a number of modifications and improvements can be made, which are within the protection scope of the present application.

Claims

1. A method of operating a non-volatile ovonic threshold switch memory, comprising: Includes write and read operations; The write operation includes: acquiring the logic state to be written, and applying a conduction voltage pulse to the corresponding memory according to the mapping relationship; the mapping relationship specifies at least three different logic states and their corresponding conduction voltage pulses, with different logic states corresponding to different conduction voltage pulses, one of which is a reset logic state and corresponds to a negative conduction voltage pulse, and the remaining logic states are set logic states, with different set logic states corresponding to positive conduction voltage pulses of different amplitudes; when it is necessary to rewrite the reset logic state to any set logic state, a positive conduction voltage pulse corresponding to the logic state to be written is applied to the memory; when it is necessary to rewrite any set logic state to the reset logic state, a negative conduction voltage pulse corresponding to the logic state to be written is applied to the memory; when it is necessary to rewrite any set logic state to another set logic state, a negative conduction voltage pulse is first applied to the memory, and then a positive conduction voltage pulse corresponding to the logic state to be written is applied to it; The read operation includes: applying the same subthreshold voltage to the memory, reading its current or resistance to identify the stored logic state, wherein, under the same subthreshold voltage, the memory with a set logic state has a higher resistance than the memory with a reset logic state, and the larger the amplitude of the forward conduction voltage pulse applied during the write operation, the greater the resistance of the resulting memory under the same subthreshold voltage; the subthreshold voltage is less than the threshold voltage of the memory in all set logic states.

2. The operating method of a nonvolatile ovonic threshold switch memory according to claim 1, wherein, Different logical states represent different binary logical values.

3. The operating method of a nonvolatile ovonic threshold switch memory according to claim 1, wherein, The mapping relationship constrains four different logical states, which are divided into one reset logical state and three set logical states.

4. The method of operating a nonvolatile ovonic threshold switch memory as claimed in claim 1, wherein, The memory in different logic states has different threshold voltages, and the threshold window between adjacent threshold voltages is greater than 0.4V.

5. The method of operating a nonvolatile ovonic threshold switch memory as claimed in claim 1, wherein, The memory includes a first metal electrode layer, a threshold switch layer, and a second metal electrode layer stacked sequentially. The threshold switch layer contains a chalcogenide semiconductor material, which contains one or more of the elements Ge, Se, Te, S, and As.

6. The operating method of a nonvolatile ovonic threshold switch memory according to claim 5, wherein, The chalcogenide semiconductor material contains doping elements, which include one or more of the elements C, Si, N, Sb, B, O, Al, Ga, In, and Sn, and the doping ratio of the doping elements does not exceed 60%.

7. The operation method of the non-volatile threshold switch memory as described in claim 5, characterized in that, The threshold switch layer is doped Ge x Se 1-x , x is 0.2≤x≤0.8, the doping element includes one of In element and B element and mixed doping of both, and the doping ratio is between 1% and 20%.

8. An operating device for a non-volatile threshold switch memory, comprising a memory and a processor, wherein the memory stores a computer program, characterized in that, When the processor executes the computer program, it implements the steps of the method as described in any one of claims 1 to 7.

9. A storage system comprising a storage array and an operating device, the storage array including non-volatile threshold-switched memories arranged in an array, the operating device being the operating device for the non-volatile threshold-switched memory as described in claim 8.

10. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by a processor, it implements the steps of the method as described in any one of claims 1 to 7.

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