Memory device and operating method thereof

Abstract

A memory device and an operating method thereof are disclosed. In one embodiment, a memory device may include: a memory cell array including a plurality of memory cells, each of the plurality of memory cells configured to store a data value corresponding to read data to be read through a plurality of conductive lines; and a read circuit connected to the plurality of conductive lines to generate read data corresponding to a data value stored in a selected memory cell among the plurality of memory cells based on or according to whether there is a change in a cell current flowing through the selected memory cell during a single read cycle.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to and the benefit of Korean Patent Application No. 10-2023-0104691, filed on August 10, 2023, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] The technology disclosed in this patent relates to semiconductor design, and more particularly, to a memory device for storing data by using a variable resistance characteristic and an operating method of the memory device. Background Art

[0004] With the increasing demand for high-capacity, low-power memory devices, a large amount of research is being conducted on next-generation memory devices (such as non-volatile memory devices) that do not require refresh operations. Such next-generation memory devices need to have the high density of dynamic random access memory (DRAM) devices, the non-volatility of flash memory devices, and the high speed of static random access memory (SRAM) devices. Examples of next-generation memory devices may include phase change random access memory (PRAM), nano floating gate memory (NFGM), polymer random access memory (PoRAM), magnetic random access memory (MRAM), ferroelectric random access memory (FeRAM), and resistive random access memory (RRAM). Summary of the invention

[0005] Various embodiments of the disclosed technology relate to a memory device capable of preventing a read error when reading data from a selected memory cell, and an operating method of the memory device.

[0006] In one embodiment, a memory device may include: a memory cell array including a plurality of memory cells, each of the plurality of memory cells being configured to store a data value corresponding to read data to be read out through a plurality of conductive lines; and a read circuit coupled to the plurality of conductive lines to generate read data corresponding to the data value stored in a selected memory cell based on whether a cell current flowing through the selected memory cell among the plurality of memory cells during a single read cycle exists. In some implementations, the plurality of conductive lines may include word lines and bit lines.

[0007] In one embodiment, a memory device may include: a memory cell array including a plurality of memory cells, each of the plurality of memory cells being configured to store a data value corresponding to read data to be read out through a plurality of conductive lines; a sensing circuit coupled to the plurality of conductive lines to compare a cell current flowing through a selected memory cell among the plurality of memory cells with a reference current during a single read cycle; and a determination circuit coupled to the sensing circuit to: generate read data having a first data value in response to a comparison result of the sensing circuit indicating that the cell current has a constant level during the single read cycle; or generate read data having a second data value in response to a comparison result of the sensing circuit indicating that the cell current has an oscillating level during the single read cycle.

[0008] In one embodiment, a method for operating a memory device may include: setting a reference current to: a level lower than a cell current distribution flowing through memory cells in a low resistance state; or a level higher than a cell current distribution flowing through memory cells in a high resistance state higher than the low resistance state; performing M comparison operations to compare a cell current flowing through a selected memory cell among the memory cells with the reference current, wherein M is an integer greater than 1; and generating read data having a second data value in response to the comparison result indicating that the cell current has an oscillation level. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Figure 1 is a block diagram illustrating a memory device based on one embodiment of the disclosed technology.

[0010] Figure 2 It is a graphic Figure 1 A block diagram of an example of a memory cell array is illustrated in FIG.

[0011] Figure 3 It is a graphic Figure 2 Block diagram of memory cells, word lines, and bit lines illustrated in FIG.

[0012] Figure 4 It is a graphic Figure 1 A block diagram of an example of a read circuit is shown in FIG.

[0013] Figure 5 It is a graphic Figure 1 0047 is a block diagram of another example of a read circuit illustrated in FIG.

[0014] Figure 6 It is a graphic Figure 1 Flowchart of the operation of the memory device illustrated in FIG.

[0015] Figure 7 and Figure 8 Diagram Figure 6An example of the operation of the memory device illustrated in FIG. DETAILED DESCRIPTION

[0016] Some embodiments of the disclosed technology will be described below with reference to the accompanying drawings.

[0017] It will be understood that when an element is referred to as being "connected to" or "coupled to" another element, the element may be directly connected to or directly coupled to the other element, or electrically connected to or electrically coupled to the other element, with one or more elements interposed therebetween. In addition, it will be understood that the terms "comprises, comprising, includes, including" when used in this specification do not exclude the presence of one or more other elements, but may further include or have one or more other elements, unless otherwise mentioned. In the description throughout the specification, some components are described in the singular, but the disclosed technology is not limited thereto, and it will be understood that these components may be formed in the plural.

[0018] Magnetic random access memory (MRAM) has attracted a lot of attention due to its fast read and write speed, high durability, non-volatility, and low power consumption during operation. MRAM includes a plurality of memory cells, and each of the plurality of memory cells includes a variable resistance element. The variable resistance element may have a characteristic of switching between different resistance states in response to a change in the magnetization direction of the magnetic layer. For example, when the magnetization directions of the two magnetic layers are parallel, the variable resistance element may be in a low resistance state, and when the magnetization directions of the two magnetic layers are antiparallel, the variable resistance element may be in a high resistance state. When the variable resistance element is in the low resistance state, it is defined that a "low (0)" data bit is stored in the corresponding memory cell. When the variable resistance element is in the high resistance state, it is defined that a "high (1)" data bit is stored in the corresponding memory cell.

[0019] Figure 1 is a block diagram illustrating a memory device 100 based on one embodiment of the disclosed technology.

[0020] The memory device 100 may include a memory cell array 110 , a word line selection circuit 120 , a bit line selection circuit 130 , and a read circuit 140 .

[0021] The memory cell array 110 may include a plurality of memory cells arranged in a 2D or 3D structure. The plurality of memory cells may be connected to a plurality of word lines WLs extending in parallel in a row direction and a plurality of bit lines BLs extending in parallel in a column direction. The plurality of memory cells may be arranged at intersections between the plurality of word lines WLs and the plurality of bit lines BLs.

[0022] The word line selection circuit 120 may be connected to the memory cell array 110 through a plurality of word lines WLs. The word line selection circuit 120 may control corresponding voltages applied to the plurality of word lines WLs based on the row address XADD.

[0023] The bit line selection circuit 130 may be connected to the memory cell array 110 through a plurality of bit lines BLs. The bit line selection circuit 130 may control corresponding voltages applied to the plurality of bit lines BLs based on the column address YADD.

[0024] The read circuit 140 may be used to read out data (read data) DT from a selected memory cell among a plurality of memory cells included in the memory cell array 110. The selected memory cell may be a memory cell connected between a selected word line among a plurality of word lines WLs and a selected bit line among a plurality of bit lines BLs. The read circuit 140 may be connected to the plurality of bit lines BLs through the bit line selection circuit 130. The read circuit 140 may read a data value stored in the selected memory cell through a selected bit line among a plurality of bit lines BLs.

[0025] Based on the read enable signal RD, the read circuit 140 can generate read data DT corresponding to the data value stored in the selected memory cell based on or according to whether there is a change in the cell current IC flowing through the selected memory cell during a single read cycle. A single read cycle can be a predetermined unit read time when the read data DT is read from the selected memory cell. For example, during a single read cycle, when the cell current IC has a constant level, the read circuit 140 can generate read data DT having a first data value, and when the cell current IC has an oscillating level, the read circuit 140 can generate read data DT having a second data value. The read data DT can correspond to the resistance state of the selected memory cell. For example, the first data value can correspond to the high resistance state of the selected memory cell, and the second data value can correspond to the low resistance state of the selected memory cell.

[0026] Figure 2 It is a graphic Figure 1 A block diagram of an example of a memory cell array 110 is shown in FIG. Figure 2 A memory cell array 110 connected to first to fifth word lines WL1 to WL5 and first to fifth bit lines BL1 to BL5 is shown.

[0027] refer to Figure 2, the memory cell array 110 may include first to 25th memory cells MC. The first to 25th memory cells MC may be disposed at intersections between the first to fifth word lines WL1 to WL5 and the first to fifth bit lines BL1 to BL5, and may be connected to the corresponding word lines and the corresponding bit lines. The first to fifth word lines WL1 to WL5 may extend in parallel in the row direction and be spaced apart from each other by a predetermined interval in the column direction. The first to fifth bit lines BL1 to BL5 may extend in parallel in the column direction and be spaced apart from each other by a predetermined interval in the row direction.

[0028] Although the memory cell array 111 has the following structure as an example in the present embodiment, Figure 2 2D structure shown in FIG, but the disclosed technology is not necessarily limited thereto, and the memory cell array 110 may have a 3D structure. For example, the 3D structure may include a plurality of layers stacked in a vertical direction. Each layer may include Figure 2 The 2D structure shown in the figure.

[0029] Figure 3 It is a graphic Figure 2 2 is a block diagram of a memory cell MC# among the memory cells MC, a word line WL# among the word lines WL1 to WL5 , and a bit line BL# among the bit lines BL1 to BL5 illustrated in FIG.

[0030] refer to Figure 3 , the memory cell MC# may be disposed and connected between the corresponding word line WL# and the corresponding bit line BL#. The memory cell MC# may include a selection element SE and a variable resistance element VR connected in series between the word line WL# and the bit line BL#.

[0031] The selection element SE may be electrically connected between the word line WL# and the variable resistance element VR. The selection element SE may control the flow of current, such as the direction of the current, according to the voltage difference between its ends or the magnitude of the current flowing through it. Examples of the selection element SE may include a MOS transistor, a PN diode, and a bidirectional threshold switching (OTS) element.

[0032] The variable resistance element VR may be electrically connected between the bit line BL# and the selection element SE. According to the voltage difference between the two ends of the variable resistance element VR or the current flowing through the variable resistance element VR, the variable resistance element VR may be converted into different resistance states. For example, the variable resistance element VR may have a high resistance state or a low resistance state.

[0033] Figure 4 It is a graphic Figure 1 A block diagram of one example of a read circuit 140 is illustrated in FIG.

[0034] refer to Figure 4, the read circuit 140 may include a reference current generating circuit 141 , a sensing circuit 143 , a determining circuit 145 , and a control circuit 147 .

[0035] The reference current generating circuit 141 may generate a reference current IR during a single read cycle based on the read enable signal RD. When the selected memory cell is in a high resistance state, the reference current IR may have a level lower than the cell current IC flowing through the selected memory cell. In addition, when the selected memory cell is in a low resistance state, the reference current IR may have a current value among possible current values ​​of the cell current IC flowing through the selected memory cell. For example, when the selected memory cell is in a low resistance state, the cell current IC flowing through the selected memory cell may have an oscillation level within a predetermined swing range, and the reference current IR may have a value between the highest value and the lowest value of the predetermined swing range, such as an average value within the predetermined swing range.

[0036] The sensing circuit 143 may be connected to the plurality of bit lines BLs through the bit line selection circuit 130. Based on the first control signal CTRL1, the sensing circuit 143 may compare the cell current IC flowing through the selected memory cell with the reference current IR during a single read cycle. For example, the sensing circuit 143 may include a sense amplifier.

[0037] Based on the first control signal CTRL1, the sensing circuit 143 can compare the cell current IC with the reference current IR several times at a predetermined time interval during a single read cycle. When the cell current IC has an oscillation level, the time interval can be set according to the oscillation period of the cell current IC. The sensing circuit 143 can perform a predetermined number of comparison operations on the selected memory cell during a single read cycle, regardless of the comparison result. The sensing circuit 143 can generate a sensing signal SA according to the level (e.g., a constant level or an oscillation level) of the cell current IC.

[0038] Based on the second control signal CTRL2 and the sensing signal SA, the determination circuit 145 may generate read data DT corresponding to the level (e.g., constant level or oscillation level) of the cell current IC during a single read cycle. For example, the determination circuit 145 may generate read data DT having a first data value when the comparison result of the sensing circuit 143 indicates that the cell current IC has a constant level, and generate read data DT having a second data value when the comparison result of the sensing circuit 143 indicates that the cell current IC has an oscillation level. In other words, when the comparison results of a predetermined number of comparison operations performed by the sensing circuit 143 are the same as each other, the determination circuit 145 may generate read data DT having a first data value, and when the comparison results of a predetermined number of comparison operations performed by the sensing circuit 143 are different from each other (e.g., the comparison results are different from each other), the determination circuit 145 may generate read data DT having a second data value.

[0039] The control circuit 147 may generate the first control signal CTRL1 and the second control signal CTRL2 based on the read enable signal RD and the set information signal SI. The activation period of the read enable signal RD may correspond to a single read period. The set information signal SI may correspond to a predetermined number of comparison operations of the sensing circuit 143.

[0040] Figure 5 It is a graphic Figure 1 2 is a block diagram of another example of the read circuit 140 illustrated in FIG.

[0041] refer to Figure 5 , the reading circuit 140 may include a sensing circuit 141 , a determining circuit 143 , and a control circuit 145 .

[0042] The sensing circuit 141 may be connected to the plurality of bit lines BLs through the bit line selection circuit 130. Based on the first control signal CTRL1, the sensing circuit 141 may analyze the waveform of the cell current IC flowing through the selected memory cell during a single read cycle. For example, the sensing circuit 141 may include an oscilloscope.

[0043] Based on the first control signal CTRL1, the sensing circuit 141 may generate a sensing signal SA corresponding to an analysis result of the waveform of the cell current IC during a single read cycle. For example, the sensing circuit 141 may analyze whether the cell current IC has a constant level or an oscillating level and generate a sensing signal SA corresponding to the analysis result.

[0044] Based on the second control signal CTRL2 and the sensing signal SA, the determination circuit 143 may generate read data DT corresponding to the level (e.g., constant level or oscillating level) of the cell current IC during a single read cycle. For example, the determination circuit 143 may generate read data DT having a first data value when the analysis result of the sensing circuit 141 indicates that the cell current IC has a constant level, and generate read data DT having a second data value when the analysis result of the sensing circuit 141 indicates that the cell current IC has an oscillating level.

[0045] The control circuit 145 may generate the first control signal CTRL1 and the second control signal CTRL2 based on the read enable signal RD. An activation period of the read enable signal RD may correspond to a single read period.

[0046] In the following, reference Figures 6 to 8 The operation of the memory device 100 according to the present embodiment having the above-described configuration is described.

[0047] Figure 6 It is a graphic Figure 1 Flowchart of the operation of the memory device 100 is shown in FIG. Figure 6 The diagram includes Figure 4 2. The operation of the memory device 100 of the read circuit 140 is illustrated in FIG.

[0048] refer to Figure 6 , at S10, the reference current generating circuit 141 may generate a reference current IR. When the plurality of memory cells MC are all in a low resistance state, the reference current IR may have a level lower than the distribution of cell currents flowing through the plurality of memory cells MC ("first distribution"). In addition, when the plurality of memory cells MC are all in a high resistance state, the reference current IR may have a level higher than the distribution of cell currents flowing through the plurality of memory cells MC ("second distribution"). In other words, the reference current IR may be set to have a level between the first distribution and the second distribution.

[0049] At S12, one memory cell among the plurality of memory cells MC may be selected. The selected memory cell may be a memory cell connected between a selected word line among the plurality of word lines WLs and a selected bit line among the plurality of bit lines BLs.

[0050] At S14, the sensing circuit 143 may compare the cell current IC of the selected memory cell among the plurality of memory cells MC with the reference current IR. In this case, the sensing circuit 143 may compare the cell current IC with the reference current IR several times during a single read cycle. For example, at S16, the sensing circuit 143 may perform a comparison operation several times during a single read cycle until the number of comparison operations performed by comparing the cell current IC with the reference current IR reaches a predetermined number. For reference, when the cell current IC is compared with the reference current IR several times during a single read cycle, the sensing circuit 143 may perform a comparison operation at a predetermined time interval. It is desirable that when the cell current IC has an oscillation level, the time interval is set according to the oscillation period of the cell current IC. In one example, when the sensing circuit 143 compares the cell current IC with the reference current IR twice, the time interval may be set between 1 / 2 and 2 / 3 of the oscillation period. In another example, when the sensing circuit 143 compares the cell current IC with the reference current IR three or more times, the time interval may be set between 1 / 4 and 1 / 2 of the oscillation period.

[0051] At S18, the determination circuit 145 may generate read data DT corresponding to the comparison result of the sensing circuit 143. When the cell current IC has a constant level, the determination circuit 145 may generate read data DT having a first data value. When the cell current IC has an oscillating level, the determination circuit 145 may generate read data DT having a second data value. The first data value may be a data value corresponding to a high resistance state, and the second data value may be a data value corresponding to a low resistance state.

[0052] Figure 7 and Figure 8 It is used to describe why Figure 6 The graph of the medium cell current IC having an oscillation level. Figure 7 shows a current-voltage characteristic curve of a memory cell MC# included in the memory device 100, and Figure 8 The cell current IC is shown with an oscillating level.

[0053] refer to Figure 7 and Figure 8 , the turn-on condition of the selection element SE included in the memory cell MC# can be expressed as shown in the following equation (inequality) 1.

[0054] [Formula 1]

[0055] VC>VTH, and IC>ITH

[0056] Here, “VC” may denote a voltage at one end of the selection element SE, for example, a voltage applied to the word line WL# or the bit line BL#, “VTH” may denote a threshold voltage for turning on the selection element SE, and “ITH” may denote a threshold current for turning on the selection element SE.

[0057] The turn-off condition of the selection element SE can be expressed as shown in the following equation (inequality) 2.

[0058] [Formula 2]

[0059] VC<VHOLD, or IC<IHOLD

[0060] Here, “VHOLD” may denote a minimum voltage for maintaining the on-state of the selection element SE, and “IHOLD” may denote a minimum current for maintaining the on-state of the selection element SE.

[0061] When a single read cycle starts, the voltage VC of one end of the selection element SE may become higher than the threshold voltage VTH while being raised. In this case, the cell current IC may be less than the minimum current IHOLD and greater than the threshold current ITH. Therefore, since the selection element SE satisfies the on condition (e.g., "TON"), the selection element SE may be turned on, and the cell current IC with a gradually increasing level may flow through the selection element SE. However, since the cell current IC is less than the minimum current IHOLD, the selection element SE does not meet the condition (e.g., "TOFF") for maintaining the on state, and therefore the selection element SE may be turned off, and the cell current IC with a gradually decreasing level may flow through the selection element SE. At the same time, since the voltage VC of one end of the selection element SE is continuously raised, the selection element SE again satisfies the on condition (e.g., "TON"), and therefore the selection element SE may be turned on, and the cell current IC with a gradually increasing level may flow through the selection element SE. However, since the cell current IC is still less than the minimum current IHOLD, the selection element SE does not satisfy the condition (eg, “TOFF”) for maintaining the on state, and thus the selection element SE may be turned off and the cell current IC having a gradually decreasing level may flow through the selection element SE.

[0062] In this way, the selection element SE can be repeatedly in a state satisfying the on condition of the selection element SE (e.g., "TON") and a state not satisfying the condition for maintaining the on state of the selection element SE (e.g., "TOFF"). Therefore, the cell current IC flowing through the memory cell MC# can have an oscillation level.

[0063] The disclosed technology can be implemented in some embodiments to detect the resistance state based on or according to the change of cell current during a read operation, thereby minimizing read errors even when the sensing spacing between two distributions (e.g., the first distribution and the second distribution) is not sufficiently guaranteed.

[0064] In addition, the disclosed technology may be implemented in some embodiments to provide a memory device that can prevent read errors when reading data from a selected memory cell, thereby improving the reliability of a read operation.

[0065] Although the disclosed technology has been illustrated and described with respect to specific embodiments, it should be understood that various enhancements and modifications can be made to the disclosed embodiments and other embodiments based on what is described and illustrated in this patent document.

Claims

1. A memory device, comprising: a memory cell array including a plurality of memory cells, each of the plurality of memory cells being configured to store a data value corresponding to read data to be read out through a plurality of conductive lines; as well as A read circuit is coupled to the plurality of conductive lines to generate the read data corresponding to the data value stored in the selected memory cell among the plurality of memory cells based on whether a cell current flowing through the selected memory cell among the plurality of memory cells changes during a single read cycle.

2. The memory device of claim 1 , wherein during the single read cycle, the read circuit generates the read data having a first data value in response to the cell current having a constant level, and generates the read data having a second data value in response to the cell current having an oscillating level.

3. The memory device of claim 2 , wherein the read data corresponds to a resistance state of the selected memory cell, wherein the resistance state of the selected memory cell comprises a high resistance state and a low resistance state lower than the high resistance state, wherein the first data value corresponds to the high resistance state, and the second data value corresponds to the low resistance state. 4 . The memory device of claim 1 , wherein the read circuit performs N sensing operations during the single read cycle to detect the cell current flowing through the selected memory cell, wherein N is an integer greater than 1. 5 . 5 . The memory device of claim 4 , wherein the N sensing operations are performed on the selected memory cell during the single read cycle regardless of a sensing result of at least one sensing operation among the N sensing operations. 6 . The memory device of claim 4 , wherein in response to sensing results for the N sensing operations being the same, the read data has a first data value, or in response to sensing results for the N sensing operations being different, the read data has a second data value.

7. The memory device of claim 6, wherein the read data corresponds to a resistance state of the selected memory cell, wherein the resistance state of the selected memory cell comprises a high resistance state and a low resistance state lower than the high resistance state, wherein the first data value corresponds to the high resistance state, and the second data value corresponds to the low resistance state.

8. The memory device of claim 1 , wherein the read circuit comprises: a sensing circuit for detecting a change in the cell current flowing through the selected memory cell during the single read cycle; as well as A determination circuit is used to determine the data value stored in the selected memory cell according to the sensing result of the sensing circuit.

9. A memory device comprising: a memory cell array including a plurality of memory cells, each of the plurality of memory cells being configured to store a data value corresponding to read data to be read out through a plurality of conductive lines; a sensing circuit coupled to the plurality of conductive lines to compare a cell current flowing through a selected memory cell among the plurality of memory cells with a reference current during a single read cycle; as well as a determination circuit coupled to the sensing circuit to: generate the read data having a first data value in response to a comparison result of the sensing circuit indicating that the cell current has a constant level during the single read cycle; Or in response to the comparison result of the sensing circuit indicating that the cell current has an oscillation level during the single read cycle, generating the read data having a second data value. 10 . The memory device of claim 9 , wherein the sensing circuit performs M comparison operations during the single read cycle to compare the cell current with the reference current at predetermined time intervals, wherein M is an integer greater than 1. 11 . The memory device according to claim 10 , wherein the time interval is set according to an oscillation period of the cell current having the oscillation level. 12 . The memory device of claim 10 , wherein the sensing circuit performs M comparison operations on the selected memory cell during the single read cycle regardless of a comparison result of at least one comparison operation among the M comparison operations.

13. The memory device of claim 10, wherein in response to comparison results for the M comparison operations being the same, the read data has the first data value, or in response to comparison results for the M comparison operations being different, the read data has the second data value.

14. The memory device of claim 9, wherein the read data corresponds to a resistance state of the selected memory cell, wherein the resistance state of the selected memory cell includes a high resistance state and a low resistance state lower than the high resistance state, wherein the first data value corresponds to the high resistance state, and the second data value corresponds to the low resistance state.

15. A method for operating a memory device, comprising: setting the reference current to: a level lower than a cell current distribution flowing through the memory cells in the low resistance state; or a level higher than a cell current distribution flowing through memory cells in a high resistance state higher than said low resistance state; performing M comparison operations to compare a cell current flowing through a selected memory cell among the memory cells with the reference current, wherein M is an integer greater than 1; as well as Read data having a second data value is generated in response to the comparison result indicating that the cell current has an oscillation level. 16 . The operating method according to claim 15 , wherein the read data has a first data value in response to the comparison result indicating that the cell current has a constant level.

17. The operating method according to claim 16, wherein the read data corresponds to a resistance state of the selected memory cell, wherein the resistance state of the selected memory cell includes a high resistance state and a low resistance state lower than the high resistance state, wherein the first data value corresponds to the high resistance state, and the second data value corresponds to the low resistance state.

18. The operating method according to claim 15, wherein the M comparison operations are performed at predetermined time intervals during a single read cycle.

19. The operating method according to claim 18, wherein the time interval is set according to an oscillation period of the cell current having the oscillation level.

Images