Compact k-XOR-sat filtering with cam

Abstract

Examples of the technology of the present disclosure relate to compact K-XOR-SAT filtering with CAM. In particular, CAM-based circuits are provided, which are specifically configured to implement Boolean satisfiability issues involving k-XOR-SAT clauses. Circuits of the present technology may utilize a common CAM (i.e., a common CAM) by strategically adding an auxiliary count and logic circuit that evaluates a matching line voltage output of the CAM at k discrete times in order to determine whether a counted matching number returned by the matching line satisfies a predetermined parity condition (where k represents a number of word values of k-XOR-SAT clauses of a Boolean satisfiability problem). The k-XOR-SAT clause and the k-SAT clause are implemented by using the k-XOR-SAT clause (such as the same CAM). Therefore, compared with an existing hardware accelerator, the circuit with extremely high universality can be used for implementing k-XOR-SAT and k-SAT-k-XOR-SAT mixing problems in less time and with less hardware and power consumption.

Description

Background Art

[0001] The Boolean satisfiability problem (i.e., the propositional satisfiability problem, abbreviated as satisfiability, SAT, or B-SAT) involves determining whether there is an interpretation that satisfies a Boolean formula (sometimes referred to herein as a Boolean satisfiability formula). For example, the SAT problem attempts to determine whether the variables of a Boolean formula can be consistently replaced by true or false values ​​in such a way that the Boolean formula evaluates to true. If this is the case, the Boolean formula is said to be satisfiable. For example, the Boolean formula "a AND NOT b" is satisfiable because the values ​​a = true and b = false will make the Boolean formula "a AND NOT b" = true. On the other hand, if the variables of a Boolean formula cannot be consistently replaced by true or false values ​​in such a way that the Boolean formula evaluates to true, the Boolean formula is unsatisfiable. For example, "a AND NOT a" is unsatisfiable.

[0002] Content addressable memory ("CAM") is a type of computational memory in which stored data is searched by its content rather than its location. When a "word" is input to the CAM, the CAM searches for the word in its content. If the CAM finds the word (i.e., "returns a match"), the CAM returns the address of the location where the found word resides. The individual cells of the CAM (i.e., CAM cells) can be arranged in rows and columns. The CAM cells of a common row can be connected along a common match line. Words can be stored along the rows of the CAM, and each CAM cell of a given row can store an entry of the stored word. When the CAM receives an input word (e.g., a series of voltage signals, each voltage signal representing an entry of the input word, sometimes referred to herein as an input vector), the CAM can search for the input word by entry along the columns of the CAM (i.e., the first entry of the input word can be searched down along the first column of the CAM, the second entry of the input word can be searched down along the second column of the CAM, etc.). If all CAM cells of a given row return a match for their respective entries of the input word, the CAM can "find" the input word in that given row. BRIEF DESCRIPTION OF THE DRAWINGS

[0003] The present disclosure is described in detail according to one or more various embodiments with reference to the following drawings. The drawings are provided for illustration purposes only and depict examples only.

[0004] Figure 1 An example CAM cell is depicted according to examples of the presently disclosed techniques.

[0005] Figure 2 An example CAM according to an example of the presently disclosed techniques is depicted.

[0006] Figure 3A Another example CAM according to examples of the presently disclosed techniques is depicted.

[0007] Figure 3B Depicted is an example of a method for using the technology according to the present disclosure Figure 3A Example truth table for CAM evaluating a k-SAT clause.

[0008] Figure 4A Depicted is an example CAM-based circuit for implementing a k-XOR-SAT clause according to examples of the presently disclosed techniques.

[0009] Figure 4B Depicted is an example of a method for using the technology according to the present disclosure Figure 4A Example truth table for a CAM-based circuit evaluating the k-XOR-SAT formula.

[0010] Figure 5 Depicted is an example graph illustrating comparisons between threshold voltages and voltage outputs of a match line associated with a row of CAM cells programmed to store a k-XOR-SAT clause in accordance with an example of the presently disclosed technique.

[0011] Figure 6 Depicted is an example flow chart for solving a Boolean satisfiability problem using a CAM-based circuit, according to an example of the presently disclosed techniques.

[0012] Figure 7 Depicted is a block diagram of an example computer system in which various examples described herein may be implemented.

[0013] The drawings are not exhaustive and do not limit the disclosure to the precise forms disclosed. DETAILED DESCRIPTION

[0014] The k-SAT problem is a type of SAT problem characterized by the number of variables V, the number of literals k, and the number of clauses C. A k-SAT clause typically includes k literals. A literal of a k-SAT clause is either a variable or the negation of a variable. Conjunctive Normal Form (CNF) (particularly, where each k-SAT clause has k=3 literals) is often considered to be the canonical representation of a k-SAT formula. In CNF, a k-SAT clause is a disjunction of literals (i.e., a logical OR operation), and a k-SAT formula is a conjunction of k-SAT clauses (i.e., a logical AND operation). A k-SAT formula can also be converted into Disjunctive Normal Form (DNF), where a k-SAT clause is a conjunction of literals (i.e., a logical AND operation), and a k-SAT formula is a disjunction of k-SAT clauses (i.e., a logical OR operation). The k-SAT problem is a non-deterministic polynomial time (NP) hard problem and is among the first problems proven to be NP-complete. All problems in the NP-hard complexity class (which includes a wide range of natural decision and optimization problems) are at most as hard to solve as the k-SAT problem.

[0015] Because the k-SAT problem is the backbone of many industrial and scientific problems (such as electronic design automation and cryptography), various hardware accelerators have been specially designed to implement (i.e., represent and evaluate) the k-SAT problem. For example, certain quadratic unconstrained binary optimization (QUBO) based solvers, Ising machines, and CAMs have been specially designed to implement the k-SAT problem. In the case of a specially designed CAM, the clauses of the k-SAT problem / formula can be programmed into the corresponding rows of the CAM, and each CAM cell of a given row can be programmed to represent the literal value of the corresponding k-SAT clause. Then, an input vector (e.g., representing a set of variables) can be applied down the columns of the CAM to evaluate whether the set of variables represented by the input vector satisfies the k-SAT clauses programmed into the CAM.

[0016] Although many industrial and scientific optimization problems can be formulated as k-SAT problems, some optimization problems are better formulated in different ways. For example, some optimization problems (such as low-density parity check (LDPC) in networking systems) are best formulated as k-exclusive-OR-satisfiability (k-XOR-SAT) problems (i.e., Boolean satisfiability problems formulated using k-XOR-SAT clauses). Relatedly, some optimization problems are best formulated as "k-SAT-k-XOR-SAT hybrid problems" that include a combination of k-SAT clauses and k-XOR-SAT clauses.

[0017] Unlike k-SAT clauses (in CNF) which include logical OR operations between their constituent literals, k-XOR-SAT clauses include logical XOR operations between their constituent literals. This seemingly minor distinction has significant implications for problem types / classifications. For example, the k-SAT problem (i.e., the Boolean satisfiability problem formulated using k-SAT clauses) is an NP-hard problem, while k-XOR-SAT (i.e., the Boolean satisfiability problem formulated using k-XOR-SAT clauses) is a polynomial (P) problem. P problems can be solved in polynomial time and are generally easier to represent and solve than NP-hard problems. Therefore, expressing the native k-XOR-SAT optimization problem as a k-XOR-SAT problem instead of a k-SAT problem (or using k-XOR-SAT clauses instead of k-SAT clauses) can reduce the complexity of the optimization problem.

[0018] Unfortunately, the above-mentioned hardware accelerators specially designed for implementing (i.e., representing and evaluating) the k-SAT problem are generally unable to natively implement k-XOR-SAT clauses. Therefore, using these existing hardware accelerators to implement the k-XOR-SAT problem generally involves reformulating the k-XOR-SAT problem as a k-SAT problem, which generally increases the complexity of the problem (e.g., increases the number of variables involved) and moves the evaluation of the k-XOR-SAT problem from polynomial time to non-polynomial time. Therefore, reformulating the k-XOR-SAT problem as a k-SAT problem generally increases the amount of time, hardware, and power consumption required to implement the k-XOR-SAT problem. Relatedly, using these existing hardware accelerators to implement a k-SAT-k-XOR-SAT hybrid problem (i.e., a problem formulated using a combination of k-SAT clauses and k-XOR-SAT clauses) generally involves reformulating the constituent k-XOR-SAT clauses as k-SAT clauses. Again, such a reformulation increases the complexity of the problem, thereby increasing the amount of time, hardware, and power consumption required to implement the k-SAT-k-XOR-SAT mixing problem.

[0019] In this context, examples of the technology disclosed herein provide CAM-based circuits that are specifically constructed to implement Boolean satisfiability problems involving k-XOR-SAT clauses. By strategically adding auxiliary counting and logic circuits that evaluate the match line voltage output of the CAM at k discrete times to determine whether the counted number of matches returned by the match line satisfies a predetermined parity condition (where k represents the number of literal values ​​of the k-XOR-SAT clause of the Boolean satisfiability problem), the circuits of the present technology can utilize a common CAM (i.e., the same CAM) to implement k-XOR-SAT clauses and k-SAT clauses. Therefore, compared to existing hardware accelerators, this highly versatile circuit can be used to implement k-XOR-SAT and k-SAT-k-XOR-SAT mixed problems in less time and with less hardware and power consumption.

[0020] Circuitry of the disclosed technology may include: (1) a row of CAM cells programmed to store k-XOR-SAT clauses of a Boolean satisfiability problem; (2) a sense amplifier that compares a voltage output of a match line associated with the row of CAM cells with a threshold voltage at k discrete times in response to an input vector being applied to the row of CAM cells, where k represents a literal number of the k-XOR-SAT clause; (3) a counter circuit that counts the number of matches returned by the match line based on the k voltage comparisons by the sense amplifier (e.g., the counted number of matches may correspond to the number of k voltage comparisons in which the voltage output of the match line exceeds the threshold voltage); and (4) a logic circuit that outputs a signal indicating that the input vector satisfies the k-XOR-SAT clause based on the counted number of matches satisfying a predetermined parity condition (e.g., the counted number of matches includes an odd number of matches). The row of CAM cells may include at least k literal representation type CAM cells. One of the k literal-value-representing CAM cells may be programmed to store a literal value of the k-XOR-SAT clause.

[0021] In various examples, a literal representation CAM cell may be programmed to: (a) store a first value when the literal value is negated in a k-XOR-SAT clause; and (b) store a second value when the literal value is not negated in the k-XOR-SAT clause. As will be described in more detail below, programming a literal representation CAM cell to store a literal value of a k-XOR-SAT clause may include programming the conductance of one or more memristors included in the literal representation CAM cell. As mentioned above, the circuit may also be used to represent / evaluate a k-SAT clause of a Boolean satisfiability problem. In other words, a Boolean satisfiability problem may include a k-SAT-k-XOR-SAT hybrid problem. For example, the circuit may further include: (1) a second row of CAM cells programmed to store a k-SAT clause of the Boolean satisfiability problem; and (2) a processor that determines that the input vector satisfies the Boolean satisfiability problem in response to receiving: (a) a signal indicating that the input vector satisfies the k-XOR-SAT clause; and (b) a second signal indicating that the input vector satisfies the k-SAT clause (such signal may be based on a comparison between a threshold voltage and a voltage of a match line associated with the second row of CAM cells).

[0022] As mentioned above, the CAM-based circuits of the present technique present numerous advantages over existing hardware accelerators for implementing Boolean satisfiability problems.

[0023] For example, existing CAMs designed to implement k-SAT problems typically require k-XOR-SAT clauses to be reformulated as k-SAT clauses in order to implement k-XOR-SAT problems and / or k-SAT-k-XOR-SAT mixed problems. Such reformulations can increase the complexity of the problem, thereby increasing the amount of time, hardware, and power consumption required to represent and evaluate such problems. In contrast, by strategically adding auxiliary counting circuits and logic circuits that evaluate the match line voltage output of the CAM at k discrete times to determine whether the counted number of matches returned by the match line satisfies a predetermined parity condition (where k represents the number of literal values ​​of the k-XOR-SAT clause of the Boolean satisfiability problem), the CAM-based circuit of the present technology can utilize a common CAM to implement k-XOR-SAT clauses and k-SAT clauses. Therefore, compared with existing CAMs, this highly versatile circuit can be used to implement k-XOR-SAT and k-SAT-k-XOR-SAT mixed problems in less time and with less hardware and power consumption.

[0024] Using CAM-based circuits to implement k-XOR-SAT problems and / or k-SAT-k-XOR-SAT hybrid problems can also be faster / more efficient than using other types of hardware accelerators (e.g., QUBO-based solvers and Ising machines). For example, utilizing the unique parallel search capabilities of CAMs, the circuits of the present disclosure can evaluate input vectors against all (potentially many) clauses of a Boolean satisfiability problem in a single search operation. In other words, for CAM-based circuits of the presently disclosed techniques, the amount of time required to evaluate a Boolean satisfiability problem remains approximately constant even as the number of clauses (e.g., k-XOR-SAT clauses and / or k-SAT clauses) used to express the Boolean satisfiability problem increases. Therefore, the CAM-based circuits of the disclosed technology can evaluate large / complex Boolean satisfiability problems (i.e., Boolean satisfiability problems formulated using a large number of k-XOR-SAT clauses and / or k-SAT clauses) faster than other types of hardware accelerators (e.g., QUBO-based solvers and Ising machines) that lack this unique parallel search capability.

[0025] Examples of the technology of the present disclosure will be described in more detail using the following drawings.

[0026] Figure 1 An example CAM cell 100 according to an example of the techniques of this disclosure is depicted. The CAM cell 100 may be an example of a 4-transistor-2-memristor (4T2M) CAM cell that may be used in a CAM-based circuit of the techniques of this disclosure. For example, the CAM cell 100 may be programmed to represent a k-XOR-SAT clause or a literal value of a k-SAT clause.

[0027] As depicted, the CAM cell 100 includes a switching transistor T1 connected to a data line SL and a switching transistor T2 connected to an inverted data line SL. As mentioned above, the data line SL and the reverse data line The voltage across the data line SL may correspond to a value / entry (e.g., a voltage signal) of an input vector applied to a CAM (of which the CAM cell 100 is a part). For example, the voltage across the data line SL may correspond to a value / entry (e.g., a logic 1) of the input vector, while the voltage across the data line SL may correspond to a logic 1. The voltage across the two ends may correspond to a negated version (e.g., a logical 0) of the value / entry of the input vector. Memristor M2 is connected to switching transistor T1, and memristor M1 is connected to switching transistor T2. As depicted, the gate terminals of switching transistors T1 and T2 are connected to word line WL, which biases switching transistors T1 and T2. Immediately before and during the search / match operation, the voltage of word line WL may increase to exceed a threshold, thereby activating switching transistors T1 and T2. When switching transistor T1 is activated, switching transistor T1 may provide an electrical connection between data line SL and memristor M2. In contrast, when switching transistor T1 is not activated (i.e., when the voltage across word line WL is below the threshold), data line SL and memristor M2 may be electrically disconnected. Similarly, when switching transistor T2 is activated, switching transistor T2 may be on the reverse data line In contrast, when the switch transistor T2 is not activated (ie, when the voltage across the word line WL is below the threshold), the reverse data line Therefore, including the switch transistors T1 and T2 can ensure that the memristors M1 and M2 are disconnected from the data line of the CAM cell 100 when the search / match operation is not performed, which can reduce the overall power consumption of the CAM cell 100.

[0028] As depicted, memristors M1 and M2 are connected in series to form a resistor divider 102. The output voltage of resistor divider 102 (i.e., the voltage on common node G) is applied to the gate of match line transistor T4 to control the activation of match line transistor T4. When match line transistor T4 is activated, it may discharge (i.e., "pull down") the voltage of match line ML. For example, if the voltage applied to the gate of match line transistor T4 exceeds a threshold, match line transistor T4 will activate and discharge (i.e., "pull down") the voltage across match line ML, thereby returning to mismatch. In contrast, when the voltage applied to the gate of match line transistor T4 is less than or equal to a threshold, match line transistor T4 may not activate. Therefore, match line transistor T4 will not discharge (i.e., "pull down") the voltage across match line ML, thereby returning to match. Although in Figure 1 Although “pull-down” logic is described in the specific example of FIG. 1 , it should be understood that in other examples, the CAM cell 100 may instead implement “pull-up” logic.

[0029] As mentioned above, CAM cell 100 can be programmed to store a k-XOR-SAT clause or a literal value of a k-SAT clause by programming the conductance of memristors M1 and M2. Although the programmed conductance of memristors M1 and M2 will generally remain the same, unless reprogrammed, the output voltage of resistor divider 102 (i.e., the voltage on common node G) will change based on the voltages received by memristors M2 and M1 from data line SL and reverse data line SL, respectively. For example, memristors M1 and M2 can be programmed to a first conductance state (e.g., a logic 0 conductance state, which can correspond to a negated literal value) when a voltage is received from the data line SL and the reverse data line When the received voltage represents a logic 1, the first conduction state causes the output voltage of the resistor divider to be high (eg, exceeding a threshold), thereby activating the match line transistor T4 and activating the data line SL and the reverse data line T4. The voltage across the two terminals represents a logic 1 when the mismatch is returned. In contrast, memristors M1 and M2 can be programmed to a second conductance state (e.g., a logic 1 conductance state, which can correspond to a non-negated literal value) when the data line SL and the reverse data line When the received voltage represents a logic 0, the second conduction state causes the output voltage of the resistor divider to be high (eg, exceeding a threshold), thereby activating the match line transistor T4 and activating the data line SL and the reverse data line T4. The voltage across the two terminals represents a logic 0 and returns a mismatch. As described in more detail below, in various examples, memristors M1 and M2 can be programmed to a third conductance state (e.g., a wildcard conductance state, which can correspond to a variable not included in a k-XOR-SAT or k-SAT clause) that causes the output voltage of the resistor divider to remain low (e.g., below a threshold value) regardless of the voltage from the data line SL and the reverse data line The received voltage represents a logic 0 or a logic 1, thus ensuring that the match line transistor T4 remains inactive and that the data line SL and the reverse data line The voltage across the terminals represents a logic 0 or logic 1 when returned matched.

[0030] As depicted, service line transistor T3 may work in conjunction with switch transistor T1 and / or switch transistor T2 to program the conductance of memristors M1 and M2 using service line SX.

[0031] It should be understood that CAM cell 100 is only one example of a CAM cell that may be included in a CAM-based circuit of the present technology. In general, any type of CAM cell that can be programmed to represent a literal value of a k-XOR-SAT or k-SAT clause may be used. For example, examples of the disclosed technology may utilize a six-transistor-two-memristor (6T2M) CAM cell, a 3-terminal CAM cell, a 16-transistor (16T) ternary CAM (TCAM) cell, etc.

[0032] Figure 2 An example CAM 200 is depicted in accordance with an example of techniques of this disclosure. CAM 200 may be programmed to represent a Boolean satisfiability problem, such as a k-SAT problem, a k-XOR-SAT problem, or a k-SAT-k-XOR-SAT hybrid problem.

[0033] As described above, a content addressable memory ("CAM") is a type of computational memory in which stored data is searched by its content rather than its location. When a "word" is input to the CAM, the CAM searches for the word in its content. If the CAM finds the word (i.e., "returns a match"), the CAM returns the address of the location where the found word resides. The individual cells of the CAM (i.e., CAM cells) can be arranged in rows and columns. The CAM cells of a common row can be connected along a common match line. Words can be stored along the rows of the CAM, and each CAM cell of a given row can store an entry of the stored word. When the CAM receives an input word (e.g., a series of voltage signals, each voltage signal representing an entry of the input word, sometimes referred to as an input vector herein), the CAM can search for the input word by entry along the columns of the CAM (i.e., the first entry of the input word can be searched down along the first column of the CAM, the second entry of the input word can be searched down along the second column of the CAM, etc.). If all CAM cells of a given row return a match for their respective entries of the input word, the CAM can "find" the input word in the given row.

[0034] Because the k-SAT problem is the backbone of many industrial and scientific problems (such as electronic design automation and cryptography), various hardware accelerators have been specially designed to implement (i.e., represent and evaluate) the k-SAT problem. For example, certain CAMs (e.g., CAM 200) have been specially designed to implement the k-SAT problem. For example, clauses of the k-SAT problem / formula can be programmed into corresponding rows of CAM 200, and each CAM cell of a given row can be programmed to represent the literal value of the corresponding k-SAT clause. Then, an input vector (e.g., representing a set of variables) can be applied down the columns of CAM 200 to evaluate whether the set of variables represented by the input vector satisfies the k-SAT clauses programmed into CAM 200.

[0035] As described above, while many industrial and scientific optimization problems can be formulated as k-SAT problems, some optimization problems are better formulated in different ways. For example, some optimization problems (such as low-density parity check (LDPC) in networking systems) are best formulated as kk-XOR-SAT problems (i.e., Boolean satisfiability problems formulated using k-XOR-SAT clauses). Relatedly, some optimization problems are best formulated as "k-SAT-k-XOR-SAT hybrid problems" that include a combination of k-SAT clauses and k-XOR-SAT clauses.

[0036] Unlike k-SAT clauses (in CNF) which include logical OR operations between their constituent literals, k-XOR-SAT clauses include logical XOR operations between their constituent literals. This seemingly minor distinction has significant implications for problem types / classifications. For example, the k-SAT problem (i.e., the Boolean satisfiability problem formulated using k-SAT clauses) is an NP-hard problem, while k-XOR-SAT (i.e., the Boolean satisfiability problem formulated using k-XOR-SAT clauses) is a polynomial (P) problem. P problems can be solved in polynomial time and are generally easier to represent and solve than NP-hard problems. Therefore, expressing the native k-XOR-SAT optimization problem as a k-XOR-SAT problem instead of a k-SAT problem (or using k-XOR-SAT clauses instead of k-SAT clauses) can reduce the complexity of the optimization problem.

[0037] Unfortunately, many hardware accelerators (e.g., CAM 200) designed specifically for implementing (i.e., representing and evaluating) k-SAT problems are generally unable to natively implement k-XOR-SAT clauses. Therefore, implementing the k-XOR-SAT problem on CAM 200 using conventional techniques will generally involve reformulating the k-XOR-SAT problem as a k-SAT problem, which generally increases the complexity of the problem (e.g., increases the number of variables involved) and moves the evaluation of the k-XOR-SAT problem from polynomial time to non-polynomial time. Therefore, reformulating the k-XOR-SAT problem as a k-SAT problem generally increases the amount of time, hardware, and power consumption required to implement the k-XOR-SAT problem. Relatedly, implementing a k-SAT-k-XOR-SAT hybrid problem (i.e., a problem formulated using a combination of k-SAT clauses and k-XOR-SAT clauses) on CAM 200 using conventional techniques will generally involve reformulating the constituent k-XOR-SAT clauses as k-SAT clauses. Again, such a reformulation increases the complexity of the problem, thereby increasing the amount of time, hardware, and power consumption required to implement the k-SAT-k-XOR-SAT mixing problem.

[0038] To address the above shortcomings of conventional techniques / techniques, examples of the technology disclosed herein provide CAM-based circuits that are specifically constructed to implement Boolean satisfiability problems involving k-XOR-SAT clauses. By strategically adding auxiliary counting and logic circuits that evaluate the match line voltage output of the CAM at k discrete times to determine whether the counted number of matches returned by the match line satisfies a predetermined parity condition (where k represents the number of literal values ​​of the k-XOR-SAT clause of the Boolean satisfiability problem), the circuits of the present technology can utilize a common CAM (i.e., the same CAM) to implement k-XOR-SAT clauses and k-SAT clauses. Therefore, compared to existing hardware accelerators, this highly versatile circuit can be used to implement k-XOR-SAT and k-SAT-k-XOR-SAT mixed problems in less time and with less hardware and power consumption.

[0039] A circuit of the disclosed technique may include: (1) a row of CAM cells programmed to store k-XOR-SAT clauses of a Boolean satisfiability problem (e.g., a row of CAM 200); (2) sense amplifiers ( Figure 2 Not depicted in, but in Figure 4A ), which compares the voltage output of the match line associated with the row of CAM cells with a threshold voltage at k discrete times in response to an input vector applied to the row of CAM cells, where k represents the literal number of k-XOR-SAT clauses; (3) a counter circuit ( Figure 2 Not depicted in, but in Figure 4A ), which counts the number of matches returned by the match line based on k voltage comparisons of the sense amplifier (e.g., the counted number of matches may correspond to the number of k voltage comparisons in which the voltage output of the match line exceeds the threshold voltage); and (4) a logic circuit ( Figure 2 Not depicted in, but in Figure 4A ), which outputs a signal indicating that the input vector satisfies the k-XOR-SAT clause based on the counted number of matches satisfying a predetermined parity condition (e.g., the counted number of matches includes an odd number of matches). The row of CAM cells may include at least k literal value representation type CAM cells. A literal value representation type CAM cell (e.g., Figure 2 The CAM cell 100) can be programmed to store a literal value of the k-XOR-SAT clause.

[0040] In various examples, a literal value representation CAM cell may be programmed to: (a) store a first value when the literal value is negated (e.g., logical 0) in a k-XOR-SAT clause; and (b) store a second value when the literal value is not negated (e.g., logical 1) in the k-XOR-SAT clause. As will be described in more detail below, programming a literal value representation CAM cell to store a literal value of a k-XOR-SAT clause may include programming the conductance of one or more memristors included in the literal value representation CAM cell (e.g., programming the conductance of memristors M1 and M2 of CAM cell 100). As mentioned above, the circuit may also be used to implement a k-SAT clause of a Boolean satisfiability problem. In other words, the Boolean satisfiability problem may include a k-SAT-k-XOR-SAT hybrid problem. For example, the circuit may further include: (1) a second row of CAM cells (e.g., second row CAM 200) programmed to store a k-SAT clause of the Boolean satisfiability problem; and (2) a processor (not depicted) that determines that the input vector satisfies the Boolean satisfiability problem in response to receiving: (a) a signal indicating that the input vector satisfies the k-XOR-SAT clause; and (b) a second signal indicating that the input vector satisfies the k-SAT clause (such signal may be based on a comparison between a threshold voltage and a voltage of a match line associated with the second row of CAM cells).

[0041] Reference again Figure 2, some CAMs (e.g., CAM 200) may be classified as "ternary". A ternary CAM ("TCAM") may evaluate an input vector containing binary bits 0, 1, and / or wildcard values ​​for TCAM cells that store / represent either bits 0, 1, or wildcard values ​​(as mentioned above, wildcard values ​​are sometimes referred to as "don't care" or "always match" values). For example, and as mentioned above, one or more memristors of a TCAM cell may be programmed to a first conductance state (e.g., logic 0) that returns a match when a voltage signal representing a logic 0 or a wildcard value is applied to the TCAM cell. In contrast, the one or more memristors of the TCAM cell may be programmed to a second conductance state (e.g., logic 1) that returns a match when a voltage signal representing a logic 1 or a wildcard value is applied to the TCAM cell. Additionally, the one or more memristors of the TCAM cell can be programmed to a third conductance state (e.g., a wildcard conductance state) that returns a match when a voltage signal representing a logic 0, 1, or a wildcard value is applied to the TCAM cell. In various embodiments, CAM 200 may include a TCAM. However, in other embodiments, CAM 200 may include a high-order CAM (e.g., a quad CAM ("QCAM"), an analog CAM ("aCAM"), etc.).

[0042] As depicted, CAM 200 includes columns 202A, 202B, ..., 202L. The number of columns of CAM 200 may be equal to the number of variables V in the total set of variables x1, x2, ..., xL that the Boolean satisfiability formula may be set to be the same or to be its negation (negative). Therefore, the columns of CAM 200 may correspond to variables x1, x2, ..., xL, respectively. CAM 200 also includes rows 204A, 204B, ..., 204S. The number of rows of CAM 200 may be equal to the number S of clauses (e.g., k-XOR-SAT clauses and / or k-SAT clauses) that make up the Boolean satisfiability formula. As depicted, the CAM cells of each row may be connected to a common match line. For example, the CAM cells of row 204A are connected to match line 212A, the CAM cells of row 204B are connected to match line 212B, the CAM cells of row 204S are connected to match line 212S, and so on. As mentioned above, CAM 200 may be an "AND" type CAM that performs logical AND operations between CAM cells in a common row.

[0043] As depicted, the CAM cells of a common row may also be connected to a common word line. For example, the CAM cells of row 204A are connected to word line 213A, the CAM cells of row 204B are connected to word line 213B, the CAM cells of row 204S are connected to word line 213S, and so on. As mentioned above, the word lines of CAM 200 may bias the switch transistors that make up the CAM cells so that the memristors that make up the CAM cells are only electrically connected to the data lines / reverse data lines of CAM 200 immediately before and during the matching / searching operation, which may reduce the power consumption of CAM 200.

[0044] As depicted, each column of CAM 200 includes a data line (e.g., SL 206A for column 202A, SL 206B for column 202B, SL 206L for column 202L, and so on) and an inverted data line (e.g., SL 206A for column 202A). 207A, for column 202B 207B, for column 202L Each column may also include a service line for programming the CAM cells (eg, SX 208A for column 202A, SX 208B for column 202B, SX 208L for column 202L, and so on).

[0045] As mentioned above, CAM 200 can be programmed to implement (i.e., represent and evaluate) both k-SAT clauses and k-XOR-SAT clauses of the Boolean satisfiability problem. Figure 3A-3B ) describes an exemplary implementation of the k-SAT formula 250. As mentioned above, implementing the k-SAT clause on the CAM 200 may not require auxiliary counting and logic circuits utilized by an example of the disclosed techniques for implementing the k-XOR-SAT clause on a CAM-based circuit.

[0046] As described above, the canonical representation of the k-SAT formula 250 may be in conjunctive normal form (CNF). However, the k-SAT formula 250 may also be converted into disjunctive normal form (DNF), where: (1) the DNF k-SAT formula 252 (i.e., the k-SAT formula 250 converted to DNF) is a disjunction (i.e., a logical OR operation) of DNF k-SAT clauses; (2) each DNF k-SAT clause (i.e., the k-SAT clause converted to DNF) is a conjunction (i.e., a logical AND operation) of literal values; and (3) the literal value of the corresponding DNF k-SAT clause is the negated form of the literal value of the corresponding k-SAT clause in CNF. For example, if the k-SAT formula 250 is represented in CNF as Then the DNF k-SAT formula 252 can be expressed as As mentioned above, DNF can be naturally mapped to an AND-type CAM (eg, CAM 200), where the literal values ​​of the DNF k-SAT clauses are programmed into individual CAM cells of the corresponding row.

[0047] For example, a DNF k-SAT clause of a DNF-k-SAT formula 252 may be programmed into row 204A by programming the CAM cells of row 204A to correspond to the variable assignments of the DNF k-SAT clauses. Here, the DNF k-SAT clauses programmed into row 204A may include the first clause of the DNF-k-SAT formula 252. As mentioned above, the columns of the CAM 200 may correspond to the total number of V variables of the DNF-k-SAT clauses. For example, column 202B may correspond to the second variable x2 of the total set of V variables x1, x2, ..., xV, and thus the corresponding variable assignment corresponds to the variable x2.

[0048] Each DNF k-SAT clause of the DNF k-SAT formula 252 may be programmed into a corresponding row of the CAM 200 according to the mapping order. Therefore, the inherent AND property of the CAM 200 may be used to solve the DNF k-SAT formula 252, and by extension, the k-SAT formula 250. For example, because (1) the DNF k-SAT formula 252 includes a plurality of DNF k-SAT clauses connected by logical ORs, and (2) each DNF k-SAT clause includes a plurality of literal values ​​connected by logical ANDs, the DNF k-SAT clauses of the DNF k-SAT formula 252 may be separated into corresponding rows of the CAM 200 without interfering with the DNF k-SAT formula 252. Once the DNF k-SAT formula 252 is mapped into rows, each variable within the row may be arranged into a column so that a guess (i.e., an input vector) may be applied to each variable via each column.

[0049] like Figure 3A As seen in the example CAM 300 (which may have the same / similar construction as the CAM 200) includes a plurality of columns 307 and rows 305. Each DNF k-SAT clause of the DNF k-SAT formula 252 may be mapped to the row 305 of the plurality of CAM cells 306 according to a mapping order. In one embodiment, the mapping order includes programming a first DNF k-SAT clause including a plurality of literal values ​​to the first row 305A, and programming a second DNF k-SAT clause including a plurality of literal values ​​to the second row 305B. Each of the plurality of literal values ​​may further include a first value assigned to each non-negated literal value (e.g., z), and a first value assigned to each negated literal value (e.g., )’s second value.

[0050] exist Figure 3A In a specific example of , k-SAT formula 250 (and, by extension, DNF k-SAT formula 252) includes an exemplary 2-SAT formula that includes two literal values ​​(i.e., k=2), three variables (i.e., V=3), and two k-SAT clauses (i.e., C=2). In this example, CAM 300 includes an array of CAM cells that include two rows and three columns. Each DNF k-SAT clause of DNF k-SAT formula 252 is mapped to a row of CAM 300. For example, a first DNF k-SAT clause is mapped to a first row 305A, and a second DNF k-SAT clause is mapped to a second row 305B. In addition, each column of CAM 300 includes a variable (e.g., 1, 0, or a wildcard value ("X")). Each DNF k-SAT clause has k literal values ​​selected between V variables. In this example, each DNF k-SAT clause includes two literal values. Non-negated literal values ​​are programmed as 1 in their corresponding CAM cells, and negated literal values ​​are programmed as 0 in their corresponding CAM cells. Variables not present in the DNF k-SAT clause are programmed as 'X' (ie, wildcard value) in their corresponding CAM cells.

[0051] As mentioned above, the k-SAT formula 250 may be represented in CNF as follows: Then, the k-SAT formula 250 can be converted into DNF as follows: The DNF k-SAT formula 252 may be programmed (ie, mapped) onto the CAM 300. In this example, the first DNF k-SAT clause (x∧y) is programmed into the first row 305A, and the second DNF k-SAT clause is programmed into the second row 305B. Each literal value within each DNF k-SAT clause is mapped to its own corresponding column 307A-C. For example, x is mapped to the first column 307A, y is mapped to the second column 307B, and z is mapped to the third column 307C. In addition, each literal value is assigned a bit value (ternary 0 or 1 or "X") depending on whether the literal value is a negated literal value, a non-negated literal value, or a non-existent literal value in the corresponding DNF k-SAT clause. Here, a negated literal value may be assigned a bit value of 0, a non-negated literal value may be assigned a bit value of 1, and a non-existent literal value may be assigned a bit value of 'X' (i.e., a wildcard value). For example, the first DNF k-SAT clause includes literal values ​​x, y. The values ​​of x, y are programmed into the CAM 300 such that x is represented as 1 in cell 311, y is represented as 1 in cell 312, and z is represented as "X" in cell 313. As Figure 3A As further seen in the second DNFk-SAT clause is programmed into the second row 305 of the CAM 300, so that x is represented as "X" in cell 314, is represented as "0" in cell 315, and z is represented as "1" in cell 316. Therefore, the DNF k-SAT expression The first DNF k-SAT clause (x∧y) is denoted 1 1X in the first row, and the second DNF k-SAT clause In the second row it is represented as X 0 1.

[0052] like Figure 3A As depicted in , each row includes a match line. For example, cells 311-313 in a first row 305A are connected to a first match line ML1, and cells 314-316 in a second row 305B are connected to a second match line ML2.

[0053] As mentioned above, the circuitry of the disclosed technique may apply each entry (representing a variable) of an input vector (representing a set of variables evaluated for a Boolean satisfiability problem) in parallel to each column of the CAM to determine which clauses of the Boolean satisfiability problem are satisfied. Figure 3A In the specific example of , because k-SAT clauses are programmed into CAM 300 in DNF, a DNF k-SAT clause that is satisfied (e.g., corresponding to match line output 1) may correspond to a CNF k-SAT clause that is not satisfied (and vice versa). For example, if the first DNF k-SAT clause (x∧y) of DNF k-SAT formula 252 is satisfied, then the corresponding first CNF k-SAT clause of k-SAT formula 250 may not be satisfied (and vice versa). Figure 3A, if the input vector [1 1 0] is applied to CAM 300, match line ML1 will return a high voltage value (e.g., a high-order bit value of 1). Here, match line ML1 will return a high voltage value because each variable of the input vector (i.e., input value / entry) matches the values ​​stored in cells 311, 312, and 313, respectively. Additionally, match line ML2 will return a low voltage value (e.g., a low-order bit value of 0) because the input vector [1 1 0] does not match the values ​​stored in cells 314, 315, and 316. Thus, the first CNF k-SAT clause (i.e., the original first k-SAT clause in CNF) is not satisfied because the corresponding first DNF k-SAT clause is satisfied, and the second CNF k-SAT clause (i.e., the original second k-SAT clause in CNF) is satisfied because the second DNF k-SAT clause is not satisfied. In contrast, if the input vector [0 0 0] is applied to CAM 300, ML1 and ML2 will return ML low values ​​(e.g., low-order bit value 0) because the input vector does not match the values ​​stored in cells 311, 312, 313, 314, 315, and 316. Because both match lines ML1 and ML2 return low values, both original CNF k-SAT clauses (i.e., both k-SAT clauses of the Boolean satisfiability formula in CNF) are satisfied because both DNF k-SAT clauses are not satisfied.

[0054] Figure 3B The truth table 370 of the k-SAT formula 250 is depicted in FIG. , solve the k-SAT formula 250. Each row can be connected to an OR gate to verify whether the k-SAT formula 250 is satisfied.

[0055] In an alternative embodiment, the analog value of each match line can be passed through an analog adder. The analog adder can combine the analog values ​​of each match line (i.e., non-binary signals) to calculate a sum value. The sum of the analog values ​​can be returned as an output, which can be used to solve the Boolean satisfiability formula.

[0056] Figure 4AAn example CAM-based circuit 400 for implementing a k-XOR-SAT clause according to various examples of the technology disclosed herein is depicted. Before describing the CAM-based circuit 400 in more detail, some background on the k-XOR-SAT problem / clause may be instructive. As mentioned above, unlike a k-SAT clause that includes a logical OR operation between its constituent literals (in CNF), a k-XOR-SAT clause includes a logical XOR operation between its constituent literals. This seemingly minor difference has a significant impact on the problem type / classification. For example, the k-SAT problem (i.e., a Boolean satisfiability problem expressed using a k-SAT clause) is an NP-hard problem, while k-XOR-SAT (i.e., a Boolean satisfiability problem expressed using a k-XOR-SAT clause) is a polynomial (P) problem. P problems can be solved in polynomial time and are generally easier to represent and solve than NP-hard problems. Therefore, expressing the native k-XOR-SAT optimization problem as a k-XOR-SAT problem instead of a k-SAT problem (or using k-XOR-SAT clauses instead of k-SAT clauses) can reduce the complexity of the optimization problem.

[0057] The k-XOR-SAT formula can be viewed as a system of linear equations modulo 2 and can be solved in polynomial time (e.g., O(V 3 In other words, if the k-XOR-SAT formula includes V variables, solving the k-XOR-SAT formula may require O(V 3 ) iterations.

[0058] An example k-XOR-SAT formula 450 may include Here, the k-XOR-SAT formula 450 includes four variables (i.e., p, q, r, s), two k-XOR-SAT clauses (i.e., and ), and three literal values ​​of each k-XOR-SAT clause. Because the XOR operation effectively performs an inverse parity check, if the number of matches between the input vector and the literal values ​​of the corresponding k-XOR-SAT clause satisfies the predetermined parity condition, the input vector (or more specifically, the variable assignment represented by the input vector) can satisfy the k-XOR-SAT clause. For example, if the input vector matches the odd number of literal values ​​of the k-XOR-SAT clause, the input vector can satisfy the k-XOR-SAT clause. In contrast, if the input vector matches the even number of literal values ​​of the k-XOR-SAT clause, the input vector can violate the k-XOR-SAT clause. As mentioned above, when both of the constituent k-XOR-SAT clauses of the k-XOR-SAT formula 450 are satisfied, the k-XOR-SAT formula is satisfied. The k-XOR-SAT formula 450 is not satisfied when at least one of its constituent k-XOR-SAT clauses is not satisfied.

[0059] Reference again Figure 4A , the CAM-based circuit 400 includes a CAM 410. In some embodiments, the constituent CAM cells of the CAM 410 may have Figure 1 CAM cell 100 may be constructed the same / similarly, although this need not be the case. In general, any CAM cell that can be programmed to two possible values ​​(eg, logic 1 or logic 0) may be utilized in CAM 410.

[0060] As depicted, CAM 410 includes a bottom row of CAM cells and a top row of CAM cells. The bottom row of CAM cells are associated with a first match line ML1, and the top row of CAM cells are associated with a second match line ML2. As described in more detail below, the bottom row of CAM cells are programmed to store a first k-XOR-SAT clause (i.e., ), and the top row of CAM cells are programmed to store the second k-XOR-SAT clause of k-XOR-SAT formula 450 (i.e., ). Although Figure 4A In a specific embodiment, CAM 410 includes two rows (i.e., one row for each clause of k-XOR-SAT formula 450), but in other embodiments, CAM 410 may include a different number of rows. For example, if CAM-based circuit 400 is used to implement an arbitrary Boolean satisfiability problem (e.g., including one or more k-XOR-SAT clauses), the number of rows of CAM 410 may be equal to the number of clauses of the Boolean satisfiability problem.

[0061] CAM 410 also includes four columns, and thus each row of CAM 410 includes four CAM cells. As depicted, the first column (i.e., the leftmost column) of CAM 410 is associated with variable p of k-XOR-SAT formula 450. The second column of CAM 410 is associated with variable q of k-XOR-SAT formula 450, the third column of CAM 410 is associated with variable r of k-XOR-SAT formula 450, and the fourth column of CAM 410 is associated with variable s of k-XOR-SAT formula 450. Thus, when an input vector is applied to CAM 410, a first entry of the input vector associated with variable p (e.g., a first voltage signal) may be applied to a first column of CAM 410, a second entry of the input vector associated with variable q (e.g., a second voltage signal) may be applied to a second column of CAM 410, a third entry of the input vector associated with variable r (e.g., a third voltage signal) may be applied to a third column of CAM 410, and a fourth entry of the input vector associated with variable s (e.g., a fourth voltage signal) may be applied to a fourth column of CAM 410. Although in Figure 4A In a specific embodiment of the present invention, CAM 410 includes four columns (i.e., one column for each variable of k-XOR-SAT formula 450), but in other embodiments, CAM 410 may include a different number of columns. For example, if CAM-based circuit 400 is used to implement an arbitrary Boolean satisfiability problem (e.g., including one or more k-XOR-SAT clauses), the number of columns of CAM 410 may be equal to the number of variables in the Boolean satisfiability problem.

[0062] As mentioned above, the bottom row of CAM 410 is programmed to store the first k-XOR-SAT clause of k-XOR-SAT formula 450 (ie, ).exist Figure 4A In the specification examples, logical 1 is used to represent literal values / variables that are not negated in a clause, logical 0 is used to represent literal values / variables that are negated in a clause, and a wildcard value (i.e., "X") is used to represent variables that do not appear in the k-XOR-SAT clause.

[0063] Therefore, because variable q is not included in the first k-XOR-SAT clause of k-XOR-SAT formula 450, the second CAM cell of the bottom row is programmed to always return a matching wildcard value. This ensures that the second CAM cell of the bottom row does not interrupt the evaluation of the first k-XOR-SAT clause of k-XOR-SAT formula 450. The first, third, and fourth CAM cells of the bottom row may be referred to as literal value representation type CAM cells because they are programmed to store the literal value of the first k-XOR-SAT clause of k-XOR-SAT formula 450. In contrast, the second CAM cell of the bottom row may be referred to as a non-literal value representation type CAM cell because it is programmed to a wildcard value to account for the fact that the first k-XOR-SAT clause of k-XOR-SAT formula 450 does not include variable q.

[0064] The top row of CAM 410 is programmed to store the second k-XOR-SAT clause of k-XOR-SAT formula 450 (i.e., ). As depicted, the second through fourth CAM cells in the top row are literal value representation type CAM cells, while the first CAM cell in the top row is a non-literal value representation type CAM cell that is programmed to a wildcard value to account for the fact that the second k-XOR-SAT clause of the k-XOR-SAT formula 450 does not include the variable p.

[0065] The CAM-based circuit 400 also includes auxiliary circuits connected to the first match line ML1 and the second match line ML2, respectively. As mentioned above (and described in more detail below), these auxiliary circuits enable the CAM-based circuit 400 to implement the k-XOR-SAT clause using the same CAM hardware (e.g., CAM 410) used to implement the k-SAT clause.

[0066] As described above, unlike a k-SAT clause (in CNF) that includes a logical OR operation between its constituent literals, a k-XOR-SAT clause includes a logical XOR operation between its constituent literals. Because the XOR operation effectively performs an inverse parity check, an input vector (or more specifically, a set of variable assignments represented by the input vector) may satisfy the k-XOR-SAT clause if the number of matches between the input vector and the literal values ​​of the corresponding k-XOR-SAT clause satisfies a predetermined parity condition. For example, an input vector may satisfy the k-XOR-SAT clause if the input vector matches an odd number of literal values ​​of the k-XOR-SAT clause.

[0067] As the examples of the disclosed technology are designed for appreciation, the voltage of the match line typically decays at different rates, depending on the number of mismatches returned by the CAM cells connected to the match line (in various embodiments, this can be equivalent to the Hamming distance between the input vector and the stored word). That is, as the number of mismatches increases, the voltage of the match line will typically decay faster. In other words, relative to the number of mismatches, as the number of matches increases, the voltage of the match line will typically decay slower. Based on this insight, examples of the disclosed technology can count the number of matches (or conversely the number of mismatches) returned by the CAM cells connected to the match line based on the decay rate of the match line voltage. For example, the example can compare the match line voltage to a threshold voltage at multiple discrete times (e.g., at time intervals of 0.25 au seconds) to count the number of matches returned by the match line. For example, the number of matches returned by the match line can correspond to the number of comparisons described above in which the match line voltage exceeds the threshold voltage.

[0068] Combining the above insights with programming k-XOR-SAT clauses into rows of CAM, an example can count the number of matches between an input vector and a k-XOR-SAT clause comprising k literal values ​​by: (1) comparing a threshold voltage with the voltage of a match line associated with a row of CAM cells programmed to store the k-XOR-SAT clause at k discrete times (e.g., at 0.25 au second intervals); and (2) counting the number of matches returned by the match line based on k voltage comparisons (e.g., the number of comparisons in which the match line voltage exceeds the threshold voltage). For conceptual illustration, Figure 5 An example graph 500 is depicted illustrating a comparison between a threshold voltage and a voltage output of a match line associated with a row of CAM cells that are programmed to store a k-XOR-SAT clause that includes k=3 literal values. As depicted, the threshold voltage is 0.9 au volts, and the match line voltage is compared to the threshold voltage at three discrete times: t=10.00 au seconds; t=10.25 au seconds; and t=10.50 au seconds. If the match line returns three matches (as illustrated by curve 502), the match line voltage will exceed the threshold voltage three times. If the match line returns two matches (as illustrated by curve 504), the match line voltage will exceed the threshold voltage twice. If the match line returns one match (as illustrated by curve 506), the match line voltage will exceed the threshold voltage once. If the match line returns zero matches (as illustrated by curve 508), the match line voltage will exceed the threshold voltage zero times. Here, the threshold voltage and sense / compare times can be strategically selected to match such a relationship.

[0069] Reference again Figure 4A, CAM 400 includes auxiliary voltage comparison, counting and logic circuits to implement the above method. For example, sense amplifier 410 is electrically connected to the first match line ML1 associated with the bottom row of CAM 410. Therefore, sense amplifier 410 can receive the voltage output of the first match line ML1 and compare the voltage output of the first match line ML1 with the threshold voltage at k=3 discrete times.

[0070] As depicted, counter circuit 420 is electrically connected to sense amplifier 410 and accordingly receives an output from sense amplifier 410. Based on the output from sense amplifier 410, counter circuit 420 may count the number of matches returned by first match line ML1 (e.g., count the number of comparisons in which the voltage of first match line ML1 exceeds a threshold voltage).

[0071] As depicted, logic circuit 430 is electrically connected to counter circuit 420 and accordingly receives output from counter circuit 420. Based on the output from counter circuit 420, logic circuit 430 may determine whether the counted number of matches satisfies a predetermined parity condition (e.g., an odd number of matches) and output an indication of whether the input vector satisfies or violates the k-XOR-SAT clause (i.e., ) signal.

[0072] Similarly, sense amplifier 412 is electrically connected to a second match line ML2 associated with the top row of CAM 410. Thus, sense amplifier 412 can receive the voltage output of second match line ML2 and compare the voltage output of second match line ML2 to a threshold voltage at k=3 discrete times.

[0073] As depicted, counter circuit 422 is electrically connected to sense amplifier 412 and accordingly receives the output from sense amplifier 412. Based on the output from sense amplifier 412, counter circuit 422 can count the number of matches returned by second match line ML2 (e.g., count the number of comparisons in which the voltage of second match line ML2 exceeds the threshold voltage).

[0074] As depicted, logic circuit 432 is electrically connected to counter circuit 422 and accordingly receives output from counter circuit 422. Based on the output from counter circuit 422, logic circuit 432 may determine whether the counted number of matches satisfies a predetermined parity condition (e.g., an odd number of matches) and output an indication of whether the input vector satisfies or violates the k-XOR-SAT clause (i.e., ) signal.

[0075] In various embodiments, logic circuits 430 and 432 may be connected to a processor (or in some embodiments, to additional logic circuits) that determines whether the input vector satisfies k-XOR-SAT formula 450. For example, the processor may determine that the input vector satisfies k-XOR-SAT formula 450 if the processor receives signals from both logic circuits 430 and 432 indicating that the input vector satisfies their respective k-XOR-SAT clauses. Figure 4B A truth table 470 for evaluating the k-XOR-SAT formula 450 using the CAM-based circuit 400 is depicted in FIG. As depicted, the k-XOR-SAT formula 450 is solved when (f=1).

[0076] As mentioned above, the CAM-based circuit 400 may also be used to implement larger Boolean satisfiability problems. For example, the CAM-based circuit 400 may include additional rows programmed to store additional clauses of the larger Boolean satisfiability problem. These additional rows may be programmed to store k-XOR-SAT clauses, but may also store k-SAT clauses. In the case where the CAM-based circuit 400 is also used to implement k-SAT clauses, the match lines associated with the k-SAT clauses may not include a combination of Figure 4A This is because implementing the k-SAT clause may not involve counting the number of matches returned by the CAM cells of the common row. In the case where the k-SAT clause is implemented in DNF (e.g., in conjunction with Figure 2 and Figure 3A-3B ), the match line output associated with the DNF k-SAT clause (or alternatively, the match line output associated with the k-XOR-SAT clause) can be connected to logic circuits and / or inverters to illustrate the fact that the original k-SAT clause converted to DNF for CAM programming is satisfied with a mismatch, while the k-XOR-SAT clause implemented on the CAM-based circuit 400 is satisfied with a match.

[0077] Figure 6 Depicted is an example flow chart for solving a Boolean satisfiability problem using a CAM-based circuit, in accordance with various examples of the presently disclosed techniques.

[0078] Operation 606 includes comparing the voltage output of the match line associated with a row of CAM cells with a threshold voltage at k discrete times. The row of CAM cells can be programmed to store a k-XOR-SAT clause of a Boolean satisfiability problem. k can represent the number of literal values ​​of the k-XOR-SAT clause. Therefore, the row of CAM cells can include at least k literal value representation type CAM cells. One literal value representation type CAM cell among the k literal value representation type CAM cells can be programmed to store a literal value of the k-XOR-SAT clause. The literal value representation type CAM cell can be programmed to store a first value (e.g., a logical 0 or a logical 1) when the literal value is negated in the k-XOR-SAT clause. The literal value representation type CAM cell can be programmed to store a second value (e.g., the other of a logical 0 and a logical 1) when the literal value is not negated in the k-XOR-SAT clause. As mentioned above, programming the literal value representation type CAM cell may include programming the conductance of one or more memristors of the literal value representation type CAM cell. As described above, operation 606 may be performed by a sense amplifier electrically connected to the match line.

[0079] Operation 608 includes counting the number of matches returned by the match line based on the k voltage comparisons. As mentioned above, counting the number of matches returned by the match line based on the k voltage comparisons may include counting the number of k voltage comparisons in which the voltage output of the match line exceeds the threshold voltage. As described above, operation 608 may be performed by a counting circuit electrically connected to the sense amplifier.

[0080] Operation 610 includes determining that the input vector satisfies the k-XOR-SAT clause based on that the counted number of matches satisfies a predetermined parity condition. In some embodiments, the predetermined parity condition may include an odd number of matches. In other embodiments, the predetermined parity condition may include an even number of matches. As described above, operation 610 may be performed by a processor that receives an output from a logic circuit electrically connected to a counting circuit. The output from the logic circuit may be a signal indicating that the input vector satisfies the k-XOR-SAT clause based on that the counted number of matches satisfies a predetermined parity condition.

[0081] As depicted, in certain implementations, the flowchart may further include operations 612 - 616. Here, it should be understood that operations 612 - 616 may be performed in parallel (ie, approximately concurrently) with operations 606 - 610 due to the parallel search capability of the CAM.

[0082] For example, operation 612 may include comparing the voltage output of the second match line associated with the second row of CAM cells with a threshold voltage at k discrete times. The second row of CAM cells may be programmed to store a second k-XOR-SAT clause of the Boolean satisfiability problem. In some embodiments, the second k-XOR-SAT clause may include less than k literals. For example, the second k-XOR-SAT clause may include (kn) literals. Therefore, the second row of CAM cells may include (kn) literal representation type CAM cells and n non-literal representation type CAM cells. As mentioned above, the n non-literal representation type CAM cells may be programmed to store wildcard values ​​that always return a match so that they do not interrupt the evaluation of the second k-XOR-SAT clause programmed into the second row of CAM cells. As described above, operation 612 may be performed by a second sense amplifier electrically connected to the second match line.

[0083] Operation 614 includes counting the number of matches returned by the second match line based on the k voltage comparisons associated with the voltage output of the second match line. As mentioned above, counting the number of matches returned by the second match line may include counting the number of k voltage comparisons associated with the voltage output of the second match line in which the voltage output of the second match line exceeds the threshold voltage. As described above, operation 614 may be performed by a second counting circuit electrically connected to the second sense amplifier.

[0084] Operation 616A includes: determining that the input vector satisfies the second k-XOR-SAT clause based on the counted number of matches satisfying the predetermined parity condition. Alternatively, operation 616B includes: determining that the input vector violates the second k-XOR-SAT clause based on the counted number of matches violating the predetermined parity condition. As described above, operations 616A-B can be performed by a processor that receives an output from a second logic circuit electrically connected to a second counting circuit. A first output from the second logic circuit (corresponding to operation 616A) can be a signal indicating that the input vector satisfies the k-XOR-SAT clause based on the counted number of matches satisfying the predetermined parity condition. A second output from the second logic circuit (corresponding to operation 616B) can be a signal indicating that the input vector violates the k-XOR-SAT clause based on the counted number of matches violating the predetermined parity condition. In various embodiments, a common (i.e., identical) processor can perform operations 616A-B and operation 610. In some embodiments, the processor may also determine whether the input vector satisfies or violates the Boolean satisfiability problem based on the output of the logic circuit from the CAM-based circuit. For example, if the processor receives an indication that the input vector satisfies all clauses programmed into the CAM-based circuit, the processor may determine that the input vector satisfies the Boolean satisfiability problem.

[0085] Figure 7 A block diagram of an example computer system 700 is depicted in which various examples described herein may be implemented.

[0086] Computer system 700 includes a bus 712 or other communication mechanism for communicating information, and one or more hardware processors 704 coupled with bus 712 for processing information. Hardware processor(s) 704 may be, for example, one or more general-purpose microprocessors.

[0087] The computer system 700 also includes a main memory 706, such as a random access memory (RAM), cache, and / or other dynamic storage device, coupled to the bus 712 for storing information and instructions to be executed by the processor 704. The main memory 706 may also be used for storing temporary variables or other intermediate information during execution of instructions to be executed by the processor 704. When stored in a storage medium accessible to the processor 704, such instructions cause the computer system 700 to appear as a special-purpose machine customized to perform the operations specified in the instructions.

[0088] The computer system 700 further includes a read only memory (ROM) 712 or other static storage device coupled to the bus 712 for storing static information and instructions for the processor 704. A storage device 714, such as a magnetic disk, optical disk, or USB thumb drive (flash drive), etc., is provided and coupled to the bus 712 for storing information and instructions.

[0089] The computer system 700 additionally includes a hardware accelerator 708. The hardware accelerator 708 may be configured to execute instructions (i.e., programming or software code) stored in the main memory 706, the read-only memory (ROM) 712, and / or the storage device 714 to encode a set of logic rules embodied in a Boolean satisfiability problem (e.g., the k-XOR-SAT problem) into a CAM-based circuit 710. In an example implementation, the exemplary hardware accelerator 708 may include a plurality of integrated circuits, which in turn may include an application specific integrated circuit (ASIC), a field programmable gate array (FPGA), or other very large scale integrated circuit (VLSI). The integrated circuits of the exemplary hardware accelerator 708 may be specifically optimized to perform a discrete subset of computer processing operations or to execute a discrete subset of computer executable instructions in an accelerated manner. For example, the hardware accelerator 708 may be configured or manufactured to implement a set of logic rules embodied in a Boolean satisfiability problem (e.g., the k-XOR-SAT problem) into a CAM-based circuit 710.

[0090] CAM-based circuit 710 may include non-volatile memory constructed using technologies including, for example, resistive switch memory (i.e., memristor), phase change memory, magnetoresistive memory, ferroelectric memory, some other resistive random access memory device (Re-RAM), or a combination of those technologies. More generally, CAM-based circuit 710 may be implemented using technologies that permit CAM-based circuit 710 to retain its contents even when power is lost or otherwise removed. Thus, data in CAM-based circuit 710 "persists," and CAM-based circuit 710 may act as so-called "non-volatile memory."

[0091] The computer system 700 may be coupled to a display 716, such as a liquid crystal display (LCD) (or touch screen), via bus 712 for displaying information to a computer user. An input device 718, including alphanumeric and other keys, is coupled to bus 712 for communicating information and command selections to processor 704. Another type of user input device is a cursor control 720, such as a mouse, trackball, or cursor direction keys, for communicating direction information and command selections to processor 704 and for controlling cursor movement on display 716. In some embodiments, the same direction information and command selections as a cursor control may be implemented via receiving touches on a touch screen without a cursor.

[0092] The computing system 700 may include a user interface module to implement a GUI, which may be stored in a mass storage device as executable software code executed by the computing device(s). This module and other modules may include components such as software components, object-oriented software components, class components, and task components, processes, functions, properties, procedures, subroutines, program code segments, drivers, firmware, microcode, circuit systems, data, databases, data structures, tables, arrays, and variables, for example.

[0093] In general, as used herein, the terms "component", "engine", "system", "database", "data storage device", etc. may refer to logic embodied in hardware or firmware, or to a collection of software instructions, possibly with entry and exit points, written in a programming language such as, for example, Java, C, or C++. Software components may be compiled and linked into executable programs installed in dynamic link libraries, or may be written in interpreted programming languages ​​such as, for example, BASIC, Perl, or Python. It will be appreciated that software components may be callable from other components or themselves, and / or may be called in response to detected events or interrupts. Software components configured for execution on a computing device may be provided on a computer-readable medium such as a compact disc, digital video disc, flash drive, magnetic disk, or any other tangible medium, or provided as a digital download (and may be initially stored in a compressed or installable format that requires installation, decompression, or decryption prior to execution). Such software code may be stored in part or in whole on a memory device of an executing computing device for execution by the computing device. Software instructions may be embedded in firmware such as an EPROM. It will be further appreciated that hardware components may include connected logic units (such as gates and flip-flops), and / or may include programmable units (such as a programmable gate array or processor).

[0094] The computer system 700 may implement the techniques described herein using custom hardwired logic, one or more ASICs or FPGAs, firmware, and / or program logic that, in combination with the computer system, causes the computer system 700 to become a special-purpose machine or programs the computer system to become a special-purpose machine. According to one embodiment, the techniques herein are performed by the computer system 700 in response to the processor(s) 704 executing one or more sequences of one or more instructions contained in the main memory 706. Such instructions may be read into the main memory 706 from another storage medium, such as the storage device 714. Execution of the sequences of instructions contained in the main memory 706 causes the processor(s) 704 to perform the process steps described herein. In alternative embodiments, hardwired circuitry may be used in place of or in combination with software instructions.

[0095] As used herein, the term "non-transitory media" and similar terms refer to any medium that stores data and / or instructions that cause a machine to operate in a particular manner. Such non-transitory media may include non-volatile media and / or volatile media. Non-volatile media include, for example, optical or magnetic disks, such as storage device 714. Volatile media include dynamic memory, such as main memory 706. Common forms of non-transitory media include, for example, floppy disks, diskettes, hard disks, solid-state drives, tapes or any other magnetic data storage media, CD-ROMs, any other optical data storage media, any physical media with a pattern of holes, RAM, PROMs and EPROMs, FLASH-EPROMs, NVRAMs, any other memory chips or cassettes, and network versions thereof.

[0096] Non-transitory media are distinct from, but may be used in conjunction with, transmission media. Transmission media participate in the transfer of information between non-transitory media. For example, transmission media include coaxial cables, copper wire, and optical fiber, including the cables that comprise bus 712. Transmission media may also take the form of acoustic or light waves, such as those generated during radio wave and infrared data communications.

[0097] The computer system 700 also includes a communication / network interface 722 coupled to the bus 712. The network interface 722 provides a bidirectional data communication connection to one or more network links (the one or more network links are connected to one or more local networks). For example, the communication interface 722 can be an integrated services digital network (ISDN) card, a cable modem, a satellite modem, or a modem for providing a data communication connection to a corresponding type of telephone line. As another example, the network interface 722 can be a local area network (LAN) card to provide a data communication connection to a compatible LAN (or a WAN component for communicating with a WAN). A wireless link can also be implemented. In any such implementation, the network interface 718 sends and receives electrical, electromagnetic, or optical indicators that carry digital data streams representing various types of information.

[0098] A network link typically provides data communication through one or more networks to other data devices. For example, a network link may provide a connection through a local network to a host computer or to data devices operated by an Internet Service Provider (ISP). The ISP, in turn, provides data communication services through the global packet data communication network now commonly referred to as the "Internet." Both the local network and the Internet use electrical, electromagnetic, or optical indicators that carry digital data streams. The indicators through the various networks and on the network link and through the communication interface 722 carry the digital data to and from the computer system 700, and these indicators are exemplary forms of transmission media.

[0099] Computer system 700 can send messages and receive data, including program code, through the network(s), network links and communications interface 718. In the Internet example, a server can transmit code requested for an application through the Internet, an ISP, a local network and communications interface 722.

[0100] The received code may be executed by processor 704 as it is received, and / or stored in storage device 714 or other non-volatile storage for later execution.

[0101] Each of the processes, methods and algorithms described in the foregoing sections may be embodied in a code component executed by one or more computer systems or computer processors including computer hardware, and fully or partially automated by the code component. The one or more computer systems or computer processors may also be operable to support the performance of related operations in a "cloud computing" environment or as a "software as a service" (SaaS). These processes and algorithms may be implemented in part or in whole in a dedicated circuit system. The various features and processes described above may be used independently of each other, or may be combined in various ways. Different combinations and sub-combinations are intended to fall within the scope of the present disclosure, and certain methods or process blocks may be omitted in some embodiments. The methods and processes described herein are also not limited to any particular sequence, and the blocks or states associated therewith may be executed in other appropriate sequences, or may be executed in parallel, or in some other manner. Blocks or states may be added to or removed from the disclosed example embodiments. The execution of certain operations or processes may be distributed among computer systems or computer processors, not only residing in a single machine, but also deployed across several machines.

[0102] As used herein, any form of hardware, software or combination thereof may be utilized to implement the circuit. For example, one or more processors, controllers, ASICs, PLAs, PALs, CPLDs, FGAs, logic components, software routines or other mechanisms may be implemented to form the circuit. In an embodiment, the various circuits described herein may be implemented as discrete circuits, or the functions and features described may be partially or entirely shared in the middle of one or more circuits. Even if the various features or elements of the functions may be described or claimed separately as separate circuits, these features and functions may be shared in the middle of one or more common circuits, and such descriptions should not require or imply the need for separate circuits to implement such features or functions. In the case of using software to implement the circuit in whole or in part, such software may be implemented to operate together with a computing or processing system (such as, computer system 700) that can implement the functions described therein.

[0103] As used herein, the term "or" may be interpreted in either an inclusive or exclusive sense. Furthermore, descriptions of resources, operations, or structures in the singular should not be interpreted as excluding the plural. Conditional language (such as, among others, "may," "might," "might," or "could"), unless specifically stated otherwise or otherwise understood within the context as used, is generally intended to convey that certain embodiments include certain features, elements, and / or steps, while other embodiments do not include certain features, elements, and / or steps.

[0104] Unless expressly stated otherwise, the terms and phrases used in this document and variations thereof should be interpreted as open-ended and not restrictive. Adjectives such as "conventional," "traditional," "normal," "standard," "known," and terms of similar meaning should not be interpreted as limiting the items described to a given time period or items available at a given time, but should be interpreted as covering conventional, traditional, normal, or standard technology that may be available or known at any time now or in the future. In some cases, the appearance of expanding words and phrases (such as, "one or more," "at least," "but not limited to," or other similar phrases) should not be interpreted as meaning that a narrower scope is intended or required where such expanding phrases might not exist.

Claims

1. A circuit comprising: a row of content addressable memory (CAM) cells programmed to store k-XOR-SAT clauses of a Boolean satisfiability problem; A sense amplifier that performs the following operations in response to an input vector applied to the row of CAM cells: comparing a voltage output of a match line associated with the row of CAM cells to a threshold voltage at k discrete times, wherein k represents the number of literal values ​​of the k-XOR-SAT clause; a counter circuit that counts the number of matches returned by the match line based on the k voltage comparisons of the sense amplifier; and A logic circuit outputs a signal indicating that the input vector satisfies the k-XOR-SAT clause based on the counted number of matches satisfying a predetermined parity condition.

2. The circuit according to claim 1, wherein: The row of CAM cells includes k literal value representation type CAM cells; and A literal value representation type CAM cell among the k literal value representation type CAM cells is programmed to store a literal value of the k-XOR-SAT clause.

3. The circuit according to claim 1, wherein: The counted number of matches corresponds to the number of the k voltage comparisons in which the voltage output of the match line exceeds the threshold voltage.

4. The circuit according to claim 1, wherein: The predetermined parity condition includes an odd matching number.

5. The circuit according to claim 2, wherein: Programming the literal value representation type CAM cell to store the literal value of the k-XOR-SAT clause comprises: programming the literal value representation type CAM cell to: store a first value when the literal value is negated in the k-XOR-SAT clause; and The literal-representing CAM cell is programmed to store a second value when the literal is not negated in the k-XOR-SAT clause.

6. The circuit of claim 5, wherein: The row of CAM cells further includes non-literal CAM cells programmed to store wildcard values.

7. The circuit according to claim 2, wherein: Programming the literal value representation type CAM cell to store the literal value of the k-XOR-SAT clause comprises: The conductance of a memristor included in the literal value representation type CAM cell is programmed.

8. The circuit of claim 1, further comprising: a second row of CAM cells programmed to store a second k-XOR-SAT clause of the Boolean satisfiability problem; A second sense amplifier, in response to the input vector being applied to the second row of CAM cells, performs the following operations: comparing a voltage output of a second match line associated with the second row of CAM cells with the threshold voltage at the k discrete times; a second counter circuit that counts a number of matches returned by the second match line based on the k voltage comparisons of the second sense amplifier; as well as A second logic circuit outputs a signal indicating that the input vector satisfies the second k-XOR-SAT clause based on the counted number of matches satisfying the predetermined parity condition.

9. The circuit of claim 8, further comprising a processor, the processor performing the following operations in response to receiving the signal from the first logic circuit and the signal from the second logic circuit: It is determined that the input vector satisfies the Boolean satisfiability problem.

10. A method for solving a Boolean satisfiability problem using a CAM-based circuit, the method comprising: The voltage output of a match line associated with a row of CAM cells is compared to a threshold voltage at k discrete times, where: The CAM-based circuit comprises the row of CAM cells, The row of CAM cells is programmed to store k-XOR-SAT clauses of the Boolean satisfiability problem, and k represents the number of literal values ​​of the k-XOR-SAT clause; counting a number of matches returned by the match line based on the k voltage comparisons; and The input vector is determined to satisfy the k-XOR-SAT clause based on the counted number of matches satisfying a predetermined parity condition.

11. The method according to claim 10, further comprising: comparing a voltage output of a second match line associated with a second row of CAM cells with the threshold voltage at the k discrete times, wherein: The CAM-based circuit comprises the second row of CAM cells, The second row of CAM cells is programmed to store a second k-XOR-SAT clause of the Boolean satisfiability problem, counting a number of matches returned by the second match line based on the k voltage comparisons associated with the voltage output of the second match line; and The input vector is determined to satisfy the second k-XOR-SAT clause based on the counted number of matches returned by the second match line satisfying the predetermined parity condition.

12. The method according to claim 10, further comprising: comparing a voltage output of a second match line associated with a second row of CAM cells with the threshold voltage at the k discrete times, wherein: The CAM-based circuit comprises the second row of CAM cells, The second row of CAM cells is programmed to store a second k-XOR-SAT clause of the Boolean satisfiability problem, counting a number of matches returned by the second match line based on the k voltage comparisons associated with the voltage output of the second match line; and The input vector is determined to violate the second k-XOR-SAT clause based on the counted number of matches returned by the second match line violating the predetermined parity condition.

13. The method according to claim 11, further comprising: It is determined that the input vector satisfies the Boolean satisfiability problem.

14. The method according to claim 12, further comprising: It is determined that the input vector violates the Boolean satisfiability problem.

15. The method of claim 10, wherein: The row of CAM cells includes k literal value representation type CAM cells; and A literal value representation type CAM cell among the k literal value representation type CAM cells is programmed to store a literal value of the k-XOR-SAT clause.

16. The method according to claim 15, further comprising: programming the literal value representation type CAM cell to: store a first value when the literal value is negated in the k-XOR-SAT clause; as well as The CAM cell is programmed to store a second value when the literal value is not negated in the k-XOR-SAT clause.

17. The method according to claim 15, further comprising: The literal value representing CAM cell is programmed to store the literal value of the k-XOR-SAT clause by programming a conductance of a memristor included in the literal value representing CAM cell.

18. A CAM-based circuit comprising: A row of CAM cells is programmed to store k-XOR-SAT clauses of a Boolean satisfiability problem, where: k represents the number of literal values ​​of the k-XOR-SAT clause, The row of CAM cells includes k literal value representation type CAM cells, and A literal value representation type CAM cell among the k literal value representation type CAM cells is programmed to store a literal value of the k-XOR-SAT clause; A sense amplifier that performs the following operations in response to an input vector applied to the row of CAM cells: comparing a voltage output of a match line associated with the row of CAM cells to a threshold voltage at k discrete times; a counter circuit that counts the number of matches returned by the match line based on the k voltage comparisons of the sense amplifier; and A logic circuit outputs a signal indicating that the input vector satisfies the k-XOR-SAT clause based on the counted number of matches satisfying a predetermined parity condition.

19. The CAM-based circuit of claim 18, wherein: The counted number of matches corresponds to the number of the k voltage comparisons in which the voltage output of the match line exceeds the threshold voltage.

20. The CAM-based circuit of claim 18, wherein: Programming the literal value representation type CAM cell to store the literal value of the k-XOR-SAT clause comprises: programming the literal value representation type CAM cell to: store a first value when the literal value is negated in the k-XOR-SAT clause; and The literal-representing CAM cell is programmed to store a second value when the literal is not negated in the k-XOR-SAT clause.

Images