Memory device including charge pump for generating voltage and method of operating same

Abstract

The present disclosure relates to a memory device including a charge pump for generating a voltage and a method of operating the same, the memory device including: a memory cell array including a plurality of planes; a charge pump configured to generate an operating voltage for operating each of the plurality of planes according to a first clock signal having a first period; page buffers each configured to store pass data indicating whether an operation of each of the plurality of planes has been completed; and an operation control circuit configured to control the charge pump to generate an operation voltage according to a second clock signal having a second period longer than the first period, based on an amount of pass data received from the page buffer.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the priority of Korean Patent Application No. 10-2023-0103402 filed on August 8, 2023 in the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] The present disclosure relates generally to an electronic device, and more particularly, to a memory device including a charge pump for generating a voltage and an operating method thereof. Background Art

[0004] A memory system is a device that stores data under the control of a host device such as a computer or a smart phone. A memory system may include a memory device for storing data and a memory controller for controlling the memory device. Memory devices are classified into volatile memory devices and nonvolatile memory devices.

[0005] A nonvolatile memory device is a memory device in which data does not disappear even if power supply is interrupted. Nonvolatile memory devices may include read only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable ROM (EEROM), flash memory, etc.

[0006] The non-volatile memory device may include a charge pump for generating a voltage for operation. The charge pump may generate the voltage in response to a clock signal. The amount of current consumed when generating the voltage may vary according to the cycle of the clock signal. As the cycle of the clock signal becomes shorter, the amount of current consumed by the charge pump increases. Summary of the invention

[0007] According to one aspect of the present disclosure, a memory device is provided, comprising: a memory cell array including a plurality of planes; a charge pump configured to generate an operating voltage for operation on each of the plurality of planes according to a first clock signal having a first period; page buffers, each page buffer being configured to store pass data indicating whether the operation of each of the plurality of planes has been completed; and an operation control circuit configured to control the charge pump to generate an operating voltage according to a second clock signal having a second period longer than the first period based on the amount of pass data received from the page buffer.

[0008] According to another aspect of the present disclosure, a memory device is provided, which includes: a plurality of memory blocks included in different planes; a clock generation circuit configured to generate a clock signal; a charge pump configured to generate an operating voltage to be applied to each of the plurality of memory blocks in response to the clock signal; and an operation control circuit configured to control the clock generation circuit to change the period of the clock signal from a first period to a second period longer than the first period based on the number of memory blocks among the plurality of memory blocks for which operations corresponding to a command have been completed.

[0009] According to another aspect of the present disclosure, a memory device is provided, the memory device comprising a memory cell array and a control circuit. The memory cell array may include a plurality of planes. The control circuit may be configured to: generate a first clock having a first cycle when the number of operating planes in the plurality of planes is greater than a threshold number; and generate a second clock having a second cycle longer than the first cycle when the number of operating planes in the plurality of planes is equal to or less than the threshold number.

[0010] According to another aspect of the present disclosure, a method for operating a memory device is provided, the method comprising: generating an operating voltage in a first cycle according to a first clock signal having a first period; storing data indicating whether an operation on each of a plurality of planes in the first cycle has been completed; and generating an operating voltage in a second cycle according to a second clock signal having a second period longer than the first period based on the number of pass data indicating that the operation on each of the plurality of planes in the first cycle has been completed. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Example embodiments will now be described more fully hereinafter with reference to the accompanying drawings; however, they may be implemented in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the example embodiments to those skilled in the art.

[0012] In the accompanying drawings, dimensions may be exaggerated for clarity of illustration. It will be understood that when an element is referred to as being "between" two elements, it may be the only element between the two elements, or one or more intermediate elements may be present. The same reference numerals represent the same elements throughout the disclosure.

[0013] Figure 1 is a diagram illustrating a memory system including a memory device according to an embodiment of the present disclosure.

[0014] Figure 2 is a diagram illustrating threshold voltage distributions of memory cells according to a program operation.

[0015] Figure 3 is a diagram illustrating a program operation including a plurality of program loops.

[0016] Figure 4 is a diagram illustrating threshold voltage distributions of memory cells according to an erase operation.

[0017] Figure 5 is a diagram illustrating an erase operation including a plurality of erase cycles.

[0018] Figure 6 is a diagram illustrating a memory device for generating an operating voltage according to a clock signal determined based on operating plane information.

[0019] Figure 7 is a diagram illustrating a charge pump.

[0020] Figure 8 is a diagram illustrating a memory device for changing a period of a clock signal according to operation plane information in a plurality of cycles.

[0021] Fig. 9 is a diagram illustrating a memory device for changing a period of a clock signal according to operation plane information and bad block information in a plurality of cycles.

[0022] Fig.10 and Fig.11 is a diagram illustrating a memory device for determining a period of a clock signal based on operation plane information provided by a first operation plane counter and a second operation plane counter, respectively.

[0023] Fig.12 is a flow chart showing that a memory device generates an operating voltage according to a clock signal determined based on the number of passed data.

[0024] Fig.13 is a diagram showing the structure of a memory device. DETAILED DESCRIPTION

[0025] The specific structural or functional descriptions disclosed herein are merely illustrative and are intended to describe embodiments of the present disclosure. Embodiments of the present disclosure may be implemented in various forms and should not be construed as being limited to the embodiments described herein.

[0026] Embodiments provide a memory device capable of reducing current consumption of a charge pump generated voltage and an operating method of the memory device.

[0027] Figure 1 is a diagram illustrating a memory system including a memory device according to an embodiment of the present disclosure.

[0028] Reference Figure 1, the memory system 50 may include a memory device 100 and a memory controller 200. The memory system 50 may be included not only in mobile devices such as mobile phones, tablet PCs, and wearable devices, but also in various electronic devices such as computers, servers, and cars. The memory system 50 may be a device that stores data under the control of a host 300 as an external device.

[0029] The memory system 50 may be manufactured as any of various types of storage devices, such as a solid state drive (SSD) and a universal flash memory (UFS), according to a host interface as a communication scheme with the host 300. The memory system 50 may be manufactured as any of various package types, such as a system on chip (SOC).

[0030] The memory device 100 may store data. The memory device 100 may operate under the control of the memory controller 200. In an embodiment, the memory device 100 may be a nonvolatile memory device or a volatile memory device.

[0031] The memory device 100 may receive a command and an address from the memory controller 200, and perform an operation indicated by the command on an area selected by the address. The memory device 100 may perform a program operation (write operation) to store data in an area selected by the address, a read operation to read data from an area selected by the address, or an erase operation to erase data in an area selected by the address.

[0032] The memory controller 200 may control the overall operations of the memory system 50 .

[0033] When power is applied to the memory system 50, the memory controller 200 may run firmware (FW). In an embodiment, the memory controller 200 may control communication between the host 300 and the memory device 100 by running the FW. In an embodiment, the memory controller 200 may convert a logical address of the host 300 into a physical address of the memory device 100.

[0034] The memory controller 200 may control the memory device 100 to perform a program operation, a read operation, an erase operation, etc. in response to a request of the host 300. The memory controller 200 may provide a command, a physical address, or data to the memory device 100 according to the program operation, the read operation, or the erase operation.

[0035] In an embodiment, the memory controller 200 may autonomously generate commands, addresses, and data regardless of any request from the host 300, and send the commands, addresses, and data to the memory device 100. For example, the memory controller 200 may provide the memory device 100 with commands, addresses, and data for performing a program operation, a read operation, and an erase operation accompanying a background operation such as wear leveling, read reclamation, or garbage collection.

[0036] In an embodiment, the memory controller 200 may control at least two memory devices 100. The memory controller 200 may control the memory devices 100 according to an interleaving scheme in order to improve operation performance. The interleaving scheme may be a scheme for controlling internal operations of at least two memory devices 100 to overlap each other.

[0037] The host 300 may communicate with the memory system 50 using various communication schemes.

[0038] In an embodiment, memory device 100 may include memory cell array 140, page buffer group 160, and control circuit 180. Page buffer group 160 may include first to fourth page buffers 161 to 164. Control circuit may include voltage generation circuit 150 and operation control circuit 170.

[0039] The memory cell array 140 may include a plurality of planes. In an embodiment, when the memory cell array 140 is configured with four planes, the memory cell array 140 may include first to fourth planes 141 to 144. In another embodiment, the memory cell array 140 may include less than three or more than five planes.

[0040] The first plane 141 to the fourth plane 144 may include a plurality of storage blocks BLK1 to BLKi. Each of the plurality of storage blocks BLK1 to BLKi may include a plurality of memory cells. Each of the first plane 141 to the fourth plane 144 may independently perform a programming operation, a read operation, or an erase operation. In an embodiment, the first storage block BLK1 included in the first plane 141, the second storage block BLK2 included in the second plane 142, the third storage block BLK3 included in the third plane 143, and the fourth storage block BLK4 included in the fourth plane 144 may simultaneously perform a programming operation of storing data. In another embodiment, the first storage block BLK1 to the fourth storage block BLK4 included in different planes may simultaneously perform an erase operation of erasing stored data or a read operation of reading stored data.

[0041] The first to fourth planes 141 to 144 may be connected to the first to fourth page buffers 161 to 164 through the first to fourth bit lines BL1 to BL4, respectively. Figure 1 In the description, a case where one page buffer is connected to one plane is taken as an example. Two or more page buffers may be connected to one plane.

[0042] In a program operation, the first to fourth planes 141 to 144 may store data received from the first to fourth page buffers 161 to 164. In a verification operation or a read operation, the first to fourth page buffers 161 to 164 may store data sensed from the first to fourth planes 141 to 144, respectively. The first to fourth page buffers 161 to 164 may provide the operation control circuit 170 with the data sensed from the first to fourth planes 141 to 144. The first to fourth page buffers 161 to 164 may provide the operation control circuit 170 with pass data or fail data indicating whether an operation on each of the first to fourth planes 141 to 144 has been completed.

[0043] In an embodiment, the control circuit 180 may be configured to generate a first clock having a first period when the number of operating planes in the plurality of planes is greater than a threshold number. In addition, the control circuit 180 may be configured to generate a second clock having a second period longer than the first period when the number of operating planes in the plurality of planes is equal to or less than the threshold number.

[0044] In an embodiment, the voltage generating circuit 150 of the control circuit 180 may be configured to generate an operating voltage for driving a plurality of planes in response to at least one of the first clock and the second clock. For example, the voltage generating circuit 150 may generate an operating voltage for a programming operation, a read operation, or an erase operation. In an embodiment, the operating voltage may include a programming voltage, a programming pass voltage, and a programming verification voltage for a programming operation. In an embodiment, the operating voltage may include a read voltage and a read pass voltage for a read operation. In an embodiment, the operating voltage may include an erase voltage, an erase pass voltage, and an erase verification voltage for an erase operation.

[0045] In an embodiment, the voltage generating circuit 150 may generate an operating voltage and may provide the generated operating voltage to each of the first to fourth planes 141 to 144 and the page buffer group 160. Each of the first to fourth planes 141 to 144 may perform a program operation, a read operation, or an erase operation according to the operating voltage.

[0046] In an embodiment, the voltage generating circuit 150 may include a charge pump 151 and a clock generating circuit 152. The clock generating circuit 152 may generate a clock signal according to a clock control signal generated in the operation control circuit 170. In an embodiment, the clock generating circuit 152 may generate a first clock signal having a first period or a second clock signal having a second period. For example, the first period is different from the second period. In an embodiment, the period of the first period may be longer than the period of the second period. The clock generating circuit 152 may provide at least one of the first clock signal and the second clock signal to the charge pump 151.

[0047] The charge pump 151 may generate at least one operating voltage by pumping a power supply voltage based on a clock signal.

[0048] The operation control circuit 170 may control an operation corresponding to a command in response to a command provided from the memory controller 200. In an embodiment, the operation control circuit 170 may control the voltage generation circuit 150 to generate an operation voltage for a program operation, a read operation, or an erase operation.

[0049] In an embodiment, the operation control circuit 170 may include a clock control circuit 171 , an operation plane counter 172 , and a bad block information storage device 173 .

[0050] The clock control circuit 171 may provide a clock control signal for generating a clock signal to the clock generation circuit 152. In an embodiment, the clock control circuit 171 may provide a first clock control signal to the clock generation circuit 152 in response to a first clock signal or provide a second clock control signal to the clock generation circuit 152 in response to a second clock signal.

[0051] The operation plane counter 172 may generate operation plane information indicating the number of planes to be operated based on the number of pass data received from the first to fourth page buffers 161 to 164. In other words, the operation plane counter 172 may count the number of operation planes among the first to fourth planes 141 to 144. The number of operation planes may be determined by the number of pass data of the first to fourth planes 141 to 144. In an embodiment, the operation plane counter 172 may receive pass data indicating that the operation has been completed from the page buffer 160 connected to the plane where the operation has been completed among the first to fourth planes 141 to 144. In an embodiment, when the threshold voltage of each of the plurality of memory cells of the plane where the operation has been completed increases to the threshold voltage of the memory cell programmed to the target programming state, the page buffer 160 connected to the plane 144 to 144 where the operation (e.g., memory operation) has been completed may store the pass data. In an embodiment, when the threshold voltage of each of the plurality of memory cells of the plane where the operation has been completed decreases to the threshold voltage of the memory cell in the erased state, the page buffer connected to the plane where the operation has been completed may store the pass data.

[0052] In an embodiment, the operation plane counter 172 may receive fail data indicating that the operation has not been completed from the page buffer 160 connected to the plane whose operation has not been completed among the first to fourth planes 141 to 144. In an embodiment, when the threshold voltage of each of the plurality of memory cells of the plane whose operation has not been completed does not reach the threshold voltage of the memory cell programmed to the target program state, the page buffer 160 connected to the planes 141 to 144 whose operation has not been completed (for example, the planes 141 to 144 are operating) may store the fail data. In an embodiment, when the threshold voltage of each of the plurality of memory cells of the plane whose operation has not been completed does not decrease to the threshold voltage of the memory cell in the erased state, the page buffer 160 connected to the plane whose operation has not been completed may store the fail data.

[0053] In an embodiment, the operation plane counter 172 may generate operation plane information indicating the number of planes to be operated based on the bad block information stored in the bad block information storage device 173. The operation plane counter 172 may provide the operation plane information to the clock control circuit 171.

[0054] In an embodiment, based on the operation plane information, the clock control circuit 171 may provide a first clock control signal corresponding to the first clock signal or a second clock control signal corresponding to the second clock signal to the clock generation circuit 152. In an embodiment, when the number of planes to be operated included in the operation plane information is greater than a threshold number, the clock control circuit 171 may provide a first clock control signal corresponding to the first clock signal to the clock generation circuit 152. In an embodiment, when the number of planes to be operated included in the operation plane information is equal to or less than a threshold number, the clock control circuit 171 may provide a second clock control signal corresponding to the second clock signal to the clock generation circuit 152.

[0055] Figure 2 is a diagram illustrating threshold voltage distributions of memory cells according to a program operation.

[0056] exist Figure 2 In the graph, the horizontal axis represents the threshold voltage Vth of the memory cell, and the vertical axis represents the number of memory cells (cells of #). Figure 2 In the description, a case where one memory cell is programmed as a TLC storing three bits of data is taken as an example.

[0057] Reference Figure 2 , the threshold voltage distribution of the memory cell may be changed from an initial state to a final programmed state according to a programming operation.

[0058] The initial state is a state in which a program operation is not performed, and the threshold voltage distribution of the memory cells may be an erase state E.

[0059] The final programming state may be a threshold voltage distribution of a memory cell on which a programming operation is performed. The memory cell on which a programming operation is performed may have a threshold voltage corresponding to any one of a plurality of programming states. For example, when a memory cell is programmed as a TLC storing three bits of data, the plurality of programming states may include an erase state E and a first programming state PV1 to a seventh programming state PV7.

[0060] In an embodiment, a memory cell on which a programming operation is performed may have a threshold voltage corresponding to the erase state E and any one of the first to seventh programming states PV1 to PV7. Through the programming operation, the threshold voltage of the memory cell in the initial state may be increased to a threshold voltage corresponding to any one of the erase state E and the first to seventh programming states PV1 to PV7.

[0061] Each of the memory cells may have an erase state E and any one of the first programming state PV1 to the seventh programming state PV7 as a target programming state. The target programming state may be determined according to the data to be stored in the memory cell. Each of the memory cells may have any one of a plurality of programming states (i.e., erase state E and the first programming state PV1 to the seventh programming state PV7) as a target programming state according to the data to be stored. When the threshold voltage of each of the memory cells increases to the threshold voltage corresponding to the target programming state, the programming operation may be completed.

[0062] In an embodiment, the first to seventh program verification voltages pvfy1 to pvfy7 may be voltages corresponding to the first to seventh program states PV1 to PV7, respectively. The program verification voltage may be a voltage for identifying whether a threshold voltage of a memory cell has increased to a threshold voltage corresponding to a target program state.

[0063] Figure 3 is a diagram illustrating a program operation including a plurality of program loops.

[0064] exist Figure 3 , the horizontal axis of the graph represents time “Time”, and the vertical axis of the graph represents voltage “V” applied to the word line. The voltage V applied to the word line may include a program voltage Vpgm and a program verification voltage pvfy.

[0065] Reference Figure 3 , the memory device 100 may perform a program operation including a plurality of program loops PL1 to PLn. The memory device 100 may perform a plurality of program loops PL1 to PLn so that each selected memory cell connected to a selected word line has a threshold voltage corresponding to a target program state.

[0066] Each of the plurality of program loops PL1 to PLn may include a program voltage applying operation Pgm Pulse and a program verifying operation Verify.

[0067] The program voltage applying operation Pgm Pulse may be an operation of applying a program voltage to a selected word line connected to a selected memory cell. The program voltage applying operation Pgm Pulse may be an operation of increasing a threshold voltage of a selected memory cell by using the program voltage.

[0068] The program verification operation Verify may be an operation of identifying a threshold voltage of a memory cell, which is increased by a program voltage applying operation. The program verification operation Verify may be an operation of applying a program verification voltage pvfy to a selected word line connected to a selected memory cell. Specifically, the program verification operation Verify may be an operation of storing sensed data to a page buffer through a bit line connected to the selected memory cell when the program verification voltage pvfy is applied to a selected word line connected to the selected memory cell.

[0069] In an embodiment, when the threshold voltage of the selected memory cell exceeds the program verification voltage pvfy in the program verification operation Verify, pass data indicating that the program verification operation has passed may be stored in the page buffer. In an embodiment, when the threshold voltage of the selected memory cell is equal to or lower than the program verification voltage pvfy in the program verification operation Verify, fail data indicating that the program verification operation has failed may be stored in the page buffer.

[0070] In an embodiment, in a first programming loop LP1, the memory device 100 may apply a first programming voltage Vpgm1 to a selected word line connected to a selected memory cell, and then may apply a first programming verification voltage pvfy1 to a seventh programming verification voltage pvfy7 to the selected word line. The memory device 100 may apply a programming verification voltage corresponding to a target programming state of the memory cell among the first programming verification voltage pvfy1 to the seventh programming verification voltage pvfy7 to the selected word line. For example, the memory device 100 may perform a programming verification operation on a memory cell having a first programming state as a target programming state by using the first programming verification voltage pvfy. The magnitude of the programming verification voltage may increase stepwise from the first programming verification voltage pvfy1 to the seventh programming verification voltage pvfy7. Specifically, among the magnitudes of the programming verification voltages, the magnitude of the first programming verification voltage pvfy1 may be the smallest, and the magnitude of the seventh programming verification voltage pvfy7 may be the largest. The number of programming verification voltages is not limited to this embodiment.

[0071] For example, memory cells passed the program verification operation Verify based on each of the program verification voltages pvfy1 to pvfy7 may have a threshold voltage corresponding to a target program state. A program inhibit voltage may be applied to bit lines connected to the memory cells passed the program verification operation Verify.

[0072] On the other hand, a memory cell that fails the program verification operation Verify based on each of the program verification voltages pvfy1 to pvfy7 may not have a threshold voltage corresponding to a target program state. A second program loop PL2 may be performed on the memory cell that fails the program verification operation Verify. A program enable voltage may be applied to a bit line connected to the memory cell that fails the program verification operation Verify.

[0073] In the second programming loop PL2, the memory device 100 may apply a second programming voltage Vpgm2 that is a step voltage ΔVstep higher than the first programming voltage Vpgm1 to a selected word line connected to the selected memory cell. Thereafter, the memory device 100 may perform a program verification operation Verify in the second programming loop PL2 that is the same as the program verification operation Verify in the first programming loop PL1.

[0074] Thereafter, the memory device 100 may perform the same subsequent program loop as the second program loop PL2 a predetermined number of times.

[0075] In an embodiment, when the programming operation is not completed within a predetermined number of programming loops, the programming operation may fail. When the programming operation is completed within a predetermined number of programming loops, the programming operation may pass. When all programming verification operations Verify for selected memory cells pass, the programming operation may be completed. When the programming verification operations Verify for all selected memory cells pass, the next programming loop may not be performed.

[0076] In an embodiment, the programming voltage may be determined according to an incremental step pulse programming (ISPP) method. As the programming loops PL1 to PLn are repeated, the level of the programming voltage may be increased or decreased in a stepwise manner. The number of times the programming voltage is applied for each programming loop, the voltage level of the programming voltage, the time for applying the programming voltage, etc. may be changed under the control of the memory controller 200.

[0077] Figure 4 is a diagram illustrating threshold voltage distributions of memory cells according to an erase operation.

[0078] exist Figure 4 In the graph, the horizontal axis represents the threshold voltage Vth of the memory cell, and the vertical axis represents the number of memory cells (cells of #).

[0079] Reference Figure 4, the memory cells that complete the programming operation may have a threshold voltage distribution corresponding to the final programming state. Thereafter, the memory device 100 may perform an erase operation on the memory cells that complete the programming operation. Through the erase operation, the threshold voltage distribution of the memory cells may be changed from the final programming state to the initial state. The erase operation may be an operation in which the threshold voltage of the memory cell is reduced to a threshold voltage corresponding to the erase state E. Specifically, through the erase operation, the memory cells having a threshold voltage corresponding to the erase state E and each of the first programming state PV1 to the seventh programming state PV7 may have a threshold voltage corresponding to the erase state.

[0080] In an embodiment, the erase verification voltage evfy1 may be a voltage corresponding to the erase state E. The erase verification voltage evfy1 may be a voltage for identifying whether a threshold voltage of a memory cell has been lowered to a threshold voltage corresponding to the erase state E.

[0081] Figure 5 is a diagram illustrating an erase operation including a plurality of erase cycles.

[0082] exist Figure 5 In the graph, the horizontal axis represents time "Time", and the vertical axis represents the voltage "V" applied to the word line, the common source line or the bit line. For example, the erase voltage Vers may be applied to the common source line or the bit line, and the erase verification voltage evfy may be applied to the word line.

[0083] Reference Figure 5 , the memory device 100 may perform an erase operation. The erase operation may include a plurality of erase cycles EL1 to ELn. The memory device 100 may perform a plurality of erase cycles EL1 to ELn so that each of the memory cells has a threshold voltage corresponding to an erase state.

[0084] Each of the plurality of erase loops EL1 to ELn may include an erase voltage applying operation Erase Pulse and an erase verification operation Verify.

[0085] The erase voltage applying operation Erase Pulse may be an operation of applying an erase voltage Vers to a common source line or a bit line connected to a memory cell. The erase verification operation Verify may be an operation of identifying a threshold voltage of a memory cell, which is lowered by the erase voltage applying operation Erase Pulse. The erase verification operation Verify may be an operation of storing sensed data in a page buffer through a bit line connected to a memory cell when an erase verification voltage evfy1 is applied to a word line connected to the memory cell.

[0086] In an embodiment, when the threshold voltage of the memory cell exceeds the erase verification voltage evfy1 in the erase verification operation Verify, fail data indicating that the erase verification operation Verify has failed may be stored in the page buffer. In an embodiment, when the threshold voltage of the memory cell is equal to or lower than the erase verification voltage evfy1 in the erase verification operation Verify, pass data indicating that the erase verification operation Verify has passed may be stored in the page buffer.

[0087] In an embodiment, in the first erase cycle EL1, the memory device 100 may apply a first erase voltage Vers1 to a common source line or a bit line, and then may apply an erase verification voltage evfy1 to a word line. When the erase verification operation Verify passes, it may be determined that the memory cell has a threshold voltage corresponding to the erase state E. When the erase verification operation Verify fails, it may be determined that the memory cell does not have a threshold voltage corresponding to the erase state E.

[0088] When the erase verification operation Verify in the first erase cycle EL1 fails, the memory device may perform a second erase cycle EL2. In the erase voltage application operation Erase Pulse in the second erase cycle EL2, the memory device 100 may apply a second erase voltage Vers2 that is a step voltage ΔVstep higher than the first erase voltage Vers1 to the common source line or the bit line. In the erase verification operation Verify in the second erase cycle EL2, the memory device 100 may identify the threshold voltage of the memory cell by using the erase verification voltage evfy1.

[0089] Thereafter, when the erase verification operation Verify of the second erase loop EL2 fails, the memory device 100 may perform a subsequent erase cycle that is the same as the second erase loop EL2 .

[0090] In an embodiment, when the erase operation is completed within a predetermined number of erase cycles, the erase operation may pass. When the threshold voltage of each of the memory cells is reduced to a threshold voltage corresponding to the erase state E, the erase operation may be completed. When the erase verification operation Verify of the memory cell passes, the erase operation may be completed. In an embodiment, in the second erase cycle EL2, when the erase verification operation Verify of the memory cell passes, the erase operation may be completed. In an embodiment, when the erase operation is not completed within a predetermined number of erase cycles, the erase operation may fail.

[0091] Figure 6 is a diagram illustrating a memory device for generating an operating voltage according to a clock signal determined based on operating plane information.

[0092] Will refer to Figure 1 describe Figure 6 . Reference Figure 6 , the memory device 100 may include first to fourth planes 141 to 144, a voltage generating circuit 150, first to fourth page buffers 161 to 164, and an operation control circuit 170. The voltage generating circuit 150 may include a charge pump 151 and a clock generating circuit 152. The operation control circuit 170 may include a clock control circuit 171, an operation plane counter 172, and a bad block information storage device 173.

[0093] The memory device 100 may perform an operation corresponding to the command in response to the command received from the memory controller 200. The operation corresponding to the command may be a program operation, a read operation, or an erase operation.

[0094] In an embodiment, the clock control circuit 171 may provide the clock generation circuit 152 with a first clock control signal CLK_sig1 for performing an operation corresponding to a command. The clock generation circuit 152 may generate a first clock signal CLK1 having a first period in response to the first clock control signal CLK_sig1. The clock generation circuit 152 may provide the first clock signal CLK1 to the charge pump 151.

[0095] The charge pump 151 may perform a pump operation to generate an operation voltage Vop in response to the first clock signal CLK1 . The charge pump 151 may provide the operation voltage Vop to each of the first to fourth planes 141 to 144 .

[0096] Each of the first to fourth planes 141 to 144 may perform an operation corresponding to a command by using an operation voltage Vop. In an embodiment, the first to fourth memory blocks BLK1 to BLK4 respectively included in the first to fourth planes 141 to 144 may perform a program operation, a read operation, or an erase operation.

[0097] After performing an operation on each of the first to fourth planes 141 to 144, pass data or fail data indicating whether the operation on each of the first to fourth planes 141 to 144 has been completed may be stored in each of the first to fourth page buffers 161 to 164 respectively connected to the first to fourth planes 141 to 144. For example, when the operation on the first plane 141 is completed, the pass data may be stored in the first page buffer 161. When the operation on the first plane 141 is not completed, the fail data may be stored in the first page buffer 161.

[0098] In an embodiment, when a threshold voltage of each of the plurality of memory cells included in the first memory block BLK1 of the first plane 141 increases to a threshold voltage corresponding to a target program state, pass data may be stored in the first page buffer 161. In an embodiment, when a program verification operation on each of the plurality of memory cells included in the first memory block BLK1 of the first plane 141 passes, pass data may be stored in the first page buffer 161.

[0099] In an embodiment, when a threshold voltage of each of the plurality of memory cells included in the first memory block BLK1 of the first plane 141 does not reach a threshold voltage corresponding to a target program state, fail data may be stored in the first page buffer 161. In an embodiment, when a program verification operation fails for each of the plurality of memory cells included in the first memory block BLK1 of the first plane 141, fail data may be stored in the first page buffer 161.

[0100] In an embodiment, when a threshold voltage of each of the plurality of memory cells included in the first memory block BLK1 of the first plane 141 is lowered to a threshold voltage corresponding to an erase state, pass data may be stored in the first page buffer 161. In an embodiment, when an erase verification operation of the plurality of memory cells included in the first memory block BLK1 of the first plane 141 is passed, pass data may be stored in the first page buffer 161.

[0101] In an embodiment, when a threshold voltage of each of the plurality of memory cells included in the first memory block BLK1 of the first plane 141 is not lowered to a threshold voltage corresponding to an erase state, fail data may be stored in the first page buffer 161. In an embodiment, when an erase verification operation on the plurality of memory cells included in the first memory block BLK1 of the first plane 141 fails, fail data may be stored in the first page buffer 161.

[0102] Similar to the operation on the first storage block BLK1 of the first plane 141, pass data or fail data indicating whether the operation on each of the second storage blocks BLK2 to the fourth storage blocks BLK4 respectively included in the second plane 142 to the fourth plane 144 has been completed can be stored in each of the second page buffer 162 to the fourth page buffer 164.

[0103] The pass data or fail data stored in each of the first to fourth page buffers 161 to 164 may be provided to the operation plane counter 172 .

[0104] The operation plane counter 172 may generate the operation plane information Plane_info indicating the number of planes to be operated based on the number of pass data received from the first to fourth page buffers 161 to 164. In an embodiment, when the operation plane counter 172 receives the pass data from the first to fourth page buffers 161 and receives the fail data from the second to fourth page buffers 162 to 164, the second to fourth planes 142 to 144 other than the first plane 141 may be the planes to be operated, and therefore, the operation plane counter 172 may generate the operation plane information Plane_info indicating that the number of planes to be operated is 3.

[0105] In an embodiment, the operation plane counter 172 may generate the operation plane information Plane_info based on the bad block information Bad_info stored in the bad block information storage device 173. In an embodiment, when the operation plane counter 172 receives the bad block information Bad_info indicating that the first storage block BLK1 is a bad block, the second plane 142 to the fourth plane 144 other than the first plane 141 may be the planes to be operated, and therefore, the operation plane counter 172 may generate the operation plane information Plane_info indicating that the number of the planes to be operated is 3. The operation plane counter 172 may provide the operation plane information Plane_info to the clock control circuit 171.

[0106] The clock control circuit 171 may provide the first clock control signal CLK_sig1 or the second clock control signal CLK_sig2 to the clock generation circuit 152 based on a result obtained by comparing the information about the number of planes to be operated included in the operation plane information Plane_info with the threshold number. In an embodiment, when the number of planes to be operated is greater than the threshold number, the clock control circuit 152 may provide the first clock control signal CLK_sig1 corresponding to the first clock signal CLK1 to the clock generation circuit 152. The clock generation circuit 152 may provide the first clock signal CLK1 having a first period to the charge pump 151 in response to the first clock control signal CLK_sig1.

[0107] In an embodiment, when the number of planes to be operated is equal to or less than the threshold number, the clock control circuit 171 may provide the second clock control signal CLK_sig2 corresponding to the second clock signal CLK2 to the clock generation circuit 152. The clock generation circuit 152 may provide the second clock signal CLK2 having a second period longer than the first period to the charge pump 151 in response to the second clock control signal CLK_sig2.

[0108] The charge pump 151 may perform a pumping operation to generate an operation voltage Vop in response to the first clock signal CLK1 or the second clock signal CLK2. The charge pump 151 may provide the operation voltage Vop to the remaining planes among the first plane 141 to the fourth plane 144 except the plane where the operation is completed. In an embodiment, when the pass data is stored in the first page buffer 161, the charge pump 151 may provide the operation voltage Vop to each of the second plane 142 to the fourth plane 144 except the first plane 141. The second plane 142 to the fourth plane 144 may perform an operation corresponding to the command by using the operation voltage Vop.

[0109] In an embodiment, the memory device 100 may store pass data or fail data indicating whether an operation on each of the first plane 141 to the fourth plane 144 has been completed. The memory device 100 may change the cycle of the clock signal from the first cycle to the second cycle based on the number of pass data stored in the first plane 141 to the fourth plane 144. When the number of pass data stored in the first page buffer 161 to the fourth page buffer 164 is equal to or greater than a threshold value, the memory device 100 may generate an operating voltage according to the clock signal having the second cycle. When the number of pass data stored in the first page buffer 161 to the fourth page buffer 164 is less than a threshold value, the memory device 100 may generate an operating voltage according to the clock signal having the first cycle.

[0110] In an embodiment, when the number of planes whose operations have been completed is greater than a threshold number, the memory device may generate the operating voltage Vop according to the clock signal having the second cycle, thereby reducing the amount of current consumed when generating the operating voltage Vop.

[0111] Figure 7 is a diagram illustrating a charge pump.

[0112] Reference Figure 7 The charge pump 151 may receive a first clock signal CLK1 and a second clock signal CLK2 from the clock generating circuit 152. The first clock signal CLK1 may be a clock signal having a first period T1, and the second clock signal CLK2 may be a clock signal having a second period T2 longer than the first period T1.

[0113] The charge pump 151 may include first to nth stages Stage_1 to Stage_n connected in series between an input node NDin and an nth output node NDon. Each of the first to nth stages Stage_1 to Stage_n may perform a pumping operation to generate an operating voltage Vop in response to a clock signal and an inverted clock signal received from the clock generating circuit 152 .

[0114] In an embodiment, the first stage Stage_1 may include first and second switches SW1 and SW2 and third and fourth switches SW3 and SW4 connected between the input node NDin and the second stage Stage_2. A power supply voltage VCC may be applied to the input node NDin.

[0115] The first switch SW1 and the second switch SW2 and the third switch SW3 and the fourth switch SW4 may be connected in parallel. The first switch SW1 and the second switch SW2 may be connected in series. The third switch SW3 and the fourth switch SW4 may be connected in series. Each of the first switch SW1 and the third switch SW3 may be an NMOS transistor. Each of the second switch SW2 and the fourth switch SW4 may be a PMOS transistor.

[0116] The first capacitor CP1 may be connected to a first node ND1 between the first switch SW1 and the second switch SW2. The first clock signal CLK1 or the second clock signal CLK2 may be applied to the first capacitor CP1. The second capacitor CP2 may be connected to a second node ND2 between the third switch SW3 and the fourth switch SW4. The inverted first clock signal nCLK1 or the inverted second clock signal nCLK2 may be applied to the second capacitor CP2.

[0117] In an embodiment, when the first clock signal CLK1 or the second clock signal CLK2 is at a logic high, the inverted first clock signal nCLK1 or the inverted second clock signal nCLK2 may be at a logic low. When the first clock signal CLK1 or the second clock signal CLK2 is at a logic high, the potential of the first node ND1 may become high. When the potential of the first node ND1 is high, the third switch SW3 connected to the first node ND1 may be turned on, and the fourth switch SW4 may be turned off. When the third switch SW3 is turned on, the power supply voltage VCC applied to the input node NDin may be transmitted to the second capacitor CP2.

[0118] When the inverted first clock signal nCLK1 or the inverted second clock signal nCLK2 is at logic low, the potential of the second node ND2 may become low. When the potential of the second node ND2 is low, the first switch SW1 connected to the second node ND2 may be turned off, and the second switch SW2 may be turned on. The charge charged in the first capacitor CP1 may be transferred to the first output node NDo1.

[0119] In an embodiment, when the first clock signal CLK1 or the second clock signal CLK2 is at a logic low, the inverted first clock signal nCLK1 or the inverted second clock signal nCLK2 may be at a logic high. When the first clock signal CLK1 or the second clock signal CLK2 is at a logic low, the potential of the first node ND1 may become low. When the potential of the first node ND1 is low, the third switch SW3 connected to the first node ND1 may be turned off, and the fourth switch SW4 may be turned on. When the fourth switch SW4 is turned on, the charge charged in the second capacitor CP2 may be transferred to the first output node NDo1.

[0120] When the inverted first clock signal nCLK1 or the inverted second clock signal nCLK2 is at a logic high, the potential of the second node ND2 may become high. When the potential of the second node ND2 is high, the first switch SW1 connected to the second node ND2 may be turned on, and the second switch SW2 may be turned off. When the first switch SW1 is turned on, the power supply voltage VCC applied to the input node NDin may be transmitted to the first capacitor CP1.

[0121] In an embodiment, the first stage Stage_1 may perform a pumping operation according to the first clock signal CLK1 or the second clock signal CLK2 and the inverted first clock signal nCLK1 or the inverted second clock signal nCLK2, and may output a first output voltage Vout1 higher than the power supply voltage VCC applied to the input node NDin to the first output node NDol.

[0122] The second stage Stage_2 to the nth stage Stage_n may be implemented in the same manner as the first stage Stage_1. In an embodiment, the second stage Stage_2 may output a second output voltage Vout2 higher than the first output voltage Vout1 according to the first clock signal CLK1 or the second clock signal CLK2 and the inverted first clock signal nCLK1 or the inverted second clock signal nCLK2. The nth stage Stage_n may output an operating voltage Vop higher than the (n-1)th output voltage Voutn-1 according to the first clock signal CLK1 or the second clock signal CLK2 and the inverted first clock signal nCLK1 or the inverted second clock signal nCLK2.

[0123] Figure 8 is a diagram illustrating a memory device for changing a period of a clock signal according to operation plane information in a plurality of cycles.

[0124] Will refer to Figure 6 describe Figure 8 . Reference Figure 8Each of the first to fourth planes 141 to 144 may perform an operation corresponding to a command received from the memory controller 200. In an embodiment, the operation may include a first loop to a fifth loop. The first loop to the fifth loop may be a program loop or an erase loop.

[0125] In an embodiment, the first to fourth planes 141 to 144 may perform a first loop 1st loop. In the first loop 1st loop, the clock control circuit 171 may output a first clock control signal CLK_sig1. In the first loop 1st loop, the clock generation circuit 152 may output a first clock signal CLK1 having a first period in response to the first clock control signal CLK_sig1. The charge pump 151 may generate an operation voltage Vop in response to the first clock signal CLK1. The charge pump 151 may provide the operation voltage Vop to each of the first to fourth planes 141 to 144. In the first loop 1st loop, each of the first to fourth planes 141 to 144 may perform an operation corresponding to a command by using the operation voltage Vop.

[0126] In an embodiment, in the first loop 1st loop, the operation on each of the first to fourth planes 141 to 144 may not be completed. For example, in the first loop 1st loop, the verification operation on each of the first to fourth planes 141 to 144 may fail. The verification operation may be a program verification operation or an erase verification operation. In the first loop 1st loop, the failure data may be stored in the first to fourth page buffers 161 to 164 connected to the first to fourth planes 141 to 144, respectively. The operation plane counter 172 may receive the failure data from the first to fourth page buffers 161 to 164. That is, the number of pass data received from the first to fourth page buffers 161 to 164 may be 0. Since the number of pass data received in the first loop 1st loop is 0, the operation plane counter 172 may generate the operation plane information Plane_info indicating that the number of planes to be operated in the second loop 2nd loop is 4.

[0127] In the second loop 2nd loop, the clock control signal 171 may output the first clock control signal CLK_sig1 or the second clock control signal CLK_sig2 based on a result obtained by comparing information about the number of planes to be operated included in the operation plane information Plane_info with a threshold number. Figure 8In the description, the case where the threshold number is 1 is taken as an example. In the second loop 2nd loop, since the number 4 of the planes to be operated is greater than the threshold number 1, the clock control circuit 171 can output the first clock control signal CLK_sig1. The clock generation circuit 152 can output the first clock signal CLK1 in response to the first clock control signal CLK_sig1. The charge pump 151 can generate an operating voltage Vop in response to the first clock signal CLK1, and can provide the generated operating voltage Vop to each of the first plane 141 to the fourth plane 144.

[0128] In an embodiment, in the second loop 2nd loop, the operation on the first plane 141 may be completed, and the operation on each of the second to fourth planes 142 to 144 may not be completed. In the second loop 2nd loop, the pass data may be stored in the first page buffer 161 connected to the first plane 141, and the fail data may be stored in the second to fourth page buffers 162 to 164 connected to the second to fourth planes 142 to 144. In the second loop 2nd loop, the operation plane counter 172 may receive one pass data from the first to fourth page buffers 161 to 164. Based on the one pass data, the operation plane counter 172 may generate the operation plane information Plane_info indicating that the number of planes to be operated in the third loop 3rd loop is 3.

[0129] In the third loop, since the number 3 of the planes to be operated is greater than the threshold number 1, the clock control circuit 171 may output the first clock control signal CLK_sig1. The clock generation circuit 152 may output the first clock signal CLK1 in response to the first clock control signal CLK_sig1. The charge pump 151 may generate an operating voltage Vop in response to the first clock signal CLK1, and may provide the generated operating voltage Vop to each of the second to fourth planes 142 to 144.

[0130] In an embodiment, in the third loop 3rd loop, the operation on the second plane 142 may be completed, and the operation on each of the third plane 143 and the fourth plane 144 may not be completed. In the third loop 3rd loop, the pass data may be stored in the second page buffer 162 connected to the second plane 142, and the fail data may be stored in the third page buffer 163 and the fourth page buffer 164 connected to the third plane 143 and the fourth plane 144. In the third loop 3rd loop, the operation plane counter 172 may receive two pass data from the first page buffer 161 to the fourth page buffer 164. Based on the two pass data, the operation plane counter 172 may generate the operation plane information Plane_info indicating that the number of planes to be operated in the fourth loop 4th loop is 2.

[0131] In the fourth loop, since the number 2 of the planes to be operated is greater than the threshold number 1, the clock control circuit 171 may output the first clock control signal CLK_sig1. The clock generation circuit 152 may output the first clock signal CLK1 in response to the first clock control signal CLK_sig1. The charge pump 151 may generate an operating voltage Vop in response to the first clock signal CLK1, and may provide the generated operating voltage Vop to each of the third plane 143 and the fourth plane 144.

[0132] In an embodiment, in the fourth loop, the operation on the third plane 143 may be completed, and the operation on the fourth plane 144 may not be completed. In the fourth loop, the pass data may be stored in the third page buffer 163 connected to the third plane 143, and the fail data may be stored in the fourth page buffer 164 connected to the fourth plane 144. In the fourth loop, the operation plane counter 172 may receive three pass data from the first page buffer 161 to the fourth page buffer 164. Based on the three pass data, the operation plane counter 172 may generate the operation plane information Plane_info indicating that the number of planes to be operated in the fifth loop is 1.

[0133] In the fifth loop, when the number of planes to be operated is equal to or less than the threshold number, the clock control circuit 171 may output the second clock control signal CLK_sig2. Since the number 1 of the planes to be operated is equal to the threshold number 1, the clock control circuit 171 may output the second clock control signal CLK_sig2. The clock generation circuit 152 may generate a second clock signal CLK2 having a second period longer than the first period in response to the second clock control signal CLK_sig2. The charge pump 151 may generate an operating voltage Vop in response to the second clock signal CLK, and may provide the generated operating voltage Vop to the fourth plane 144.

[0134] In an embodiment, in the fifth loop, the operation on the fourth plane 144 may be completed. In the fifth loop, the pass data may be stored in the fourth page buffer 164 connected to the fourth plane 144. That is, the pass data may be stored in all of the first to fourth page buffers 161 to 164. Based on the four pass data received from the first to fourth page buffers 161 to 164, the operation plane counter 172 may generate the operation plane information Plane_info indicating that the number of planes to be operated is 0. Since the operation on each of the first to fourth planes 141 to 144 has been completed, the next loop may not be executed.

[0135] Fig. 9 is a diagram illustrating a memory device for changing a period of a clock signal according to operation plane information and bad block information in a plurality of cycles.

[0136] Will refer to Figure 6 describe Fig. 9 .exist Fig. 9 In the Figure 8 Description of the repeated portion shown. Fig. 9 The operation plane counter 172 may generate the operation plane information Plane_info based on the number of pass data and the bad block information Bad_info received from the bad block information storage device 173 .

[0137] In an embodiment, in the first loop 1st loop, the operation plane counter 172 may receive bad block information Bad_info indicating that the first memory block BLK1 included in the first plane 141 is a bad block. Based on the bad block information Bad_info, the operation plane counter 172 may generate operation plane information Plane_info indicating that the second plane 142 to the fourth plane 144 other than the first plane 141 among the first plane 141 to the fourth plane 144 are planes to be operated. The operation plane counter 172 may generate operation plane information Plane_info indicating that the number of planes to be operated is 3.

[0138] In the first loop 1st loop, since the number 3 of the planes to be operated is greater than the threshold number 1, the first clock control circuit 171 may output the first clock control signal CLK_sig1. In the first loop 1st loop, the clock generation circuit 152 may output the first clock signal CLK1 having the first period in response to the first clock control signal CLK_sig1. In the first loop 1st loop, the charge pump 151 may generate an operation voltage Vop in response to the first clock signal CLK1, and may provide the generated operation voltage Vop to each of the second to fourth planes 142 to 144. The first plane 141 may include the first memory block BLK1 as a bad block, and thus may not perform any operation.

[0139] In an embodiment, in the first loop, operations on each of the second to fourth planes 142 to 144 may not be completed. In the first loop, the fail data may be stored in the second to fourth page buffers 162 to 164 respectively connected to the second to fourth planes 142 to 144. Based on the bad block information Bad_info and the three fail data received from the second to fourth page buffers 162 to 164, the operation plane counter 172 may generate the operation plane information Plane_info indicating that the number of planes to be operated in the second loop 2nd loop is 3.

[0140] Thereafter, in the second loop 2nd loop, the operation on each of the second to fourth planes 142 to 144 may not be completed. Based on the three failure data received from the second to fourth page buffers 162 to 164 and the bad block information Bad_info, the operation plane counter 172 may generate operation plane information Plane_info indicating that the number of planes to be operated in the third loop 3rd loop is 3.

[0141] Thereafter, in the third loop 3rd loop, the operation on each of the second plane 142 and the third plane 143 may be completed, and the operation on the fourth plane 144 may not be completed. The pass data may be stored in the second page buffer 162 and the third page buffer 163 respectively connected to the second plane 142 and the third plane 143. Based on the bad block information Bad_info and the two pass data received from the second page buffer 162 to the fourth page buffer 164, the operation plane counter 172 may generate the operation plane information Plane_info indicating that the number of planes to be operated in the fourth loop 4th loop is 1.

[0142] In the fourth loop, the clock control circuit 171 may output the first clock control signal CLK_sig1 or the second clock control signal CLK_sig2 based on the result obtained by comparing the number of planes to be operated with the threshold number. In the fourth loop, since the number 1 of the planes to be operated is equal to the threshold number 1, the clock control circuit 171 may output the second clock control signal CLK_sig2. The clock generation circuit 152 may output the second clock signal CLK2 having a second period longer than the first period in response to the second clock control signal CLK_sign2. In the fourth loop, the charge pump 151 may generate an operating voltage Vop in response to the second clock signal CLK2, and may provide the generated operating voltage Vop to the fourth plane 144.

[0143] Thereafter, in the fifth loop, when the operation on the fourth plane 144 is completed, the pass data may be stored in the fourth page buffer 164 connected to the fourth plane 144. In the fifth loop, when the operation on the fourth plane 144 is completed, the next loop may not be performed.

[0144] Fig.10 and Fig.11 is a diagram illustrating a memory device for determining a period of a clock signal based on operation plane information provided by a first operation plane counter and a second operation plane counter, respectively.

[0145] Reference Fig.10 and Fig.11, the voltage generating circuit 150 may include a plurality of clock generating circuits and a plurality of charge pumps. The operation control circuit 170 may include a plurality of clock control circuits and a plurality of operation plane counters. In an embodiment, the voltage generating circuit 150 may include a first charge pump 153 and a second charge pump 155 and a first clock generating circuit 154 and a second clock generating circuit 156. In an embodiment, the operation control circuit 170 may include a first clock control circuit 174 and a second clock control circuit 176 and a first operation plane counter 175 and a second operation plane counter 177.

[0146] In an embodiment, the first charge pump 153 may provide the operating voltage Vop generated according to the first clock signal CLK1 or the second clock signal CLK2 to the first plane 141 and the second plane 142. The second charge pump 155 may provide the operating voltage Vop to the third plane 143 and the fourth plane 144.

[0147] The first operation plane counter 175 may receive pass data or fail data indicating whether an operation on each of the first memory block BLK1 and the second memory block BLK2 respectively included in the first plane 141 and the second plane 142 has been completed from the first page buffer 161 and the second page buffer 162. Based on the number of pass data received from the first page buffer 161 and the second page buffer 162, the first operation plane counter 175 may generate operation plane information Plane_info indicating the number of planes to be operated.

[0148] The first clock control circuit 174 may output the first clock control signal CLK_sig1 or the second clock control signal CLK_sig2 based on a result obtained by comparing information about the number of planes to be operated included in the operation plane information Plane_info received from the first operation plane counter 175 with a threshold number. The first clock generation circuit 154 may output the first clock signal CLK1 or the second clock signal CLK2 in response to the first clock control signal CLK_sig1 or the second clock control signal CLK_sig2 received from the first clock control circuit 174. The first charge pump 153 may generate the operation voltage Vop in response to the first clock signal CLK1 or the second clock signal CLK2 received from the first clock generation circuit 154.

[0149] The second operation plane counter 177 may receive pass data or fail data indicating whether an operation on each of the third memory block BLK3 and the fourth memory block BLK4 respectively included in the third plane 143 and the fourth plane 144 has been completed from the third page buffer 163 and the fourth page buffer 164. Based on the number of pass data received from the third page buffer 163 and the fourth page buffer 164, the second operation plane counter 177 may generate operation plane information Plane_info indicating the number of planes to be operated.

[0150] The second clock control circuit 176 may output the first clock control signal CLK_sig1 or the second clock control signal CLK_sig2 based on a result obtained by comparing information about the number of planes to be operated included in the operation plane information Plane_info received from the second operation plane counter 177 with a threshold number. The second clock generation circuit 156 may output the first clock signal CLK1 or the second clock signal CLK2 in response to the first clock control signal CLK_sig1 or the second clock control signal CLK_sig2 received from the second clock control circuit 176. The second charge pump 155 may generate the operation voltage Vop in response to the first clock signal CLK1 or the second clock signal CLK2 received from the second clock generation circuit 156.

[0151] In an embodiment, a plurality of storage blocks included in different planes may simultaneously perform operations corresponding to commands. The memory device 100 may change the cycle of the clock signal from a first cycle to a second cycle longer than the first cycle based on the number of storage blocks whose operations corresponding to the commands have been completed among the plurality of storage blocks. When the number of storage blocks whose operations have been completed in the first cycle is greater than a threshold number, the memory device 100 may generate an operating voltage Vop in a second cycle according to a clock signal having a second cycle. When the number of storage blocks whose operations have been completed in the first cycle is less than a threshold number, the memory device 100 may generate an operating voltage Vop in a second cycle according to a clock signal having a first cycle.

[0152] Fig.12 is a flow chart showing that a memory device generates an operating voltage according to a clock signal determined based on the number of passed data.

[0153] Reference Fig.12 In step S1201 , the memory device 100 may receive a command and an address from the memory controller 200 .

[0154] In step S1203, the memory device 100 may generate an operating voltage in response to a first clock signal having a first cycle. The operating voltage may be provided to each of the plurality of planes.

[0155] In step S1205 , each of the plurality of planes may perform an operation corresponding to the command by using an operating voltage.

[0156] In step S1207, the memory device 100 may determine whether the operation on each of the plurality of planes has been completed. When the pass data is stored in each of the plurality of page buffers respectively connected to the plurality of planes, the operation on each of the plurality of planes may be completed. When the operation on each of the plurality of planes is completed, the step may end. When the operation on each of the plurality of planes is not completed, step S1209 may be performed. When at least one fail data is stored in the plurality of page buffers respectively connected to the plurality of planes, the operation on each of the plurality of planes may not be completed.

[0157] In step S1209 , the memory device 100 may increase the program voltage or the erase voltage by a step voltage.

[0158] In step S1211, the memory device 100 may compare whether the number of pass data stored in the plurality of page buffers is equal to or greater than a threshold number. When the number of pass data stored in the plurality of page buffers is equal to or greater than the threshold number, step S1213 may be performed. When the number of pass data stored in the plurality of page buffers is less than the threshold number, step S1203 may be performed.

[0159] In step S1213, when the number of pass data stored in the plurality of page buffers is equal to or greater than the threshold number, the memory device 100 may generate an operating voltage in response to a second clock signal having a second period. The second clock signal may be a clock signal having a period longer than that of the first clock signal. Thereafter, the memory device 100 may perform an operation corresponding to the command by using the operating voltage generated according to the second clock signal.

[0160] Fig.13 is a diagram showing the structure of a memory device.

[0161] Reference Fig.13 , the memory device 100 may include a memory cell array 110 , a peripheral circuit 120 , and a control logic circuit 130 .

[0162] The memory cell array 110 may include a plurality of memory blocks BLK1 to BLK4. The plurality of memory blocks BLK1 to BLK4 may be connected to the address decoder 121 through the row lines RL. The plurality of memory blocks BLK1 to BLK4 may be connected to the page buffer group 123 through the bit lines BL1 to BL4. Each of the plurality of memory blocks BLK1 to BLK4 may include a plurality of memory cells. In an embodiment, the plurality of memory cells may be nonvolatile memory cells. The plurality of memory blocks BLK1 to BLK4 may simultaneously perform operations corresponding to the CMD command.

[0163] In an embodiment, any one of the plurality of memory blocks BLK1 to BLK4 may include a plurality of word lines WL1 to WLn arranged in parallel with each other between a drain select line DSL and a source select line SSL. A plurality of memory cells may be connected to the plurality of word lines WL1 to WLn. The memory block BLK1 may include a memory cell string connected between any one of the bit lines and a common source line CSL. Each of the bit lines BL1 to BL4 may be connected to a plurality of memory cell strings, respectively, and the common source line CSL may be connected to the plurality of memory cell strings in common.

[0164] Each of the plurality of memory cells may be configured as a single-level cell (SLC) storing 1-bit data, a multi-level cell (MLC) storing 2-bit data, a triple-level cell (TLC) storing 3-bit data, a quad-level cell (QLC) storing 4-bit data, or a memory cell storing 5 or more bits of data.

[0165] The peripheral circuit 120 may drive the memory cell array 110. For example, the peripheral circuit 120 may drive the memory cell array 110 to perform a program operation, a read operation, and an erase operation under the control of the control logic circuit 130. In another example, the peripheral circuit 120 may apply various operating voltages to the row lines RL and the bit lines BL1 to BL4 under the control of the control logic circuit 130, or may discharge the applied voltages.

[0166] The peripheral circuit 120 may include an address decoder 121 , a voltage generating circuit 122 , a page buffer group 123 , and a data input / output circuit 124 .

[0167] The address decoder 121 may be connected to the memory cell array 110 through row lines RL. The row lines RL may include a drain select line DSL, a plurality of word lines WL to WLn, and a source select line SSL.

[0168] The address decoder 121 may operate under the control of the control logic circuit 130 .

[0169] In a program operation, the address decoder 121 may apply a program voltage to a selected word line, and may apply a pass voltage having a level lower than the program voltage to non-selected word lines. In a program verification operation, the address decoder 121 may apply a verification voltage to a selected word line, and may apply a verification pass voltage having a level higher than the verification voltage to non-selected word lines.

[0170] The voltage generating circuit 122 may generate a plurality of operating voltages by using an external power supply voltage supplied to the memory device 100. The voltage generating circuit 122 may operate under the control of the control logic circuit 130.

[0171] In an embodiment, the voltage generation circuit 122 can generate various operating voltages for programming operations, reading operations, and erasing operations. For example, the voltage generation circuit 122 can generate multiple erase voltages, multiple programming voltages, multiple pass voltages, multiple selection read voltages, and multiple non-selection read voltages. The generated multiple operating voltages can be supplied to the memory cell array 110 by the address decoder 121.

[0172] In an embodiment, the voltage generating circuit 122 may include a charge pump 151 and a clock generating circuit 152. The clock generating circuit may generate a clock signal. The charge pump may perform a pumping operation to generate an operating voltage in response to the clock signal.

[0173] The page buffer group 123 may include first to fourth page buffers PB1 to PB4 . The first to fourth page buffers PB1 to PB4 may be connected to the memory cell array 110 through first to fourth bit lines BL1 to BL4 , respectively. The first to fourth page buffers PB1 to PB4 may operate under the control of the control logic circuit 130 .

[0174] In a programming operation, the first to fourth page buffers PB1 to PB4 may transmit data received through the data input / output circuit 124 to a selected memory cell through the bit lines BL1 to BL4. The selected memory cell may be programmed according to the transmitted data. In a verification operation, the first to fourth page buffers PB1 to PB4 may read data stored in the selected memory cell from the selected memory cell through the bit lines BL1 to BL4.

[0175] The data input / output circuit 124 may be connected to the first to fourth page buffers PB1 to PB4 through the data lines DL The data input / output circuit 124 may operate under the control of the control logic circuit 130 .

[0176] The control logic circuit 130 may be connected to the address decoder 121, the voltage generating circuit 122, the page buffer group 123, and the data input / output circuit 124. The control logic circuit 130 may control the overall operation of the memory device 100. The control logic circuit 130 may operate in response to a CMD command transmitted from the memory controller 200.

[0177] The control logic circuit 130 may control the peripheral circuit 120 by generating several signals in response to a command CMD and an address ADDR.

[0178] In an embodiment, the control logic circuit 130 may include an operation control circuit 170. The operation control circuit 170 may include a clock control circuit 171, an operation plane counter 172, and a bad block information storage device 173.

[0179] The operating plane counter 172 may generate operating plane information indicating the number of planes to be operated based on the bad block information stored in the bad block information storage device 173 and the number of pass data received from the first to fourth page buffers PB1 to PB4 .

[0180] The clock control circuit 171 may output a clock control signal based on the operation plane information. The clock generation circuit 152 may provide a clock signal corresponding to the clock control signal received from the clock control circuit 171 to the charge pump 151 .

[0181] According to the present disclosure, a memory device capable of reducing the amount of current consumed by a charge pump to generate a voltage and an operating method of the memory device can be provided.

[0182] Although the present disclosure has been shown and described with reference to certain exemplary embodiments of the present disclosure, it will be understood by those skilled in the art that various changes may be made in form and details without departing from the spirit and scope of the present disclosure as defined by the appended claims and their equivalents. Therefore, the scope of the present disclosure should not be limited to the above-mentioned exemplary embodiments, but should be determined not only by the appended claims, but also by their equivalents.

[0183] In the above-mentioned embodiments, all steps may be selectively performed or some steps may be omitted. In each embodiment, the steps are not necessarily performed in the order described, and the steps may be rearranged. The embodiments disclosed in this specification and the accompanying drawings are only examples for facilitating understanding of the present disclosure, and the present disclosure is not limited thereto. That is, it is obvious to those skilled in the art that various modifications may be made based on the technical scope of the present disclosure.

[0184] On the other hand, exemplary embodiments of the present disclosure have been described in the drawings and the specification. Although specific terms are used herein, these terms are only used to explain the embodiments of the present disclosure. Therefore, the present disclosure is not limited to the above-described embodiments, and there may be many changes within the spirit and scope of the present disclosure. It is obvious to those skilled in the art that, in addition to the embodiments disclosed herein, various modifications may also be made based on the technical scope of the present disclosure.

Claims

1. A memory device, comprising: a memory cell array including a plurality of planes; a charge pump that generates an operating voltage for operation of each of the plurality of planes according to a first clock signal having a first period; a page buffer, each of the page buffers storing pass data indicating whether an operation of each of the plurality of planes has been completed; as well as The operation control circuit controls the charge pump to generate the operation voltage according to a second clock signal having a second cycle longer than the first cycle based on the amount of pass data received from the page buffer.

2. The memory device according to claim 1, wherein: The operation control circuit includes an operation plane counter that generates operation plane information indicating the number of remaining planes among the plurality of planes based on the number of pass data received from the page buffer, the remaining planes being planes other than the planes on which the operation has been completed.

3. The memory device according to claim 2, wherein: The operation control circuit includes a clock control circuit that outputs a clock control signal based on a result obtained by comparing the number of the remaining planes with a threshold number. 4 . The memory device according to claim 3 , further comprising a clock generation circuit that outputs the first clock signal or the second clock signal in response to the clock control signal.

5. The memory device according to claim 3, wherein: When the number of the remaining planes is greater than the threshold number, the clock control circuit outputs a clock control signal corresponding to the first clock signal.

6. The memory device according to claim 3, wherein: When the number of the remaining planes is equal to or less than the threshold number, the clock control circuit outputs a clock control signal corresponding to the second clock signal.

7. The memory device according to claim 1, wherein: The operation includes a plurality of cycles, and When the number of pass data received from the page buffer in a first cycle among the plurality of cycles is greater than a threshold number, the operation control circuit controls the charge pump to generate the operation voltage according to the second clock signal in a second cycle among the plurality of cycles.

8. The memory device according to claim 1, wherein: A page buffer connected to the plane on which the operation has been completed among the page buffers stores the pass data, and A page buffer connected to a plane for which the operation has not been completed among the page buffers stores fail data.

9. The memory device according to claim 1, wherein: The operations include verification operations, and When a verification operation on each of the plurality of planes passes, each of the page buffers stores the passed data.

10. The memory device according to claim 9, wherein: The verification operation passes when a threshold voltage of each of the plurality of memory cells included in each of the plurality of planes increases to a threshold voltage corresponding to a target program state or decreases to a threshold voltage corresponding to an erase state.

11. A memory device comprising: multiple storage blocks, including in different planes; A clock generating circuit for generating a clock signal; a charge pump that generates an operating voltage to be applied to each of the plurality of memory blocks in response to the clock signal; as well as The operation control circuit controls the clock generation circuit to change the cycle of the clock signal from a first cycle to a second cycle longer than the first cycle based on the number of memory blocks among the plurality of memory blocks for which the operation corresponding to the command has been completed.

12. The memory device according to claim 11, wherein: When the number of storage blocks in which the operation has been completed in a first cycle among multiple cycles included in the operation is greater than a threshold number, in a second cycle among the multiple cycles, the operation control circuit controls the clock generation circuit to generate a clock signal having the second period.

13. The memory device according to claim 12, wherein: In the second cycle, the operation control circuit controls the charge pump to apply the operation voltage to each remaining memory block among the plurality of memory blocks except for the memory block for which the operation has been completed.

14. The memory device according to claim 11, wherein: The operation control circuit includes a bad block information storage device that stores information on bad blocks among the plurality of storage blocks.

15. The memory device of claim 14, wherein: The operation control circuit includes an operation plane counter, which generates information about the number of storage blocks among the multiple storage blocks on which the operation is to be performed in a second cycle among the multiple cycles included in the operation based on information about the number of storage blocks on which the operation has been completed in a first cycle among the multiple cycles and information about the bad blocks.

16. The memory device of claim 15, wherein: The operation control circuit includes a clock control circuit that provides a clock control signal corresponding to a clock signal having the second period to the clock generation circuit in the second cycle when the number of memory blocks on which the operation is to be performed is less than a threshold number.

17. The memory device according to claim 11, wherein: When a threshold voltage of each of the plurality of memory cells included in any one of the plurality of memory blocks increases to a threshold voltage corresponding to a target programmed state or decreases to a threshold voltage corresponding to an erased state, an operation on the any one memory block is completed.

18. A method of operating a memory device, comprising: generating an operating voltage in a first cycle according to a first clock signal having a first period; storing data indicating whether the operation on each of the plurality of planes in the first cycle has been completed; as well as The operating voltage is generated in a second cycle according to a second clock signal having a second cycle longer than the first cycle based on the number of pass data indicating that the operation on each of the plurality of planes in the first cycle has been completed.

19. The method according to claim 18, wherein: In the process of generating the operating voltage according to the second clock signal, when the number of the passing data in the first cycle is greater than a threshold number, the operating voltage is generated according to the second clock signal in the second cycle.

20. The method according to claim 19, wherein: In the process of generating the operation voltage according to the second clock signal, the operation voltage is provided to a plane among the plurality of planes, for which the operation has not been completed, in the second cycle.

21. A memory device comprising: a memory cell array including a plurality of planes; as well as A control circuit generates a first clock signal having a first period when the number of operating planes among the multiple planes is greater than a threshold number, and generates a second clock signal having a second period longer than the first period when the number of operating planes among the multiple planes is equal to or less than the threshold number.

22. The memory device of claim 21, wherein: The control circuit comprises: a voltage generating circuit that generates an operating voltage for driving the plurality of planes in response to at least one of the first clock signal and the second clock signal; and The operation control circuit includes an operation plane counter, which counts the number of operation planes among the plurality of planes.

Images