Method and device for adjusting read voltage in memory, storage medium and electronic device

Abstract

The embodiment of the present application provides a method and device for adjusting the read voltage in a memory, a storage medium and an electronic device. The method includes: obtaining a first data set including multiple first data objects from a cache, and when the multiple first data objects are respectively written into multiple storage units included in the memory, performing a read operation on the multiple storage units according to a first read voltage combination to obtain a second data set, obtaining a first unique hot code set matching the first data set, and a second unique hot code set matching the second data set, obtaining a calculation result set of multiple bit operations performed according to the first unique hot code set and the second unique hot code set, and determining a numerical difference parameter matching the first data set and the second data set according to the calculation result set, and when the numerical difference parameter meets the read voltage adjustment condition, adjusting the first read voltage combination according to the numerical difference parameter to obtain the second read voltage combination.

Description

Technical Field

[0001] The embodiments of the present application relate to the field of computers, and more specifically, to a method and device for adjusting a read voltage in a memory, a storage medium, and an electronic device. Background Art

[0002] As the amount of data increases, the capacity and performance of data storage systems are also growing rapidly. In particular, enterprises currently need large-scale data centers to support business digitization and enterprise data storage. The huge demand for data storage has put forward higher requirements for the performance and reliability of storage devices. SSDs have been widely used in the field of data storage because of their huge advantages in performance, reliability and power consumption.

[0003] However, in the existing solid-state hard disk technology, it is necessary to determine the data stored in the hard disk by applying a voltage to turn on the transistor. The applied voltage is also called a read voltage. If the applied read voltage value is incorrect, erroneous data will be obtained. In the related art, in order to determine whether the read data is correct, it is necessary to read the specific value in the storage unit, and compare the read value with the stored value to determine whether the read value is incorrect. The process of converting the bit value in the storage unit into a value consumes a large amount of processor resources. In other words, the process of determining whether the read data is correct in the related art has the problem of low efficiency.

[0004] To address the above-mentioned problems, no effective solution has been proposed yet. Summary of the invention

[0005] The embodiments of the present application provide a method and device for adjusting the read voltage in a memory, a storage medium, and an electronic device, so as to at least solve the technical problem of low efficiency in the operation process of determining whether the data read from the hard disk is correct in the related art.

[0006] According to an embodiment of the present application, a method for adjusting a read voltage in a memory is provided, comprising: obtaining a first data set including a plurality of first data objects from a cache, and performing a read operation on the plurality of storage cells according to a first read voltage combination when the plurality of first data objects are respectively written into the plurality of storage cells included in the memory, to obtain a second data set, wherein the first data set includes the plurality of first data objects, the first read voltage combination includes a plurality of read voltage values, the read voltage value is used to indicate a voltage applied to the storage cell when reading the first data object stored in the storage cell, and the second data object included in the second data set is determined according to a conduction threshold voltage corresponding to the storage cell and a conduction condition corresponding to the first read voltage combination; obtaining a first data set corresponding to the first data object; and A first unique hot code set that matches the set, and a second unique hot code set that matches the second data set, wherein the first unique hot code object in the first unique hot code set is used to characterize the first data object in the first data set, and the second unique hot code object in the second unique hot code set is used to characterize the second data object in the second data set; obtaining a result set of multiple bit operations performed according to the first unique hot code set and the second unique hot code set, and determining a numerical difference parameter that matches the first data set and the second data set according to the result set, wherein the numerical difference parameter is used to indicate a change in the data object between the first data set and the second data set; when the numerical difference parameter meets the read voltage adjustment condition, adjusting the first read voltage combination according to the numerical difference parameter to obtain the second read voltage combination.

[0007] According to another aspect of an embodiment of the present application, a read voltage adjustment device in a memory is also provided, comprising: a first acquisition unit, used to acquire a first data set including a plurality of first data objects from a cache, and when the plurality of first data objects are respectively written into a plurality of storage cells included in the memory, a read operation is performed on the plurality of storage cells according to a first read voltage combination to obtain a second data set, wherein the first data set includes a plurality of first data objects, the first read voltage combination includes a plurality of read voltage values, the read voltage value is used to indicate a voltage applied to the storage cell when reading the first data object stored in the storage cell, and the second data object included in the second data set is determined according to a conduction threshold voltage corresponding to the storage cell and a conduction condition corresponding to the first read voltage combination; and a second acquisition unit, used to acquire a first data set corresponding to the first data set. A first unique hot code set matching a data set, and a second unique hot code set matching a second data set, wherein the first unique hot code object in the first unique hot code set is used to characterize the first data object in the first data set, and the second unique hot code object in the second unique hot code set is used to characterize the second data object in the second data set; a third acquisition unit, used to acquire a set of operation results of multiple bit operations performed according to the first unique hot code set and the second unique hot code set, and determine a numerical difference parameter matching the first data set and the second data set according to the operation result set, wherein the numerical difference parameter is used to indicate a change in the data object between the first data set and the second data set; an adjustment unit, used to adjust the first read voltage combination according to the numerical difference parameter when the numerical difference parameter meets the read voltage adjustment condition to obtain a second read voltage combination.

[0008] Optionally, the third acquisition unit includes: a first acquisition module, used to acquire a bitwise XOR result vector between a plurality of first unique hot code objects in the first unique hot code set and a plurality of second unique hot code objects in the second unique hot code set corresponding to the plurality of first unique hot code objects one by one, wherein the bitwise XOR result vector is a numerical vector obtained by performing XOR operations on the numerical values ​​of each numerical bit of the first unique hot code object and the corresponding second unique hot code object; determining the plurality of bitwise XOR result vectors as an operation result set; a second acquisition module, used to acquire a first reference matrix matching the first unique hot code set and a second reference matrix matching the second unique hot code set, wherein a plurality of first column vectors in the first reference matrix respectively correspond to a first unique hot code object in the first unique hot code set, and a plurality of second column vectors in the second reference matrix respectively correspond to a first unique hot code object in the second unique hot code set; acquiring a bitwise AND operation result vector between a plurality of first row vectors in the first reference matrix and a plurality of second row vectors in the second reference matrix; and determining the plurality of bitwise AND operation result vectors as an operation result set.

[0009] Optionally, the second acquisition unit is further used to: determine the number of one-hot code bits M according to the numerical range corresponding to the first data object and the second data object included in the first data set; convert the first data objects included in the first data set into corresponding first one-hot code objects in sequence according to the number of one-hot code bits M, and convert the second data objects included in the second data set into corresponding second one-hot code objects in sequence; wherein the one-hot code object is a numerical combination composed of M-1 numerical values ​​0 and 1 numerical value 1, the number of bits i corresponding to the numerical value 1 is used to indicate the numerical value of the data object corresponding to the one-hot code, the one-hot code object includes the first one-hot code object and the second one-hot code object, the data object includes the first data object and the second data object, M is an integer greater than 1, and i is an integer greater than or equal to M.

[0010] Optionally, the read voltage adjustment device in the above-mentioned memory further includes: a first determination unit, used to: determine first parameter values ​​matching the multiple bitwise XOR result vectors in sequence according to the numerical values ​​included in the multiple bitwise XOR result vectors, wherein the first parameter value is the cumulative result of the multiple bitwise XOR results in the bitwise XOR result vector; a second determination unit, used to determine at least one first reference data object from the first data set and second reference data objects respectively corresponding to the at least one first reference data object determined from the second data set according to the target result vector composed of the multiple first parameter values, wherein the first reference data object is a data object corresponding to the same storage unit as the second reference data object, and the first reference data object has different numerical values ​​from the second reference data object; a third determination unit, used to determine a numerical difference parameter matching the first data set and the second data set according to one less first reference data object and the second reference data objects respectively corresponding to the one less first reference data object.

[0011] Optionally, the read voltage adjustment device in the above-mentioned memory also includes: a fourth acquisition unit, used to: execute the following steps until traversing multiple first row vectors in the first reference matrix: obtain the current first row vector from the multiple first row vectors; obtain the second row vectors in sequence from the second reference matrix, and perform a bitwise AND operation between the current first row vector and the multiple second row vectors obtained in sequence, to obtain a bitwise AND operation result vector that matches the multiple second row vectors in sequence.

[0012] Optionally, the apparatus for adjusting the read voltage in the memory further includes: a fifth acquisition unit, configured to accumulate the bitwise AND operation results in the bitwise AND operation result vector to obtain a second parameter value matching the bitwise AND operation result vector.

[0013] Optionally, the third acquisition unit is also used to: obtain second parameter values ​​that match multiple bitwise AND operation result vectors respectively, wherein the second parameter value is a numerical value obtained by accumulating the bitwise AND operation results in the bitwise AND operation result vector; and determine the multiple second parameter values ​​as numerical difference parameters that match the first data set and the second data set.

[0014] Optionally, the third acquisition unit is also used to: obtain the current bit AND operation result vector between the i-th first row vector in the first reference matrix and the j-th second row vector in the second reference matrix; accumulate the current bit AND operation results in the operation result vector to obtain a current second parameter value that matches the current bit AND operation result vector; determine the current second parameter value as the matrix element of the i-th row and j-th column in the target matrix with a dimension of M*M, where M matches the number of bits of the one-hot code object, i is an integer greater than or equal to 1 and less than or equal to M, and j is an integer greater than or equal to 1 and less than or equal to M; when each matrix element in the target matrix is ​​determined, it is determined as a numerical difference parameter according to the matrix element in the target matrix.

[0015] Optionally, the first acquisition unit is also used to: when the first read voltage combination includes L read voltage sub-combinations, acquire L reference data sets respectively according to the L read voltage sub-combinations, wherein the reference value stored in the kth reference data set of the L reference data sets is the bit value at the i-th bit position of the corresponding second data object, L is an integer greater than or equal to 1, and k is an integer greater than or equal to 0 and less than or equal to L; and combine the bit values ​​corresponding to the same data object in the L reference data sets to obtain the second data object included in the second data set.

[0016] Optionally, the first acquisition unit is further used to: perform the following steps until L read voltage subcombinations are traversed: obtain the i-th read voltage subcombination from the L read voltage subcombinations as the current read voltage subcombination; obtain the current conduction state corresponding to the current storage unit when a voltage is applied to the current storage unit based on the current read voltage subcombination, wherein, when the current read voltage subcombination includes at least one read voltage, the current conduction state includes conduction results that match the at least one read voltage respectively; determine the bit value of the i-th bit position of the second data object read from the current storage unit according to the current conduction state. According to another aspect of the embodiment of the present application, a computer-readable storage medium is also provided, in which a computer program is stored, wherein the computer program is configured to execute the data processing method in the above-mentioned memory when it is run.

[0017] Optionally, the read voltage adjustment device in the above-mentioned memory also includes: a sixth acquisition unit, used to obtain the cell type of the storage cell, wherein the cell type is used to indicate the number of bit positions corresponding to the first data object stored in the storage cell; and obtain a first read voltage combination matching the cell type, wherein the number of combinations of read voltage sub-combinations in the first read voltage combination matches the number of bit positions.

[0018] Optionally, the read voltage adjustment device in the above-mentioned memory also includes: a storage unit, used to determine a target matrix area matching the cell type of the storage cell from a reference matrix; and store numerical difference parameters according to the target matrix area; wherein the reference matrix is ​​a numerical storage matrix corresponding to a first type of storage cell in the memory, the first bit number P of the data object stored in the first type of storage cell is greater than the second bit number Q of the second data object stored in the second type of storage cell in the memory, the dimension of the reference matrix is ​​P*P, the dimension corresponding to the target matrix area is Q*Q, and P is an integer greater than 1.

[0019] Optionally, the read voltage adjustment device in the above-mentioned memory also includes: a fourth determination unit, used to obtain at least one numerical value change combination indicated by the numerical value difference parameter, and the number of repetitions corresponding to each of the at least one numerical value change combinations, wherein the numerical value change combination includes a first data object and a second data object with different values; when the number of repetitions of at least one target numerical value change combination in the at least one numerical value change combination is greater than or equal to a target quantity threshold, it is determined that the numerical difference parameter satisfies the read voltage adjustment condition.

[0020] Optionally, the above-mentioned adjustment unit is also used to: obtain a reference read voltage corresponding to at least one target numerical value change combination, wherein the reference read voltage is a read voltage value included in the first read voltage combination; adjust at least one reference read voltage respectively to obtain at least one target read voltage; and update the first read voltage combination to a second read voltage combination according to at least one target read voltage.

[0021] Optionally, the read voltage adjustment device in the above-mentioned memory also includes: a seventh acquisition unit, used to acquire a third data set including multiple third data objects from the cache, and when the multiple third data objects are respectively written into the multiple storage units included in the memory, perform a read operation on the multiple storage units according to the second read voltage combination to obtain a fourth data set; acquire a third unique code set matching the third data set, and a fourth unique code set matching the fourth data set, and acquire a reference operation result set of multiple bit operations performed according to the third unique code set and the fourth unique code set; when the reference value difference parameter matching the reference operation result set meets the read voltage adjustment condition, adjust the second read voltage combination according to the reference value difference parameter to obtain a third read voltage combination.

[0022] Optionally, the read voltage adjustment device in the above-mentioned memory also includes: a reference adjustment unit, used to determine a reference storage unit corresponding to at least one reference numerical value change combination when the number of repetitions of at least one reference numerical value change combination in at least one numerical value change combination is greater than or equal to a reference quantity threshold and less than a target quantity threshold; and adjust the electrical parameters of the reference storage unit.

[0023] According to another aspect of the embodiments of the present application, a computer program product or a computer program is provided, the computer program product or the computer program including computer instructions, the computer instructions being stored in a computer-readable storage medium. A processor of a computer device reads the computer instructions from the computer-readable storage medium, and the processor executes the computer instructions, so that the computer device executes the method for adjusting the read voltage in the memory as described above.

[0024] According to another aspect of an embodiment of the present application, there is also provided an electronic device, including a memory and a processor, wherein the memory stores a computer program, and the processor is configured to execute the method for adjusting the read voltage in the memory through the computer program.

[0025] Through the present application, data to be stored in a memory is first obtained from a cache, and after the data is stored in the memory, a set of read voltages is applied to the memory to obtain the stored data, the two sets of data obtained are each combined into a data set, and a one-hot code transformation is performed on the two sets of data sets, so that each data in the data set becomes a data form of a one-hot code, multiple bit operations are performed on the transformed data set, and the difference between the data in the memory and the data read from the memory is determined based on the operation results. According to the difference, it can be determined whether the currently applied read voltage makes the data read from the memory different from the data in the memory, and what kind of changes have occurred in the read data compared to the data in the memory, and then it can be determined that the read voltage needs to be adjusted, thereby solving the problem of low efficiency in the process of judging whether the read data is correct when performing a read operation on the data in the memory in the related technology. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] The drawings described herein are used to provide a further understanding of the present application and constitute a part of the present application. The illustrative embodiments of the present application and their descriptions are used to explain the present application and do not constitute an improper limitation on the present application. In the drawings:

[0027] Figure 1 It is a hardware structure block diagram of a server device of a method for adjusting a read voltage in a memory according to an embodiment of the present application;

[0028] Figure 2is a flow chart of a method for adjusting a read voltage in a memory according to an embodiment of the present application;

[0029] Figure 3 is a schematic diagram of bit reading of a method for adjusting a read voltage in a memory according to an embodiment of the present application;

[0030] Figure 4 is a schematic diagram of bit reading of another method for adjusting a read voltage in a memory according to an embodiment of the present application;

[0031] Figure 5 is a schematic diagram of bit reading of another method for adjusting a read voltage in a memory according to an embodiment of the present application;

[0032] Figure 6 is a one-hot code representation schematic diagram of a method for adjusting a read voltage in a memory according to an embodiment of the present application;

[0033] Figure 7 is a schematic diagram of determining a one-hot code object in a method for adjusting a read voltage in a memory according to an embodiment of the present application;

[0034] Figure 8 is a schematic diagram of determining a one-hot code object in another method for adjusting a read voltage in a memory according to an embodiment of the present application;

[0035] Fig. 9 is a schematic diagram of a bitwise XOR operation of a method for adjusting a read voltage in a memory according to an embodiment of the present application;

[0036] Fig.10 is a schematic diagram of a one-hot code set of a method for adjusting a read voltage in a memory according to an embodiment of the present application;

[0037] Fig.11 is a schematic diagram of a one-hot code set of another method for adjusting a read voltage in a memory according to an embodiment of the present application;

[0038] Fig.12 is a schematic diagram of a calculation result of a method for adjusting a read voltage in a memory according to an embodiment of the present application;

[0039] Fig.13 is a target result vector schematic diagram of a method for adjusting a read voltage in a memory according to an embodiment of the present application;

[0040] Fig.14 is a flow chart of another method for adjusting a read voltage in a memory according to an embodiment of the present application;

[0041] Fig.15 is a structural schematic diagram of a read voltage adjustment device in a memory according to an embodiment of the present application;

[0042] Fig.16 It is a structural schematic diagram of an electronic device for adjusting a read voltage in a memory according to an embodiment of the present application; DETAILED DESCRIPTION

[0043] The embodiments of the present application will be described in detail below with reference to the accompanying drawings and in combination with the embodiments.

[0044] It should be noted that the terms "first", "second", etc. in the specification and claims of this application and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence.

[0045] The method embodiments provided in the embodiments of the present application can be executed in a server device or a similar computing device. Taking running on a server device as an example, Figure 1 1 is a hardware structure block diagram of a server device of a method for adjusting a read voltage in a memory according to an embodiment of the present application. Figure 1 As shown, the server device may include one or more ( Figure 1 Only one is shown in the figure) a processor 102 (the processor 102 may include but is not limited to a processing device such as a microprocessor MCU or a programmable logic device FPGA) and a memory 104 for storing data, wherein the above-mentioned server device may also include a transmission device 106 and an input / output device 108 for communication functions. It can be understood by those skilled in the art that Figure 1 The structure shown is only for illustration and does not limit the structure of the above server device. Figure 1 More or fewer components as shown, or with Figure 1 Different configurations are shown.

[0046] The memory 104 can be used to store computer programs, for example, software programs and modules of application software, such as a computer program corresponding to a method for adjusting a read voltage in a memory in an embodiment of the present application. The processor 102 executes various functional applications and data processing by running the computer program stored in the memory 104, that is, to implement the above method. The memory 104 may include a high-speed random access memory, and may also include a non-volatile memory, such as one or more magnetic storage devices, flash memory, or other non-volatile solid-state memory. In some instances, the memory 104 may further include a memory remotely arranged relative to the processor 102, and these remote memories may be connected to a server device via a network. Examples of the above-mentioned network include, but are not limited to, the Internet, an intranet, a local area network, a mobile communication network, and combinations thereof.

[0047] The transmission device 106 is used to receive or send data via a network. The specific example of the above network may include a wireless network provided by a communication provider of the server device. In one example, the transmission device 106 includes a network adapter (Network Interface Controller, referred to as NIC), which can be connected to other network devices through a base station so as to communicate with the Internet. In one example, the transmission device 106 can be a radio frequency (RF) module, which is used to communicate with the Internet wirelessly.

[0048] As an optional implementation, Figure 2 As shown, the method for adjusting the read voltage in the above memory includes:

[0049] S202, acquiring a first data set including a plurality of first data objects from a cache, and performing a read operation on the plurality of storage cells included in a memory according to a first read voltage combination when the plurality of first data objects are respectively written into the plurality of storage cells, to obtain a second data set, wherein the first data set includes the plurality of first data objects, the first read voltage combination includes a plurality of read voltage values, the read voltage value is used to indicate a voltage applied to the storage cell when reading the first data object stored in the storage cell, and the second data object included in the second data set is determined according to a conduction threshold voltage corresponding to the storage cell and a conduction condition corresponding to the first read voltage combination;

[0050] S204, obtaining a first unique hot code set matching the first data set and a second unique hot code set matching the second data set, wherein a first unique hot code object in the first unique hot code set is used to represent a first data object in the first data set, and a second unique hot code object in the second unique hot code set is used to represent a second data object in the second data set;

[0051] S206, obtaining a result set of multiple bit operations performed according to the first one-hot code set and the second one-hot code set, and determining a numerical difference parameter matching the first data set and the second data set according to the result set, wherein the numerical difference parameter is used to indicate a change in data objects between the first data set and the second data set;

[0052] S208 , when the value difference parameter satisfies the read voltage adjustment condition, adjusting the first read voltage combination according to the value difference parameter to obtain a second read voltage combination.

[0053] It can be understood that the above-mentioned first data set is a data set read from the cache. After the above-mentioned first data set is stored in the memory, the above-mentioned reading operation is a reading operation on the first data set, and the read data is determined as the second data set.

[0054] It should be noted that the flash memory responsible for storing data in the memory stores electrons through floating gate transistors. A floating gate transistor serves as a storage unit of a memory. Depending on the number of electrons in the floating gate transistor, the floating gate transistor will have different on-threshold voltages. The on-threshold voltage represents the data stored in the storage unit. The number of electrons in the floating gate transistor can be divided into different quantity levels so that the memory can store different data. For example, in a memory where the number of electrons is divided into 8, a storage unit can store 8 types of data from 0 to 7. The floating gate transistor determines the data to be stored and the corresponding on-threshold voltage by controlling the number of electrons inside. When the voltage applied to the floating gate transistor is higher than the on-threshold voltage, the floating gate transistor is turned on. When the voltage applied to the floating gate transistor is lower than the on-threshold voltage, the floating gate transistor is not turned on. The range of the on-threshold voltage can be determined based on the conduction condition obtained according to the applied voltage range, and the value corresponding to the on-threshold voltage can be further obtained.

[0055] In the above step S202, the first data object in the first data set is first obtained from the cache, and when the first data object is written into multiple storage units in the memory, the first data object in the multiple storage units is read through a set of read voltages, and the read multiple data are determined as the second data set. Figure 3 To explain in detail:

[0056] like Figure 3 As shown, the memory has three bits: high bit, middle bit and low bit. Each bit can store two data, 0 or 1. A total of eight data can be stored: 111, 011, 001, 000, 010, 110, 100 and 101. Corresponding to the eight electron quantity levels on the floating gate transistor, the storage cells storing different data have their own conduction threshold voltages. When the first data object stored in a storage cell is 010, the conduction threshold voltage of the storage cell is Figure 3Vth in the transistor is used to read the first data object. A first read voltage combination is applied to the transistor. A read voltage R1 is applied to the transistor first. The voltage value of the read voltage R1 is less than Vth. At this time, the transistor is not conducting. A read voltage R5 is applied to the transistor. The voltage of R5 is greater than Vth. At this time, the transistor is conducting. At this time, the data of the low bit can be determined to be 0. A read voltage R2 is applied to the transistor. The voltage value of the read voltage R2 is less than Vth. At this time, the transistor is not conducting. A read voltage R4 is applied to the transistor. The voltage value of the read voltage R4 is less than Vth. At this time, the transistor is not conducting. A read voltage R6 is applied to the transistor. The voltage value of the read voltage R6 is greater than Vth. At this time, the transistor is conducting. At this time, the data of the middle bit can be determined to be 1. A read voltage R3 is applied to the transistor. The voltage value of the read voltage R3 is less than Vth. At this time, the transistor is not conducting. A read voltage R7 is applied to the transistor. The voltage value of the read voltage R7 is greater than Vth. The transistor is conducting. At this time, the data of the high bit can be determined to be 0. At this time, after applying the above-mentioned read voltage combination, the first data object in a storage unit has been completely read, and the read result is determined as the second data object, and the multiple second data objects obtained by applying a set of read voltages to multiple storage units are determined as the second data set.

[0057] It should be noted that the above-mentioned encoding rules of the read voltage combination and the corresponding values ​​of the threshold conduction voltage are only an example and do not constitute any limitation. For example, when the number of bits in the memory is 4, the threshold conduction voltage can have 16 different corresponding values, and the read voltage combination is a combination of 15 different read voltages. For another example, when the number of bits in the memory is 2, the threshold conduction voltage can have 4 different corresponding values, and there is only 1 read voltage in the read voltage combination.

[0058] It should be noted that in the above step S202, the second data object obtained after performing the read operation on the storage unit is not necessarily the same as the first data object stored in the storage unit. In the case where a set of wrong first read voltage combinations are applied to the transistor, the second data object read from the storage unit may be inconsistent with the first data object stored in the storage unit. Figure 4 Specific instructions:

[0059] In such Figure 4In the storage unit shown, the first data object stored is 010, and the corresponding conduction threshold voltage is Vth. To read the first data object, a first read voltage combination is applied to the transistor. First, a read voltage R1 is applied to the transistor. The voltage value of the read voltage R1 is less than Vth, and the transistor is not conducting at this time. Then, a read voltage R5 is applied to the transistor. The voltage value of R5 is less than Vth, and the transistor is not conducting at this time. Then, a read voltage R7 is applied to the transistor. The voltage value of R7 is greater than Vth, and the transistor is conducting at this time. At this time, it can be determined that the data of the low bit is 1. Then, a read voltage R2 is applied to the transistor. The voltage value of the read voltage R2 is less than Vth, and the transistor is not conducting at this time. Then, a read voltage R4 is applied to the transistor. The voltage value of the read voltage R4 is less than Vth, and the transistor is not conducting at this time. Then, a read voltage R6 is applied to the transistor. The voltage value of the read voltage R6 is greater than Vth, and the transistor is conducting at this time. At this time, it can be determined that the data of the middle bit is 1. Then, a read voltage R3 is applied to the transistor. The voltage value of the read voltage R3 is less than Vth. At this time, the transistor is not turned on. Then, a read voltage R7 is applied to the transistor. The voltage value of the read voltage R7 is greater than Vth. At this time, the transistor is turned on. At this time, it can be determined that the data of the high bit is 0. At this time, after applying the above read voltage combination, the three bits of the first data object in a storage unit have been read, and the read result is determined as the second data object. At this time, the second data object is inconsistent with the first data object. The low bit of the second data object is 1, and the low bit of the first data object actually stored in the storage unit is 0, that is, the data 010 stored in the memory is read as 011.

[0060] Optionally, the above situation that the second data object read from the storage unit is inconsistent with the first data object stored in the storage unit may also occur when a certain read voltage is incorrectly applied, such as Figure 5 As shown, Figure 5In the first read voltage combination, the voltage value of the read voltage R5 is inaccurate, and the voltage values ​​of the other read voltages are correct. In this case, in order to read the first data object, the first read voltage combination is applied to the transistor, and the read voltage R1 is first applied to the transistor. The voltage value of the read voltage R1 is less than Vth, and it is not conducting at this time. Then, the read voltage R5 is applied to the transistor, and the voltage value of R5 is less than Vth, and it is not conducting at this time. Then, the read voltage R7 is applied to the transistor, and the voltage value of R7 is greater than Vth, and it is conducting at this time. At this time, it can be determined that the data of the low bit is 1, and then the read voltage R2 is applied to the transistor, and the voltage value of the read voltage R2 is less than Vth, and it is not conducting at this time. Then, the read voltage R4 is applied to the transistor, and the voltage value of the read voltage R4 is less than Vth, and it is not conducting at this time. Then, the read voltage R6 is applied to the transistor, and the read voltage R7 is greater than Vth, and it is conducting at this time. The voltage value of voltage R6 is greater than Vth, so it is turned on. At this time, it can be determined that the data of the middle bit is 1. Then, a read voltage R3 is applied to the transistor, and the voltage value of the read voltage R3 is less than Vth, so it is not turned on. Then, a read voltage R7 is applied to the transistor, and the voltage value of the read voltage R7 is greater than Vth, so it is turned on. At this time, it can be determined that the data of the high bit is 0. At this time, after applying the above-mentioned read voltage combination, the three bits of the first data object in a storage unit have been read, and the read result is determined as the second data object. At this time, the second data object is inconsistent with the first data object. The low bit of the second data object is 1, and the low bit of the first data object actually stored in the storage unit is 0, that is, the data 010 stored in the memory is read as 011.

[0061] Then, step S204 is continued to be executed, the first data object in the first data set is transformed into a one-hot code form, and the transformed first data set is determined as a first one-hot code set, and the second data object in the second data set is transformed into a one-hot code form, and the transformed second data set is determined as a second one-hot code set, and the transformation method is as follows Figure 6 As shown, taking the transformation of the first data set as an example, in Figure 6 In the data set shown, each storage unit can store 4 bits of data. The same bits of each storage unit of the first data set are determined as a page. In the storage unit with an index value of N-1, if the stored binary value is 0011, the decimal value of the value can be determined to be 3, and then converted into a one-hot code 0000, 0000, 0000, 1000. After performing the one-hot code transformation on all storage units with indexes 0 to N-1, the first one-hot code set can be determined. Similarly, the second one-hot code set can be determined by using the same transformation method for the second data set. It should be noted that in this embodiment, the step of determining the decimal value of the binary value 0011 to be 3 is only listed for ease of understanding. In the actual one-hot code transformation, the binary value can be directly converted into the one-hot code form.

[0062] Afterwards, step S206 is executed to perform bit operations on the first unique hot code set and the second unique hot code set, and the results of multiple operations are determined as an operation result set. The numerical difference parameters matching the first data set and the second data set are determined according to the operation result set. The above-mentioned bit operation can be a bit AND operation, or a bit XOR operation, etc., which is not specifically limited here.

[0063] Then, step S208 may be performed, where, when the value difference parameter satisfies the read voltage adjustment condition, the first read voltage combination is adjusted according to the value difference parameter to obtain a second read voltage combination.

[0064] Optionally, through the present application, the first data set and the second data set are first obtained, and then a one-hot code transformation is performed on each first data object in the first data set and each second data object in the second data set to obtain the first one-hot code set and the second one-hot code set, so that after the transformation, only one bit of the first data object and the second data object is 1, and the remaining bits are 0. The bit where the value "1" appears represents the value of the one-hot code, and then multiple bit operations can be performed on the first one-hot code set and the second one-hot code set to determine the difference between the first one-hot code set and the second one-hot code set, and the difference is expressed in the form of a numerical difference parameter in a numerical difference parameter table. When the numerical difference parameter meets the read voltage adjustment condition, the first read voltage combination is adjusted to obtain the second read voltage combination, so that the second data set obtained by the second read voltage combination is the same as the first data set stored in the memory, thereby solving the problem of low efficiency in the process of judging whether the read data is correct when reading data in the hard disk in the related technology.

[0065] In an optional implementation, obtaining a set of operation results of multiple bit operations performed according to the first one-hot code set and the second one-hot code set includes one of the following:

[0066] Method 1: obtaining a bitwise XOR result vector between a plurality of first unique hot code objects in the first unique hot code set and a plurality of second unique hot code objects in the second unique hot code set that correspond one to one with the plurality of first unique hot code objects, wherein the bitwise XOR result vector is a numerical vector obtained by performing XOR operations on the numerical values ​​of each numerical bit of the first unique hot code object and the corresponding second unique hot code object; determining the plurality of bitwise XOR result vectors as an operation result set;

[0067] Method 2: Obtain a first reference matrix matching the first unique hot code set and a second reference matrix matching the second unique hot code set, wherein the multiple first column vectors in the first reference matrix respectively correspond to a first unique hot code object in the first unique hot code set, and the multiple second column vectors in the second reference matrix respectively correspond to a first unique hot code object in the second unique hot code set; obtain a bitwise AND operation result vector between the multiple first row vectors in the first reference matrix and the multiple second row vectors in the second reference matrix; and determine the multiple bitwise AND operation result vectors as an operation result set.

[0068] In the first embodiment of the present invention, when the bit operation is a bitwise XOR operation, when the corresponding bits of the two values ​​involved in the operation are the same, the result is 1. At this time, each first unique code object in the first unique code set is subjected to a bitwise XOR operation with the corresponding second unique code object in the second unique code set. Figures 7 to 9 For specific instructions, such as Figure 7 As shown, the value corresponding to each horizontal index in the first unique-hot code set 701 is a first unique-hot code object. For example, the column with a horizontal index of 0 represents the first unique-hot code object 711. Figure 8 As shown, the value corresponding to each horizontal index in the second unique hot code set 801 is a second unique hot code object. For example, the column with horizontal index 0 represents the second unique hot code object 811. Each first unique hot code object is subjected to a bitwise XOR operation with the corresponding second unique hot code object. The result of each bitwise XOR operation is used as a bitwise XOR result vector. The bitwise XOR operation of the first unique hot code object 711 and the second unique hot code object 811 is used as an example for explanation below. Figure 7 The first bit of the first unique-hot code object 711 is 1, and the other bits are 0. Figure 8 The 0th bit of the second unique code object 811 is 1, and the other bits are 0. At this time, it can be determined that the 0th bit and the 1st bit between the first unique code object 711 and the second unique code object 811 are different, and the other bits are the same. The bitwise XOR result of the first unique code object 711 and the second unique code object 811 is as follows: Fig. 9 As shown in the median XOR result vector 901, the 0th and 1st bits are 0, and the remaining bits are 1. Figure 7 Each column of the first unique-hot code set 701 in Figure 8 By performing a bitwise XOR operation on the corresponding columns in the second unique hot code set 801, a bitwise XOR result vector between multiple first unique hot code objects and the corresponding second unique hot code objects can be obtained, and the multiple bitwise XOR result vectors are determined as the operation result set.

[0069] It should be noted that Figure 8 The matrix representation in is only drawn to facilitate the understanding of the reader. In fact, in the bitwise XOR operation between the first unique hot code set and the second unique hot code set, it is not necessary to first make a matrix representation of the first unique hot code set and the second unique hot code set.

[0070] In the second embodiment of the present invention, when the bit operation is a bitwise AND operation, the result is 1 only when the corresponding bits of the two values ​​involved in the operation are both 1. Figures 10 to 12 Take this as an example to explain in detail. Fig.10 , Fig.11 As shown, the one-hot code set is represented in matrix form, and the matrix corresponding to the first one-hot code set is Fig.10 The first reference matrix 1001 ( Fig.10 Only some values ​​of the rows with vertical index 3 are shown in the figure, and the rest are not shown in the figure). The matrix corresponding to the second unique code set is Fig.11 The second reference matrix 1101 ( Fig.11 Only part of the values ​​of the rows with the vertical index of 2 are shown in the figure, and the rest are not shown). In the first reference matrix 1001 and the second reference matrix 1101, each column vector corresponds to a unique hot code object. Fig.10 In the row vector 1002 whose vertical index is 3 (binary index is 0011b), the area corresponding to the horizontal index N-1, N-2, and 3 is a high level represented by grayscale, and the high level represents a value of 1, indicating that the value of the one-hot code object corresponding to the index N-1, N-2, and 3 is 3, and the binary value is 0011. Then, it can be determined that the value of the first data object of the three storage units N-1, N-2, and N-3 is 3, and the binary value is 0011. Fig.11 In the row vector row 1102 whose vertical index is 2 (binary index is 0010b), the area corresponding to the horizontal index N-2, 3, and 0 is a high level of the grayscale mark, and the high level represents a value of 1. It can be determined that the value of the second data object of the three storage units N-2, 3, and 0 is 2, and the binary value is 0010. The bitwise AND operation is performed on the row vector 1002 and the row vector 1102. In the row vector 1002 and the row vector 1102, only the values ​​corresponding to the horizontal indexes N-2 and 3 are both 1 ( Fig.10 , Fig.11 In this case, it can be determined that the values ​​corresponding to the horizontal indexes N-2 and 3 of the bitwise AND operation result vector are 1, and the rest are 0, such as Fig.12 As shown in the median AND operation result vector 1202, at this time, according to the operation result, it can be determined that the value of the first data object stored in the storage unit corresponding to the index N-2, 3 is 0011, and the second data object with a value of 0010 is erroneously read. The bitwise AND operation is performed on each row vector of 1001 in the first reference matrix and each row vector of the second reference matrix 1101 to obtain multiple bitwise AND operation result vectors, and the multiple bitwise AND operation result vectors are determined as the operation result set.

[0071] Through the above implementation of the present application, a bitwise XOR operation can be performed on each unique code object in the first unique hot code set and the corresponding unique code object in the second unique hot code set to obtain a calculation result set, and the first unique hot code set and the second unique hot code set can be represented as a matrix, and each row vector in the first reference matrix matching the first unique hot code set and each row vector in the second reference matrix matching the second unique hot code set can be bitwise ANDed to obtain a calculation result set.

[0072] In an optional implementation, obtaining a first unique-hot code set matching the first data set and a second unique-hot code set matching the second data set includes:

[0073] S1, determining a number M of one-hot code bits according to a numerical range corresponding to a first data object and a second data object included in a first data set;

[0074] S2, according to the number of one-hot code bits M, the first data objects included in the first data set are converted into corresponding first one-hot code objects in sequence, and the second data objects included in the second data set are converted into corresponding second one-hot code objects in sequence; wherein the one-hot code object is a numerical combination composed of M-1 numerical values ​​0 and 1 numerical value 1, the number of bits i corresponding to the numerical value 1 is used to indicate the numerical value of the data object corresponding to the one-hot code, the one-hot code object includes the first one-hot code object and the second one-hot code object, the data object includes the first data object and the second data object, M is an integer greater than 1, and i is an integer greater than or equal to M.

[0075] The following combination Figure 6 The above steps S1-S3 are described in detail:

[0076] like Figure 6 As shown, in data set 601, each column is a data object. Data set 601 has N data objects from 0 to N-1. Data set 601 has pages storing four bits: page 611, page 612, page 613 and page 614. Each page in each data object can store two data, 0 or 1. When the number of pages is four, the four pages can make the data object have a total of sixteen different combinations from 0000 to 1111. At this time, sixteen is determined as the number of unique hot code bits. It should be noted that the number of pages in the above data set is four only for example. The data set can have any number of pages. For example, when the number of pages is three, the three pages can make the data object have a total of sixteen different combinations from 0000 to 1111. Figure 3 As shown, there are 8 different combinations from 000 to 111.

[0077] After determining the number of one-hot code bits, perform one-hot code transformation on each first data object in the first data set to obtain a first one-hot code transformation, and perform one-hot code transformation on each second data object in the second data set to obtain a second one-hot code object; for example, perform one-hot code transformation on the N-1th data object in the data set 601, assuming that the value of the N-1th data object in the data set 601 is 0010 (2 in decimal), then the one-hot code object after this transformation is 0000,0000,0000,0100.

[0078] It can be understood that the one-hot code object consists of a value "1" and M-1 "0s". For example, when M is 16, the one-hot code object consists of a 1 and 15 0s. The position where 1 appears represents the value of the data object corresponding to the one-hot code object. For example, the first one-hot code object is 0000,0000,0000,0100, from the zeroth position to the fifteenth position from right to left, and 1 appears in the second position, which means that the value of the first data object is 0010.

[0079] Through the above implementation of the present application, the number of bits of the one-hot code is determined by the numerical range corresponding to the first data object and the second data object, and then the first data object and the second data object can be transformed into one-hot codes according to the determined number of bits of the one-hot code to obtain the first one-hot code object and the second one-hot code object.

[0080] In an optional implementation, after determining the plurality of bitwise XOR result vectors as the operation result set, the following steps are performed:

[0081] S1, determining first parameter values ​​that match the multiple bitwise XOR result vectors in sequence according to the numerical values ​​included in the multiple bitwise XOR result vectors, wherein the first parameter value is the accumulated result of the multiple bitwise XOR results in the bitwise XOR result vectors;

[0082] S2, determining at least one first reference data object from the first data set and second reference data objects respectively corresponding to the at least one first reference data object from the second data set according to a target result vector composed of a plurality of first parameter values, wherein the first reference data object is a data object corresponding to the same storage unit as the second reference data object, and the first reference data object and the second reference data object have different values;

[0083] S3: Determine a numerical difference parameter matching the first data set and the second data set according to the at least one first reference data object and the second reference data objects respectively corresponding to the at least one first reference data object.

[0084] Optionally, in the above step S1, after obtaining the bitwise XOR result vector, the value in the bitwise XOR result vector is determined, and all the values ​​are added to obtain the first parameter value, such as Fig. 9 As shown, the values ​​corresponding to the vertical indexes 0 and 1 in the XOR result vector 901 are 0, and the rest are 1, that is, the values ​​corresponding to two vertical indexes are 0, and the values ​​corresponding to the remaining 14 vertical indexes are 1. The values ​​corresponding to the vertical indexes in the XOR result vector 901 are added together to determine that the first parameter value corresponding to the XOR result vector 901 is 14. The above-mentioned numerical addition operation performed on the XOR result vector 901 is performed on each other XOR result vector to obtain multiple first parameter values.

[0085] Then, step S2 is performed to combine the multiple first parameter values ​​into Fig.13 The target result vector 1301 with indices 0 to N-1 ( Fig.13 Only the first parameter value corresponding to the bitwise XOR result vector 901 in the target result vector 1301 is shown in the figure, and the first parameter values ​​corresponding to other bitwise XOR result vectors are not shown in the figure). The index of the target result vector 1301 represents which first unique-hot code object and the second unique-hot code object are subjected to the XOR operation. For example, in the first unique-hot code set, the 0th unique-hot code object and the corresponding 0th unique-hot code object in the second unique-hot code set are subjected to the bitwise XOR operation, and the sum of the values ​​of each bit in the bitwise XOR operation result vector is 14. Then Fig.13 The value area corresponding to the 0th index of the target result vector 1301 shown in is filled with the value 14, and the above operation is performed on the N first unique hot code objects and the corresponding N unique hot code objects to determine each value in the target result vector 1301. Thereafter, at least one first reference data object is determined from the first data set according to the target result vector 1301, and a second reference data object corresponding to the at least one first reference data object is determined from the second data set. Specifically, first determine that the horizontal index of the target result vector 1301 whose corresponding value is not the single hot code bit M, in this embodiment, M is 16, and after determining that the horizontal index of the target result vector 1301 whose corresponding value is not 16 is 0, Figure 6 Determining the value with the horizontal index N-1 in the data set 601 shown includes determining the value with the horizontal index N-1 in the first data set and determining the value with the horizontal index N-1 in the second data set, and then using the value with the horizontal index N-1 in the first data set as the first reference data object and using the value with the horizontal index N-1 in the second data set as the second reference data object.

[0086] Then, step S3 is performed to determine the numerical difference parameter matching the first data set and the second data set according to at least one first reference data object and the second reference data object respectively corresponding to the at least one first reference data object, specifically, to count the number of identical changes between the plurality of first reference data objects and the matching second reference data objects, and to use the counted number as the numerical difference parameter: for example, Figure 6 The first reference data object corresponding to the horizontal indexes N-2, N-3, and N-4 of the first data set corresponding to the data set 601 in is 0011. Figure 6 The second reference data object corresponding to the horizontal indexes N-2, N-3, and N-4 of the second data set corresponding to the data set 601 is 0010. At this time, it can be determined that the data sets corresponding to the three horizontal indexes N-2, N-3, and N-4 have undergone a change from the value 0011 in the first data set to the value 0010 in the second data set. At this time, the number of horizontal indexes "3" is determined to be the numerical difference parameter corresponding to the change from 0011 to 0010.

[0087] Through the above-mentioned implementation mode of the present application, first, a cumulative operation is performed on the numerical values ​​included in multiple bitwise XOR result vectors, and first parameter values ​​matching the multiple bitwise XOR result vectors are determined in turn, and then the multiple first parameter values ​​are combined into a target result vector. According to the value of the target result vector, at least one first reference data object is determined from the first data set, and second reference data objects corresponding to the at least one first reference data object are determined from the second data set. According to the at least one first reference data object and the second reference data objects corresponding to the at least one first reference data object, numerical difference parameters matching the first data set and the second data set are determined.

[0088] In an optional implementation, obtaining a bitwise AND operation result vector between a plurality of first row vectors in the first reference matrix and a plurality of second row vectors in the second reference matrix includes:

[0089] S1, execute the following steps until a plurality of first row vectors in the first reference matrix are traversed:

[0090] S2, obtain the current first row vector from multiple first row vectors;

[0091] S3, sequentially obtain second row vectors from the second reference matrix, and perform a bitwise AND operation between the current first row vector and the plurality of sequentially obtained second row vectors to obtain a bitwise AND operation result vector that sequentially matches the plurality of second row vectors.

[0092] Optionally, in step S1, it is ensured that each row vector in the first reference matrix performs subsequent operations.

[0093] Then execute step S2 to determine the current first row vector to be operated from each row vector in the first reference matrix. It should be noted that the determination method can be a sequential traversal or a random selection. After the random selection, the remaining first row vectors are randomly selected until each first row vector is operated, etc. This application does not make specific limitations here.

[0094] Then execute step S3 to sequentially obtain the second row vectors from the second reference matrix. The sequential acquisition method can be sequential traversal or random selection. After the random selection, the remaining second row vectors are randomly selected until each second row vector is operated. The present application does not make specific limitations here. The current first row vector is subjected to a bitwise AND operation with the multiple second row vectors obtained, and the result of the bitwise AND operation is determined as the bitwise AND operation result vector.

[0095] Through the above-mentioned implementation mode of the present application, a bitwise AND operation is performed on each row vector in each first reference matrix and each row vector in the second reference matrix to determine the operation result vector, and then the change between the first data object and the second data object can be determined based on the bitwise AND operation result vector.

[0096] In an optional implementation, after obtaining the bitwise AND operation result vectors between the plurality of first row vectors in the first reference matrix and the plurality of second row vectors in the second reference matrix, the method further includes:

[0097] S1, accumulating each bitwise AND operation result in the bitwise AND operation result vector to obtain a second parameter value matching the bitwise AND operation result vector.

[0098] Optionally, in the above step S1, each bitwise AND operation result is added to obtain a second parameter value, such as Fig.12 As shown, the number of "1"s in the bitwise AND operation result vector 1202 is added, Fig.12 The number of "1"s in the median AND operation result vector 1202 is 2, so the second parameter value is 2.

[0099] Through the above implementation of the present application, each bit AND operation result in the bitwise AND operation is added to determine the second parameter value, and then the change between the first data object and the second data object can be determined according to the second parameter value.

[0100] In an optional implementation, determining a numerical difference parameter matching the first data set and the second data set according to the operation result set includes:

[0101] S1, obtaining second parameter values ​​that match a plurality of bitwise AND operation result vectors respectively, wherein the second parameter value is a value obtained by accumulating the bitwise AND operation results in the bitwise AND operation result vectors;

[0102] S2, determining a plurality of second parameter values ​​as numerical difference parameters matching the first data set and the second data set.

[0103] Optionally, in the above steps S1 to S2, the second parameter value is firstly acquired, and the second parameter value is further determined as a numerical difference parameter.

[0104] Optionally, record the numerical difference parameter in Fig.12 In the target matrix 1201, the changes between the first data object and the second data object are intuitively reflected.

[0105] Through the above implementation of the present application, the second parameter value is first obtained, and the second parameter value is determined as a numerical difference parameter. The numerical difference parameter can be recorded in a numerical difference table to intuitively reflect the changes between the first data object and the second data object.

[0106] In an optional implementation, determining a numerical difference parameter matching the first data set and the second data set according to the operation result set includes:

[0107] S1, obtaining a current bitwise AND operation result vector between the i-th first row vector in the first reference matrix and the j-th second row vector in the second reference matrix;

[0108] S2, accumulating the bit AND operation results in the current bit AND operation result vector to obtain a current second parameter value matching the current bit AND operation result vector;

[0109] S3, determining the current second parameter value as the matrix element of the i-th row and the j-th column in the target matrix with a dimension of M*M, where M matches the number of bits of the one-hot code object, i is an integer greater than or equal to 1 and less than or equal to M, and j is an integer greater than or equal to 1 and less than or equal to M;

[0110] S4, when each matrix element in the target matrix is ​​determined, determining a numerical difference parameter according to the matrix element in the target matrix.

[0111] The following combination Figures 10 to 12 The above steps S1-S4 are described in detail. Fig.10 , Fig.11 As shown, the bitwise AND operation result vector between the fourth first row vector of the first reference matrix 1001, namely, the row vector 1002, and the third second row vector of the second reference matrix 1101, namely, the row vector 1102, is obtained. The bitwise AND operation result vector is as follows: Fig.12 As shown in the median AND operation result vector 1202, the bit AND operation result vector 1202 is determined as the current bit AND operation result vector, and the bit AND operation results in the bit AND operation result vector 1202 are accumulated. The values ​​corresponding to the horizontal indexes N-2 and 3 in the bit AND operation result vector 1202 are 1, and the rest are 0. At this time, the accumulated result is determined to be 2, and the accumulated result is determined as the current second parameter value. Then, in the target matrix 1201 with a dimension of 16*16, the matrix element of the fourth row corresponding to the row vector 1002 and the third column corresponding to the row vector 1102 is determined to be "2". When a bit AND operation is performed once on each first row vector of the first reference matrix 1001 and each second row vector of the second reference matrix 1101, the value of each matrix element in the target matrix is ​​determined, and then the matrix element in the target matrix is ​​determined as the numerical difference parameter.

[0112] Through the above-mentioned implementation mode of the present application, the current second parameter value is obtained by accumulating the values ​​of each unsigned integer in the bitwise AND operation result vector of each row vector of the first reference matrix and each row vector of the second reference matrix, and the matrix element at the corresponding position in the target matrix is ​​determined according to the current second parameter value. When the bitwise AND operation is performed once on each first row vector of the first reference matrix and each second row vector of the second reference matrix, the value of each matrix element in the target matrix is ​​determined, and the matrix elements in the target matrix can be determined as numerical difference parameters.

[0113] In an optional implementation, when the plurality of first data objects are respectively written into the plurality of storage cells included in the memory, a read operation is performed on the plurality of storage cells according to the first read voltage combination to obtain a second data set, including:

[0114] S1, when the first read voltage combination includes L read voltage sub-combinations, respectively obtain L reference data sets according to the L read voltage sub-combinations, wherein the reference value stored in the k-th reference data set among the L reference data sets is the bit value at the i-th bit position of the corresponding second data object, L is an integer greater than or equal to 1, and k is an integer greater than or equal to 0 and less than or equal to L;

[0115] S2, combining the bit values ​​corresponding to the same data object in the L reference data sets to obtain a second data object included in the second data set.

[0116] The following combination Figure 3 The above steps S1 to S2 are explained. Figure 3There are read voltage sub-combinations R1, R5, R7; R2, R4, R6, R7; R3, R7 in the memory. The memory has high bits, middle bits and low bits. Each bit can store two data, 0 or 1. The reference data set corresponding to the read voltage sub-combination R1, R5, R7 is Figure 3 For the row corresponding to the low-order bit in , the reference data set corresponding to the read voltage sub-combinations R2, R4, R6, and R7 is Figure 3 For the row corresponding to the median bit in , the reference data set corresponding to the read voltage sub-combinations R3 and R7 is Figure 3 The row corresponding to the high-order bit in the reference data set is determined, and then the bit value of each bit is determined by determining the value in each reference data set, and then the bit values ​​of the same data object are combined to obtain the second data object included in the second data set.

[0117] Through the above-mentioned implementation mode of the present application, the bit values ​​at different bits in the storage unit are read out respectively through multiple read voltage sub-combinations, and then the value in the storage unit can be read out, and the read value is used as the second data object to be compared with the first data object to determine whether the applied read voltage is incorrect.

[0118] In an optional implementation, when the first read voltage combination includes L read voltage sub-combinations, acquiring L reference data sets according to the L read voltage sub-combinations respectively includes:

[0119] Perform the following steps until L read voltage sub-combinations are traversed:

[0120] S1, obtaining the i-th read voltage sub-combination from L read voltage sub-combinations as the current read voltage sub-combination;

[0121] S2, when a voltage is applied to the current memory cell based on the current read voltage sub-combination, obtaining a current conduction state corresponding to the current memory cell, wherein when the current read voltage sub-combination includes at least one read voltage, the current conduction state includes conduction results respectively matching the at least one read voltage;

[0122] S3, determining a bit value of an i-th bit position of a second data object read from a current storage unit according to the current conduction status.

[0123] The following combination Figure 3 The above steps S1 to S3 are explained. Figure 3 There are read voltage sub-combinations R1, R5, R7; R2, R4, R6, R7; R3, R7 in the memory. The memory has high bits, middle bits and low bits. Each bit can store two data, 0 or 1. The reference data set corresponding to the read voltage sub-combination R1, R5, R7 is Figure 3For the row corresponding to the low-order bit in , the reference data set corresponding to the read voltage sub-combinations R2, R4, R6, and R7 is Figure 3 The row corresponding to the median bit in the memory has three bits, so that the memory can store eight kinds of data: 111, 011, 001, 000, 010, 110, 100, and 101, corresponding to the eight levels of electron quantity on the floating gate transistor. The storage cells storing different data have their own conduction threshold voltages. When the first data object stored in a storage cell is 010, the conduction threshold voltage of the storage cell is Figure 3 Vth in the figure is used to read the first data object. A first read voltage combination is applied to the transistor. First, the first read voltage sub-combination R1, R5, and R7 are applied to the transistor. Specifically, a read voltage R1 is applied to the transistor first. The voltage value of the read voltage R1 is less than Vth. At this time, the transistor is not turned on. Then a read voltage R5 is applied to the transistor. The voltage of R5 is greater than Vth. At this time, the transistor is turned on. At this time, it can be determined that the data of the low bit is 0.

[0124] Then, a second read voltage sub-combination R2, R4, R6, and R7 is applied to the transistor. Specifically, a read voltage R2 is applied to the transistor, and the voltage value of the read voltage R2 is less than Vth, so it is not conducting at this time. Then, a read voltage R4 is applied to the transistor, and the voltage value of the read voltage R4 is less than Vth, so it is not conducting at this time. Then, a read voltage R6 is applied to the transistor, and the voltage value of the read voltage R6 is greater than Vth, so it is conducting at this time. At this time, it can be determined that the data of the middle bit is 1.

[0125] Finally, a second read voltage sub-combination R3 and R7 is applied to the transistor, specifically: a read voltage R3 is applied to the transistor, and the voltage value of the read voltage R3 is less than Vth, so it is not turned on at this time; then a read voltage R7 is applied to the transistor, and the voltage value of the read voltage R7 is greater than Vth, so it is turned on at this time. At this time, it can be determined that the data of the high bit is 0. At this time, by applying the above read voltage combination, the first data object in a storage unit has been completely read, and the read result is determined as the second data object.

[0126] Through the above-mentioned implementation mode of the present application, by using multiple read voltage diodes to apply a read voltage to the transistor, the bit values ​​of different bits in the storage unit are determined in turn, and then the bit values ​​of different bits can be combined into the value in the storage unit, and the read value is used as the second data object to compare with the first data object to determine whether the applied read voltage is incorrect.

[0127] In an optional implementation, when the first read voltage combination includes L read voltage sub-combinations, before respectively acquiring L reference data sets according to the L read voltage sub-combinations, the method further includes:

[0128] S1, obtaining a unit type of a storage unit, wherein the unit type is used to indicate the number of bits corresponding to a first data object stored in the storage unit;

[0129] S2, obtaining a first read voltage combination matching the cell type, wherein the number of combinations of read voltage sub-combinations in the first read voltage combination matches the number of bit positions.

[0130] Optionally, in the above step S1, the unit type of the storage unit is first determined, and the number of bits of the first data object is determined according to the unit type, such as Figure 3 In the example, the cell type of the storage cell is a cell type with bit 3.

[0131] Optionally, in the above step S2, the read voltage combination is determined according to the cell type. For example, when the cell type of the memory cell is determined to be Figure 3 In the case of a cell type in which the bit position in is 3, it is determined that the number of combinations of read voltage sub-combinations is 3, and the three read voltage sub-combinations are R1, R5, R7; R2, R4, R6, R7; R3, R7.

[0132] Through the above-mentioned implementation mode of the present application, the cell type of the storage cell is first determined, and then the number of combinations of read voltage sub-combinations and the specific combination of read voltage sub-combinations are determined according to the number of bits indicated by the cell type, so as to ensure that the second data object can be further determined through the determined read voltage sub-combination.

[0133] In an optional implementation, after determining the numerical difference parameter matching the first data set and the second data set according to the operation result set, the method further includes:

[0134] S1, determining a target matrix region matching a cell type of a storage cell from a reference matrix;

[0135] S2, stores numerical difference parameters according to target matrix regions;

[0136] It should be noted that the reference matrix is ​​a numerical storage matrix corresponding to the first type of storage unit in the memory. The first bit number P of the data object stored in the first type of storage unit is greater than the second bit number Q of the second data object stored in the second type of storage unit in the memory. The dimension of the reference matrix is ​​P*P, and the corresponding dimension of the target matrix area is Q*Q, where P is an integer greater than 1.

[0137] The following combination Figures 10 to 12 The above steps S1-S2 are specifically described. For example, when the cell type of the storage unit is a cell type storing four bits, it is determined that the longitudinal dimensions of the first reference matrix 1001 and the second reference matrix 1101 are .

[0138] It is then determined that the longitudinal dimension of the first reference matrix 1001 and the second reference matrix 1101 is 16, and then based on the longitudinal dimension 16 of the first reference matrix 1001 and the second reference matrix 1101, the dimension of the target matrix area in the target matrix 1201 is determined to be 16*16.

[0139] For another example, when the cell type of the storage unit is a cell type storing three bits, the longitudinal dimensions of the first reference matrix 1001 and the second reference matrix 1101 are determined to be .

[0140] It is then determined that the longitudinal dimension of the first reference matrix 1001 and the second reference matrix 1101 is 8. Then, based on the longitudinal dimension 8 of the first reference matrix 1001 and the second reference matrix 1101, the dimension of the target area in the target matrix 1201 is determined to be 8*8. It should be noted that the above three-bit unit type and four-bit unit type are only used for illustration, and this application does not impose any specific restrictions.

[0141] Optionally, after determining the target matrix region, numerical difference parameters are calculated in the target matrix region.

[0142] Through the above-mentioned implementation mode of the present application, when the cell type of the storage unit is determined, the target matrix area can be determined according to the number of bits of the storage unit indicated by the cell type, and then the numerical difference parameters can be stored in the target matrix area, ensuring that storage cells with different bits can store the numerical difference parameters in the target matrix.

[0143] In an optional implementation manner, before adjusting the first read voltage combination according to the value difference parameter, the method further includes:

[0144] S1, obtaining at least one value change combination indicated by a value difference parameter and a number of recurrences corresponding to each of the at least one value change combination, wherein the value change combination includes a first data object and a second data object having different values;

[0145] S2: When the number of repetitions of at least one target value change combination in the at least one value change combination is greater than or equal to a target quantity threshold, determine that the value difference parameter satisfies a read voltage adjustment condition.

[0146] It can be understood that the above-mentioned value change combination refers to the combination before the change and the combination after the change when the value changes, such as Fig.12 The values ​​of the elements in the target matrix 1201 except the diagonal elements from the upper left to the lower right indicate the recurrence of a combination of value changes.

[0147] It should be noted that the above target quantity threshold can be any natural number set artificially, such as 2, 4, 9, etc., and no specific limitation is made here.

[0148] The following combination Fig.12 The above steps S1 to S2 are explained in detail. When the target quantity threshold is 2, in the target matrix 1201, the numerical difference parameter "2" indicates that among the first data objects with a value of 3, there are two second data objects that are read as having a value of 2. At this time, it is determined that the numerical change combination of the numerical value 3 changing to the numerical value 2 is repeated twice, and then it is determined that the numerical change combination of the numerical value 3 changing to the numerical value 2 is repeated twice, and then it is determined that the number of times the numerical change combination of the numerical value 3 changing to the numerical value 2 is repeated is equal to the target quantity threshold. At this time, it is determined that the numerical difference parameter meets the read voltage adjustment condition.

[0149] Through the above-mentioned implementation mode of the present application, a numerical difference parameter is first obtained, and then the number of repetitions corresponding to each of the multiple numerical change combinations is determined based on the obtained numerical difference parameter, and when the number of repetitions of at least one target numerical change combination in at least one numerical change combination is greater than or equal to the target number threshold, it is determined that the numerical difference parameter satisfies the read voltage adjustment condition, and then the read voltage can be adjusted so that the number of repetitions of the target numerical change combination is less than the target number threshold.

[0150] In an optional implementation manner, adjusting the first read voltage combination according to the numerical difference parameter to obtain the second read voltage combination includes:

[0151] S1, obtaining a reference read voltage corresponding to at least one target value change combination, wherein the reference read voltage is a read voltage value included in a first read voltage combination;

[0152] S2, adjusting at least one reference read voltage respectively to obtain at least one target read voltage;

[0153] S3 , updating the first read voltage combination to a second read voltage combination according to at least one target read voltage.

[0154] Optionally, in the above step S1, firstly, a reference read voltage corresponding to at least one target value change combination is obtained, for example, Fig.12 In the target matrix 1201, the value of the matrix element with the horizontal index of 2 and the vertical index of 3 is 4, which means that four first data objects with the value of 2 (binary 010) are read as second data objects with the value of 3 (binary 011).

[0155] Optionally, the process in which the four first data objects are incorrectly read is as follows: Figure 4 As shown, Figure 4In the example, the first data object stored in the storage unit is 010, and the corresponding on-threshold voltage is Vth. To read the first data object, a first read voltage combination is applied to the transistor, such as Figure 4 As shown, the first read voltage combination applied at this time is overall small. In this case, the reference read voltage R1 is first applied to the transistor, and the voltage value of the reference read voltage R1 is less than Vth. At this time, it is not conducting. Then, the reference read voltage R5 is applied to the transistor, and the reference read voltage R5 is less than Vth. At this time, it is not conducting. Then, the reference read voltage R7 is applied to the transistor, and the voltage of R7 is greater than Vth, and it is conducting at this time. At this time, it can be determined that the data of the low bit is 1. Then, the reference read voltage R2 is applied to the transistor, and the voltage value of the reference read voltage R2 is less than Vth. At this time, it is not conducting. Then, the reference read voltage R4 is applied to the transistor, and the voltage value of the read voltage R4 is less than Vth. At this time, it is not conducting. Then, the reference read voltage R6 is applied to the transistor, and the voltage value of the reference read voltage R6 is greater than Vth, and it is conducting at this time. , at this time, it can be determined that the data of the middle bit is 1, and then the reference read voltage R3 is applied to the transistor. The voltage value of the reference read voltage R3 is less than Vth, and it is not turned on at this time. Then the reference read voltage R7 is applied to the transistor. The voltage value of the reference read voltage R7 is greater than Vth, and it is turned on at this time. At this time, it can be determined that the data of the high bit is 0. At this time, after applying the above-mentioned first read voltage combination, the three bits of the first data object in a storage unit have been read, and the read result is determined as the second data object. At this time, the second data object is inconsistent with the first data object. The value of the second data object is 011, and the value of the first data object actually stored in the storage unit is 010. At this time, it means that the applied reference voltage is incorrect and the reference voltage needs to be adjusted.

[0156] Optionally, the process in which the four first data objects are incorrectly read may also be as follows: Figure 5 As shown, Figure 5 In the example, the first data object stored in the storage unit is 010, and the corresponding on-threshold voltage is Vth. To read the first data object, a first read voltage combination is applied to the transistor, such as Figure 5As shown, the value of the read voltage R5 in the first read voltage combination applied at this time is too small, and the values ​​of other read voltages are normal. In this case, the reference read voltage R1 is first applied to the transistor, and the voltage value of the reference read voltage R1 is less than Vth, so it is not conducting at this time. Then, the reference read voltage R5 is applied to the transistor, and the reference read voltage R5 is less than Vth, so it is not conducting at this time. Then, the reference read voltage R7 is applied to the transistor, and the voltage of R7 is greater than Vth, so it is conducting at this time. At this time, it can be determined that the data of the low bit is 1, and then the reference read voltage R2 is applied to the transistor, and the voltage value of the reference read voltage R2 is less than Vth, so it is not conducting at this time. Then, the reference read voltage R4 is applied to the transistor, and the voltage value of the read voltage R4 is less than Vth, so it is not conducting at this time. Then, the reference read voltage R6 is applied to the transistor, and the voltage value of the reference read voltage R6 is greater than Vth. Vth, it is turned on at this time. At this time, it can be determined that the data of the middle bit is 1, and then the reference read voltage R3 is applied to the transistor. The voltage value of the reference read voltage R3 is less than Vth, and it is not turned on at this time. Then the reference read voltage R7 is applied to the transistor. The voltage value of the reference read voltage R7 is greater than Vth, and it is turned on at this time. At this time, it can be determined that the data of the high bit is 0. At this time, after applying the above-mentioned first read voltage combination, the three bits of the first data object in a storage unit have been read, and the read result is determined as the second data object. At this time, the second data object is inconsistent with the first data object. The value of the second data object is 011, and the value of the first data object actually stored in the storage unit is 010. At this time, it means that the applied reference voltage is incorrect and the reference voltage needs to be adjusted.

[0157] Then, steps S2 to S3 are performed to adjust at least one reference read voltage respectively to obtain at least one target read voltage. Specifically, the same voltage value adjustment is performed on each reference read voltage. For example, the reference voltages R1-R7 are all increased by 5V or decreased by 5V at the same time. One of the read voltage values ​​can also be adjusted. No specific limitation is made here. The adjusted reference voltage is determined as the target read voltage, and the first read voltage combination before adjustment is updated to a second read voltage combination including at least one target read voltage.

[0158] Through the above implementation of the present application, by adjusting the read voltage values ​​corresponding to the target value change combination, a second read voltage combination is obtained to ensure that after the read voltage value adjustment, the values ​​of the first data object and the second data object are the same.

[0159] In an optional implementation manner, after the first read voltage combination is adjusted according to the numerical difference parameter to obtain the second read voltage combination, the method further includes:

[0160] S1, acquiring a third data set including a plurality of third data objects from a cache, and performing a read operation on the plurality of storage cells according to a second read voltage combination when the plurality of third data objects are respectively written into a plurality of storage cells included in the memory, to obtain a fourth data set;

[0161] S2, obtaining a third unique-hot code set matching the third data set and a fourth unique-hot code set matching the fourth data set, and obtaining a reference operation result set of multiple bit operations performed according to the third unique-hot code set and the fourth unique-hot code set;

[0162] S3, when the reference value difference parameter matching the reference operation result set meets the read voltage adjustment condition, the second read voltage combination is adjusted according to the reference value difference parameter to obtain a third read voltage combination.

[0163] In the above step S1, the third data object in the third data set is firstly obtained from the cache, and when the third data object is written into multiple storage cells in the memory, the third data object in the multiple storage cells is read through a set of read voltages, and the read multiple data are determined as the fourth data set.

[0164] Then, step S2 is executed to perform a one-hot code change on the third data set to obtain a third one-hot code set, perform a one-hot code change on the fourth data set to obtain a fourth one-hot code set, and perform multiple bit operations on the third one-hot code set and the fourth one-hot code set to obtain a reference operation result set.

[0165] Furthermore, in the above step S3, a reference value difference parameter is determined by referring to the operation result set, and when the reference value difference parameter satisfies the read voltage condition, the second read voltage combination is adjusted according to the reference value difference parameter to obtain a third read voltage combination.

[0166] Through the above-mentioned implementation mode of the present application, after adjusting the first read voltage combination to obtain the second read voltage combination, the third data set and the fourth data set are obtained, and then the third data set is transformed into a one-hot code to obtain a third one-hot code set, and the fourth data set is transformed into a one-hot code to obtain a fourth one-hot code set, and then multiple bit operations can be performed on the third one-hot code set and the fourth one-hot code set to determine a reference operation result set of the multiple bit operations of the third one-hot code set and the fourth one-hot code set. When the numerical difference parameters matched by the reference operation result set meet the read voltage adjustment conditions, the second read voltage combination is adjusted to obtain the third read voltage combination, and then the value read by the adjusted read voltage combination can be the same as the stored value, thereby solving the technical problem in the related art that when reading data in the hard disk, erroneous data is obtained due to the application of an erroneous read voltage.

[0167] In an optional implementation, after obtaining at least one value change combination indicated by the value difference parameter and the number of recurrences corresponding to each of the at least one value change combination, the method further includes:

[0168] S1, when the number of repetitions of at least one reference value change combination in at least one value change combination is greater than or equal to a reference quantity threshold and less than a target quantity threshold, determining a reference storage unit corresponding to at least one reference value change combination;

[0169] S2, adjusting the electrical parameters of the reference storage unit.

[0170] Optionally, in the above steps S1-S2, a reference quantity threshold and a target quantity threshold are determined, wherein the reference quantity threshold and the target quantity threshold can be artificially set natural numbers with arbitrary values. For example, when the reference threshold is set to 1 and the target quantity threshold is set to 2, if the number of recurrences of a certain value change combination is 1, then at this time, it is considered that the cause of the occurrence of the value change combination is that the electrical parameters of the memory have changed, resulting in a misjudgment. At this time, the electrical parameters of the memory are adjusted, including: changing the gate voltage, amplification factor, cut-off frequency, etc. of the storage unit, and no specific restrictions are made here.

[0171] Through the above steps of the present application, the situation of data misreading caused by the electrical parameters of the memory is taken into account, and the situation in which the first data object and the second data object are incorrectly caused by other factors except the case of incorrect application of the read voltage is improved. Furthermore, when the read voltage is applied correctly, the data misreading caused by electrical characteristics can be corrected by changing the operation of electrical parameters.

[0172] The following combination Fig.14 A method for adjusting the read voltage in a complete memory is described.

[0173] First, the x and y storage unit values ​​can be determined through steps S1402 to S1403, and then the change between the x and y storage unit values ​​can be determined through steps S1404 to S1405. Specifically:

[0174] S1401, obtain requirements and configuration.

[0175] The requirement in the above step S1404 may be data to be compared, and the configuration may include setting a target threshold, determining the number of bits of the memory, etc.

[0176] S1402-1, obtain part of the x data to be compared.

[0177] S1402-2, obtain part of the y data to be compared.

[0178] The x data is the data to be written into the memory, and the y data is the data read back from the same position in the memory. The x and y data can be obtained by Figure 6 The comparison module 603 in the system uses a bus interface (such as an AXI Master interface) to actively retrieve data from certain memories in the system, or it can passively receive data written by an external controller into the buffer storage area in the module. Figure 6 Take the bus interface 604 actively going to the system to obtain data as an example.

[0179] S1403-1, assemble to obtain the x storage unit value.

[0180] S1403-2, assemble to obtain the y storage unit value.

[0181] Figure 6 The bus interface 604 actively obtains x and y data from the system and assembles them to obtain x storage unit value and y storage unit value. Specifically, the same bits of multiple data to be written into the memory are assembled to obtain a storage unit value to obtain the x storage unit value, the x data written into the memory are read to obtain the y data value, and the y data value is assembled to obtain the y storage unit value.

[0182] It should be noted that the x storage cell value is not necessarily the same as the y storage cell value. For example, when the memory is a solid-state drive, the data is stored in the flash memory of the solid-state drive. The flash memory uses floating-gate transistors to store electrons to achieve the effect of non-volatile storage. A floating-gate transistor is used as a storage cell. The transistor has different conduction threshold voltages according to the number of electrons, so as to represent different storage data. For example, if the number of electrons in the transistor is divided into two levels, that is, the threshold voltage is divided into two gears, then a transistor can only represent two types of data, 1 and 0, and it is SLC (Single-level cell); and if the number of electrons in the transistor is divided into 8 levels, that is, the threshold voltage is divided into 8 gears, then a transistor can represent 8 types of data from 0 to 7, and it is TLC (Triple-level cell). There are four other storage cells, MLC (Multi-level cell) and QLC (Quad-level cell). The following uses the case where the number of electrons in the transistor is divided into 8 levels to illustrate that the x storage cell value is not necessarily the same as the y storage cell value:

[0183] like Figure 4As shown, the memory has three bits: high bit, middle bit and low bit. Each bit can store two data, 0 or 1. A total of eight data can be stored: 111, 011, 001, 000, 010, 110, 100 and 101. Corresponding to the eight levels of electron quantity on the floating gate transistor, the storage cells storing different data have their own conduction threshold voltages. When the x storage cell value stored in a storage cell is 010, the conduction threshold voltage of the storage cell is Figure 3 Vth in the figure is used to read the first data object. A set of read voltages are applied to the transistor. First, a read voltage R1 is applied to the transistor. The voltage value of the read voltage R1 is less than Vth. At this time, the transistor is not conducting. Then, a read voltage R5 is applied to the transistor. The voltage value of R5 is less than Vth. At this time, the transistor is not conducting. Then, a read voltage R7 is applied to the transistor. The voltage value of R7 is greater than Vth. At this time, the transistor is conducting. At this time, it can be determined that the data of the low bit is 1. Then, a read voltage R2 is applied to the transistor. The voltage value of the read voltage R2 is less than Vth. At this time, the transistor is not conducting. Then, a read voltage R4 is applied to the transistor. The voltage value of the read voltage R4 is less than Vth. At this time, the transistor is not conducting. Then, a read voltage R6 is applied to the transistor. The voltage value of the read voltage R6 is greater than Vth. At this time, the transistor is conducting. At this time, it can be determined that the data of the middle bit is 1, and then the read voltage R3 is applied to the transistor. The voltage value of the read voltage R3 is less than Vth, and it is not turned on at this time. Then the read voltage R7 is applied to the transistor. The voltage value of the read voltage R7 is greater than Vth, and it is turned on at this time. At this time, it can be determined that the data of the high bit is 0. At this time, after applying the above-mentioned read voltage combination, the three bits of the x storage cell value in a storage cell have been read, and the read result is determined as the y storage cell value. At this time, the y storage cell value is inconsistent with the x storage cell value. The low bit of the y storage cell value is 1, and the low bit of the x storage cell value actually stored in the storage cell is 0, that is, the data 010 stored in the memory is read as 011.

[0184] S1404, checking the change of the value of each x to y storage unit.

[0185] pass Figure 6 The comparison module 603 checks the change of each x to y storage unit value. The change of the unit value may have different situations due to the different bit positions of the unit value. For example, TLC may have up to 56 possible changes such as 000 to 001, 000 to 010, 000 to 100, 001 to 000, ..., 111 to 110, etc., and QLC may have up to 240 possible changes such as 0000 to 0001, 0000 to 0010, ... 11 to 1110. Considering compatibility with various storage units, the comparison module 603 processes according to the maximum number of required results, and also counts the situation where there is no change, so QLC will have 256 comparison results.

[0186] The following is an example of a QLC mode in which the storage unit is 4 bits. Figure 6 As shown, the x data set is a data set with four bits as shown in the data set 601. Each page in each x storage unit value of the x data set can store two types of data, 0 or 1. When the number of pages is four, the four pages can have a total of sixteen different combinations of x storage unit values ​​from 0000 to 1111. Each x storage unit value is transformed into a one-hot code with a length of 16 to obtain an array with a length of N and each element being 16 bits. After operating in a manner similar to matrix transposition, an array with a length of 16 and each element being N bits is obtained, which is recorded as the x data table. The form of the x data table is as follows Figure 6 The unique hot code table 602 is shown in FIG. 6. Similarly, the y data table can be obtained from the y data set. If no data is changed during the process of writing to the flash memory and then reading back, then the x data table should be completely equal to the y data table.

[0187] Perform a bitwise AND operation on each N-bit data in the x data table and the y data table, that is, perform a bitwise AND operation on each row in the x data table and the y data table. It should be noted that the bitwise AND operation on each row in the x data table and the y data table does not mean performing a bitwise AND operation on each row in the x data table and the corresponding row in the y data table, but first taking any row in the x data table, performing a bitwise AND operation on all rows in the y data table, and then traversing and performing the above operation on other rows in the x data table.

[0188] The following Figure 10 to Figure 11 For example, take the row with vertical index 3 (0011b) in the x data table, such as Fig.10 In the row vector 1002, the N-1, N-2 and 3 bits of the row vector 1002 are high (indicated by grayscale in the figure), indicating that the N-1, N-2 and 3 storage unit values ​​assembled from the X data set above are 0011b; take the row with the vertical index 2 (0010b) in the y data table, such as Fig.11 In row vector 1102, the N-2, 3 and 0th storage unit values ​​of row vector 1102 are 0010b. At this time, it is found that the N-2th storage unit value of the x data set is 0011b, and the N-2th storage unit value of the y data set is 0010b, that is, the value of the N-2th storage unit changes from 0011b to 0010b, and similarly, the value of the 3rd storage unit changes from 0011b to 0010b. It should be noted that the "b" in the above values ​​0010b and 0011b indicates that the value is a binary value.

[0189] S1405, record the occurrence of each change.

[0190] like Fig.12As shown, by performing a bitwise AND operation on two N-bit data, the change position of the above value 0011b to 0010b can be recorded in Fig.12 The number of 1s in the bitwise AND operation result vector 1202 is calculated (indicated by grayscale in the figure), and the number of times the value changes from 0011b to 0010b in this round of data comparison is obtained. This number is accumulated in the target matrix 1201, completing a round of data acquisition, assembly, comparison, and recording.

[0191] This embodiment is described by taking the QLC mode as an example, and storage methods in other modes may use the resources compared in the QLC mode.

[0192] For example, comparing the TLC mode data, the assembled storage cell value only occupies Figure 6 The unique hot code table 602 is an 8*8 matrix with horizontal indexes from 0 to 7 and vertical indexes from 0 to 7. Then, when monitoring and recording the data changes from x to y, only Fig.12 In the target matrix 1201, 64 result storage bits of the 8*8 matrix with horizontal indexes from 0 to 7 and vertical indexes from 0 to 7 are used, and other result bits are ignored.

[0193] For example, by comparing the MLC mode data, the assembled storage cell value only occupies Figure 6 The unique hot code table 602 has a 4*4 matrix with horizontal indexes from 0 to 3 and vertical indexes from 0 to 3. When monitoring and recording the data changes from x to y, only Fig.12 In the target matrix 1201, 16 result storage bits of the 4*4 matrix with horizontal indexes from 0 to 3 and vertical indexes from 0 to 3 are used, and other result bits are ignored.

[0194] For example, by comparing the SLC mode data, the assembled storage unit value only occupies Figure 6 The unique hot code table 602 is a 2*2 matrix with horizontal indexes from 0 to 1 and vertical indexes from 0 to 1. Then, when monitoring and recording the data changes from x to y, only Fig.12 In the target matrix 1201, the 4 result storage bits of the 2*2 matrix with horizontal index from 0 to 1 and vertical index from 0 to 1 are used, and the other result bits are ignored.

[0195] S1406, determining whether all data comparison is completed.

[0196] If the comparison is completed, step S1407 is executed; if not, the comparison is restarted from S1401.

[0197] S1407, result output.

[0198] It should be noted that, for the aforementioned method embodiments, for the sake of simplicity, they are all expressed as a series of action combinations, but those skilled in the art should be aware that the present application is not limited by the described order of actions, because according to the present application, certain steps can be performed in other orders or simultaneously. Secondly, those skilled in the art should also be aware that the embodiments described in the specification are all preferred embodiments, and the actions and modules involved are not necessarily required by the present application.

[0199] According to another aspect of the embodiments of the present application, a device for adjusting a read voltage in a memory for implementing the above-mentioned method for adjusting a read voltage in a memory is also provided. Fig.15 As shown, the device comprises:

[0200] The first acquisition unit 1502 is used to acquire a first data set including a plurality of first data objects from a cache, and when the plurality of first data objects are respectively written into a plurality of storage units included in the memory, perform a read operation on the plurality of storage units according to a first read voltage combination to obtain a second data set, wherein the first data set includes a plurality of first data objects, the first read voltage combination includes a plurality of read voltage values, the read voltage value is used to indicate a voltage applied to the storage unit when reading the first data object stored in the storage unit, and the second data object included in the second data set is determined according to a conduction threshold voltage corresponding to the storage unit and a conduction condition corresponding to the first read voltage combination;

[0201] A second acquisition unit 1504 is used to acquire a first unique hot code set matching the first data set and a second unique hot code set matching the second data set, wherein the first unique hot code object in the first unique hot code set is used to represent the first data object in the first data set, and the second unique hot code object in the second unique hot code set is used to represent the second data object in the second data set;

[0202] A third acquisition unit 1506 is used to acquire a set of operation results of multiple bit operations performed according to the first unique hot code set and the second unique hot code set, and determine a numerical difference parameter matching the first data set and the second data set according to the operation result set, wherein the numerical difference parameter is used to indicate a change in data objects between the first data set and the second data set;

[0203] The adjusting unit 1508 is configured to adjust the first read voltage combination according to the numerical difference parameter to obtain a second read voltage combination when the numerical difference parameter satisfies the read voltage adjustment condition.

[0204] Optionally, the third acquisition unit 1506 includes: a first acquisition module, used to acquire a bitwise XOR result vector between a plurality of first unique hot code objects in the first unique hot code set and a plurality of second unique hot code objects in the second unique hot code set corresponding to the plurality of first unique hot code objects, wherein the bitwise XOR result vector is a numerical vector obtained by performing XOR operations on the numerical values ​​of each numerical bit of the first unique hot code object and the corresponding second unique hot code object; determining the plurality of bitwise XOR result vectors as an operation result set; a second acquisition module, used to acquire a first reference matrix matching the first unique hot code set and a second reference matrix matching the second unique hot code set, wherein a plurality of first column vectors in the first reference matrix respectively correspond to a first unique hot code object in the first unique hot code set, and a plurality of second column vectors in the second reference matrix respectively correspond to a first unique hot code object in the second unique hot code set; acquiring a bitwise AND operation result vector between a plurality of first row vectors in the first reference matrix and a plurality of second row vectors in the second reference matrix; and determining the plurality of bitwise AND operation result vectors as an operation result set.

[0205] Optionally, the second acquisition unit 1504 is further used to: determine a one-hot code bit number M according to a numerical range corresponding to the first data object and the second data object included in the first data set; convert the first data objects included in the first data set into corresponding first one-hot code objects in sequence according to the one-hot code bit number M, and convert the second data objects included in the second data set into corresponding second one-hot code objects in sequence; wherein the one-hot code object is a numerical combination composed of M-1 numerical values ​​0 and 1 numerical value 1, the bit number i corresponding to the numerical value 1 is used to indicate the numerical value of the data object corresponding to the one-hot code, the one-hot code object includes the first one-hot code object and the second one-hot code object, the data object includes the first data object and the second data object, M is an integer greater than 1, and i is an integer greater than or equal to M.

[0206] Optionally, the read voltage adjustment device in the above-mentioned memory further includes: a first determination unit, used to: determine first parameter values ​​matching the multiple bitwise XOR result vectors in sequence according to the numerical values ​​included in the multiple bitwise XOR result vectors, wherein the first parameter value is the cumulative result of the multiple bitwise XOR results in the bitwise XOR result vector; a second determination unit, used to determine at least one first reference data object from the first data set and second reference data objects respectively corresponding to the at least one first reference data object determined from the second data set according to the target result vector composed of the multiple first parameter values, wherein the first reference data object is a data object corresponding to the same storage unit as the second reference data object, and the first reference data object has different numerical values ​​from the second reference data object; a third determination unit, used to determine a numerical difference parameter matching the first data set and the second data set according to one less first reference data object and the second reference data objects respectively corresponding to the one less first reference data object.

[0207] Optionally, the read voltage adjustment device in the above-mentioned memory also includes: a fourth acquisition unit, used to: execute the following steps until traversing multiple first row vectors in the first reference matrix: obtain the current first row vector from the multiple first row vectors; obtain the second row vectors in sequence from the second reference matrix, and perform a bitwise AND operation between the current first row vector and the multiple second row vectors obtained in sequence, to obtain a bitwise AND operation result vector that matches the multiple second row vectors in sequence.

[0208] Optionally, the apparatus for adjusting the read voltage in the memory further includes: a fifth acquisition unit, configured to accumulate the bitwise AND operation results in the bitwise AND operation result vector to obtain a second parameter value matching the bitwise AND operation result vector.

[0209] Optionally, the third acquisition unit 1506 is further used to: obtain second parameter values ​​that match multiple bitwise AND operation result vectors respectively, wherein the second parameter value is a numerical value obtained by accumulating the bitwise AND operation results in the bitwise AND operation result vector; and determine the multiple second parameter values ​​as numerical difference parameters that match the first data set and the second data set.

[0210] Optionally, the third acquisition unit is also used to: obtain the current bit AND operation result vector between the i-th first row vector in the first reference matrix and the j-th second row vector in the second reference matrix; accumulate the current bit AND operation results in the operation result vector to obtain a current second parameter value that matches the current bit AND operation result vector; determine the current second parameter value as the matrix element of the i-th row and j-th column in the target matrix with a dimension of M*M, where M matches the number of bits of the one-hot code object, i is an integer greater than or equal to 1 and less than or equal to M, and j is an integer greater than or equal to 1 and less than or equal to M; when each matrix element in the target matrix is ​​determined, it is determined as a numerical difference parameter according to the matrix element in the target matrix.

[0211] Optionally, the first acquisition unit 1502 is further used to: when the first read voltage combination includes L read voltage sub-combinations, acquire L reference data sets respectively according to the L read voltage sub-combinations, wherein the reference value stored in the kth reference data set of the L reference data sets is the bit value at the i-th bit position of the corresponding second data object, L is an integer greater than or equal to 1, and k is an integer greater than or equal to 0 and less than or equal to L; and combine the bit values ​​corresponding to the same data object in the L reference data sets to obtain the second data object included in the second data set.

[0212] Optionally, the first acquisition unit 1502 is further used to: perform the following steps until the L read voltage subcombinations are traversed: obtain the i-th read voltage subcombination from the L read voltage subcombinations as the current read voltage subcombination; obtain the current conduction state corresponding to the current storage unit when a voltage is applied to the current storage unit based on the current read voltage subcombination, wherein, when the current read voltage subcombination includes at least one read voltage, the current conduction state includes conduction results that match the at least one read voltage respectively; determine the bit value of the i-th bit position of the second data object read from the current storage unit according to the current conduction state. According to another aspect of the embodiment of the present application, a computer-readable storage medium is also provided, in which a computer program is stored, wherein the computer program is configured to execute the data processing method in the above-mentioned memory when it is run.

[0213] Optionally, the read voltage adjustment device in the above-mentioned memory also includes: a sixth acquisition unit, used to obtain the cell type of the storage cell, wherein the cell type is used to indicate the number of bit positions corresponding to the first data object stored in the storage cell; and obtain a first read voltage combination matching the cell type, wherein the number of combinations of read voltage sub-combinations in the first read voltage combination matches the number of bit positions.

[0214] Optionally, the read voltage adjustment device in the above-mentioned memory also includes: a storage unit, used to determine a target matrix area matching the cell type of the storage cell from a reference matrix; and store numerical difference parameters according to the target matrix area; wherein the reference matrix is ​​a numerical storage matrix corresponding to a first type of storage cell in the memory, the first bit number P of the data object stored in the first type of storage cell is greater than the second bit number Q of the second data object stored in the second type of storage cell in the memory, the dimension of the reference matrix is ​​P*P, the dimension corresponding to the target matrix area is Q*Q, and P is an integer greater than 1.

[0215] Optionally, the read voltage adjustment device in the above-mentioned memory also includes: a fourth determination unit, used to obtain at least one numerical value change combination indicated by the numerical value difference parameter, and the number of repetitions corresponding to each of the at least one numerical value change combinations, wherein the numerical value change combination includes a first data object and a second data object with different values; when the number of repetitions of at least one target numerical value change combination in the at least one numerical value change combination is greater than or equal to a target quantity threshold, it is determined that the numerical difference parameter satisfies the read voltage adjustment condition.

[0216] Optionally, the above-mentioned adjustment unit 1508 is also used to: obtain a reference read voltage corresponding to at least one target numerical value change combination, wherein the reference read voltage is a read voltage value included in the first read voltage combination; adjust at least one reference read voltage respectively to obtain at least one target read voltage; and update the first read voltage combination to a second read voltage combination according to at least one target read voltage.

[0217] Optionally, the read voltage adjustment device in the above-mentioned memory also includes: a seventh acquisition unit, used to acquire a third data set including multiple third data objects from the cache, and when the multiple third data objects are respectively written into the multiple storage units included in the memory, perform a read operation on the multiple storage units according to the second read voltage combination to obtain a fourth data set; acquire a third unique code set matching the third data set, and a fourth unique code set matching the fourth data set, and acquire a reference operation result set of multiple bit operations performed according to the third unique code set and the fourth unique code set; when the reference value difference parameter matching the reference operation result set meets the read voltage adjustment condition, adjust the second read voltage combination according to the reference value difference parameter to obtain a third read voltage combination.

[0218] Optionally, the read voltage adjustment device in the above-mentioned memory also includes: a reference adjustment unit, used to determine a reference storage unit corresponding to at least one reference numerical value change combination when the number of repetitions of at least one reference numerical value change combination in at least one numerical value change combination is greater than or equal to a reference quantity threshold and less than a target quantity threshold; and adjust the electrical parameters of the reference storage unit.

[0219] According to another aspect of the embodiment of the present application, an electronic device for implementing the above-mentioned method for processing data in a memory is also provided. The electronic device may be Figure 1 The terminal device or server shown in the figure. This embodiment is described by taking the electronic device as a mobile phone or a computer as an example. Fig.16 As shown, the electronic device includes a memory 1602 and a processor 1604. The memory 1602 stores a computer program, and the processor 1604 is configured to execute the steps in any of the above method embodiments through the computer program.

[0220] Optionally, in this embodiment, the electronic device may be located in at least one network device among a plurality of network devices of a computer network.

[0221] Optionally, in this embodiment, the processor may be configured to perform the following steps through a computer program:

[0222] S1, obtaining a first data set including a plurality of first data objects from a cache, and performing a read operation on the plurality of storage cells included in a memory according to a first read voltage combination when the plurality of first data objects are respectively written into the plurality of storage cells, to obtain a second data set, wherein the first data set includes the plurality of first data objects, the first read voltage combination includes a plurality of read voltage values, the read voltage value is used to indicate a voltage applied to the storage cell when reading the first data object stored in the storage cell, and the second data object included in the second data set is determined according to a conduction threshold voltage corresponding to the storage cell and a conduction condition corresponding to the first read voltage combination;

[0223] S2, obtaining a first unique hot code set matching the first data set and a second unique hot code set matching the second data set, wherein a first unique hot code object in the first unique hot code set is used to represent a first data object in the first data set, and a second unique hot code object in the second unique hot code set is used to represent a second data object in the second data set;

[0224] S3, obtaining a set of operation results of multiple bit operations performed according to the first unique hot code set and the second unique hot code set, and determining a numerical difference parameter matching the first data set and the second data set according to the operation result set, wherein the numerical difference parameter is used to indicate a change in data objects between the first data set and the second data set;

[0225] S4, when the value difference parameter satisfies the read voltage adjustment condition, adjusting the first read voltage combination according to the value difference parameter to obtain a second read voltage combination.

[0226] Alternatively, a person skilled in the art may understand that: Fig.16 The structure shown is for illustration only, and the electronic device may also be a smart phone (such as an Android phone, an iOS phone, etc.), a tablet computer, a PDA, a mobile Internet device (Mobile Internet Devices, MID), a PAD, or other terminal devices. Fig.15 The structure of the electronic device is not limited. Fig.15 More or fewer components (such as network interfaces, etc.) as shown in, or with Fig.15 Different configurations are shown.

[0227] Among them, the memory 1602 can be used to store software programs and modules, such as the program instructions / modules corresponding to the method and device for adjusting the read voltage in the memory in the embodiment of the present application. The processor 1604 executes various functional applications and data processing by running the software programs and modules stored in the memory 1602, that is, realizing the above-mentioned method for adjusting the read voltage in the memory. The memory 1602 may include a high-speed random access memory, and may also include a non-volatile memory, such as one or more magnetic storage devices, flash memory, or other non-volatile solid-state memory. In some instances, the memory 1602 may further include a memory remotely arranged relative to the processor 1604, and these remote memories may be connected to the terminal via a network. Examples of the above-mentioned networks include, but are not limited to, the Internet, corporate intranets, local area networks, mobile communication networks, and combinations thereof. Among them, the memory 1602 can be specifically, but not limited to, used to store information such as page elements and page styles. As an example, such as Fig.16 As shown, the memory 1602 may include, but is not limited to, the first acquisition unit 1502, the second acquisition unit 1504, the third acquisition unit 1506, and the adjustment unit 1508 in the device for adjusting the read voltage in the memory. In addition, other module units in the device for adjusting the read voltage in the memory may also be included but are not limited to, which will not be described in detail in this example.

[0228] Optionally, the transmission device 1606 is used to receive or send data via a network. Specific examples of the network may include a wired network and a wireless network. In one example, the transmission device 1606 includes a network adapter (Network Interface Controller, NIC), which can be connected to other network devices and routers via a network cable so as to communicate with the Internet or a local area network. In one example, the transmission device 1606 is a radio frequency (RF) module, which is used to communicate with the Internet wirelessly.

[0229] In addition, the electronic device further includes: a display 1608 for displaying the target page; and a connection bus 1610 for connecting various module components in the electronic device.

[0230] In other embodiments, the terminal device or server may be a node in a distributed system, wherein the distributed system may be a blockchain system, and the blockchain system may be a distributed system formed by connecting the multiple nodes through network communication. The nodes may form a point-to-point network, and any form of computing device, such as a server, terminal or other electronic device, may become a node in the blockchain system by joining the point-to-point network.

[0231] According to one aspect of the present application, a computer-readable storage medium is provided, and a processor of a computer device reads the computer instruction from the computer-readable storage medium, and the processor executes the computer instruction, so that the computer device executes the method provided in the above various optional implementations;

[0232] Optionally, in this embodiment, the computer-readable storage medium may be configured to store a computer program for performing the following steps:

[0233] S1, obtaining a first data set including a plurality of first data objects from a cache, and performing a read operation on the plurality of storage cells included in a memory according to a first read voltage combination when the plurality of first data objects are respectively written into the plurality of storage cells, to obtain a second data set, wherein the first data set includes the plurality of first data objects, the first read voltage combination includes a plurality of read voltage values, the read voltage value is used to indicate a voltage applied to the storage cell when reading the first data object stored in the storage cell, and the second data object included in the second data set is determined according to a conduction threshold voltage corresponding to the storage cell and a conduction condition corresponding to the first read voltage combination;

[0234] S2, obtaining a first unique hot code set matching the first data set and a second unique hot code set matching the second data set, wherein a first unique hot code object in the first unique hot code set is used to represent a first data object in the first data set, and a second unique hot code object in the second unique hot code set is used to represent a second data object in the second data set;

[0235] S3, obtaining a set of operation results of multiple bit operations performed according to the first unique hot code set and the second unique hot code set, and determining a numerical difference parameter matching the first data set and the second data set according to the operation result set, wherein the numerical difference parameter is used to indicate a change in data objects between the first data set and the second data set;

[0236] S4, when the value difference parameter satisfies the read voltage adjustment condition, adjusting the first read voltage combination according to the value difference parameter to obtain a second read voltage combination.

[0237] Optionally, in the embodiments of the present application, the term "module" or "unit" refers to a computer program or a part of a computer program that has a predetermined function and works together with other related parts to achieve a predetermined goal, and can be implemented in whole or in part by using software, hardware (such as processing circuits or memories), or a combination thereof. Similarly, a processor (or multiple processors or memories) can be used to implement one or more modules or units. In addition, each module or unit can be part of an overall module or unit that includes the function of the module or unit.

[0238] Optionally, in this embodiment, a person of ordinary skill in the art may understand that all or part of the steps in the various methods of the above embodiments may be completed by instructing hardware related to the terminal device through a program, and the program may be stored in a computer-readable storage medium, and the storage medium may include: a flash drive, a read-only memory (ROM), a random access memory (RAM), a magnetic disk or an optical disk, etc.

[0239] If the integrated units in the above embodiments are implemented in the form of software functional units and sold or used as independent products, they can be stored in the above computer-readable storage medium. Based on this understanding, the technical solution of the present application, or the part that contributes to the prior art, or all or part of the technical solution can be embodied in the form of a software product, which is stored in a storage medium and includes several instructions for enabling one or more computer devices (which can be personal computers, servers or network devices, etc.) to execute all or part of the steps of the methods of each embodiment of the present application.

[0240] In the above embodiments of the present application, the description of each embodiment has its own emphasis. For parts that are not described in detail in a certain embodiment, please refer to the relevant description of other embodiments.

[0241] In the several embodiments provided in the present application, it should be understood that the disclosed client can be implemented in other ways. Among them, the device embodiments described above are only schematic, for example, the division of units is only a logical function division, and there may be other division methods in actual implementation, for example, multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some interfaces, indirect coupling or communication connection of units or modules, which can be electrical or other forms.

[0242] The units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed on multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0243] In addition, each functional unit in each embodiment of the present application may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit. The above-mentioned integrated unit may be implemented in the form of hardware or in the form of software functional units.

[0244] The above are only preferred implementations of the present application. It should be pointed out that for ordinary technicians in this technical field, several improvements and modifications can be made without departing from the principles of the present application. These improvements and modifications should also be regarded as the scope of protection of the present application.

[0245] It should be noted that the above modules can be implemented by software or hardware. For the latter, it can be implemented in the following ways, but not limited to: the above modules are all located in the same processor; or the above modules are located in different processors in any combination.

[0246] An embodiment of the present application further provides a computer-readable storage medium, in which a computer program is stored, wherein the computer program is configured to execute the steps of any of the above method embodiments when run.

[0247] In an exemplary embodiment, the computer-readable storage medium may include, but is not limited to, various media that can store computer programs, such as a USB flash drive, a read-only memory (ROM), a random access memory (RAM), a mobile hard disk, a magnetic disk or an optical disk.

[0248] An embodiment of the present application further provides an electronic device, including a memory and a processor, wherein a computer program is stored in the memory, and the processor is configured to run the computer program to execute the steps in any one of the above method embodiments.

[0249] In an exemplary embodiment, the electronic device may further include a transmission device and an input / output device, wherein the transmission device is connected to the processor, and the input / output device is connected to the processor.

[0250] An embodiment of the present application further provides a computer program product, which includes a computer program. When the computer program is executed by a processor, the steps in any of the above method embodiments are implemented.

[0251] An embodiment of the present application further provides another computer program product, including a non-volatile computer-readable storage medium, wherein the non-volatile computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the steps in any of the above method embodiments are implemented.

[0252] The embodiments of the present application also provide a computer program, which includes computer instructions, which are stored in a computer-readable storage medium; a processor of a computer device reads the computer instructions from the computer-readable storage medium, and the processor executes the computer instructions, so that the computer device performs the steps in any one of the above method embodiments.

[0253] For specific examples in this embodiment, reference may be made to the examples described in the above embodiments and exemplary implementation modes, and this embodiment will not be described in detail herein.

[0254] Obviously, those skilled in the art should understand that the above modules or steps of the present application can be implemented by a general computing device, they can be concentrated on a single computing device, or distributed on a network composed of multiple computing devices, they can be implemented by a program code executable by a computing device, so that they can be stored in a storage device and executed by the computing device, and in some cases, the steps shown or described can be executed in a different order from that herein, or they can be made into individual integrated circuit modules, or multiple modules or steps therein can be made into a single integrated circuit module for implementation. Thus, the present application is not limited to any specific combination of hardware and software.

[0255] The above are only preferred embodiments of the present application and are not intended to limit the present application. For those skilled in the art, the present application may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the principles of the present application shall be included in the protection scope of the present application.

Claims

1. A method for adjusting a read voltage in a memory, characterized in that: include: A first data set including a plurality of first data objects is acquired from a cache, and when the plurality of first data objects are respectively written into a plurality of storage cells included in a memory, a read operation is performed on the plurality of storage cells according to a first read voltage combination to obtain a second data set, wherein the first data set includes a plurality of first data objects, the first read voltage combination includes a plurality of read voltage values, the read voltage values ​​are used to indicate a voltage applied to the storage cells when reading the first data objects stored in the storage cells, and the second data objects included in the second data set are determined according to a conduction threshold voltage corresponding to the storage cells and a conduction condition corresponding to the first read voltage combination; Obtain a first unique-hot code set matching the first data set and a second unique-hot code set matching the second data set, wherein a first unique-hot code object in the first unique-hot code set is used to represent the first data object in the first data set, and a second unique-hot code object in the second unique-hot code set is used to represent the second data object in the second data set; Obtaining a result set of multiple bit operations performed according to the first set of one-hot codes and the second set of one-hot codes, and determining a numerical difference parameter matching the first data set and the second data set according to the result set of the operations, wherein the numerical difference parameter is used to indicate a change in data objects between the first data set and the second data set; In the case where the numerical difference parameter satisfies the read voltage adjustment condition, the first read voltage combination is adjusted according to the numerical difference parameter to obtain a second read voltage combination.

2. The method according to claim 1, characterized in that The obtaining a set of operation results of multiple bit operations performed according to the first one-hot code set and the second one-hot code set includes one of the following: Obtaining a bitwise XOR result vector between a plurality of the first unique-hot code objects in the first unique-hot code set and a plurality of the second unique-hot code objects in the second unique-hot code set that correspond one-to-one to the plurality of the first unique-hot code objects, wherein the bitwise XOR result vector is a numerical vector obtained by performing XOR operations on the numerical values ​​of each numerical bit of the first unique-hot code object and the corresponding second unique-hot code object; determining the plurality of bitwise XOR result vectors as the operation result set; Obtain a first reference matrix matching the first unique hot code set and a second reference matrix matching the second unique hot code set, wherein a plurality of first column vectors in the first reference matrix respectively correspond to one of the first unique hot code objects in the first unique hot code set, and a plurality of second column vectors in the second reference matrix respectively correspond to one of the first unique hot code objects in the second unique hot code set; obtain a bitwise AND operation result vector between a plurality of first row vectors in the first reference matrix and a plurality of second row vectors in the second reference matrix; and determine a plurality of the bitwise AND operation result vectors as the operation result set.

3. The method according to claim 2, characterized in that The obtaining of a first unique-hot code set matching the first data set and a second unique-hot code set matching the second data set includes: Determine the number of one-hot code bits M according to the value ranges corresponding to the first data object and the second data object included in the first data set; Convert the first data objects included in the first data set into corresponding first one-hot code objects in sequence according to the one-hot code bit number M, and convert the second data objects included in the second data set into corresponding second one-hot code objects in sequence; Among them, the one-hot code object is a numerical combination composed of M-1 numerical values ​​0 and 1 numerical value 1, the bit i corresponding to the numerical value 1 is used to indicate the numerical value of the data object corresponding to the one-hot code, the one-hot code object includes the first one-hot code object and the second one-hot code object, the data object includes the first data object and the second data object, M is an integer greater than 1, and i is an integer greater than or equal to M.

4. The method according to claim 2, characterized in that: After determining the plurality of bitwise XOR result vectors as the operation result set, the method further comprises: Determining first parameter values ​​that match the plurality of bitwise XOR result vectors in sequence according to the numerical values ​​included in the plurality of bitwise XOR result vectors, wherein the first parameter value is an accumulated result of the plurality of bitwise XOR results in the bitwise XOR result vectors; According to the target result vector composed of the plurality of first parameter values, at least one first reference data object is determined from the first data set, and second reference data objects corresponding to at least one of the first reference data objects are determined from the second data set, wherein the first reference data object is a data object corresponding to the same storage unit as the second reference data object, and the first reference data object and the second reference data object have different values; A numerical difference parameter matching the first data set and the second data set is determined based on at least one of the first reference data objects and the second reference data objects respectively corresponding to the at least one of the first reference data objects.

5. The method according to claim 2, characterized in that: The obtaining a bitwise AND operation result vector between a plurality of first row vectors in the first reference matrix and a plurality of second row vectors in the second reference matrix comprises: Perform the following steps until a plurality of the first row vectors in the first reference matrix are traversed: Obtain a current first row vector from the plurality of first row vectors; The second row vectors are sequentially acquired from the second reference matrix, and a bitwise AND operation is performed between the current first row vector and the plurality of second row vectors acquired sequentially, so as to obtain the bitwise AND operation result vector that sequentially matches the plurality of second row vectors.

6. The method according to claim 5, characterized in that After obtaining the bitwise AND operation result vectors between the plurality of first row vectors in the first reference matrix and the plurality of second row vectors in the second reference matrix, the method further includes: Each bit AND operation result in the bit AND operation result vector is accumulated to obtain a second parameter value matching the bit AND operation result vector.

7. The method according to claim 5, characterized in that The determining, according to the operation result set, a numerical difference parameter matching the first data set and the second data set comprises: Obtaining second parameter values ​​that match the plurality of bitwise AND operation result vectors respectively, wherein the second parameter value is a value obtained by accumulating the bitwise AND operation results in the bitwise AND operation result vectors; A plurality of the second parameter values ​​are determined as the numerical difference parameters matching the first data set and the second data set.

8. The method according to claim 5, characterized in that The determining, according to the operation result set, a numerical difference parameter matching the first data set and the second data set comprises: Obtaining a current bitwise AND operation result vector between the i-th first row vector in the first reference matrix and the j-th second row vector in the second reference matrix; Accumulate the bit AND operation results in the current bit AND operation result vector to obtain a current second parameter value matching the current bit AND operation result vector; Determine the current second parameter value as the matrix element at the i-th row and j-th column in a target matrix of dimension M*M, where M matches the number of bits of the one-hot code object, i is an integer greater than or equal to 1 and less than or equal to M, and j is an integer greater than or equal to 1 and less than or equal to M; When each matrix element in the target matrix is ​​determined, the numerical difference parameter is determined according to the matrix element in the target matrix.

9. The method according to claim 1, characterized in that: In the case where the plurality of first data objects are respectively written into a plurality of storage cells included in the memory, a read operation is performed on the plurality of storage cells according to a first read voltage combination to obtain a second data set, including: In a case where the first read voltage combination includes L read voltage sub-combinations, L reference data sets are respectively acquired according to the L read voltage sub-combinations, wherein the reference value stored in the k-th reference data set among the L reference data sets is the bit value at the i-th bit position of the corresponding second data object, L is an integer greater than or equal to 1, and k is an integer greater than or equal to 0 and less than or equal to L; The bit values ​​corresponding to the same data object in the L reference data sets are combined to obtain the second data object included in the second data set.

10. The method according to claim 9, characterized in that In the case where the first read voltage combination includes L read voltage sub-combinations, acquiring L reference data sets according to the L read voltage sub-combinations respectively includes: Perform the following steps until L read voltage sub-combinations are traversed: Obtaining the i-th read voltage sub-combination from the L read voltage sub-combinations as the current read voltage sub-combination; In a case where a voltage is applied to a current memory cell based on the current read voltage sub-combination, obtaining a current conduction condition corresponding to the current memory cell, wherein, in a case where the current read voltage sub-combination includes at least one read voltage, the current conduction condition includes conduction results respectively matching at least one of the read voltages; The bit value of the i-th bit position of the second data object read from the current storage unit is determined according to the current conduction status.

11. The method according to claim 9, characterized in that In the case where the first read voltage combination includes L read voltage sub-combinations, before respectively acquiring L reference data sets according to the L read voltage sub-combinations, the method further includes: Obtaining a unit type of the storage unit, wherein the unit type is used to indicate a number of bits corresponding to the first data object stored in the storage unit; The first read voltage combination matching the cell type is obtained, wherein the number of combinations of the read voltage sub-combinations in the first read voltage combination matches the number of bit positions.

12. The method according to claim 9, characterized in that After determining the numerical difference parameter matching the first data set and the second data set according to the operation result set, the method further includes: Determining a target matrix region matching a cell type of the memory cell from a reference matrix; storing the numerical difference parameter according to the target matrix region; In which, the reference matrix is ​​a numerical storage matrix corresponding to the first type of storage unit in the memory, the first bit number P of the data object stored in the first type of storage unit is greater than the second bit number Q of the second data object stored in the second type of storage unit in the memory, the dimension of the reference matrix is ​​P*P, the dimension corresponding to the target matrix area is Q*Q, and P is an integer greater than 1.

13. The method according to claim 1, characterized in that Before adjusting the first read voltage combination according to the numerical difference parameter, the method further includes: Acquire at least one value change combination indicated by the value difference parameter, and the number of recurrences corresponding to each of the at least one value change combination, wherein the value change combination includes a first data object and a second data object having different values; In the case where the number of repetitions of at least one target numerical value change combination in at least one of the numerical value change combinations is greater than or equal to a target quantity threshold, it is determined that the numerical value difference parameter satisfies a read voltage adjustment condition.

14. The method according to claim 13, characterized in that The step of adjusting the first read voltage combination according to the numerical difference parameter to obtain a second read voltage combination includes: Acquire a reference read voltage corresponding to at least one of the target value change combinations, wherein the reference read voltage is a read voltage value included in the first read voltage combination; Adjusting at least one of the reference read voltages to obtain at least one target read voltage; The first read voltage combination is updated to the second read voltage combination according to at least one of the target read voltages.

15. The method according to claim 13, characterized in that After the first read voltage combination is adjusted according to the numerical difference parameter to obtain a second read voltage combination, the method further includes: Acquire a third data set including a plurality of third data objects from the cache, and perform a read operation on the plurality of storage cells according to the second read voltage combination when the plurality of third data objects are respectively written into the plurality of storage cells included in the memory, so as to obtain a fourth data set; Obtain a third unique-hot code set matching the third data set and a fourth unique-hot code set matching the fourth data set, and obtain a reference operation result set of multiple bit operations performed according to the third unique-hot code set and the fourth unique-hot code set; In the case where the reference value difference parameter matching the reference operation result set meets the read voltage adjustment condition, the second read voltage combination is adjusted according to the reference value difference parameter to obtain a third read voltage combination.

16. The method according to claim 1, characterized in that After obtaining at least one value change combination indicated by the value difference parameter and the number of recurrences corresponding to each of the at least one value change combination, the method further includes: When the number of repetitions of at least one reference value change combination in at least one of the value change combinations is greater than or equal to the reference quantity threshold and less than the target quantity threshold, determining a reference storage unit corresponding to at least one of the reference value change combinations; The electrical parameters of the reference storage unit are adjusted.

17. A device for adjusting a read voltage in a memory, characterized in that: include: a first acquisition unit, configured to acquire a first data set including a plurality of first data objects from a cache, and, when the plurality of first data objects are respectively written into a plurality of storage cells included in a memory, perform a read operation on the plurality of storage cells according to a first read voltage combination to obtain a second data set, wherein the first data set includes a plurality of first data objects, the first read voltage combination includes a plurality of read voltage values, the read voltage values ​​are used to indicate a voltage applied to the storage cells when reading the first data objects stored in the storage cells, and the second data objects included in the second data set are determined according to a conduction threshold voltage corresponding to the storage cells and a conduction condition corresponding to the first read voltage combination; a second acquiring unit, configured to acquire a first unique-hot code set matching the first data set and a second unique-hot code set matching the second data set, wherein a first unique-hot code object in the first unique-hot code set is used to represent the first data object in the first data set, and a second unique-hot code object in the second unique-hot code set is used to represent the second data object in the second data set; a third acquisition unit, configured to acquire a set of operation results of multiple bit operations performed according to the first set of unique hot codes and the second set of unique hot codes, and determine a numerical difference parameter matching the first data set and the second data set according to the set of operation results, wherein the numerical difference parameter is used to indicate a change in a data object between the first data set and the second data set; The adjustment unit is used to adjust the first read voltage combination according to the numerical difference parameter to obtain a second read voltage combination when the numerical difference parameter satisfies a read voltage adjustment condition.

18. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores a computer program, wherein the computer program implements the steps of the method described in any one of claims 1 to 16 when executed by a processor.

19. An electronic device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that: When the processor executes the computer program, the steps of the method described in any one of claims 1 to 16 are implemented.

20. A computer program product, comprising a computer program, characterized in that When the computer program is executed by a processor, the steps of the method described in any one of claims 1 to 16 are implemented.

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