Decoding method and storage device

Abstract

The invention provides a decoding method and a storage device. The method comprises the following steps: reading first data, wherein the first data comprises a plurality of bits; performing a decoding operation on the first data to obtain first guide data and second guide data, the first guide data reflecting an attractive force for performing bit flipping on each of the bits, and the second guide data reflecting a repulsive force for performing bit flipping on each of the bits; generating third boot data according to the first boot data and the second boot data; according to third guide data, performing bit flipping on at least one of the plurality of bits to obtain a flipping result; and performing a second decoding operation on the flipping result. Therefore, decoding efficiency can be improved.

Description

Technical Field

[0001] The present invention relates to the field of storage technology, and in particular to a decoding method and a storage device. Background Art

[0002] Generally speaking, in order to ensure the correctness of the data read from the memory module, the data read from the memory module can be decoded. In the specific decoding process, the more commonly used error correction code is the low-density parity check code (LDPC) to correct the erroneous bits in the data. The bit flipping decoder is widely used in error correction codes in practical applications, especially in the decoding process of low-density parity check (LDPC) codes. The bit flipping decoder is a hard decision decoding method that attempts to correct errors by flipping the erroneous bits. However, for data containing more erroneous bits, the bit flipping algorithm also has the problem of low decoding.

[0003] Therefore, how to effectively improve the decoding efficiency of the decoding operation for read data without increasing the complexity of the decoding operation as much as possible is a problem that needs to be solved urgently. Summary of the invention

[0004] The present invention provides a decoding method and a storage device, which can improve the above-mentioned problem, and further effectively improve the decoding efficiency of the decoding operation for the read data without increasing the complexity of the decoding operation as much as possible.

[0005] An embodiment of the present invention provides a decoding method for a storage device, the decoding method comprising: reading first data, wherein the first data comprises a plurality of bits; performing a first decoding operation on the first data to obtain first guide data and second guide data, wherein the first guide data reflects an attractive force for performing a bit flip on each of the bits, and the second guide data reflects a repulsive force for performing the bit flip on each of the bits; generating third guide data according to the first guide data and the second guide data; performing the bit flip on at least one of the plurality of bits according to the third guide data to obtain a flip result; and performing a second decoding operation on the flip result.

[0006] An embodiment of the present invention further provides a storage device, which includes a connection interface, a memory module and a memory controller. The connection interface is used to connect to a host system. The memory controller is connected to the connection interface and the memory module. The memory controller is used to: read first data from the memory module, wherein the first data includes a plurality of bits; perform a first decoding operation on the first data to obtain first boot data and second boot data, wherein the first boot data reflects an attractive force for bit flipping each of the bits, and the second boot data reflects a repulsive force for bit flipping each of the bits; generate third boot data based on the first boot data and the second boot data; perform the bit flip on at least one of the plurality of bits based on the third boot data to obtain a flip result; and perform a second decoding operation on the flip result.

[0007] Based on the above, after reading the first data including a plurality of bits from the first physical unit, the first data may be subjected to a decoding operation to obtain the first guide data and the second guide data. The first guide data may reflect the attraction for bit flipping the plurality of bits. The second guide data may reflect the repulsion for bit flipping the plurality of bits. According to the first guide data and the second guide data, the third guide data may be generated and used to bit flip at least one of the plurality of bits. Thus, the decoding efficiency of the decoding operation for the read data is effectively improved without increasing the complexity of the decoding operation as much as possible. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figure 1 is a schematic diagram of a data storage system according to an embodiment of the present invention;

[0009] Figure 2 is a schematic diagram of a memory controller according to an embodiment of the present invention;

[0010] Figure 3 is a schematic diagram of a management memory module according to an embodiment of the present invention;

[0011] Figure 4 is a schematic diagram of obtaining first state information according to an embodiment of the present invention;

[0012] Figure 5 and Figure 6 is a schematic diagram of multiple iterative decoding of first data according to an embodiment of the present invention;

[0013] Figure 7 and Figure 8 is a schematic diagram of force field information used to guide bit flipping in a decoding operation according to an embodiment of the present invention;

[0014] Fig. 9 is a flowchart of a decoding method according to an embodiment of the present invention. DETAILED DESCRIPTION

[0015] Reference will now be made in detail to exemplary embodiments of the present invention, examples of which are illustrated in the accompanying drawings. Whenever possible, the same reference numerals are used in the drawings and the description to refer to the same or like parts.

[0016] Figure 1 is a schematic diagram of a data storage system according to an embodiment of the present invention. Figure 1 , the data storage system 10 includes a host system 11 and a storage device 12. The storage device 12 can be connected to the host system 11 and can be used to store data from the host system 11. For example, the host system 11 can be a smart phone, a tablet computer, a notebook computer, a desktop computer, an industrial computer, a game console, a server, or a computer system disposed in a specific carrier (such as a vehicle, an aircraft, or a ship), and the type of the host system 11 is not limited thereto. In addition, the storage device 12 may include a solid state drive, a USB flash drive, a memory card, or other types of non-volatile storage devices.

[0017] The storage device 12 includes a connection interface 121, a memory module 122, and a memory controller 123. The connection interface 121 is used to connect the storage device 12 to the host system 11. For example, the connection interface 121 may support an embedded Multi-Media Card (eMMC), a Universal Flash Storage (UFS), a Peripheral Component Interconnect Express (PCI Express), a Non-Volatile Memory Express (NVM express), a Serial Advanced Technology Attachment (SATA), a Universal Serial Bus (USB), or other types of connection interface standards. Therefore, the storage device 12 can communicate with the host system 11 (e.g., exchange signals, instructions, and / or data) via the connection interface 121.

[0018] The memory module 122 is used to store data. For example, the memory module 122 may include one or more rewritable non-volatile memory modules. Each rewritable non-volatile memory module may include one or more memory cell arrays. The memory cells in the memory cell array store data in the form of voltage (also called threshold voltage). For example, the memory module 122 may include a single-level cell (SLC) NAND flash memory module, a multi-level cell (MLC) NAND flash memory module, a triple-level cell (TLC) NAND flash memory module, a quad-level cell (QLC) NAND flash memory module and / or other memory modules having the same or similar characteristics.

[0019] The memory controller 123 is connected to the connection interface 121 and the memory module 122. The memory controller 123 can be regarded as the control core of the storage device 12 and is used to control the storage device 12. For example, the memory controller 123 can be used to control or manage the entire or partial operation of the storage device 12. For example, the memory controller 123 may include a central processing unit (CPU), or other programmable general-purpose or special-purpose microprocessors, digital signal processors (DSP), programmable controllers, application-specific integrated circuits (ASIC), programmable logic devices (PLD) or other similar devices or combinations of these devices. In one embodiment, the memory controller 123 may include a flash memory controller.

[0020] The memory controller 123 may send a command sequence to the memory module 122 to access the memory module 122. For example, the memory controller 123 may send a write command sequence to the memory module 122 to instruct the memory module 122 to store data in a specific storage unit. For example, the memory controller 123 may send a read command sequence to the memory module 122 to instruct the memory module 122 to read data from a specific storage unit. For example, the memory controller 123 may send an erase command sequence to the memory module 122 to instruct the memory module 122 to erase the data stored in a specific storage unit. In addition, the memory controller 123 may also send other types of command sequences to the memory module 122 to instruct the memory module 122 to perform other types of operations, which are not limited by the present invention. The memory module 122 may receive the command sequence from the memory controller 123 and access the storage unit inside the memory module 122 according to the command sequence.

[0021] Figure 2 FIG. 1 is a schematic diagram of a memory controller according to an embodiment of the present invention. Figure 1 and Figure 2 The memory controller 123 includes a host interface 21, a memory interface 22 and a memory control circuit 23. The host interface 21 is used to connect to the host system 11 through the connection interface 121 to communicate with the host system 11. The memory interface 22 is used to connect to the memory module 122 to access the memory module 122.

[0022] The memory control circuit 23 is connected to the host interface 21 and the memory interface 22. The memory control circuit 23 may be used to control or manage the whole or part of the operation of the memory controller 123. For example, the memory control circuit 23 may communicate with the host system 11 through the host interface 21 and access the memory module 122 through the memory interface 22. For example, the memory control circuit 23 may include a control circuit such as an embedded controller or a microcontroller. In the following embodiments, the description of the memory control circuit 23 is equivalent to the description of the memory controller 123.

[0023] In one embodiment, the memory controller 123 may further include a buffer memory 24. The buffer memory 24 is connected to the memory control circuit 23 and used to cache data. For example, the buffer memory 24 may be used to cache instructions from the host system 11, data from the host system 11, and / or data from the memory module 122.

[0024] In one embodiment, the memory controller 123 may further include a decoding circuit 25. The decoding circuit 25 is connected to the memory control circuit 23 and is used to perform encoding and decoding on the data to ensure the correctness of the data. For example, the decoding circuit 25 may support various encoding / decoding algorithms such as Low Density Parity Check Code (LDPC code), BCH code, Reed-Solomon code (RS code), Exclusive OR (XOR) code, etc. In one embodiment, the memory controller 123 may also include various other types of circuit modules (such as power management circuits, etc.), which are not limited by the present invention.

[0025] Figure 3 FIG. 1 is a schematic diagram of a management memory module according to an embodiment of the present invention. Figures 1 to 3 The memory module 122 includes a plurality of physical units 301 ( 1 ) to 301 (B). Each physical unit includes a plurality of storage cells and is used to store data in a non-volatile manner.

[0026] In one embodiment, a physical unit may include one or more physical programming units. In one embodiment, a physical programming unit may include multiple physical sectors. For example, the data capacity of a physical sector may be 512 bytes (Bytes, B), and a physical programming unit may include 32 physical sectors. However, the data capacity of a physical sector and / or the total number of physical sectors included in a physical programming unit can be adjusted according to practical needs, and the present invention is not limited thereto. In one embodiment, a physical programming unit can be regarded as a physical page. For example, the storage capacity of a physical programming unit may be 16 kilobytes, and the present invention is not limited thereto.

[0027] In one embodiment, a physical programming unit is a minimum unit for synchronously writing data in the memory module 122. For example, when a programming operation (also referred to as a write operation) is performed on a physical programming unit to write data to the physical programming unit, multiple memory cells in the physical programming unit may be synchronously programmed to store corresponding data. For example, when programming a physical programming unit, a write voltage may be applied to the physical programming unit to change the threshold voltage of at least some of the memory cells in the physical programming unit. For example, the threshold voltage of a memory cell may reflect the bit data stored in the memory cell.

[0028] In one embodiment, a physical erase unit may include a plurality of physical programming units. The plurality of physical programming units in a physical erase unit may be erased synchronously. For example, when performing an erase operation on a physical erase unit, an erase voltage may be applied to the plurality of physical programming units in the physical erase unit to change the threshold voltage of at least some of the storage cells in the physical programming units. By performing an erase operation on a physical erase unit, the data stored in the physical erase unit may be cleared.

[0029] In one embodiment, the memory control circuit 23 can logically associate the physical units 301(1)-301(A) and 301(A+1)-301(B) to the data area 31 and the idle area 32, respectively. The physical units 301(1)-301(A) in the data area 31 all store data (also called user data) from the host system 11. For example, any physical unit in the data area 31 can store valid data and / or invalid data. In addition, the physical units 301(A+1)-301(B) in the idle area 32 do not store data (e.g., valid data).

[0030] In one embodiment, if a physical unit does not store valid data, the physical unit can be associated with the idle area 32. In addition, the physical unit in the idle area 32 can be erased to clear the data in the physical unit. In one embodiment, the physical unit in the idle area 32 is also called an idle physical unit. In one embodiment, the idle area 32 is also called an idle pool.

[0031] In one embodiment, when data is to be stored, the memory control circuit 23 may select one or more physical cells from the idle area 32 and instruct the memory module 122 to store the data in the selected physical cells. After the data is stored in the physical cell, the physical cell may be associated with the data area 31. In other words, one or more physical cells may be used alternately between the data area 31 and the idle area 32.

[0032] In one embodiment, the memory control circuit 23 may configure a plurality of logical units 302(1)-302(C) to map the physical units (i.e., the physical units 301(1)-301(A)) in the data area 31. For example, one logical unit may correspond to one logical block address (LBA) or other logical management unit. One logical unit may be mapped to one or more physical units.

[0033] In one embodiment, if a physical unit is currently mapped by any logical unit, the memory control circuit 23 can determine that the data currently stored in the physical unit includes valid data. Conversely, if a physical unit is not currently mapped by any logical unit, the memory control circuit 23 can determine that the physical unit does not currently store any valid data.

[0034] In one embodiment, the memory control circuit 23 may record the mapping relationship between the logical unit and the physical unit in at least one management table (also referred to as a logical-to-physical mapping table). In one embodiment, the memory control circuit 23 may instruct the memory module 122 to perform operations such as data reading, writing or erasing according to the information in the management table (i.e., the logical-to-physical mapping table).

[0035] In one embodiment, the memory control circuit 23 may read data (also referred to as first data) from at least one physical unit (also referred to as a first physical unit) in the memory module 122. For example, the first physical unit may be at least one of the physical units 301(1) to 301(B). The first data includes a plurality of bits. For example, the memory control circuit 23 may send a read instruction sequence to the memory module 122. The memory module 122 may perform a read operation on the first physical unit according to the read instruction sequence. The memory module 122 may return the first data to the memory control circuit 23 according to the read result of the read operation.

[0036] In one embodiment, after obtaining the first data, the decoding circuit 25 may perform a decoding operation (also referred to as a first decoding operation) on the first data to obtain multiple types of pilot data. Then, the decoding circuit 25 may bit flip at least one bit in the first data according to the multiple types of pilot data.

[0037] In one embodiment, the guide data includes first guide data and second guide data. The first guide data reflects an attractive force for bit flipping multiple bits in the first data. The second guide data reflects a repulsive force for bit flipping multiple bits in the first data.

[0038] In one embodiment, the gravity may be used to increase the probability of performing a bit flip on at least one of the plurality of bits. That is, if the gravity reflected by the first pilot data is greater, it means that the probability of at least one bit in the first data being flipped (e.g., flipped from "1" to "0" or from "0" to "1") in the first decoding operation is higher.

[0039] In one embodiment, the repulsive force may be used to reduce the probability of bit flipping of at least one of the plurality of bits. That is, if the repulsive force reflected by the second guide data is greater, it means that the probability of at least one bit in the first data being flipped (e.g., flipped from "1" to "0" or from "0" to "1") in the first decoding operation is lower.

[0040] In one embodiment, the memory control circuit 23 may generate another boot data (also referred to as third boot data) according to the first boot data and the second boot data. The decoding circuit 25 may perform bit flipping on at least one bit in the first data according to the third boot data. For example, the decoding circuit 25 may flip at least one bit in the first data (also referred to as the first bit) from "1" to "0" and / or flip at least one bit in the first data (also referred to as the second bit) from "0" to "1" according to the third boot data.

[0041] In one embodiment, in the first decoding operation, the memory control circuit 23 may obtain state information related to a plurality of bits in the first data (also referred to as first state information). The first state information may reflect the current state of the plurality of bits. For example, the first state information may reflect that some bits in the first data are error bits and / or some bits in the first data are not error bits.

[0042] Figure 4 is a schematic diagram of obtaining first state information according to an embodiment of the present invention. Figure 4 In one embodiment, it is assumed that the first data includes a codeword 42, and the codeword 42 includes bits b(1) to b(n).

[0043] In one embodiment, in the first decoding operation, the decoding circuit 25 may obtain a vector 43 (i.e., first state information) according to the check matrix 41 (also referred to as the H matrix) and the codeword 42. For example, the decoding circuit 25 may perform matrix multiplication on the check matrix 41 and the codeword 42, and obtain the vector 43 according to the result of the matrix multiplication. In one embodiment, the vector 43 is also referred to as the vector y. The vector 43 (i.e., the first state information) may reflect the current state of the codeword 42 (i.e., the first data).

[0044] Specifically, the size of the first data read by each variable node (B node) before each verification mainly depends on the following factors:

[0045] 1. Number of variable nodes: Each check node (C node) needs to read data from all the variable nodes it is connected to. In the check matrix H, the number of rows represents the number of check nodes C nodes. Each row represents multiple variable nodes connected to a check node. The number of connections is determined by the number of columns with a value of 1 in the row.

[0046] 2. The amount of data sent by each variable node: Usually, each variable node sends one bit of information (0 or 1) to the connected check node C, representing the current bit state. Therefore, each check node receives 1 bit of data from each connected variable node.

[0047] Exemplarily, it is assumed that the check matrix H has the following structure:

[0048]

[0049] Then the number of check nodes (number of C nodes) in the above H is 3, and the number of variable nodes (number of B nodes) connected thereto is 6. Set the nodes of the check matrix H by row to: C1, C2 and C3 respectively.

[0050] Before each verification: the data read by C1 from the connected B node is: b1, b3, b4, and the corresponding data size is: 3 bits (3 0s or 1s); the data read by C2 (verification node 2) from the connected B node is: b2, b4, b5, and the corresponding data size is: 3 bits (3 0s or 1s); the data read by C3 (verification node 3) from the connected B node is: b1, b2, b5, b6, and the corresponding data size is: 4 bits (4 0s or 1s).

[0051] The amount of data read by each check node is equal to the number of variable nodes it is connected to multiplied by the size of the data sent by each variable node (usually 1 bit). Correspondingly, the amount of data read by all check nodes is: if there are m check nodes and n variable nodes, then the total amount of data read is the total number of variable nodes connected to all check nodes. (For example, if the number of variable nodes connected to each check node is d1, d2, ..., dm, respectively, then the total amount of data is d1+d2+...+d m bits.)

[0052] In the above example, the total amount of data read is: 3+3+4=10 bits. Therefore, before each check, the total amount of data read is determined by the number of connections in the check matrix. The amount of data read by each check node is the number of variable nodes it is connected to, and each connected variable node transmits 1 bit of data.

[0053] It should be noted that in the existing scheme, if the 10 bits in the above example are flipped, 10 iterations are required (i.e., one target bit is selected each time for judgment before flipping). However, the method proposed in the present application scheme only needs to select at least one bit to perform flipping based on each calculation result, thereby improving the coding efficiency. In addition, the size of the data read each time in the present application scheme can be determined based on the dimension of the check matrix, or it can be performed with data of a preset size, including but not limited to: 8bit, 16bit, 1KB size, etc., which are not specifically limited here.

[0054] In one embodiment, vector 43 includes bits s(1) to s(n). Each of bits s(1) to s(n) is also referred to as a syndrome. In particular, the value of bit s(i) can reflect whether bit b(i) in codeword 42 is an error bit. For example, if bit s(i) is "1", it indicates that bit b(i) in codeword 42 has a high probability of being an error bit. On the contrary, if bit s(i) is "0", it indicates that bit b(i) in codeword 42 has a high probability of not being an error bit. In one embodiment, if bits s(1) to s(n) are all "0", it indicates that there is no error bit in codeword 42. If there is no error bit in codeword 42, decoding circuit 25 can output successfully decoded data and stop decoding.

[0055] It should be noted that, according to the parity check matrix 41 , the values ​​of multiple bits in the vector 43 may be affected by the same bit in the codeword 42 . Therefore, the error bit in the codeword 42 cannot be accurately located based on the vector 43 alone.

[0056] Conventionally, in order to determine the bit to be flipped in the current decoding operation (i.e., the error bit), the memory control circuit 23 may refer to the parity check matrix 41 to obtain the syndrome sum corresponding to each bit in the codeword 42. Then, the memory control circuit 23 may determine the bit in the codeword 42 corresponding to the largest syndrome sum as the error bit and perform a bit flip on the bit (e.g., flip from "1" to "0" or from "0" to "1"). By flipping a small number of bits one by one in multiple iterations, all errors in the codeword 42 can be corrected.

[0057] However, the disadvantage of this error correction method is also obvious, that is, only a very small number of bits can be flipped each time. Once the total number of bits flipped in a certain iteration is too large, there is a high probability that the flipping performed in this iteration will be invalid, and may even cause error divergence. Therefore, it is necessary to propose further improvement methods to effectively improve the decoding efficiency of the decoding operation for the read data without increasing the complexity of the decoding operation as much as possible.

[0058] In one embodiment, during the first decoding operation, the memory control circuit 23 may also obtain another state information (also referred to as second state information) related to the plurality of bits in the first data. The second state information may reflect the target state of the plurality of bits. For example, in one embodiment, the second state information may include a vector x, and the plurality of bits in the vector x are all "0". In other words, the target state of the plurality of bits reflected by the second state information is the expected Figure 4 The final state of the vector y in . Once the bits s(1) to s(n) in the vector y are all "0", it means that there is no error bit in the codeword 42 (ie, the first data) being decoded.

[0059] It should be noted that the target state (e.g.,

[00000] ) is an assumption that the data received by the receiver should be in a known ideal state without errors. For example, in some coding schemes, the target state may be all zeros (as set in the construction of error correction codes), so the goal of the algorithm is to flip the bits to be as close to this assumed target state as possible.

[0060] In fact, the receiver only knows the data state y currently read, but does not know whether it is correct. The read data may contain errors, but the receiver does not know the specific error location. Therefore, the goal of the error correction process is to gradually correct these errors. It is not known what the ideal target state is, but only uses a hypothetical target state to guide error correction. The algorithm continuously iterates and performs bit flipping according to the verification results and rules, so that the received signal conforms to the preset target state as much as possible.

[0061] In practical applications, the target state is unknown. By using an error correction algorithm (e.g., Bit-flipping algorithm), the redundant information provided by the check node (C node) is used to detect and correct the received erroneous bits. This process does not rely on a clear target state, and the target state is only used to guide the assumption of the flipping direction.

[0062] In one embodiment, the memory control circuit 23 may obtain distance information (also referred to as first distance information) according to the first state information and the second state information. The first distance information may reflect the Euclidean distance (also referred to as Euclidean distance) between the current state and the target state. For example, the memory control circuit 23 may obtain the first distance information according to the following formula (1.1).

[0063] D(1)=||yx||(1.1)

[0064] In formula (1.1), vector x represents the target state of the plurality of bits in the first data, vector y represents the current state of the plurality of bits, and D(1) is the first distance information. Then, the memory control circuit 23 can obtain the first guide data according to the first distance information.

[0065] In one embodiment, the memory control circuit 23 can obtain the gravitational potential field information corresponding to the first data according to the first distance information. In particular, the gravitational potential field information can be used to simulate the gravitational potential field used to pull multiple bits in the first data from the current state to the target state. For example, the memory control circuit 23 can obtain the gravitational potential field information according to the following formula (1.2).

[0066]

[0067] In formula (1.2), k(1) is an attraction constant, and U1(y) is gravitational potential field information. In particular, k(1) can be used to control the strength of the gravitational potential field. For example, the value of k(1) is positively correlated with the strength of the gravitational potential field. In one embodiment, setting k(1) to a larger value can accelerate the pulling of multiple bits in the first data from the current state to the target state, but may also cause overcorrection. In one embodiment, setting k(1) to a smaller value can slow down the pulling of multiple bits in the first data from the current state to the target state, but may also cause an increase in the number of iterations. In one embodiment, the value of k(1) can be set based on experience and can be dynamically adjusted. Then, the memory control circuit 23 can obtain the first guide data based on the gravitational potential field information.

[0068] In one embodiment, the memory control circuit 23 can obtain the gravitational field gradient information according to the gravitational potential field information. In particular, the gravitational field gradient information can be used to simulate the gradient of the gravitational potential field. For example, the memory control circuit 23 can obtain the gravitational field gradient information according to the following formula (1.3).

[0069]

[0070] In formula (1.3), is the gravitational field gradient information. Then, the memory control circuit 23 may obtain the first guidance data according to the gravitational field gradient information. For example, the first guidance data may include the gravitational field gradient information.

[0071] In one embodiment, in the first decoding operation, the memory control circuit 23 may also obtain another state information (also referred to as third state information) related to the plurality of bits in the first data. The third state information may reflect the exclusion state of the plurality of bits in the first data. For example, in one embodiment, the third state information may include vector z. The plurality of bits in vector z may all be "1". In other words, the exclusion state of the plurality of bits reflected by the third state information is the inverse state of vector x.

[0072] In one embodiment, the memory control circuit 23 may obtain distance information (also referred to as second distance information) according to the first state information and the third state information. The second distance information may reflect the Euclidean distance (i.e., the Euclidean distance) between the current state and the exclusion state. For example, the memory control circuit 23 may obtain the second distance information according to the following formula (2.1).

[0073] D(2)=||yz||(2.1)

[0074] In formula (1.1), vector z represents the exclusion state of a plurality of bits in the first data, and D(2) is the second distance information. Then, the memory control circuit 23 can obtain the second guide data according to the second distance information.

[0075] In one embodiment, the memory control circuit 23 can obtain the repulsive potential field information corresponding to the first data according to the second distance information. In particular, the repulsive potential field information can be used to simulate the repulsive potential field used to resist pulling the plurality of bits in the first data from the current state to the target state. For example, the memory control circuit 23 can obtain the repulsive potential field information according to the following formulas (2.2) and (2.3).

[0076]

[0077] U2(y)=0,if D(2)>d(2.3)

[0078] In formulas (2.2) and (2.3), k(2) is the repulsive force constant, d is the distance threshold value, and U2(y) is the repulsive potential field information. In particular, k(2) can be used to control the strength of the repulsive potential field. For example, the value of k(2) is positively correlated with the strength of the repulsive potential field. In one embodiment, setting k(2) to a larger value can increase the resistance of the repulsive potential field to the gravitational potential field. In one embodiment, setting k(2) to a smaller value can reduce the resistance of the repulsive potential field to the gravitational potential field. In one embodiment, the value of k(2) can be set based on experience and can be dynamically adjusted. Then, the memory control circuit 23 can obtain the second guide data based on the repulsive potential field information.

[0079] In one embodiment, the memory control circuit 23 can obtain the repulsive field gradient information according to the repulsive potential field information. In particular, the repulsive field gradient information can be used to simulate the gradient of the repulsive potential field. For example, the memory control circuit 23 can obtain the repulsive field gradient information according to the following formulas (2.4) and (2.5).

[0080]

[0081] In formulas (2.4) and (2.5), is the repulsive field gradient information. Then, the memory control circuit 23 may obtain the second guidance data according to the repulsive field gradient information. For example, the second guidance data may include the repulsive field gradient information.

[0082] In one embodiment, the memory control circuit 23 can obtain the synthetic gradient data according to the first guide data and the second guide data. In particular, the synthetic gradient data can be used to simulate the gradient of the synthetic potential field corresponding to the first data, and the synthetic potential field is composed of an attractive potential field and a repulsive potential field. For example, the memory control circuit 23 can obtain the synthetic gradient data according to the following formula (3.1).

[0083]

[0084] In formula (3.1), F(y) represents the synthetic gradient data. Then, the memory control circuit 23 may generate the third guidance data according to the synthetic gradient data. For example, the third guidance data may include the synthetic gradient data.

[0085] In one embodiment, the memory control circuit 23 may obtain a plurality of gradient information corresponding to the plurality of bits in the first data according to the third guide data. The memory control circuit 23 may compare the plurality of gradient information to obtain a comparison result. Then, the memory control circuit 23 may flip at least one of the plurality of bits according to the comparison result.

[0086] In one embodiment, F(y) includes f(1) to f(n) (i.e., gradient information). f(1) to f(n) correspond to the multiple bits in the first data, respectively. For example, f(i) may reflect the gradient corresponding to the i-th bit in the first data. In one embodiment, the memory control circuit 23 may compare f(1) to f(n). Then, the memory control circuit 23 may determine the bit to be flipped in the first data based on the largest one of f(1) to f(n). For example, assuming that the largest one of f(1) to f(n) is f(i), then in the first decoding operation, the decoding circuit 25 may perform a bit flip on the i-th bit in the first data, for example, flipping the i-th bit in the first data from "1" to "0" or from "0" to "1". In addition, the number of bits flipped in each iteration may be one or more, which is not limited by the present invention. It should be noted that all the above formulas can be adjusted according to practical needs, which is not limited by the present invention.

[0087] It should be noted that when selecting the target bit for flipping operation according to the result of each iterative calculation, in extreme cases, the gradient information of all bits may be the same. At this time, if all bits are directly flipped, it may not converge. If no flipping operation is performed, it will obviously be impossible to continue the iteration. Therefore, in actual scenarios, in order to avoid this situation, the following solutions can be adopted:

[0088] 1. Introducing random perturbations: When the resultant force is the same, a small random perturbation can be introduced (i.e., randomly selecting flipping or not flipping) to break the balance, thereby avoiding falling into an infinite loop or flipping all bits. For example: for all the bits of gradient information, randomly select one or a few of them as the target bits to flip.

[0089] This strategy ensures that not too many bits are flipped in one iteration, thus maintaining the process of gradually approaching the target state.

[0090] 2. Selection based on historical information: Record the flipping history of each bit in previous iterations, and combine the current gradient information to determine the flipping order. For example, select the bits that have been flipped less times in the previous iterations.

[0091] This ensures that the selections are more even for each flip, reducing the likelihood of switching back and forth between the same states repeatedly.

[0092] 3. Prioritize the most sensitive bits: By analyzing the impact of each bit on the overall potential field, select the bits that are most sensitive to the potential field change to flip. For example: calculate the local potential field change of each bit, that is, calculate the change brought about by flipping the bit on the overall potential field; give priority to flipping those bits that contribute the most to the potential field change.

[0093] 4. Introduce dynamic adjustment mechanism: Introduce dynamic adjustment mechanism in the flipping strategy, and adjust the flipping strategy according to the change of potential field during iteration. For example, in the early stage of iteration, more bits can be selected for flipping to quickly approach the target state; when close to convergence, reduce the number of flipped bits in each iteration to improve stability and convergence speed.

[0094] Specifically, a single-point flip (or a few flips) strategy can ensure that each state change is relatively small, which helps to gradually approach the target state. A strategy based on history or sensitivity can reduce unnecessary flips and prevent switching back and forth between the same states. A dynamic adjustment strategy can make the algorithm more flexible and can adaptively adjust the flip strategy according to the current state, thereby improving convergence speed and reliability.

[0095] Figure 5 and Figure 6 FIG. 1 is a schematic diagram of multiple iterative decoding of first data according to an embodiment of the present invention. Figure 5 In one embodiment, it is assumed that the codeword in the first data is represented by a vector v. For example, the vector v includes bits b(1) to b(6). For example, the vector v = [b(1), b(2), b(3), b(4), b(5), b(6)].

[0096] In the first iterative decoding of the vector v (i.e., [b(1), b(2), b(3), b(4), b(5), b(6)]), the decoding circuit 25 can obtain the vector x (i.e., the second state information) and the vector y (i.e., the first state information). The vector x can reflect the target states of the bits b(1) to b(6) in the vector v. For example, the vector x = [0, 0, 0, 0, 0, 0]. In addition, the vector y can reflect the current states of the bits b(1) to b(6) in the vector v. For example, the vector y = [1, 0, 1, 0, 1, 1].

[0097] In one embodiment, the memory control circuit 23 may obtain the vector g(1) (i.e., the first guidance information) according to formulas (1.1) to (1.3), and obtain the vector g(2) (i.e., the second guidance information) according to formulas (2.1) to (2.5). Then, the memory control circuit 23 may obtain the vector g(3) (i.e., the third guidance information) according to the vectors g(1) and g(2). According to the third guidance information, the memory control circuit 23 (or the decoding circuit 25) may bit-flip the bits b(1) and b(3) in the vector v. For example, the memory control circuit 23 (or the decoding circuit 25) may flip the bits b(1) and b(3) in the vector v to b(1)' and b(3)', respectively. At this point, the result of the first iterative decoding of the vector v is to update the vector v to [b(1)', b(2), b(3)', b(4), b(5), b(6)].

[0098] Based on the updated vector v, the decoding circuit 25 can obtain the updated vector y (i.e., y(1)). For example, vector y(1)=[0, 0, 0, 0, 1, 1]. Compared with vector y, vector y(1) reflects that the bits b(1) and b(3) in vector v that were originally error bits have been corrected (i.e., bits b(1) to b(4) in vector v are not error bits). However, vector y(1) is different from vector x. Therefore, the memory control circuit 23 and the decoding circuit 25 can perform a second iterative decoding on vector v.

[0099] Please refer to Figure 6 , continued by Figure 5 In the second iterative decoding of the vector v (i.e., [b(1)', b(2), b(3)', b(4), b(5), b(6)]), the memory control circuit 23 may again obtain the vector g(1) (i.e., the first guidance information) according to formulas (1.1) to (1.3), and obtain the vector g(2) (i.e., the second guidance information) according to formulas (2.1) to (2.5). Then, the memory control circuit 23 may obtain the vector g(3) (i.e., the third guidance information) according to the vectors g(1) and g(2). According to the third guidance information, the memory control circuit 23 (or the decoding circuit 25) may bit-flip the bits b(5) and b(6) in the vector v. For example, the memory control circuit 23 (or the decoding circuit 25) may flip the bits b(5) and b(6) in the vector v to b(5)' and b(6)', respectively. At this time, the result of the second iterative decoding of the vector v is that the vector v is updated to [b(1)', b(2), b(3)', b(4), b(5)', b(6)'].

[0100] Based on the updated vector v, the decoding circuit 25 can obtain the updated vector y (i.e., y(2)). For example, vector y(2) = [0, 0, 0, 0, 0, 0]. Compared with vector y(1), vector y(2) reflects that bits b(5) and b(6) in vector v, which were originally error bits, have been corrected (i.e., bits b(1) to b(6) in vector v are not error bits). At this point, vector y(2) is the same as vector x. Therefore, the memory control circuit 23 and the decoding circuit 25 can determine that the decoding of the first data (i.e., vector v) is successful and output the decoded first data.

[0101] Figure 7 and Figure 8 FIG. 1 is a schematic diagram of force field information used to guide bit flipping in a decoding operation according to an embodiment of the present invention. Figure 7 , curves 71, 72 and 73 can be presented respectively, Figure 5 In the embodiment, vector g(1) (i.e., the first guide information), vector g(2) (i.e., the second guide information) and vector g(3) (i.e., the third guide information) respectively correspond to the force field information of multiple bits b(1) to b(6) in the first data (i.e., vector v).

[0102] Specifically, the force field information presented by curve 71 is used to simulate the gravitational potential field that pulls bits b(1) to b(6) from the current state to the target state. The force field information presented by curve 72 is used to simulate the repulsive potential field that resists pulling bits b(1) to b(6) from the current state to the target state. In addition, the force field information presented by curve 73 is used to simulate the composite force potential field formed by the gravitational potential field and the repulsive potential field. According to the extreme value position of curve 73, bits b(1) and b(3) in the first data (i.e., vector v) can be flipped.

[0103] Please refer to Figure 8 , curves 81, 82 and 83 can be presented respectively, Figure 6 In the embodiment, vector g(1) (i.e., the first guidance information), vector g(2) (i.e., the second guidance information) and vector g(3) (i.e., the third guidance information) respectively correspond to the force field information of multiple bits b(1)', b(2), b(3)', b(4) to b(6) in the first data (i.e., vector v).

[0104] Specifically, the force field information presented by curve 81 is used to simulate the gravitational potential field that pulls bits b(1)', b(2), b(3)', b(4)~b(6) from the current state to the target state. The force field information presented by curve 82 is used to simulate the repulsive potential field that resists pulling bits b(1)', b(2), b(3)', b(4)~b(6) from the current state to the target state. In addition, the force field information presented by curve 83 is used to simulate the composite force potential field formed by the gravitational potential field and the repulsive potential field. According to the extreme value position of curve 83, bits b(5) and b(6) in the first data (i.e., vector v) can be flipped.

[0105] It should be noted that for Figure 5 In the embodiment, if the traditional bit flipping algorithm is used to determine the bit to be flipped in each iteration, it may be necessary to perform four or more iterative decoding to completely correct all errors in the first data (i.e., vector v). Figure 5 and Figure 6 (with Figure 7 and Figure 8 ), as long as two iterations of decoding are performed, all errors in the first data (i.e., vector v) can be completely corrected. Thus, the decoding efficiency of the decoding operation for the read data can be effectively improved without increasing the complexity of the decoding operation as much as possible.

[0106] Fig. 9 is a flowchart of a decoding method according to an embodiment of the present invention. Fig. 9 The steps shown are as follows:

[0107] In step S901, first data is read from a first physical unit, wherein the first data includes a plurality of bits.

[0108] In step S902, a decoding operation is performed on the first data to obtain first pilot data and second pilot data, wherein the first pilot data reflects (or provides) an attraction force for bit flipping the plurality of bits, and the second pilot data reflects (or provides) a repulsive force for bit flipping the plurality of bits.

[0109] In step S903 , third boot data is generated according to the first boot data and the second boot data.

[0110] In step S904, bit flipping is performed on at least one of the plurality of bits according to the third boot data.

[0111] However, Fig. 9 The steps in the above are described in detail, so I will not repeat them here. It is worth noting that Fig. 9 Each step in the above process can be implemented as multiple program codes or circuits, and the present invention is not limited thereto. Fig. 9 The method can be used in conjunction with the above exemplary embodiments or can be used alone, and the present invention is not limited thereto.

[0112] In summary, the decoding method and storage device proposed in the embodiment of the present invention can simulate the pull between the attraction and repulsion for each bit in the data to be decoded. In particular, the attraction is used to pull each bit in the data to be decoded to the target state of decoding, and the repulsion is used to resist pulling each bit in the data to be decoded to the target state. According to the simulation results of the attraction and repulsion, at least part of the bits in the data to be decoded can be flipped. In this way, the decoding efficiency of the decoding operation for the read data can be effectively improved without increasing the complexity of the decoding operation as much as possible.

[0113] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or replace some or all of the technical features therein with equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A decoding method, characterized in that: For a storage device, the decoding method comprises: reading first data, wherein the first data includes a plurality of bits; Performing a first decoding operation on the first data to obtain first pilot data and second pilot data, wherein the first pilot data reflects an attractive force for performing a bit flip on each of the bits, and the second pilot data reflects a repulsive force for performing the bit flip on each of the bits; generating third boot data according to the first boot data and the second boot data; and According to the third guide data, performing the bit flipping on at least one of the plurality of bits to obtain a flipping result; and A second decoding operation is performed on the flipped result.

2. The decoding method according to claim 1, wherein the attractive force is used to increase the probability of performing the bit flip on at least one of the multiple bits, and the repulsive force is used to reduce the probability of performing the bit flip on at least one of the multiple bits.

3. The decoding method according to claim 1, wherein the step of performing the first decoding operation on the first data to obtain the first boot data comprises: Determine first state information according to the first data, wherein the first state information reflects a current state of the plurality of bits; Acquire first distance information according to the first state information and the target state information, wherein the target state information is used to reflect the target state that the flip result is expected to eventually reach, and the first distance information reflects the Euclidean distance between the current state and the target state; as well as The first guide data is obtained according to the first distance information.

4. The decoding method according to claim 3, wherein the step of obtaining the first guide data according to the first distance information comprises: Obtaining gravitational potential field information corresponding to the first data according to the first distance information, wherein the gravitational potential field information is used to simulate a gravitational potential field for flipping the plurality of bits from the current state to the target state; and The first guidance data is obtained according to the gravitational potential field information.

5. The decoding method according to claim 4, wherein the step of obtaining the first guidance data according to the gravitational potential field information comprises: Obtaining gravitational field gradient information according to the gravitational potential field information, wherein the gravitational field gradient information is used to simulate the gradient of the gravitational potential field; as well as The first guidance data is obtained according to the gravitational field gradient information.

6. The decoding method according to claim 1, wherein the step of performing the first decoding operation on the first data to obtain the second boot data comprises: Obtaining first state information of the plurality of bits, wherein the first state information reflects current states of the plurality of bits; Obtaining third state information of the plurality of bits, wherein the third state information reflects an exclusion state of the plurality of bits; acquiring second distance information according to the first state information and the third state information, wherein the second distance information reflects the Euclidean distance between the current state and the exclusion state; as well as The second guide data is obtained according to the second distance information.

7. The decoding method according to claim 6, wherein the step of obtaining the second guide data according to the second distance information comprises: Obtaining repulsive potential field information corresponding to the first data according to the second distance information, wherein the repulsive potential field information is used to simulate a repulsive potential field used to resist pulling the plurality of bits from the current state to a target state; and The second guidance data is obtained according to the repulsive potential field information.

8. The decoding method according to claim 7, wherein the step of obtaining the second guidance data according to the repulsive potential field information comprises: According to the repulsive potential field information, obtaining repulsive field gradient information, wherein the repulsive field gradient information is used to simulate the gradient of the repulsive potential field; as well as The second guidance data is obtained according to the repulsive field gradient information.

9. The decoding method according to claim 1, wherein the step of generating the third boot data according to the first boot data and the second boot data comprises: Obtaining synthetic gradient data according to the first guide data and the second guide data, wherein the synthetic gradient data is used to simulate a gradient of a synthetic potential field corresponding to the first data, and the synthetic potential field is composed of an attractive potential field and a repulsive potential field; and The third guide data is generated according to the synthetic gradient data.

10. The decoding method according to claim 1, wherein the step of performing the bit flipping on the at least one of the plurality of bits according to the third guide data comprises: According to the third guide data, obtaining a plurality of gradient information respectively corresponding to the plurality of bits; Comparing the plurality of gradient information to obtain a comparison result; as well as According to the comparison result, at least one of the plurality of bits is flipped.

11. A storage device, characterized in that: include: A connection interface for connecting to a host system; Memory module; as well as a memory controller connected to the connection interface and the memory module, The memory controller is used to: reading first data from the memory module, wherein the first data comprises a plurality of bits; Performing a first decoding operation on the first data to obtain first pilot data and second pilot data, wherein the first pilot data reflects an attractive force for performing a bit flip on each of the bits, and the second pilot data reflects a repulsive force for performing the bit flip on each of the bits; generating third boot data according to the first boot data and the second boot data; According to the third guide data, performing the bit flipping on at least one of the plurality of bits to obtain a flipping result; as well as A second decoding operation is performed on the flipped result.

12. The storage device according to claim 11, wherein the attractive force is used to increase the probability of performing the bit flip on at least one of the plurality of bits, and the repulsive force is used to reduce the probability of performing the bit flip on the at least one of the plurality of bits.

13. The storage device according to claim 11, wherein the memory controller performs the first decoding operation on the first data to obtain the first boot data comprises: Determine first state information according to the first data, wherein the first state information reflects a current state of the plurality of bits; Acquire first distance information according to the first state information and the target state information, wherein the target state information is used to reflect the target state that the flip result is expected to eventually reach, and the first distance information reflects the Euclidean distance between the current state and the target state; as well as The first guide data is obtained according to the first distance information.

14. The storage device according to claim 13, wherein the operation of the memory controller obtaining the first boot data according to the first distance information comprises: Obtaining gravitational potential field information corresponding to the first data according to the first distance information, wherein the gravitational potential field information is used to simulate a gravitational potential field for flipping the plurality of bits from the current state to the target state; and The first guidance data is obtained according to the gravitational potential field information.

15. The storage device according to claim 14, wherein the operation of the memory controller obtaining the first boot data according to the gravitational potential field information comprises: Obtaining gravitational field gradient information according to the gravitational potential field information, wherein the gravitational field gradient information is used to simulate the gradient of the gravitational potential field; as well as The first guidance data is obtained according to the gravitational field gradient information.

16. The storage device according to claim 11, wherein the memory controller performs the first decoding operation on the first data to obtain the second boot data comprises: Obtaining first state information of the plurality of bits, wherein the first state information reflects current states of the plurality of bits; Obtaining third state information of the plurality of bits, wherein the third state information reflects an exclusion state of the plurality of bits; acquiring second distance information according to the first state information and the third state information, wherein the second distance information reflects the Euclidean distance between the current state and the exclusion state; as well as The second guide data is obtained according to the second distance information.

17. The storage device according to claim 16, wherein the operation of the memory controller obtaining the second boot data according to the second distance information comprises: Obtaining repulsive potential field information corresponding to the first data according to the second distance information, wherein the repulsive potential field information is used to simulate a repulsive potential field used to resist pulling the plurality of bits from the current state to a target state; and The second guidance data is obtained according to the repulsive potential field information.

18. The storage device according to claim 17, wherein the operation of the memory controller obtaining the second boot data according to the repulsive potential field information comprises: According to the repulsive potential field information, obtaining repulsive field gradient information, wherein the repulsive field gradient information is used to simulate the gradient of the repulsive potential field; as well as The second guidance data is obtained according to the repulsive field gradient information.

19. The storage device according to claim 11, wherein the operation of the memory controller generating the third boot data according to the first boot data and the second boot data comprises: Obtaining synthetic gradient data according to the first guide data and the second guide data, wherein the synthetic gradient data is used to simulate a gradient of a synthetic potential field corresponding to the first data, and the synthetic potential field is composed of an attractive potential field and a repulsive potential field; and The third guide data is generated according to the synthetic gradient data.

20. The storage device according to claim 11, wherein the memory controller performs the bit flipping operation on the at least one of the plurality of bits according to the third boot data, comprising: According to the third guide data, obtaining a plurality of gradient information respectively corresponding to the plurality of bits; Comparing the plurality of gradient information to obtain a comparison result; as well as According to the comparison result, at least one of the plurality of bits is flipped.

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