Flash memory testing method and device, electronic equipment and storage medium

Abstract

This invention provides a Flash memory testing method, apparatus, electronic device, and storage medium, relating to the field of testing technology. The method includes: writing first test data into the Flash memory using data read / write software on a host computer; reading first stored data from the Flash memory using the data read / write software, verifying the writing status of the first test data based on the first stored data, obtaining a write verification result, and controlling a relay to disconnect when the data is successfully written; controlling the relay to close after a first preset time, reading second stored data from the Flash memory using the data read / write software, verifying the reading status of the first test data based on the second stored data, obtaining a read verification result; repeating the above steps multiple times, and evaluating the read / write stability of the Flash memory based on the obtained multiple write verification results and read verification results, thereby achieving low-cost Flash memory read / write stability testing.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of testing, in particular to a Flash memory testing method and device, electronic equipment and storage medium. BACKGROUND

[0002] Flash memory is widely used in many fields due to its long service life, high reliability and fast reading performance, especially in the field of medical devices. As a key storage medium of electronic equipment, Flash memory carries the core program and parameters that control the operation of the equipment. During the startup phase of the equipment, these programs and parameters stored in the Flash memory must be accurately read to ensure the accurate execution of the equipment functions. However, in actual applications, incomplete chip initialization or program defects at power-on may affect the correct reading of parameters, thereby posing a potential threat to the safety of medical operations.

[0003] To solve these problems, an automatic test system is usually used to test the read-write stability of Flash memory. The power-on and power-off processes of the equipment are controlled by a program-controlled power supply to improve the accuracy and efficiency of parameter reading. However, this method has obvious limitations: using a program-controlled power supply to control the power-on and power-off of the equipment not only significantly increases the cost of the equipment, but also increases the complexity of the system. SUMMARY

[0004] The problem solved by the present application is how to implement low-cost read-write stability testing of Flash memory.

[0005] To solve the above problems, the present application provides a Flash memory testing method, device, electronic equipment and storage medium.

[0006] In a first aspect, the present application provides a Flash memory testing method based on a test system, the test system comprising a host computer, a single-chip microcomputer, a relay and a power supply, the host computer being in communication connection with the single-chip microcomputer, the single-chip microcomputer being connected with the relay, the relay being used to control the power supply to supply power to the Flash memory, the Flash memory testing method comprising:

[0007] S100: writing first test data into the Flash memory through data reading and writing software of the host computer;

[0008] S200: reading first storage data in the Flash memory through the data reading and writing software, verifying the writing of the first test data according to the first storage data, and obtaining a writing verification result, when the writing verification result is data writing success, controlling the relay to be disconnected to stop the power supply to supply power to the Flash memory;

[0009] S300: after the first preset time, the relay is controlled to be closed, so that the power supply continues to supply power to the Flash memory, the second storage data in the Flash memory is read through the data read-write software, and the reading of the first test data is verified according to the second storage data, and a reading verification result is obtained;

[0010] S400: S100 to S300 are cycled multiple times, and the read-write stability of the Flash memory is evaluated according to the obtained multiple write verification results and reading verification results.

[0011] Optionally, the verification of the writing of the first test data according to the first storage data to obtain a write verification result comprises:

[0012] determining whether the first test data is equal to the first storage data;

[0013] when the first test data is equal to the first storage data, the write verification result is data writing success;

[0014] when the first test data is not equal to the first storage data, the write verification result is data writing failure, the write failure number is increased by one, and S100 is returned to be executed.

[0015] Optionally, the verification of the reading of the first test data according to the second storage data to obtain a reading verification result comprises:

[0016] when the first test data is equal to the second storage data, the reading verification result is data reading success, and the cycle number is increased by one;

[0017] when the first test data is not equal to the second storage data, the reading verification result is data reading failure, the cycle number is increased by one and the read failure number is increased by one.

[0018] Optionally, in the process of cycling S100 to S300, the first test data adopted in each cycle process is not the same.

[0019] Optionally, the cycling S100 to S300 multiple times, and the read-write stability of the Flash memory is evaluated according to the obtained multiple write verification results and reading verification results, comprises:

[0020] when the cycle number is equal to or greater than a preset number, output the write failure number, the read failure number and the cycle number;

[0021] the ratio of the write failure number to the cycle number is determined as a first coefficient;

[0022] The ratio of the number of read failures to the number of loop iterations is determined as the second coefficient;

[0023] The read / write stability of the Flash memory is evaluated based on the first and second coefficients.

[0024] Optionally, the evaluation of the read / write stability of the Flash memory based on the first coefficient and the second coefficient includes:

[0025] When the first coefficient is greater than the first preset threshold, it is determined that the Flash memory has a write stability problem;

[0026] When the second coefficient is greater than the second preset threshold, it is determined that the Flash memory has a read stability problem.

[0027] Optionally, the Flash memory testing method further includes:

[0028] When the first test data is not equal to the first stored data or the first test data is not equal to the second stored data, an exception handling mechanism is triggered and execution returns to S100, wherein the exception handling mechanism includes at least one of data backup, memory replacement and system restart;

[0029] The data backup includes backing up the first test data to other storage media;

[0030] The memory replacement includes replacing the original Flash memory with a spare Flash memory;

[0031] The system restart includes restarting the electronic device to restore the Flash memory to a stable state.

[0032] Secondly, the present invention provides a Flash memory testing device based on a testing system, the testing system including a host computer, a microcontroller, a relay, and a power supply. The host computer is communicatively connected to the microcontroller, the microcontroller is connected to the relay, and the relay is used to control the power supply to the Flash memory. The Flash memory testing device includes:

[0033] The acquisition module is used to write the first test data into the Flash memory through the data reading and writing software of the host computer;

[0034] The write verification module is used to read the first stored data in the Flash memory through the data read and write software, verify the writing status of the first test data based on the first stored data, and obtain the write verification result. When the write verification result is that the data is successfully written, the module controls the relay to disconnect so that the power supply stops supplying power to the Flash memory.

[0035] The read verification module is used to control the relay to close after a first preset time so that the power supply continues to supply power to the Flash memory, read the second stored data in the Flash memory through the data read and write software, verify the reading of the first test data based on the second stored data, and obtain the read verification result.

[0036] An evaluation module is used to cycle through the acquisition module to the read verification module multiple times, and evaluate the read and write stability of the Flash memory based on the multiple write verification results and read verification results obtained.

[0037] Thirdly, the present invention provides an electronic device, including a memory and a processor;

[0038] The memory is used to store computer programs;

[0039] The processor is configured to implement the Flash memory testing method as described in the first aspect when executing the computer program.

[0040] Fourthly, the present invention provides a computer-readable storage medium storing a computer program that, when executed by a processor, implements the Flash memory testing method as described in the first aspect.

[0041] The flash memory testing method, device, electronic equipment and storage medium have the following beneficial effects: the first test data is written into the flash memory by the data reading and writing software, and the first test data is backed up at the same time, thereby providing data support for the subsequent verification process. Then, the first storage data (i.e., the first test data stored in the flash memory after the writing operation) in the flash memory is read, and it is verified whether the written data is correct, thereby ensuring the integrity and accuracy of the data. When the written data is correct, the power supply of the flash memory is cut off by the relay controlled by the communication with the single-chip microcomputer, so that the flash memory enters the power-off state. After waiting for a first preset time, the power supply of the flash memory is restored by the relay controlled by the communication with the single-chip microcomputer, so that the flash memory is powered on again, thereby avoiding the use of a program-controlled power supply, and thus reducing the cost of flash memory testing. In addition, since the program-controlled power supply needs not only a complex software program, but also high-power components such as a conducting diode, a switch and a relay, the system complexity can be significantly reduced by not using the program-controlled power supply. Subsequently, the second storage data (i.e., the first test data stored in the flash memory after the writing operation) in the flash memory is read by the same data reading and writing software, and it is verified whether the read data is correct, thereby ensuring the integrity and accuracy of the data after the power-off and power-on processing. Whether the correctness of the flash memory writing is verified or the correctness of the flash memory reading is verified, the data comparison is directly performed, so that the errors (such as data damage or loss) that may occur in the data reading process can be found and located in time, the data verification process is simplified, a complex detection mechanism is not needed, and the development and implementation difficulty and cost are reduced. By cyclically performing the above writing and reading operations and evaluating the flash memory reading and writing stability according to the results of multiple verifications, the stability and durability of the flash memory under long-time and multiple operations can be comprehensively evaluated, the electronic equipment can maintain high reliability and safety in various situations, the cost of testing the flash memory can be saved, and the complexity of the flash memory testing process is reduced. BRIEF DESCRIPTION OF DRAWINGS

[0042] Figure 1 A principle schematic diagram of a flash memory testing device according to an embodiment of the present application;

[0043] Figure 2 A flowchart of a flash memory testing method according to an embodiment of the present application;

[0044] Figure 3 A specific flowchart of a flash memory testing method according to an embodiment of the present application;

[0045] Figure 4A system architecture diagram of a Flash memory testing device according to an embodiment of the present application;

[0046] Figure 5 A system architecture diagram of an electronic device according to an embodiment of the present application. DETAILED DESCRIPTION

[0047] In order to make the above objectives, features and advantages of the present application more clear and comprehensible, specific embodiments of the present application will be described in detail below with reference to the accompanying drawings. Although some embodiments of the present application are shown in the drawings, it should be understood that the present application can be implemented in various forms, and should not be interpreted as being limited to the embodiments set forth herein, but rather, these embodiments are provided so as to make the present application more thorough and complete. It should be understood that the drawings and embodiments of the present application are merely for illustrative purposes, and are not intended to limit the scope of protection of the present application.

[0048] It should be understood that each of the steps recited in the method embodiments of the present application can be executed in different orders, and / or in parallel. In addition, the method embodiments can include additional steps and / or omit the execution of the steps shown. The scope of the present application is not limited in this respect.

[0049] As used herein, the term "comprises" and its variations are open-ended, meaning "includes but not limited to"; the term "based on" is "based, at least in part, on"; the term "one embodiment" means "at least one embodiment"; the term "another embodiment" means "at least one additional embodiment"; the term "some embodiments" means "at least some embodiments"; the term "optionally" means "optional embodiments". Related definitions will be given in the description below. It should be noted that the concepts of "first", "second", etc. mentioned in the present application are merely used to distinguish different devices, modules or units, and are not intended to limit the order or interdependence of the functions performed by these devices, modules or units.

[0050] It should be noted that the modification of "one" or "multiple" mentioned in the present application is illustrative rather than limiting, and those skilled in the art should understand that, unless otherwise explicitly indicated in the context, it should be understood as "one or more".

[0051] The names of the messages or information exchanged between the multiple devices in the embodiments of the present application are merely for illustrative purposes, and are not intended to limit the scope of these messages or information.

[0052] In the related art, Flash memory testing is performed using an automated testing system, and these systems control the power-on and power-off processes of the device through program-controlled power supply to improve the accuracy and efficiency of parameter reading. However, this method has obvious limitations:

[0053] Firstly, the program-controlled power control device requires additional hardware and software support, including precision power management chips, control circuits, and related interfaces and communication protocols. The introduction of these components significantly increases hardware costs. In addition, to achieve precise power control, some advanced functions such as overcurrent protection and overvoltage protection may also need to be added, which will further increase costs.

[0054] Secondly, the introduction of the program-controlled power control device makes the system design more complex. On the one hand, the power control algorithm needs to be designed and implemented, involving real-time monitoring and adjustment of parameters such as voltage and current; on the other hand, it is also necessary to ensure the coordination of power control with other parts of the system (such as data reading and writing, error correction, etc.) to ensure the stability and reliability of the system. These requirements increase the workload of design and testing, and increase the complexity of the system.

[0055] In addition, due to the complexity of the program-controlled power control device, its maintenance and debugging also become more difficult. Any power control-related failures may require professional technical support to solve, not only increasing maintenance costs, but also potentially causing extended system downtime.

[0056] To solve the problems in the related art, the embodiment provides a Flash memory test method and device, electronic equipment and storage medium.

[0057] As shown in Figure 1 The Flash memory test method provided by the embodiment of the application is based on a test system, the test system includes a host computer, a single-chip microcomputer, a relay and a power supply, the host computer is in communication connection with the single-chip microcomputer, the single-chip microcomputer is connected with the relay, the relay is used for controlling the power supply of the Flash memory, and the Flash memory test method is as shown in Figure 2 The Flash memory test method includes the following steps:

[0058] S100: write first test data into the Flash memory through the data reading and writing software of the host computer;

[0059] It should be noted that the host computer includes Python software and data reading and writing software, and the Python software and the data reading and writing software communicate with each other through the Automation Device Specification (ADS) protocol. Therefore, by writing a Python program, the data reading and writing software can be controlled to perform write and read operations on the Flash memory.

[0060] The ADS protocol is used to achieve efficient data exchange between the host computer and the lower computer (such as PLC), and is widely used in the TwinCAT automation software platform. Through the ADS protocol, the host computer can communicate seamlessly with the data reading and writing software, realizing monitoring, control and data reading of the device, etc. In practical applications, the ADS protocol is usually combined with the EtherCAT bus to realize high-speed and real-time data transmission. This combination not only improves the speed of data transmission, but also ensures the accuracy and reliability of data. For example, in the "Carpet tufting machine host computer software design based on ADS communication" project, the ADS protocol is used to realize communication between the carpet tufting machine host computer and the lower computer. Through the TwinCAT system architecture, the ADS protocol makes information transmission faster and more stable, significantly improving the performance and response speed of the entire system.

[0061] Specifically, the host computer sends the first test data to the data reading and writing software, and writes the first test data into the Flash memory through the Ethernet for Control Automation Technology (EtherCAT) communication of the data reading and writing software. At the same time, the host computer will save the first test data in the form of a file on the hard disk or solid state disk, or save it in a database such as SQLite, MySQL, etc. The first test data saved on the host computer serves as a reference benchmark for subsequent data verification processes, ensuring that the data written and read from the Flash memory is completely consistent with the original data.

[0062] Among them, the first test data is a set of data defined in advance for testing the Flash memory, aiming to comprehensively evaluate its performance and reliability under various conditions. These data can be randomly generated, or specific patterns or sequences, to cover various possible data types and formats. For example, randomly generated data can be used to detect the processing capability of the Flash memory for unordered data, ensuring that each byte can be correctly written and read. While specific patterns or sequences can be used to detect specific types of errors. Common specific patterns include all 0s (e.g. 0x00 0x00 0x00...), all 1s (e.g. 0xFF 0xFF 0xFF...) and alternating 01s (e.g. 0x00 0xFF 0x00 0xFF...). These patterns can help detect bit flip errors, adjacent bit interference and other hardware failures in the Flash memory.

[0063] In addition, EtherCAT is an Ethernet-based industrial fieldbus technology designed to provide a high-speed, low-latency, synchronized, and deterministic communication method for industrial automation applications that require real-time control and data exchange. The core advantage of EtherCAT is its extremely high real-time and synchronization. EtherCAT achieves efficient data transmission through the "fly read and fly write" technology. This technology allows direct insertion and extraction of data as the data frame passes, rather than using the traditional store-and-forward method, thereby significantly reducing transmission delay.

[0064] S200: reading the first storage data in the Flash memory through the data read-write software, verifying the writing situation of the first test data according to the first storage data, obtaining a writing verification result, and when the writing verification result is data writing success, controlling the relay to be disconnected to stop the power supply to the Flash memory;

[0065] Specifically, in the previous step, the data read-write software has written the first test data into the Flash memory. Now the host computer wants to verify the writing situation by obtaining these first test data. To this end, the host computer sends a request to the data read-write software through the ADS protocol. After receiving the request, the data read-write software reads the first storage data (the first test data written in the previous step) from the Flash memory through EtherCAT communication. Subsequently, the read first storage data is verified by the first test data backed up in the host computer. If the host computer obtains a writing failure verification result, it means that the data read operation fails, which may be due to hardware failure, software error or other reasons causing data corruption or loss. On the contrary, if the host computer obtains a writing success verification result, it means that the data read operation is successful and no error occurs. In this case, an instruction is sent to the single-chip microcomputer through serial communication to control the IO port of the single-chip microcomputer to disconnect the relay, thereby cutting off the power supply of the Flash memory and making it enter the power-down state, as shown in Figure 1

[0066] Among them, the hardware failure includes the damage of the Flash memory chip, power fluctuation or signal interference. The software error includes the logic error or communication protocol problem in the data read-write software. Other reasons include electromagnetic interference, unstable power supply and other external factors. Data corruption means that the data is damaged due to some external influence during the writing or reading process. Data loss means that part of the data is lost during transmission, resulting in incomplete read data.

[0067] ​S300: After the first preset time, control the relay to close, so that the power supply continues to power the Flash memory, read the second stored data in the Flash memory through the data read-write software, verify the reading of the first test data according to the second stored data, and obtain the reading verification result;

[0068] Specifically, after power failure, a predetermined time (i.e. the first preset time) is waited to ensure that the Flash memory is completely powered off and in a stable state. Subsequently, instructions are sent to the single-chip microcomputer through serial communication to control the relay to close, thereby restoring the power supply of the Flash memory and re-powering it, as shown in Figure 1 Then, the data read-write software is used to read the second stored data (the first test data written after power down and power up) from the Flash memory, and these data are compared with the first test data backed up in the upper computer to verify the correctness of the reading operation. Finally, the reading verification result is obtained according to the comparison result to confirm whether the data is complete and accurate. This process simulates the power failure that the Flash memory may encounter in actual use, aiming to detect its data retention capability and stability after power failure.

[0069] The first preset time can be set to 5S or 10S, which is suitable for simulating short power failure, such as transient power interruption or rapid restart. The first preset time can also be set to 120S or 360S to simulate longer power failure, such as restarting after device shutdown or long power outage. By setting different power failure times, various situations in actual application can be simulated more comprehensively, the data retention capability of the Flash memory in different time periods can be evaluated, and its reliability and durability in various power failure situations can be verified to ensure that its performance in actual application meets expectations.

[0070] In addition, the power up and down of the Flash memory is realized by the single-chip microcomputer controlling the opening and closing of the relay, which can simulate the power on and off in actual use, helping to detect the data storage capability of the Flash memory after re-powering. Specifically: in terms of hardware selection, commonly used single-chip microcomputers (such as Arduino, STM32, etc.) and relay modules on the market are used, which have relatively low cost. In terms of hardware design, the relay can be controlled by sending simple instructions through serial communication without complex hardware design. In terms of first preset time setting, a simple delay function or timer can be used to realize it without additional hardware support. Therefore, the power up and down of the Flash memory realized by the single-chip microcomputer controlling the opening and closing of the relay not only simplifies the system design, but also significantly reduces the cost of Flash memory testing.

[0071] S400: Circulate S100-S300 multiple times, and evaluate the read-write stability of the Flash memory according to the obtained multiple write verification results and read verification results.

[0072] Specifically, the above-mentioned write and read operations are repeatedly executed multiple times. Each cycle records the verification results of writing and reading, including success and failure cases. According to the results of multiple verifications, the stability of the Flash memory can be comprehensively evaluated. If the number of failure cases is more than that of success cases, it indicates that the stability of the Flash memory is poor. In this case, the causes of failure (such as hardware failure, software error or environmental factors) can be analyzed in detail to identify and repair existing problems, thereby significantly improving the overall quality and reliability of the Flash memory. If the number of failure cases is less than that of success cases, it indicates that the stability of the Flash memory is good. In this case, it can be ensured that the Flash memory meets the needs and expectations of customers, especially in high-reliability applications such as medical devices and industrial automation systems. Stable Flash memory not only provides reliable performance, but also enhances user trust and satisfaction.

[0073] In the embodiment, the first test data is written into the Flash memory by the data reading and writing software, and the first test data is backed up at the same time, so as to provide data support for the subsequent verification process. Then, the first storage data (i.e. the first test data stored in the Flash memory after the writing operation) in the Flash memory is read, and it is verified whether the written data is correct, so as to ensure the integrity and accuracy of the data. When the written data is correct, the power supply of the Flash memory is cut off by the relay controlled by the communication with the single-chip microcomputer, so that the Flash memory enters the power-off state. After waiting for a first preset time, the power supply of the Flash memory is restored by the relay controlled by the communication with the single-chip microcomputer, so that the Flash memory is powered on again, thereby avoiding the use of the program-controlled power supply, and thus reducing the cost of the Flash memory test. In addition, since the program-controlled power supply not only needs a complex software program, but also needs high-power components such as diodes, switches and relays, the use of the program-controlled power supply can also significantly reduce the complexity of the system. Subsequently, the second storage data (i.e. the first test data stored in the Flash memory after the writing operation) in the Flash memory is read by the same data reading and writing software, and it is verified whether the read data is correct, so as to ensure the integrity and accuracy of the data after the power-off and power-on processing. Whether it is to verify the correctness of the Flash memory writing or to verify the correctness of the reading, it is directly compared with the data, which not only can find and locate the possible errors (such as data damage or loss) in the data reading process in time, but also simplifies the data checking process, without the need for a complex detection mechanism, thereby reducing the difficulty and cost of development and implementation. By cyclically executing the above writing and reading operations, and evaluating the Flash memory reading and writing stability according to the results of multiple verifications, the stability and durability of the Flash memory under long-time and multiple operations can be comprehensively evaluated, so as to ensure that the electronic equipment can maintain high reliability and safety under various conditions, and the cost of testing the Flash memory can be saved, and the complexity of the Flash memory test process can be reduced.

[0074] Optionally, as shown in Figure 3 the first test data is equal to the first storage data, the writing verification result is that the data writing is successful;

[0075] the first test data is equal to the first storage data, the writing verification result is that the data writing is successful;

[0076] the first test data is equal to the first storage data, the writing verification result is that the data writing is successful;

[0077] the first test data is equal to the first storage data, the writing verification result is that the data writing is successful;

[0078] Specifically, after the write operation is completed, the first storage data (the first test data written in the previous step) is read from the Flash memory and compared with the first test data backed up in the host computer. If the read first storage data is consistent with the first test data backed up in the host computer, it indicates that the written first test data is correct, and the read operation can be further performed, i.e., the second storage data in the Flash memory after the power-off and power-on processing is read through the data read-write software, and the read second storage data is verified according to the first test data backed up in the host computer. If the read first storage data is inconsistent with the first test data backed up in the host computer, it indicates that the written first test data is incorrect, and the Flash memory may have a fault or data damage. At this time, the write failure number (the write failure number plus one) is updated and recorded in the host computer. Then, the write operation is performed again, i.e., the new first test data is written into the Flash memory through the data read-write software.

[0079] In the optional embodiment, by comparing the read first storage data with the first test data backed up in the host computer, it can be ensured that the written data is completely consistent with the expected data, which helps to detect and correct errors in the write process and ensures the integrity and accuracy of the data. When the write operation is successful, the subsequent Flash memory test is performed. When the write operation fails, the write failure number (the write failure number plus one) is updated and recorded in the host computer, which facilitates subsequent fault diagnosis and evaluation of the Flash memory. Then, the write operation is performed again, which ensures that even in the case of first write failure, the system can try multiple times of writing to overcome temporary write errors and improve the probability of successful writing. The data write verification process is implemented through a simple program, which does not require complex hardware configuration, reduces manual intervention, and is conducive to realizing the low-cost Flash memory read-write stability test.

[0080] Optionally, as shown in Figure 3 the read verification result is obtained by verifying the reading of the first test data according to the second storage data, including:

[0081] When the first test data is equal to the second storage data, the read verification result is data reading success, and the cycle number is increased by one;

[0082] When the first test data is not equal to the second storage data, the read verification result is data reading failure, the cycle number is increased by one, and the read failure number is increased by one.

[0083] Specifically, if the second storage data read from the Flash memory which has experienced the power-on and power-off process is completely consistent with the first test data backed up in the host computer, it indicates that the read data is correct, and the read operation is successful. At this time, the verification result of successful reading is obtained, and the cycle number is updated (the cycle number is incremented by one) and recorded in the host computer. If the second storage data read from the Flash memory which has experienced the power-on and power-off process is not the same as the first test data backed up in the host computer, it indicates that the first test data read is incorrect, and the read operation fails. At this time, the verification result of failed reading is obtained, and the cycle number and the read failure number are updated (the cycle number is incremented by one, and the read failure number is incremented by one), and recorded in the host computer.

[0084] In this optional embodiment, by comparing the consistency of the second storage data read from the Flash memory which has experienced the power-on and power-off process and the first test data backed up in the host computer, it can be verified whether the Flash memory can correctly read the first test data, and the integrity and accuracy of the data are ensured. At the same time, the direct data comparison simplifies the data verification process, without the need for complex detection mechanisms, reducing the difficulty and cost of development and implementation. According to the verification results of successful or failed reading, the cycle number and the read failure number are updated, and these data are recorded in the host computer, which helps to discover and record potential problems of the Flash memory in time, and reflects the stability of the Flash memory under different environments and conditions. The automatic recording function of the cycle number and the read failure number enables the test process to automatically continue for a long time, reducing the cost of manual operation.

[0085] In some embodiments, when the read operation fails, the cycle number is first updated (the cycle number is incremented by one), and then the read failure number is updated (the read failure number is incremented by one), and the cycle number is recorded in the host computer.

[0086] In some embodiments, when the read operation fails, the cycle number is first updated (the cycle number is incremented by one), and then the read failure number is updated (the read failure number is incremented by one), and the cycle number is recorded in the host computer.

[0087] Optionally, in the cycles S100 to S300, the first test data taken in each cycle process is not the same.

[0088] Specifically, whether the second storage data read from the Flash memory which has undergone power-on and power-off processing is consistent with the first test data backed up in the host computer or not (whether the verification result after the read operation is successful or failed), when the number of cycles is less than the preset number and the execution of S100 is returned, the first test data written is different from the first test data in the previous cycle S100 to S300 process. Specifically, the first test data written is a new test data. This new test data can be obtained by changing a certain rule, or can be randomly extracted from a data set and not used in the previous cycle process.

[0089] In this optional embodiment, by using different first test data in each cycle, not only detailed error information can be provided to facilitate error diagnosis and fault location, but also the read-write stability of the Flash memory can be comprehensively evaluated to verify its performance when processing different types of data. This method not only improves the coverage and comprehensiveness of the test, but also enhances the robustness of the system, ensuring that the Flash memory can work stably and reliably in various situations.

[0090] Optionally, the cycle S100 to S300 is performed multiple times, and the read-write stability of the Flash memory is evaluated according to the obtained multiple write verification results and read verification results, including:

[0091] When the number of cycles is equal to or greater than the preset number, output the number of write failures, the number of read failures, and the number of cycles;

[0092] The ratio of the number of write failures to the number of cycles is determined as a first coefficient;

[0093] The ratio of the number of read failures to the number of cycles is determined as a second coefficient;

[0094] The read-write stability of the Flash memory is evaluated according to the first coefficient and the second coefficient.

[0095] Specifically, the above-mentioned write and read operations are repeatedly performed multiple times, the results of each write and read are recorded, the number of read failures, the number of write failures and the number of cycles are updated, until the number of cycles is equal to the preset number. When the number of cycles is equal to or greater than the preset number, the cycle for the write operation and the read operation is stopped, the proportion of the number of write failures in the number of cycles is calculated, and the first coefficient, i.e. the frequency of write operation failure, is obtained; at the same time, the proportion of the number of read failures in the number of cycles is calculated, and the second coefficient, i.e. the frequency of read operation failure, is obtained. These two coefficients provide quantitative indicators for the reliability and stability of the Flash memory under long-time operation. Through the first coefficient and the second coefficient, the stability of the Flash memory can be comprehensively evaluated, which helps to quickly identify potential problems and take corresponding measures.

[0096] wherein the preset number refers to the total number of cycles of write and read operations preset in the Flash memory test process. This number is determined according to the time requirement of the test, the resource limitation and the test target, and can be several thousand times or several ten thousand times. When the preset number is set too large, it will occupy a large amount of hardware resources such as test equipment, power supply, etc., prolong the development cycle of the entire project, lead to reduced test efficiency and increased test cost. When the preset number is set too small, it may not be able to find all potential problems, especially those temporary failures or intermittent problems that only occur after long-term use, leading to inaccurate reflection of the real performance of the Flash memory. Reasonable setting of the preset number can reduce the test cost and improve the test efficiency on the premise of ensuring the effectiveness of the test.

[0097] The calculation formula of the first coefficient is:

[0098] First coefficient = number of write failures / total number of cycles;

[0099] For example, if the total number of cycles is 1000 times and the number of write failures is 10 times, the first coefficient is 0.01. A lower first coefficient indicates that the write operation is more reliable, while a higher first coefficient indicates that there are more write errors.

[0100] The calculation formula of the second coefficient is:

[0101] Second coefficient = number of read failures / total number of cycles;

[0102] For example, if the total number of cycles is 1000 times and the number of read failures is 20 times, the second coefficient is 0.02. A lower second coefficient indicates that the read operation is more reliable, while a higher second coefficient indicates that there are more read errors.

[0103] In some embodiments, the first coefficient can be determined first and then the second coefficient. In other embodiments, the second coefficient can be determined first and then the first coefficient.

[0104] In the optional embodiment, a large amount of test data can be collected without additional hardware by performing multiple loop read-write operations through existing data read-write software, reducing manual intervention and test cost. When the number of loops is equal to or greater than the preset number, the number of write failures, the number of read failures, and the total number of loops are output. The first coefficient and the second coefficient are determined by simple mathematical operations without complex algorithms and additional tools. The first coefficient is used to quickly evaluate the write performance of the Flash memory, and the second coefficient is used to quickly evaluate the read performance of the Flash memory. By considering these two coefficients, the stability of the Flash memory can be comprehensively evaluated. This method not only improves the test efficiency, but also simplifies the data analysis process and reduces the overall test cost.

[0105] Optionally, as shown in Figure 3 evaluating the read-write stability of the Flash memory according to the first coefficient and the second coefficient comprises:

[0106] When the first coefficient is greater than a first preset threshold, it is determined that the Flash memory has a write stability problem;

[0107] When the second coefficient is greater than a second preset threshold, it is determined that the Flash memory has a read stability problem.

[0108] Specifically, the first preset threshold and the second preset threshold are set through a simple configuration file or parameter setting. The first preset threshold limits the failure rate of the write operation (the first coefficient), and the second preset threshold limits the failure rate of the read operation (the second coefficient). These two thresholds can be determined according to actual application requirements, industry standards, and historical data. For example, the first preset threshold can be set to 0.01 (i.e., the write failure rate is not more than 1%), and the second preset threshold can be set to 0.005 (i.e., the read failure rate is not more than 0.5%). When the first coefficient exceeds the first preset threshold, it is determined that the Flash memory has a write stability problem. When the second coefficient exceeds the second preset threshold, it is determined that the Flash memory has a read stability problem. When the first coefficient exceeds the first preset threshold and the first coefficient exceeds the first preset threshold, it is determined that the Flash memory has both a write stability problem and a read stability problem. At this time, the user interface or log system of the electronic device will provide clear error prompts and operation suggestions to the operator, ensuring that the operator can take appropriate measures in a timely manner.

[0109] In the optional embodiment, the performance of the Flash memory in read and write operations can be quickly evaluated by comparing the first coefficient with the first preset threshold and the second coefficient with the second preset threshold. The method is simple and easy to implement, and does not require complex algorithms or additional software tools. The method not only provides intuitive results and facilitates the judgment of the stability of the Flash memory, but also improves the test efficiency and reduces the cost.

[0110] Optionally, as shown in Figure 3 the Flash memory test method further comprises:

[0111] When the first test data is not equal to the first storage data or the first test data is not equal to the second storage data, an exception handling mechanism is triggered, and the execution of S100 is returned, wherein the exception handling mechanism includes at least one of data backup, memory replacement, and system restart;

[0112] The data backup includes backing up the first test data to other storage media;

[0113] The memory replacement includes replacing the original Flash memory with a backup Flash memory;

[0114] The system restart includes restarting the electronic device to restore the Flash memory to a stable state.

[0115] Specifically, when the first storage data read from the Flash memory is inconsistent with the first test data backed up in the host computer, or when the second storage data read from the Flash memory after power-off and power-on processing is inconsistent with the first test data backed up in the host computer, it indicates that the Flash memory may have a fault or data damage. At this time, an exception handling mechanism is triggered to deal with this problem. The exception handling mechanism includes data backup, i.e., backing up the current first storage data or second storage data to other storage media, such as a reliable storage device, such as an external hard disk, network storage, etc., to preserve the current data state for subsequent analysis and fault diagnosis; memory replacement, i.e., physically removing the original Flash memory and installing a pre-prepared backup Flash memory to ensure that the Flash test system quickly recovers to a stable state; system restart, i.e., closing the Flash test system and then opening it again, which can be completed through a software command or manually pressing the restart button, to reinitialize the system, clear any temporary software problems (such as driver errors or system configuration problems), and restore the Flash memory to a stable state.

[0116] In the optional embodiment, the data backup retains original data, facilitates fault analysis and diagnosis, uses existing storage medium, and reduces backup cost. The memory replacement quickly restores system operation through the prepared spare memory, reduces downtime, and reduces overall operating cost. The system restart clears temporary problems, ensures stable operation of the new memory, and is realized through an automated tool or simple operation, reducing manual operation cost. After triggering these abnormal handling mechanisms, the Flash test system recovers to normal, continues from the beginning to start the unfinished test process, helps to ensure the continuity and integrity of the test, reduces the misjudgment caused by the error of the intermediate step, and improves the accuracy of the test result. Different abnormal handling mechanisms can effectively cope with the read errors of various Flash memories, ensure system stability and data security, and realize low-cost Flash testing.

[0117] The data backup retains original data, facilitates fault analysis and diagnosis, and uses existing storage medium, thereby reducing backup cost. The memory replacement quickly restores system operation through the prepared spare memory, reduces downtime, and reduces overall operating cost. The system restart clears temporary problems, ensures stable operation of the Flash memory, and is realized through an automated tool or simple operation, reducing manual operation cost. Different abnormal handling mechanisms can effectively cope with the read errors of various Flash memories, ensure system stability and data security, and realize low-cost Flash testing. After triggering these abnormal handling mechanisms, the Flash test system recovers to normal, continues from the beginning to start the unfinished test process, helps to ensure the continuity and integrity of the test, reduces the misjudgment caused by the error of the intermediate step, and improves the accuracy of the test result.

[0118] As shown in FIG. 4, the Flash memory test device 400 provided by the embodiment of the present application comprises: Figure 4 The acquisition module 410 is configured to write first test data into the Flash memory through the data read-write software of the host computer.

[0119] The write verification module 420 is configured to read first storage data in the Flash memory through the data read-write software, verify the writing of the first test data according to the first storage data, obtain a write verification result, and control the relay to be disconnected when the write verification result is data writing success, so that the power supply stops supplying power to the Flash memory.

[0120]

[0121] ​The reading verification module 430 is configured to control the relay to close after the first preset time, so that the power supply continues to supply power to the Flash memory, read second stored data in the Flash memory through the data reading and writing software, verify the reading of the first test data according to the second stored data, and obtain a reading verification result.

[0122] The evaluation module 440 is configured to cycle the obtaining module 410 to the reading verification module 430 multiple times, and evaluate the read-write stability of the Flash memory according to the obtained multiple write verification results and reading verification results.

[0123] Optionally, the write verification module 420 is specifically configured to determine whether the first test data is equal to the first stored data, when the first test data is equal to the first stored data, the write verification result is data writing success, when the first test data is not equal to the first stored data, the write verification result is data writing failure, the number of writing failures is increased by one, and the obtaining module 410 is executed again.

[0124] Optionally, the reading verification module 430 is specifically configured to determine whether the first test data is equal to the second stored data, when the first test data is equal to the second stored data, the reading verification result is data reading success, and the number of cycles is increased by one, when the first test data is not equal to the second stored data, the reading verification result is data reading failure, the number of cycles is increased by one, and the number of reading failures is increased by one.

[0125] Optionally, in the cycling of the obtaining module 410 to the reading verification module 430, the first test data adopted in each cycle is different.

[0126] Optionally, the evaluation module 440 is specifically configured to output the number of writing failures, the number of reading failures, and the number of cycles when the number of cycles is equal to or greater than a preset number, determine a first coefficient as a ratio of the number of writing failures to the number of cycles, determine a second coefficient as a ratio of the number of reading failures to the number of cycles, and evaluate the read-write stability of the Flash memory according to the first coefficient and the second coefficient.

[0127] Optionally, the evaluation module 440 is specifically configured to determine that the Flash memory has a writing stability problem when the first coefficient is greater than a first preset threshold, and determine that the Flash memory has a reading stability problem when the second coefficient is greater than a second preset threshold.

[0128] Optionally, the Flash memory testing device 400 further comprises an exception module, configured to trigger an exception handling mechanism and return to execute the obtaining module 410 when the first test data is not equal to the first storage data or the first test data is not equal to the second storage data, wherein the exception handling mechanism comprises at least one of data backup, memory replacement and system restart; the data backup comprises backing up the first test data to other storage media; the memory replacement comprises replacing the original Flash memory with a backup Flash memory; and the system restart comprises restarting the electronic device to restore the Flash memory to a stable state.

[0129] As shown in Figure 5 An electronic device 500 provided by an embodiment of the present application comprises a memory 520 and a processor 510; the memory 520 is configured to store a computer program; and the processor 510 is configured to implement the Flash memory testing method as described above when executing the computer program.

[0130] Alternatively, an electronic device 500 comprises a memory 520 and a processor 510 coupled to the memory 520; the memory 520 is configured to store a computer program; and the processor 510 is configured to perform the following operations when executing the computer program:

[0131] S100: writing first test data into a Flash memory through data read-write software of the host computer;

[0132] S200: reading first storage data in the Flash memory through the data read-write software, verifying a writing condition of the first test data according to the first storage data, obtaining a writing verification result, and controlling a relay to be disconnected when the writing verification result is data writing success, so as to stop a power supply from supplying power to the Flash memory;

[0133] S300: controlling the relay to be closed after a first preset time, so as to continue supplying power to the Flash memory by the power supply, reading second storage data in the Flash memory through the data read-write software, verifying a reading condition of the first test data according to the second storage data, and obtaining a reading verification result;

[0134] S400: repeating S100 to S300 for multiple times, and evaluating read-write stability of the Flash memory according to the obtained multiple writing verification results and reading verification results.

[0135] The embodiment of the present application provides a computer readable storage medium, and the storage medium stores a computer program.

[0136] Alternatively, a non-volatile computer readable storage medium, the storage medium stores a computer program, when the computer program is executed by a processor, the processor executes the following operations:

[0137] S100: write first test data into the Flash memory through data read-write software of the host computer;

[0138] S200: read first storage data in the Flash memory through the data read-write software, verify the writing of the first test data according to the first storage data, obtain a writing verification result, when the writing verification result is data writing success, control the relay to be disconnected, so that the power supply stops supplying power to the Flash memory;

[0139] S300: control the relay to be closed after a first preset time, so that the power supply continues to supply power to the Flash memory, read second storage data in the Flash memory through the data read-write software, verify the reading of the first test data according to the second storage data, and obtain a reading verification result;

[0140] S400: cycle S100 to S300 multiple times, and evaluate the read-write stability of the Flash memory according to the multiple writing verification results and the reading verification results obtained.

[0141] An electronic device 500 that can be a server or client of the present application will now be described, which is an example of a hardware device that can be applied to various aspects of the present application. The electronic device 500 is intended to represent various forms of digital electronic computing devices such as laptops, desktops, workstations, personal digital assistants, servers, blade servers, mainframes, and other appropriate computing devices. The electronic device 500 can also represent various forms of mobile devices such as personal digital processing, cellular telephones, smart phones, wearable devices, and other similar computing devices. The components shown herein, their connections and relationships, and their functions, are meant to be examples only, and are not intended to limit the implementations of the present application described and / or claimed in this document.

[0142] The electronic device 500 includes a computing unit that can perform various appropriate actions and processes in accordance with a computer program stored in a read-only memory (ROM) or a computer program loaded from a storage unit into a random access memory (RAM). Various programs and data required for device operation can also be stored in the RAM. The computing unit, the ROM, and the RAM are connected to each other through a bus. An input / output (I / O) interface is also connected to the bus.

[0143] Those skilled in the art can understand that all or part of the processes in the above-mentioned embodiment methods can be completed by instructing relevant hardware through a computer program, and the program can be stored in a computer-readable storage medium. When the program is executed, the processes of the above-mentioned embodiment methods can be included. The storage medium can be a magnetic disc, an optical disc, a read-only memory (ROM), a random access memory (RAM), or the like. In this application, the units described as separate components can or can not be physically separated, and the components shown as units can or can not be physical units, that is, they can be located in one place or distributed on multiple network units. Part or all of the units can be selected according to actual needs to achieve the purpose of the embodiment of the present application. In addition, the functional units in each embodiment of the present application can be integrated in one processing unit, or each unit can exist physically, or two or more units can be integrated in one unit. The integrated unit can be realized in the form of hardware or in the form of a software functional unit.

[0144] Although the present application is disclosed as above, the protection scope of the present application is not limited to this. Those skilled in the art can make various changes and modifications without departing from the spirit and scope of the present application, and these changes and modifications will fall within the protection scope of the present application.

Claims

1. A method of testing a Flash memory, characterized by, Based on a test system, the test system comprises a host computer, a single-chip microcomputer, a relay and a power supply, the host computer is in communication connection with the single-chip microcomputer, the single-chip microcomputer is connected with the relay, the relay is used for controlling the power supply to the Flash memory, and the Flash memory test method comprises: S100: write first test data into the Flash memory through the data read-write software of the host computer; S200: read the first storage data in the Flash memory through the data read-write software, verify the writing of the first test data according to the first storage data, obtain the writing verification result, when the writing verification result is data writing success, control the relay to be disconnected, so that the power supply stops supplying power to the Flash memory; S300: control the relay to be closed after a first preset time, so that the power supply continues to supply power to the Flash memory, read the second storage data in the Flash memory through the data read-write software, verify the reading of the first test data according to the second storage data, and obtain the reading verification result; S400: cycle S100 to S300 multiple times, and evaluate the read-write stability of the Flash memory according to the obtained multiple writing verification results and reading verification results.

2. The Flash memory testing method of claim 1, wherein, The verification of the writing of the first test data according to the first storage data, to obtain the writing verification result, comprises: determine whether the first test data is equal to the first storage data; when the first test data is equal to the first storage data, the writing verification result is data writing success; when the first test data is not equal to the first storage data, the writing verification result is data writing failure, the writing failure number is increased by one, and S100 is returned to be executed.

3. The Flash memory testing method of claim 1, wherein, The verification of the reading of the first test data according to the second storage data, to obtain the reading verification result, comprises: when the first test data is equal to the second storage data, the reading verification result is data reading success, and the cycle number is increased by one; when the first test data is not equal to the second storage data, the reading verification result is data reading failure, the cycle number is increased by one and the reading failure number is increased by one.

4. The Flash memory testing method of claim 1, wherein, In the cycle process of S100 to S300, the first test data adopted in each cycle process is not the same.

5. The Flash memory testing method of claim 1, wherein, The cycle S100 to S300 multiple times, and evaluate the read-write stability of the Flash memory according to the obtained multiple writing verification results and reading verification results, comprises: when the cycle number is equal to or greater than a preset number, output the writing failure number, the reading failure number and the cycle number; determine the ratio of the writing failure number to the cycle number as a first coefficient; determine the ratio of the reading failure number to the cycle number as a second coefficient; evaluate the read-write stability of the Flash memory according to the first coefficient and the second coefficient.

6. The Flash memory testing method of claim 5, wherein, The read-write stability of the Flash memory is evaluated according to the first coefficient and the second coefficient, including: When the first coefficient is greater than a first preset threshold, it is determined that the Flash memory has a write stability problem; When the second coefficient is greater than a second preset threshold, it is determined that the Flash memory has a read stability problem.

7. The Flash memory testing method of claim 2 or 3, wherein, Further comprising: When the first test data is not equal to the first storage data or the first test data is not equal to the second storage data, triggering an exception handling mechanism, and returning to execute S100, wherein the exception handling mechanism includes at least one of data backup, memory replacement, and system restart; The data backup includes backing up the first test data to other storage media; The memory replacement includes replacing the original Flash memory with a backup Flash memory; The system restart includes restarting the electronic device to restore the Flash memory to a stable state.

8. A Flash memory testing apparatus, characterized by comprising: Based on a test system, the test system includes a host computer, a single-chip microcomputer, a relay, and a power supply, the host computer is in communication connection with the single-chip microcomputer, the single-chip microcomputer is connected with the relay, the relay is used for controlling the power supply to supply power to the Flash memory, and the Flash memory test device includes: An acquisition module is configured to write first test data into a Flash memory through data read-write software of the host computer; A write verification module is configured to read first storage data in the Flash memory through the data read-write software, verify a write condition of the first test data according to the first storage data, obtain a write verification result, and control the relay to be disconnected when the write verification result is data write success, so as to make the power supply stop supplying power to the Flash memory; A read verification module is configured to control the relay to be closed after a first preset time, so as to make the power supply continue to supply power to the Flash memory, read second storage data in the Flash memory through the data read-write software, verify a read condition of the first test data according to the second storage data, and obtain a read verification result; An evaluation module is configured to cycle the acquisition module to the read verification module multiple times, evaluate read-write stability of the Flash memory according to multiple write verification results and read verification results obtained.

9. An electronic device, comprising: A memory and a processor are included; The memory is configured to store a computer program; The processor is configured to implement the Flash memory test method of any one of claims 1 to 7 when executing the computer program.

10. A computer-readable storage medium, characterized in that, The storage medium has a computer program stored thereon, and when the computer program is executed by the processor, the Flash memory test method of any one of claims 1 to 7 is implemented.

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