Method for forming mask structure and method for forming semiconductor structure

Abstract

The present disclosure provides a method for forming a mask structure, the method comprising: forming a first mask layer, a second mask layer, and a third mask layer; patterning the third mask layer and the second mask layer located in the array region and the marking region to obtain a second stacked structure having a plurality of first openings and a plurality of second openings, each first opening and each second opening penetrating the remaining third mask layer and extending into the interior of the second mask layer, the orthographic projection of each first opening on the substrate being located in the array region, and the orthographic projection of each second opening on the substrate being located in the marking region; forming a fourth mask layer, controlling the surface of the fourth mask layer to be flush with the surface of the third mask layer in the array region; etching the fourth mask layer and the second stacked structure to form a marking pattern in the marking region. The mask structure provided by the present disclosure eliminates the problem of mark formation defects caused by process defects, while reducing the number of masks required to form the mark, improving the formation quality of the device, and reducing costs.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor technology, and in particular to a method for forming a mask structure and a method for forming a semiconductor structure. Background Art

[0002] In semiconductor manufacturing, the formation of a chip usually involves stacking multiple film layers, each of which is used to form different circuit elements or implement specific functions. In order to ensure the timeliness and functionality of the circuit, it is necessary to ensure the alignment accuracy between different film layers.

[0003] Currently, to reduce misalignment between different film layers, alignment marks are typically formed in the peripheral region simultaneously with device formation in the array region. These marks are used to calibrate misalignment or misalignment between the different film layers. However, due to process limitations, the alignment marks formed in the mark region through processes such as exposure and development often contain pattern defects, resulting in poor alignment mark quality and reduced performance of subsequently formed devices.

[0004] It should be noted that the information disclosed in the above background technology section is only used to enhance the understanding of the background of the present disclosure, and therefore may include information that does not constitute prior art known to ordinary technicians in the field. Summary of the Invention

[0005] In view of this, a method for forming a mask structure and a method for forming a semiconductor structure are provided.

[0006] Other features and advantages of the present disclosure will become apparent from the following detailed description, or may be learned in part by practice of the present disclosure.

[0007] According to one aspect of the present disclosure, a method for forming a mask structure is provided, the method comprising:

[0008] Providing a substrate, the substrate comprising an array region and a peripheral region, the peripheral region comprising a mark region and a non-mark region, the non-mark region being a region of the peripheral region excluding the mark region;

[0009] forming a first stacked structure on the surface of the substrate, wherein the first stacked structure comprises a first mask layer, a second mask layer, and a third mask layer stacked in sequence;

[0010] Patterning the third mask layer and the second mask layer located in the array area and the mark area to obtain a second stacked structure having a plurality of first openings and a plurality of second openings, such that the thickness of the remaining third mask layer located in the array area and the mark area is less than the thickness of the third mask layer located in the non-mark area, the thickness of the remaining second mask layer located in the array area and corresponding to each first opening and the thickness of the remaining second mask layer located in the mark area and corresponding to each second opening are both less than the thickness of the second mask layer located in the non-mark area, each first opening and each second opening penetrates the remaining third mask layer and extends into the interior of the second mask layer, the orthographic projection of each first opening on the substrate is located in the array area, and the orthographic projection of each second opening on the substrate is located in the mark area;

[0011] forming a fourth mask layer in each of the first openings and each of the second openings, and controlling a surface of the fourth mask layer located in the array area to be flush with a surface of the remaining third mask layer located in the array area;

[0012] The fourth mask layer and the second stacked structure are etched to expose the surface of the substrate, a transfer pattern is formed in the array area, and a marking pattern is formed in the marking area.

[0013] In some embodiments of the present disclosure, based on the aforementioned solution, patterning the third mask layer and the second mask layer located in the array area and the mark area to obtain a second stacked structure having a plurality of first openings and a plurality of second openings includes:

[0014] Etching the third mask layer located in the array area and the mark area to form initial first openings corresponding to the positions of the first openings and initial second openings corresponding to the positions of the second openings in the third mask layer, wherein each of the initial first openings and each of the initial second openings penetrates the third mask layer;

[0015] forming a second photoresist layer on the third mask layer located in the non-marking area, wherein the second photoresist layer exposes the marking area and the array area;

[0016] Using the second photoresist layer as a mask, the exposed third mask layer and the second mask layer are etched to form a plurality of first openings and a plurality of second openings, wherein the thickness of the remaining third mask layer located in the array area and the mark area is less than the thickness of the third mask layer located in the non-mark area, the thickness of the remaining second mask layer located in the array area and corresponding to each first opening and the thickness of the remaining second mask layer located in the mark area and corresponding to each second opening are both less than the thickness of the second mask layer located in the non-mark area, and each first opening and each second opening penetrates the remaining third mask layer and extends to the interior of the second mask layer.

[0017] In some embodiments of the present disclosure, based on the above solution, etching the third mask layer located in the array area and the mark area includes:

[0018] forming a mask material layer on the third mask layer;

[0019] forming a patterned first photoresist layer on the mask material layer;

[0020] The mask material layer and the third mask layer are patterned using the patterned first photoresist layer as a mask to form the initial first openings and the initial second openings in the third mask layer.

[0021] In some embodiments of the present disclosure, based on the aforementioned solution, forming a mask material layer on the third mask layer includes:

[0022] A fifth mask layer and a sixth mask layer are sequentially stacked on the third mask layer. The fifth mask layer has the same etching rate as the first mask layer, and the sixth mask layer has the same etching rate as the second mask layer.

[0023] In some embodiments of the present disclosure, based on the above solution, forming a fourth mask layer in each of the first openings and each of the second openings includes:

[0024] forming an initial fourth mask layer, wherein the initial fourth mask layer fills each of the first openings and each of the second openings and covers a surface of the third mask layer;

[0025] The initial fourth mask layer is etched to obtain the fourth mask layer, wherein a surface of the fourth mask layer located in the array area is flush with a surface of the remaining third mask layer located in the array area, and the fourth mask layer is formed in each of the second openings.

[0026] In some embodiments of the present disclosure, based on the aforementioned solution, etching the fourth mask layer and the second stacked structure to expose the surface of the substrate and forming a transfer pattern in the array area includes:

[0027] In the array area, the fourth mask layer is used as a mask to etch the remaining third mask layer, the remaining second mask layer and the first mask layer in the area outside each first opening to expose the substrate. During the etching process, the etching selectivity ratio of the third mask layer to the fourth mask layer is greater than 1.

[0028] In some embodiments of the present disclosure, based on the above solution, the method further includes:

[0029] The fourth mask layer is removed to expose the remaining second mask layer covered by the fourth mask layer.

[0030] In some embodiments of the present disclosure, based on the above solution, etching the fourth mask layer and the second stacked structure to expose the surface of the substrate and forming a marking pattern in the marking area includes:

[0031] In the marking area, the fourth mask layer located in each second opening, the remaining second mask layer and the first mask layer are etched to expose the substrate. During the etching process, the etching selectivity ratio of the second mask layer to the fourth mask layer is greater than 1.

[0032] In some embodiments of the present disclosure, based on the above solution, the fourth mask layer includes a spin-on hard mask layer, and / or

[0033] The second mask layer includes a silicon oxynitride film layer or a silicon nitride layer, and / or

[0034] The first mask layer includes a spin-on hard mask layer, and / or

[0035] The third mask layer includes a silicon oxide film layer.

[0036] According to another aspect of the present disclosure, a method for forming a semiconductor structure is provided, wherein a mask structure is formed by adopting the above-mentioned method for forming a mask structure, and the substrate is etched based on the mask structure to form a semiconductor structure.

[0037] The present disclosure provides a method for forming a mask structure, which comprises forming a first stacked structure comprising a first mask layer, a second mask layer, and a third mask layer on a substrate, patterning the first stacked structure to form a second stacked structure, wherein the second stacked structure comprises a plurality of first openings located in an array region and a plurality of second openings located in a marking region, and forming a fourth mask layer covering the second stacked structure, etching the fourth mask layer and the second stacked structure to form a transfer pattern in the array region and a marking pattern in the marking region. The mask structure formed by the above method overcomes pattern defects caused by process defects when forming the transfer pattern and the marking pattern, thereby improving the integrity of the subsequently formed marking, thereby improving the formation quality of the device, and thereby improving the performance and yield of the device. At the same time, the mask structure formed by this method reduces the number of masks required, simplifies the process, and reduces production costs.

[0038] The present disclosure provides a method for forming a semiconductor structure, which adopts the above-mentioned method for forming a mask structure to form a mask structure, and etches a substrate based on the mask structure to form a semiconductor structure. The semiconductor structure formed by this method overcomes the device defect problem caused by mask defects during the pattern transfer process of the mask layer, thereby improving the performance and formation quality of the device.

[0039] It is to be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0040] The accompanying drawings are incorporated into and constitute a part of the specification, illustrate embodiments consistent with the present disclosure, and together with the specification, are used to explain the principles of the present disclosure. Obviously, the drawings described below are only some embodiments of the present disclosure, and those skilled in the art can derive other drawings based on these drawings without inventive effort.

[0041] Figure 1 Schematic diagram of a mask structure in the prior art in an exemplary embodiment of the present disclosure.

[0042] Figure 2 The present invention is a flowchart of a method for forming a mask structure in an exemplary embodiment of the present invention.

[0043] Figure 3A Schematic diagram of a first stacked structure in an exemplary embodiment of the present disclosure.

[0044] Figure 3B In the exemplary embodiment of the present disclosure Figure 3A Schematic diagram of the structure of the first stacked structure in the marking area.

[0045] Figure 4ASchematic diagram of the structure of a mask material layer and a first photoresist layer in an exemplary embodiment of the present disclosure.

[0046] Figure 4B In the exemplary embodiment of the present disclosure Figure 4A Schematic diagram of the structure of the mask material layer and the first photoresist layer in the mark area.

[0047] Figure 5A Schematic diagram of the structure of an initial first opening in an exemplary embodiment of the present disclosure.

[0048] Figure 5B Schematic diagram of the structure of an initial second opening in an exemplary embodiment of the present disclosure.

[0049] Figure 6 Schematic diagram of the structure of a second photoresist layer in an exemplary embodiment of the present disclosure.

[0050] Figure 7A This is a structural schematic diagram of a first opening in an exemplary embodiment of the present disclosure.

[0051] Figure 7B Schematic diagram of the structure of a second opening in an exemplary embodiment of the present disclosure.

[0052] Figure 8A Schematic diagram of a structure for forming a fourth mask layer in an exemplary embodiment of the present disclosure.

[0053] Figure 8B In the exemplary embodiment of the present disclosure Figure 8A Schematic diagram of the structure of forming a fourth mask layer in the mark area.

[0054] Figure 9A This is a schematic diagram of the structure after etching the fourth mask layer in an exemplary embodiment of the present disclosure.

[0055] Figure 9B In the exemplary embodiment of the present disclosure Figure 9A Schematic diagram of the structure after etching the fourth mask layer in the mark area.

[0056] Figure 10A Schematic diagram of a structure of a transfer pattern within an array region in an exemplary embodiment of the present disclosure.

[0057] Figure 10B Schematic diagram of a marking pattern in a marking area in an exemplary embodiment of the present disclosure.

[0058] The description of the accompanying drawings is as follows:

[0059] 100, substrate; 210, first stacked structure; 220, second stacked structure; 201, first mask layer; 202, second mask layer; 203, third mask layer; 204, fourth mask layer; 2041, initial fourth mask layer; 205, fifth mask layer; 206, sixth mask layer; 301, first opening; 3011, initial first opening; 302, second opening; 3021, initial second opening; 401, first photoresist layer; 402, second photoresist layer; 501, first mask material layer; 502, second mask material layer; 510, first film layer structure; 520, second film layer structure; A, array area; P, peripheral area; M, marking area; TP, transfer pattern; MP, marking pattern. DETAILED DESCRIPTION

[0060] Example embodiments will now be described more fully with reference to the accompanying drawings. However, the example embodiments can be implemented in many forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete and will fully convey the concepts of the example embodiments to those skilled in the art. Like reference numerals in the figures represent identical or similar structures, and thus their detailed descriptions will be omitted. Furthermore, the drawings are merely schematic illustrations of the present disclosure and are not necessarily drawn to scale.

[0061] Although relative terms such as "upper" and "lower" are used in this specification to describe the relationship of one illustrated component to another, these terms are used herein for convenience only, such as in accordance with the orientation of the illustrations in the accompanying drawings. It will be understood that if the illustrated device were flipped upside down, the component described as "upper" would become the component "lower." When a structure is referred to as "on" another structure, this may mean that the structure is integrally formed with the other structure, that the structure is "directly" disposed on the other structure, or that the structure is "indirectly" disposed on the other structure via the other structure.

[0062] The terms "a", "an", "the", "said" and "at least one" are used to indicate the presence of one or more elements / components / etc.; the terms "including" and "having" are used to express open-ended inclusion and mean that additional elements / components / etc. may be present in addition to the listed elements / components / etc.; the terms "first", "second" and "third" etc. are used only as labels and are not intended to limit the quantity of their objects.

[0063] In related technologies, a bitline contact (BLC) structure effectively connects a bitline to a memory cell. This structure enables current transfer from the bitline to the memory cell or other circuits, as well as data read and write operations. Since the bitline contact structure is formed in the array region, alignment marks are also required in the peripheral region to align the film layers forming the bitline contact structure, ensuring the desired accuracy.

[0064] Currently, the process of forming the bit line contact structure and the alignment mark includes steps S101 to S107 .

[0065] Wherein, step S101: providing a substrate, wherein the substrate includes an array region and a peripheral region, the peripheral region includes a marking region, and sequentially stacking a first film layer structure and a second film layer structure on the substrate, wherein the first film layer structure and the second film layer structure both include a first mask material layer and a second mask material layer;

[0066] Step S102: forming a first oxide layer on the second film structure, and patterning the first oxide layer so that the first oxide layer has a plurality of initial first openings in the array region and a plurality of initial second openings in the mark region;

[0067] Step S103: Using the second mask material layer within the first film layer structure as an etch stop layer, the first film layer structure is etched along each of the initial first openings in the array region to form a plurality of first openings, and the first film layer structure is etched along each of the initial second openings in the mark region to form a plurality of second openings.

[0068] Step S104: filling each first opening and each second opening with a second oxide layer, wherein the second oxide layer fills each first opening and extends to the surface of the second film structure;

[0069] Step S105: etching the second oxide layer to expose the surface of the second film structure in the array region and to expose the surface of the second mask material layer within the first film structure in the mark region;

[0070] Step S106: forming a photoresist layer covering the peripheral area, filling each second opening, and etching the second film layer structure outside each first opening in the array area to form a transfer pattern in the array area;

[0071] Step S107 : removing the photoresist layer covering the peripheral area to expose the mark area, and etching the first film layer structure in each second opening in the mark area to form an alignment mark in the mark area.

[0072] In step S104, when forming the second oxide layer in each first opening and each second opening, since the second opening in the mark area has a larger size in a direction parallel to the substrate, the second oxide layer deposited at the bottom of the second opening is thinner, and its thickness is less than the thickness of the second oxide layer located above the surface of the second film structure in the array area. As a result, in step S105, when etching the second oxide layers in the array area and the mark area simultaneously, Figure 1 As shown, due to the boundary effect, the second mask material layer 502 in the first film layer structure 510 is partially etched, that is, part of the first film layer structure 510 located at the bottom boundary of the second opening is etched, resulting in incompleteness of the first film layer structure 510 in the second opening, and the alignment mark formed in the subsequent process has defects, resulting in reduced alignment accuracy of the alignment mark.

[0073] Based on this, the present disclosure provides a method for forming a mask structure, such as Figure 2 As shown, the forming method includes: steps S100 to S500.

[0074] Wherein, step S100: providing a substrate, the substrate comprising an array region and a peripheral region, the peripheral region comprising a mark region and a non-mark region, the non-mark region being a region of the peripheral region excluding the mark region;

[0075] Step S200: forming a first stacked structure on the surface of the substrate, wherein the first stacked structure includes a first mask layer, a second mask layer, and a third mask layer stacked in sequence;

[0076] Step S300: patterning the third mask layer and the second mask layer located in the array area and the mark area to obtain a second stacked structure having a plurality of first openings and a plurality of second openings, so that the thickness of the remaining third mask layer located in the array area and the mark area is less than the thickness of the third mask layer located in the non-mark area, the thickness of the remaining second mask layer located in the array area and corresponding to each first opening and the thickness of the remaining second mask layer located in the mark area and corresponding to each second opening are both less than the thickness of the second mask layer located in the non-mark area, and each first opening and each second opening penetrates the remaining third mask layer and extends into the interior of the second mask layer, and the orthographic projection of each first opening on the substrate is located in the array area, and the orthographic projection of each second opening on the substrate is located in the mark area;

[0077] Step S400: forming a fourth mask layer in each of the first openings and each of the second openings, and controlling the surface of the fourth mask layer located in the array area to be flush with the surface of the remaining third mask layer located in the array area;

[0078] Step S500: etching the fourth mask layer and the second stacked structure to expose the surface of the substrate, forming a transfer pattern in the array area, and forming a marking pattern in the marking area.

[0079] The present disclosure provides a method for forming a mask structure, which comprises forming a first stacked structure comprising a first mask layer, a second mask layer, and a third mask layer on a substrate, patterning the first stacked structure to form a second stacked structure, wherein the second stacked structure comprises a plurality of first openings located in an array region and a plurality of second openings located in a marking region, and forming a fourth mask layer covering the second stacked structure, etching the fourth mask layer and the second stacked structure to form a transfer pattern in the array region and a marking pattern in the marking region. The mask structure formed by the above method overcomes pattern defects caused by process defects when forming the transfer pattern and the marking pattern, thereby ensuring good integrity of the alignment mark formed subsequently, improving the formation quality of the device, and thereby improving the performance and yield of the device. At the same time, the mask structure formed by this method reduces the number of required mask layers, simplifies the process, and reduces production costs.

[0080] The following is a detailed description of the various steps of the method for forming the mask structure provided by the embodiment of the present disclosure with reference to the accompanying drawings:

[0081] In the embodiments provided in the present disclosure, Figure 3A As shown, in step S100, a substrate 100 is provided, and the substrate 100 includes an array area A and a peripheral area P. The peripheral area P includes a marking area M and a non-marking area. The non-marking area is the area of ​​the peripheral area P excluding the marking area M. In the structural schematic diagram of a specific process step, the non-marking area can be specifically referred to as the area indicated by P in each figure, and the marking area M can be specifically referred to as the area indicated by M in each figure.

[0082] The substrate 100 may be a semiconductor substrate, for example, a silicon (Si) substrate, a germanium (Ge) substrate, a silicon-germanium (GeSi) substrate, a SOI (Silicon On Insulator), or a GOI (Germanium On Insulator). In some embodiments, the semiconductor substrate may also be a substrate including other elemental semiconductors or compound semiconductors, for example, silicon carbide (SiC), indium phosphide (InP), gallium arsenide (GaAs), cadmium telluride (CdTe), indium selenide (InSe), gallium nitride (GaN), indium gallium phosphide (InGaAs), etc.

[0083] The cross-section of the substrate 100 provided in the present disclosure may be rectangular, square, circular or other shapes. The shape of the substrate 100 may be selected according to the actual design requirements of the device, and the present disclosure does not make any specific limitation.

[0084] Substrate 100 may include an array region A and a peripheral region P. The array region A on substrate 100 is the primary portion of a semiconductor device, responsible for implementing specific functions. It may consist of transistors, capacitors, resistors, and other electronic components, and is used to perform tasks such as computing, storing data, or processing signals. The structure and function of the array region A depend on the chip's design objectives and may include processor cores, memory cells, sensor interfaces, and more.

[0085] The peripheral area P on the substrate 100 may include a marking area M and a non-marking area, and the non-marking area is an area in the peripheral area P where the marking area M is removed. The marking area M may include a mark for identifying a semiconductor device or an area for providing an alignment mark for a process. In the specific embodiment provided in the present disclosure, the peripheral area P may be a cutting path, and the marking area M may refer to an area in the cutting path for forming an alignment mark, wherein the cutting path is usually located at the edge of the wafer, forming an elongated channel along the surface of the wafer. After the semiconductor wafer completes various process steps, it will be cut into multiple independent chips. The function of the cutting path is to divide the wafer into individual chips by cutting it. Of course, the marking area M may also be located at other parts of the substrate 100, and the specific position of the marking area M may be selected according to the specific function of the marking area M and the specific structure of the device, and the present disclosure does not make specific limitations.

[0086] In the embodiments provided in the present disclosure, Figure 3A and Figure 3B As shown, in step S200 , a first stacked structure 210 is formed on the surface of the substrate 100 . The first stacked structure 210 includes a first mask layer 201 , a second mask layer 202 and a third mask layer 203 stacked in sequence.

[0087] The first mask layer 201 may be a film layer made of a material such as a spin-on hardmask (SOH), which covers the surface of the substrate 100 and can protect the substrate 100 during the manufacturing process. The first mask layer 201 can be formed by a process method such as chemical vapor deposition (CVD), spin-coating, coat-soft bake, or self-assembly. The specific formation method can be selected based on factors such as demand and manufacturing process requirements. In the present disclosure, preferably, the first mask layer 201 can be formed on the substrate 100 by spin-coating, but of course, the present invention is not limited to this.

[0088] The second mask layer 202 may be silicon oxynitride (SiON) or silicon nitride (SiNx ) and other materials, which are formed on the surface of the first mask layer 201 away from the substrate 100, and have the functions of protection and insulation, and can also serve as an etching stop layer during the etching process. The second mask layer 202 can be formed by physical vapor deposition (PVD), chemical vapor deposition (CVD), atomic layer deposition (ALD), low pressure chemical vapor deposition (LPCVD), plasma enhanced chemical vapor deposition (PECVD) or atmospheric pressure plasma enhanced chemical vapor deposition (AP-PECVD). The specific formation method can be selected according to factors such as demand, quality requirements and manufacturing process requirements, and is not specifically limited in this disclosure.

[0089] The third mask layer 203 may be a film layer formed of a material such as silicon oxide (SiO2), and the third mask layer 203 may be formed by a process such as physical vapor deposition (PVD), chemical vapor deposition (CVD), or atomic layer deposition (ALD).

[0090] In the embodiments provided in the present disclosure, Figure 7A and Figure 7BAs shown, in step S300, the third mask layer 203 and the second mask layer 202 located in the array area A and the marking area M are patterned to obtain a second stacked structure 220 having a plurality of first openings 301 and a plurality of second openings 302, so that the thickness of the remaining third mask layer 203 located in the array area A and the marking area M is less than the thickness of the third mask layer 203 located in the non-marking area, the thickness of the remaining second mask layer 202 corresponding to each first opening 301 in the array area A and the remaining second mask layer 202 corresponding to each second opening 302 in the marking area M is less than the thickness of the second mask layer 202 located in the non-marking area, and each first opening 301 and each second opening 302 penetrates the remaining third mask layer 203 and extends into the interior of the second mask layer 202, the orthographic projection of each first opening 301 on the substrate 100 is located in the array area A, and the orthographic projection of each second opening 302 on the substrate 100 is located in the marking area M.

[0091] In some embodiments, as Figure 5A and Figure 5B As shown, patterning the third mask layer 203 and the second mask layer 202 located in the array area A and the mark area M to obtain a second stacked structure 220 having a plurality of first openings 301 and a plurality of second openings 302 includes: steps S310 to S330.

[0092] In step S310, the third mask layer 203 located in the array area A and the mark area M is etched to form initial first openings 3011 corresponding to the positions of the first openings 301 and initial second openings 3021 corresponding to the positions of the second openings 302 in the third mask layer 203. Each initial first opening 3011 and each initial second opening 3021 penetrates the third mask layer 203.

[0093] Step S320 : forming a second photoresist layer 402 on the third mask layer 203 in the non-mark area, wherein the second photoresist layer 402 exposes the mark area M and the array area A;

[0094] Step S330: Using the second photoresist layer 402 as a mask, the exposed third mask layer 203 and the second mask layer 202 are etched to form a plurality of first openings 301 and a plurality of second openings 302, wherein the thickness of the remaining third mask layer 203 located in the array area A and the mark area M is less than the thickness of the third mask layer 203 located in the non-mark area, the thickness of the remaining second mask layer 202 corresponding to each first opening 301 in the array area A and the remaining second mask layer 202 corresponding to each second opening 302 in the mark area M is less than the thickness of the second mask layer 202 located in the non-mark area, and each first opening 301 and each second opening 302 penetrates the remaining third mask layer 203 and extends into the interior of the second mask layer 202.

[0095] In the above embodiment, the thickness of the third mask layer 203 located in the array area A and the mark area M is thinned so that the thickness of the remaining third mask layer 203 located in the array area A and the mark area M is smaller than the thickness of the third mask layer 203 located in the non-mark area. At the same time, the second mask layer 202 located in the array area A and the mark area M is thinned so that the thickness of the second mask layer 202 corresponding to each first opening 301 and each second opening 302 is smaller than the thickness of the second mask layer 202 located in the non-mark area. The third mask layer 203 and the second mask layer 202 are patterned. During the subsequent etching of the remaining second mask layer 202 and the remaining third mask layer 203, since the thickness of the second mask layer 202 and the third mask layer 203 in the array area A and the mark area M is different from the thickness of the second mask layer 202 and the third mask layer 203 in the non-mark area, there is no need to form a photoresist layer to distinguish between the array area A and the non-mark area. The array area A and the non-mark area can be distinguished by the above-mentioned thickness relationship, thereby saving process steps.

[0096] In some embodiments, for step S310, Figure 4A 、 Figure 4B 、 Figure 5A and Figure 5B As shown, etching the third mask layer 203 located in the array area A and the mark area M includes: steps S3101 to S3103.

[0097] Wherein, step S3101: forming a mask material layer on the third mask layer 203;

[0098] Step S3102: forming a patterned first photoresist layer 401 on the mask material layer;

[0099] Step S3103 : using the patterned first photoresist layer 401 as a mask, patterning the mask material layer and the third mask layer 203 to form initial first openings 3011 and initial second openings 3021 in the third mask layer 203 .

[0100] Among them, in step S3101, if Figure 4A and Figure 4B As shown, a mask material layer is formed on the third mask layer 203, including sequentially stacking a fifth mask layer 205 and a sixth mask layer 206 on the third mask layer 203. The fifth mask layer 205 has the same etching rate as the first mask layer 201, and the sixth mask layer 206 has the same etching rate as the second mask layer 202. Specifically, the fifth mask layer 205 can be made of the same or similar material as the first mask layer 201, for example, SOH, and the sixth mask layer 206 can be made of the same or similar material as the second mask layer 202, for example, silicon oxynitride (SiON) or silicon nitride (SiN).x The specific formation methods of the fifth mask layer 205 and the sixth mask layer 206 refer to the formation process methods of the first mask layer 201 and the second mask layer 202, which will not be repeated here.

[0101] Taking the fifth mask layer 205 as SOH and the sixth mask layer 206 as silicon oxynitride (SiON) as an example, the fifth mask layer 205 can serve as a protective layer, protecting the film layers located therebelow, and the sixth mask layer 206 can serve as an etch stop layer, which can also have protective and insulating functions. The number of layers of the fifth mask layer 205 in the mask material layer can be one or more layers, and the number of layers of the sixth mask layer 206 can also be one or more layers. The number of the fifth mask layer 205 and the sixth mask layer 206 can be the same or different. In the present disclosure, preferably, the number of the fifth mask layer 205 and the sixth mask layer 206 are both one layer, which can save process steps. Of course, the specific number of the fifth mask layer 205 and the sixth mask layer 206 can be selected according to actual process requirements.

[0102] In step S3102 and step S3103, as Figure 5A and Figure 5B As shown, a patterned first photoresist layer 401 is formed on the mask material layer; using the patterned first photoresist layer 401 as a mask, the mask material layer and the third mask layer 203 are patterned to form initial first openings 3011 and initial second openings 3021 in the third mask layer 203. When patterning the third mask layer 203, the second mask layer 202 can be used as an etch stop layer. That is, the bottom of each initial first opening 3011 and each initial second opening 3021 is flush with the surface of the second mask layer 202.

[0103] In some embodiments, for step S320, Figure 6 As shown, a second photoresist layer 402 is formed on the third mask layer 203 in the non-mark area, and the second photoresist layer 402 exposes the mark area M and the array area A. By forming the second photoresist layer 402 on the third mask layer 203, the second photoresist layer 402 exposes the mark area M and the array area A. In subsequent processing steps, the blocking effect of the second photoresist layer 402 prevents etching of the third mask layer 203 in the non-mark area, thereby further distinguishing the array area A, the mark area M, and the non-mark area.

[0104] In some embodiments, for step S330, Figure 7A and Figure 7BAs shown, the exposed third mask layer 203 and the second mask layer 202 are etched using the second photoresist layer 402 as a mask to form a plurality of first openings 301 and a plurality of second openings 302, wherein the thickness of the remaining third mask layer 203 located in the array area A and the mark area M is thinner than the thickness of the third mask layer 203 located in the non-mark area. The thickness of the remaining second mask layer 202 corresponding to each first opening 301 in the array area A and the remaining second mask layer 202 corresponding to each second opening 302 in the mark area M is thinner than the thickness of the second mask layer 202 located in the non-mark area. Each first opening 301 and each second opening 302 penetrates the remaining third mask layer 203 and extends into the interior of the second mask layer 202.

[0105] The second photoresist layer 402 is used as a mask to etch the third mask layer 203 and the second mask layer 202 located in the array area A and the mark area M. Taking the third mask layer 203 as a silicon oxide layer and the second mask layer 202 as a silicon oxynitride film layer as an example, during the etching process, the etching rate of the third mask layer 203 can be greater than the etching rate of the second mask layer 202. Therefore, when etching the third mask layer 203 in the array area A and the mark area M, the second mask layer 202 within each initial first opening 3011 and each initial second opening 3021 is partially etched at the same time, so that the thickness of the remaining third mask layer 203 located in the array area A and the mark area M is less than the thickness of the third mask layer 203 located in the non-mark area M, and the thickness of the remaining second mask layer 202 corresponding to each first opening 301 in the array area A and the remaining second mask layer 202 corresponding to each second opening 302 in the mark area M is less than the thickness of the second mask layer 202 located in the non-mark area, so as to form each first opening 301 in the array area A and each second opening 302 in the mark area M. Each first opening 301 and each second opening 302 penetrates the remaining third mask layer 203 and extends to the interior of the second mask layer 202 .

[0106] The thickness of the remaining third mask layer 203 formed in the above steps in the array area A and the mark area M is less than the thickness of the third mask layer 203 in the non-mark area. The thickness of the remaining second mask layer 202 corresponding to each first opening 301 in the array area A and the remaining second mask layer 202 corresponding to each second opening 302 in the mark area M is less than the thickness of the second mask layer 202 in the non-mark area, so as to further distinguish the array area A from the non-mark area.

[0107] After etching the third mask layer 203 and the second mask layer 202 located within the array area A and the mark area M, the process further includes removing the second photoresist layer 402 to expose the non-mark area. In the present disclosure, the removal of the second photoresist layer 402 can be performed using a process such as plasma etching, laser ablation, molten salt method, or solvent method. Of course, the specific removal method can be selected based on actual process design requirements.

[0108] In the embodiment provided by the present disclosure, in step S400, as Figure 8A 、 Figure 8B 、 Figure 9A and Figure 9B As shown, a fourth mask layer 204 is formed in each first opening 301 and each second opening 302 , and the surface of the fourth mask layer 204 in the array region A is controlled to be flush with the surface of the remaining third mask layer 203 in the array region A.

[0109] Among them, the fourth mask layer 204 can be made of materials such as spin-on hard mask (SOH), which can be formed by process methods such as chemical vapor deposition (CVD), spin-coating, coat-soft bake or self-assembly.

[0110] In some embodiments, forming the fourth mask layer 204 in each first opening 301 and each second opening 302 includes steps S410 to S420 .

[0111] In step S410 , an initial fourth mask layer 204 is formed, where the initial fourth mask layer 204 fills each of the first openings 301 and each of the second openings 302 and covers the surface of the third mask layer 203 .

[0112] Step S420: Etching the initial fourth mask layer 204 to obtain the fourth mask layer 204, wherein the surface of the fourth mask layer 204 located in the array area A is flush with the surface of the remaining third mask layer 203 located in the array area A, and the fourth mask layer 204 is formed in each of the second openings. After the initial fourth mask layer 204 is etched, it is sufficient as long as the fourth mask layer 204 remains in each of the second openings, that is, the initial fourth mask layer 204 remains, thereby forming a fourth mask layer 204 of a certain thickness. In one embodiment, the surface of the fourth mask layer 204 located in each of the second openings 302 is flush with the surface of the remaining third mask layer 203 that is close to the substrate 100.

[0113] In some embodiments, for step S410, Figure 8A and Figure 8B As shown, an initial fourth mask layer 204 is formed, which fills each first opening 301 and each second opening 302 and covers the surface of the third mask layer 203. Taking the fourth mask layer 204 as SOH as an example, due to its better fluidity, SOH can fill each first opening 301 and each second opening 302 compared to other materials, and will not form defects such as voids in each first opening 301 and each second opening 302. In addition, the SOH film layer has a simpler removal method than film layers made of other materials. For example, it can be removed using gases such as oxygen, nitrogen, or hydrogen without damaging other film layers. Therefore, the alignment mark formed using the fourth mask layer 204 as a mask avoids mark defects caused by defects in the mask properties.

[0114] In some embodiments, for step S420, Figure 9A and Figure 9B As shown, the initial fourth mask layer 204 is etched to obtain the fourth mask layer 204, wherein the surface of the fourth mask layer 204 located in the array area A is flush with the surface of the remaining third mask layer 203 located in the array area A, and the surface of the fourth mask layer 204 located in each second opening 302 is flush with the side of the remaining third mask layer 203 close to the substrate 100.

[0115] Since the initial fourth mask layer 204 is etched simultaneously in array area A, mark area M, and non-mark area, the thicknesses of third mask layer 203 and second mask layer 202 in array area A, mark area M, and non-mark area differ. Consequently, the thicknesses of initial fourth mask layer 204 formed in these three areas also differ. In the present disclosure, the etching of initial fourth mask layer 204 is based on the etching time in array area A. That is, the etching of fourth mask layer 204 is stopped when the surface of fourth mask layer 204 in array area A is flush with the surface of third mask layer 203 in array area A. Therefore, the etching time is based on the etching time in array area A.

[0116] At the same time, the thickness of the fourth mask layer 204 located in the marking region M is determined based on its initial thickness and the etching time. In some embodiments, the thickness of the fourth mask layer 204 located in each second opening 302 in the marking region M can be such that its surface is flush with the surface of the remaining third mask layer 203 close to the substrate 100. Of course, the above embodiment is merely illustrative. For different mask structures, after etching the initial fourth mask layer 204, the thickness of the fourth mask layer 204 located in each second opening 302 can also be different. For example, the surface of the fourth mask layer 204 located in each second opening 302 can be higher than the surface of the remaining third mask layer 203 close to the substrate 100, or the surface of the fourth mask layer 204 located in each second opening 302 can be lower than the surface of the remaining third mask layer 203 close to the substrate 100. The above embodiment can vary according to actual process and is not limited thereto.

[0117] In the embodiment provided by the present disclosure, in step S500, as Figure 10A and Figure 10B As shown, the fourth mask layer 204 and the second stacked structure 220 are etched to expose the surface of the substrate 100 , and a transfer pattern TP is formed in the array region A, and a marking pattern MP is formed in the marking region M.

[0118] The fourth mask layer 204 and the second stacked structure 220 are etched to expose the surface of the substrate 100, and a transfer pattern TP is formed in the array area A. The process includes: in the array area A, using the fourth mask layer 204 as a mask, etching the remaining third mask layer 203, the remaining second mask layer 202, and the first mask layer 201 in the area outside each first opening 301 to expose the substrate 100. During the etching process, the etching selectivity ratio of the third mask layer 203 to the fourth mask layer 204 is greater than 1.

[0119] During the etching process, the surface of the fourth mask layer 204 in the array area A is flush with the surface of the remaining third mask layer 203 in the array area A, and the fourth mask layer 204 fills each first opening 301. The first openings 301 penetrate the third mask layer 203 and extend into the second mask layer 202. Therefore, in the array area A, the thickness of the fourth mask layer 204 in each first opening 301 is greater than the thickness of the third mask layer 203.

[0120] Taking the fourth mask layer 204 as an SOH layer and the third mask layer 203 as a silicon oxide layer as an example, in the array area A, when the third mask layer 203 is etched using the fourth mask layer 204 as a mask, the etching selectivity ratio of the third mask layer 203 to the fourth mask layer 204 is greater than 1. That is, after etching the third mask layer 203 outside each first opening 301, the fourth mask layer 204 still serves as a mask for etching the second mask layer 202 and the first mask layer 201 outside each first opening 301. For example, when etching the second mask layer 202 outside each first opening 301 of the array area A using the fourth mask layer 204 as a mask, the etching selectivity ratio of the second mask layer 202 to the fourth mask layer 204 can be greater than 1. Similarly, when etching the first mask layer 201 outside the first openings 301 in the array region A using the fourth mask layer 204 as a mask, the etching selectivity ratio between the first mask layer 201 and the fourth mask layer 204 may be greater than or equal to 1 until the substrate 100 is exposed.

[0121] Using the fourth mask layer 204 as a mask, the remaining third mask layer 203, the remaining second mask layer 202 and the first mask layer 201 in the area outside each first opening 301 are etched to expose the substrate 100, and then the fourth mask layer 204 is removed to expose the remaining second mask layer 202 covered by the fourth mask layer 204, and a transfer pattern TP is formed in the array area A.

[0122] The fourth mask layer 204 and the second stacked structure 220 are etched to expose the surface of the substrate 100, and a marking pattern MP is formed in the marking area M, including: in the marking area M, the fourth mask layer 204, the remaining second mask layer 202 and the first mask layer 201 located in each second opening 302 are etched to expose the substrate 100, and during the etching process, the etching selectivity ratio of the second mask layer 202 to the fourth mask layer 204 is greater than 1.

[0123] In the marking area M, since the fourth mask layer 204 is filled in the second opening 302, taking the fourth mask layer 204 as an SOH layer as an example, since SOH has good fluidity, no gaps or holes will appear between the fourth mask layer 204 and the inner wall and bottom wall of each second opening 302. When the fourth mask layer 204 in each second opening 302 is etched, it will not affect the remaining second mask layer 202 and the first mask layer 201 located thereunder. In other words, the fourth mask layer 204 has a uniform blocking effect and etching uniformity, so that the marking pattern MP subsequently formed in the marking area M has integrity and uniformity, avoiding structural defects of the marking pattern MP, improving the accuracy of the alignment mark subsequently formed using this marking pattern MP, and thereby improving the overall performance and yield of the device.

[0124] The present disclosure provides a method for forming a mask structure, comprising forming a first stacked structure 210 comprising a first mask layer 201, a second mask layer 202, and a third mask layer 203 on a substrate 100, patterning the first stacked structure 210 to form a second stacked structure 220, wherein the second stacked structure 220 comprises a plurality of first openings 301 located in the array area A and a plurality of second openings 302 located in the mark area M, forming a fourth mask layer 204 covering the second stacked structure 220, and etching the fourth mask layer 204 and the second stacked structure 220 to form a transfer pattern TP in the array area A and a marking pattern MP in the mark area M. The mask structure formed by the above method overcomes pattern defects caused by process defects when forming the transfer pattern TP and the marking pattern MP, thereby ensuring good integrity of the alignment marks formed subsequently, improving device formation quality, and thereby improving device performance and yield. Furthermore, the mask structure formed by this method reduces the number of required mask layers, simplifies the process, and reduces production costs.

[0125] It should be noted that although the steps of the method for forming a mask structure in the present disclosure are described in a specific order in the accompanying drawings, this does not require or imply that the steps must be performed in this specific order, or that all steps must be performed to achieve the desired results. Additionally or alternatively, certain steps may be omitted, multiple steps may be combined into one step, and / or one step may be broken down into multiple steps.

[0126] An embodiment of the present disclosure provides a method for forming a semiconductor structure, which includes: forming a mask structure using the above-mentioned method for forming a mask structure, and etching a substrate based on the mask structure to form a semiconductor structure.

[0127] The present disclosure provides a method for forming a semiconductor structure, which adopts the above-mentioned method for forming a mask structure to form a mask structure, and etches a substrate based on the mask structure to form a semiconductor structure. The semiconductor structure formed by this method overcomes the device defect problem caused by mask defects during the pattern transfer process of the mask layer, thereby improving the performance and formation quality of the device.

[0128] In the embodiment provided by the present disclosure, a mask structure is formed by the above-mentioned mask structure forming method, and the mask structure forms a transfer pattern in the array region and forms a marking pattern in the marking region.

[0129] In the array region, the substrate is etched based on the transfer pattern of the mask structure to form a bitline contact structure (BLC). The bitline contact structure effectively connects the bitline to the memory cell, enabling current transfer and data read and write operations from the bitline to the memory cell or other circuits. Of course, in the present disclosure, in the array region, the structure formed by etching the substrate based on the mask structure can also be other device structures. That is, the transfer pattern provided by the mask structure can be adaptively deformed to meet device structure requirements.

[0130] In the mark area, based on the mark pattern of the mask structure, the mark area of ​​the substrate is etched to form alignment marks. The alignment marks can be used to locate and calibrate the processing positions of different film layers in the array area to achieve accurate pattern transfer and device formation. Of course, in the present disclosure, the formation of the alignment marks in the mark area can be varied according to the device structure formed in the array area. That is, the mark pattern provided by the mask structure can be adaptively deformed to achieve the alignment requirements of the devices in the array area.

[0131] The method for forming the above mask structure is as described above and will not be repeated here.

[0132] The present disclosure provides a method for forming a semiconductor structure, which adopts the above-mentioned method for forming a mask structure to form a mask structure, and etches a substrate based on the mask structure to form a semiconductor structure. The semiconductor structure formed by this method overcomes the device defect problem caused by mask defects during the pattern transfer process of the mask layer, thereby improving the reliability and formation quality of the device.

[0133] Those skilled in the art will readily appreciate other embodiments of the present disclosure after considering the specification and practicing the invention disclosed herein. This application is intended to cover any variations, uses, or adaptations of the present disclosure that follow the general principles of the present disclosure and include common knowledge or customary techniques in the art not disclosed herein. The description and examples are to be considered as exemplary only, with the true scope and spirit of the present disclosure being indicated by the appended claims.

Claims

1. A method for forming a mask structure, characterized in that: include: Providing a substrate, the substrate comprising an array region and a peripheral region, the peripheral region comprising a mark region and a non-mark region, the non-mark region being a region of the peripheral region excluding the mark region; forming a first stacked structure on the surface of the substrate, wherein the first stacked structure comprises a first mask layer, a second mask layer, and a third mask layer stacked in sequence; Patterning the third mask layer and the second mask layer located in the array area and the mark area to obtain a second stacked structure having a plurality of first openings and a plurality of second openings, such that the thickness of the remaining third mask layer located in the array area and the mark area is less than the thickness of the third mask layer located in the non-mark area, the thickness of the remaining second mask layer located in the array area and corresponding to each first opening and the thickness of the remaining second mask layer located in the mark area and corresponding to each second opening are both less than the thickness of the second mask layer located in the non-mark area, each first opening and each second opening penetrates the remaining third mask layer and extends into the interior of the second mask layer, the orthographic projection of each first opening on the substrate is located in the array area, and the orthographic projection of each second opening on the substrate is located in the mark area; forming a fourth mask layer in each of the first openings and each of the second openings, and controlling a surface of the fourth mask layer located in the array area to be flush with a surface of the remaining third mask layer located in the array area; The fourth mask layer and the second stacked structure are etched to expose the surface of the substrate, a transfer pattern is formed in the array area, and a marking pattern is formed in the marking area.

2. The method for forming a mask structure according to claim 1, wherein: Patterning the third mask layer and the second mask layer located in the array area and the mark area to obtain a second stacked structure having a plurality of first openings and a plurality of second openings, comprising: Etching the third mask layer located in the array area and the mark area to form initial first openings corresponding to the positions of the first openings and initial second openings corresponding to the positions of the second openings in the third mask layer, wherein each of the initial first openings and each of the initial second openings penetrates the third mask layer; forming a second photoresist layer on the third mask layer located in the non-marking area, wherein the second photoresist layer exposes the marking area and the array area; Using the second photoresist layer as a mask, the exposed third mask layer and the second mask layer are etched to form a plurality of first openings and a plurality of second openings, wherein the thickness of the remaining third mask layer located in the array area and the mark area is less than the thickness of the third mask layer located in the non-mark area, the thickness of the remaining second mask layer located in the array area and corresponding to each first opening and the thickness of the remaining second mask layer located in the mark area and corresponding to each second opening are both less than the thickness of the second mask layer located in the non-mark area, and each first opening and each second opening penetrates the remaining third mask layer and extends to the interior of the second mask layer.

3. The method for forming a mask structure according to claim 2, wherein: Etching the third mask layer located in the array area and the mark area includes: forming a mask material layer on the third mask layer; forming a patterned first photoresist layer on the mask material layer; The mask material layer and the third mask layer are patterned using the patterned first photoresist layer as a mask to form the initial first openings and the initial second openings in the third mask layer.

4. The method for forming a mask structure according to claim 3, wherein: Forming a mask material layer on the third mask layer, comprising: A fifth mask layer and a sixth mask layer are sequentially stacked on the third mask layer. The fifth mask layer has the same etching rate as the first mask layer, and the sixth mask layer has the same etching rate as the second mask layer.

5. The method for forming a mask structure according to any one of claims 1 to 4, characterized in that: forming a fourth mask layer in each of the first openings and each of the second openings, comprising: forming an initial fourth mask layer, wherein the initial fourth mask layer fills each of the first openings and each of the second openings and covers a surface of the third mask layer; The initial fourth mask layer is etched to obtain the fourth mask layer, wherein a surface of the fourth mask layer located in the array area is flush with a surface of the remaining third mask layer located in the array area, and the fourth mask layer is formed in each of the second openings.

6. The method for forming a mask structure according to any one of claims 1 to 4, characterized in that: Etching the fourth mask layer and the second stacked structure to expose the surface of the substrate and forming a transfer pattern in the array area, comprising: In the array area, the fourth mask layer is used as a mask to etch the remaining third mask layer, the remaining second mask layer and the first mask layer in the area outside each first opening to expose the substrate. During the etching process, the etching selectivity ratio of the third mask layer to the fourth mask layer is greater than 1.

7. The method for forming a mask structure according to claim 6, wherein: The method further comprises: The fourth mask layer is removed to expose the remaining second mask layer covered by the fourth mask layer.

8. The method for forming a mask structure according to any one of claims 1 to 4, characterized in that: Etching the fourth mask layer and the second stacked structure to expose the surface of the substrate and forming a marking pattern in the marking area, comprising: In the marking area, the fourth mask layer located in each second opening, the remaining second mask layer and the first mask layer are etched to expose the substrate. During the etching process, the etching selectivity ratio of the second mask layer to the fourth mask layer is greater than 1.

9. The method for forming a mask structure according to any one of claims 1 to 4, characterized in that: The fourth mask layer includes a spin-on hard mask layer, and / or The second mask layer includes a silicon oxynitride film layer or a silicon nitride layer, and / or The first mask layer includes a spin-on hard mask layer, and / or The third mask layer includes a silicon oxide film layer.

10. A method for forming a semiconductor structure, characterized in that: A mask structure is formed by the formation method according to any one of claims 1 to 9, and the substrate is etched based on the mask structure to form a semiconductor structure.

Images