Method for manufacturing top-side cooled semiconductor package by film-assisted molding and semiconductor package
By using a combination method of substrate layer and heat dissipation member in semiconductor packages and combined with cavity filling technology, the problem of difficulty in heat dissipating the package under high current density and high power cycles is solved, and higher reliability and life are achieved.
Patent Information
- Application Number
- CN202411089655.0
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Priority Date
- 2023-08-10
- Filing Date
- 2024-08-09
- Publication Date
- 2025-02-18
Smart Images
Figure CN119480648A_ABST
Abstract
Description
Technical Field
[0001] The present disclosure relates to a method for manufacturing one or more semiconductor packages and a semiconductor package. Background Art
[0002] Discrete semiconductor power packages are continuously being developed further towards higher efficiency and output power. Decisive factors here are increasing the switching speed and current density of the package to be developed. In new applications such as "green energy", e.g. solar modules, ESS (energy storage systems), electric vehicle charging, the product life is also limited by the reliability of the power cycle, so the combination of high current and high power cycling offers new commercial potential.
[0003] Compared to standard Si devices, wide bandgap devices such as GaN and SiC transistor dies in particular can achieve much higher current densities. As a result, either a smaller die can be used at the same current output, or a higher current output can be achieved at the same die size. However, if the current density increases, it must be ensured that the excess heat generated by the power dissipation is dissipated from the package as quickly as possible, since the temperature in such power transistors can easily reach 150°C or more during operation. In this context, concepts such as top-side cooling are particularly important.
[0004] For these and other reasons, there is a need for the present disclosure. Summary of the invention
[0005] A first aspect of the present disclosure relates to a method for manufacturing one or more semiconductor packages, the method comprising: providing a substrate layer comprising one or more electrical contact areas; connecting a semiconductor die to one of the electrical contact areas; providing a heat dissipation component comprising one or more contact areas; attaching a tape to the back side of the heat dissipation component so that opposite ends of the tape extend beyond opposite side edges of the heat dissipation component; connecting the front side of the heat dissipation component to the semiconductor die by coupling at least one contact area to the die; forming a mold cavity by placing a molding tool over the heat dissipation component and the substrate layer, wherein opposite ends of the tape extend beyond the molding tool so that the tape can be removed from outside the molding tool; filling the mold cavity with encapsulation material; and removing the tape.
[0006] According to an embodiment of the method of the first aspect, the strip is pulled out of the moulding tool after the encapsulating material has solidified.
[0007] According to an embodiment of the method of the first aspect, a first portion of the tape is disposed between the molding tool and the heat dissipation member, and a second portion of the tape is disposed between the molding tool and the substrate layer, so that the space between the molding tool and the substrate layer forms a molding cavity.
[0008] According to an embodiment of the method of the first aspect, the method further comprises singulating the assembly into two or more than two semiconductor packages after pulling out the tape.
[0009] According to an embodiment of the method of the first aspect, the method further comprises providing a substrate layer having a plurality of regularly arranged electrical contact areas. According to another example of the method of the first aspect, the heat dissipation member is provided with a plurality of regularly arranged contact areas. According to another example, the regularly arranged plurality of contact areas comprises a plurality of contact areas arranged in a matrix. According to another example, the plurality of contact areas comprises a plurality of pairs of contact areas.
[0010] According to an embodiment of the method of the first aspect, the substrate layer is one or more of a laminate layer, a printed circuit board (PCB), a lead frame, a direct copper bonding (DCB) structure, an active metal brazing (AMB) structure or an insulated metal substrate (IMS).
[0011] According to an embodiment of the method of the first aspect, the heat dissipation member includes one or more of a lead frame, a direct copper bonding (DCB) structure, an active metal brazing (AMB) structure, a passivated aluminum plate, an insulated metal substrate, a conductive clip or a ceramic material.
[0012] According to an embodiment of the method of the first aspect, the method further comprises providing the tape such that after placing the molding tool over the heat dissipation member and the substrate layer, the tape extends to a length outside the molding tool in the range of 2 mm to 4 mm.
[0013] According to an embodiment of the method of the first aspect, the semiconductor die comprises one or more of a semiconductor transistor die, a power transistor die, a GaN transistor die or a SiC transistor die.
[0014] A second aspect of the present disclosure relates to a method for manufacturing multiple semiconductor packages, the method comprising: providing a heat dissipation component including one or more contact areas and one or more contact elements; applying one or more semiconductor bare chips to the one or more contact areas; connecting an electrical connector between one of the contact elements and the semiconductor bare chip; attaching a tape to the back side of the electrical connector so that the opposite ends of the tape extend beyond the opposite side edges of the heat dissipation component; placing an upper molding tool over one of the contact elements and the electrical connector, and placing a lower molding tool to the back side of the heat dissipation component so that a first portion of the tape is disposed between the upper molding tool and the electrical connector and a second portion of the tape is disposed between the upper molding tool and the contact element, so that the space between the upper molding tool and the lower molding tool forms a mold cavity; filling the mold cavity with encapsulation material; and removing the tape.
[0015] According to an embodiment of the method of the second aspect, the method also includes placing two or more semiconductor dies on two or more contact areas; connecting two or more electrical connectors between one of the contact elements and the two or more semiconductor dies; placing an upper molding tool over the electrical connector and the two outermost contact elements; and after pulling out the tape, singulating the assembly into two or more semiconductor packages.
[0016] According to an embodiment of the method of the second aspect, the electrical connector comprises a clip.
[0017] According to an embodiment of the method of the second aspect, the semiconductor die comprises one or more of a semiconductor transistor die, a power transistor die, a GaN transistor die or a SiC transistor die.
[0018] A third aspect of the present disclosure relates to a semiconductor package, comprising: a substrate layer; a contact area; at least one tie rod connected to a side of the contact area; a semiconductor die disposed on the contact area so that the semiconductor die is connected to the substrate layer in a flip-chip configuration; an encapsulation material covering the top of the substrate layer and partially embedding the semiconductor die, the contact area and the tie rod, wherein the side of the contact area away from the main surface of the semiconductor die and the tie rod is exposed to the outside.
[0019] According to an embodiment of the semiconductor package of the third aspect, the semiconductor package further includes two tie bars connected to opposite sides of the contact region and including sides exposed to the outside.
[0020] According to an embodiment of the semiconductor package of the third aspect, the semiconductor package further comprises adhesive markings in the form of notches in the encapsulation material at side edges of the contact regions.
[0021] A fourth aspect of the present disclosure relates to a semiconductor package, comprising: a substrate layer, which includes a die pad and a contact element; a semiconductor die, which is connected to the die pad in a flip-chip configuration; an electrical connector, which is connected between the top of the semiconductor die and the contact element; an encapsulation material, which covers the top of the substrate layer and is partially embedded in the semiconductor die; wherein the main surface of the electrical connector away from the semiconductor die is exposed to the outside.
[0022] According to an embodiment of the semiconductor package of the fourth aspect, the electrical connector comprises a clip.
[0023] According to an embodiment of the semiconductor package of the fourth aspect, the semiconductor package further comprises adhesive markings in the form of notches in the encapsulation material at side edges of the electrical connector. BRIEF DESCRIPTION OF THE DRAWINGS
[0024] The accompanying drawings are included to provide a further understanding of the embodiments and are incorporated into and constitute a part of this specification. The accompanying drawings illustrate the embodiments and, together with the description, are used to explain the principles of the embodiments. Other embodiments and many of the expected advantages of the embodiments will be readily understood as they become better understood by reference to the following detailed description.
[0025] The elements of the drawings are not necessarily drawn to scale relative to each other. The same or similar reference numbers indicate the same or similar parts.
[0026] Figures 1A to 1G A side cross-sectional view is shown for explaining an example of a method for manufacturing a semiconductor package.
[0027] FIG. 2A to FIG. 2D A top view of a plurality of contact regions arranged in a matrix is shown to illustrate an example of a method for manufacturing a semiconductor package.
[0028] FIG. 3A to FIG. 3C A top view of a plurality of pairs of contact regions arranged in a matrix is shown to illustrate an example of a method for manufacturing a semiconductor package.
[0029] 4A to 4H A side cross-sectional view is shown for illustrating an example of a method for manufacturing a semiconductor package including a clip.
[0030] Figure 5A and Figure 5B A side cross-sectional view (A) and a top view (B) of an example of a semiconductor package are shown.
[0031] Fig. 6A and 6B A side cross-sectional view (A) and a top view (B) of an example of a semiconductor package including a clip are shown. DETAILED DESCRIPTION
[0032] In the detailed description below, reference is made to the accompanying drawings, which form a part of the detailed description, and in which specific embodiments of the present disclosure can be practiced are shown by way of illustration. In this regard, directional terms such as "top", "bottom", "front", "rear", "leading", "trailing" and the like are used with reference to the orientation of the accompanying drawings described. Because the components of the embodiments can be positioned in a plurality of different orientations, the directional terms are used for illustrative purposes and are by no means restrictive. It should be understood that other embodiments may be utilized and structural or logical changes may be made without departing from the scope of the present disclosure. Therefore, the following detailed description should not be considered restrictive, and the scope of the present disclosure is defined by the appended claims.
[0033] It should be understood that the features of the various exemplary embodiments described herein may be combined with each other, unless specifically stated otherwise.
[0034] As used in this specification, the terms "joined", "attached", "connected", "coupled" and / or "electrically connected / electrically coupled" do not mean that the elements or layers must be directly in contact with each other; intervening elements or layers may be provided between the elements that are "joined", "attached", "connected", "coupled" and / or "electrically connected / electrically coupled" accordingly. However, according to the present disclosure, the above terms may optionally also have the specific meaning that the elements or layers are directly in contact with each other, that is, no intervening elements or layers are provided between the elements that are "joined", "attached", "connected", "coupled" and / or "electrically connected / electrically coupled" accordingly.
[0035] In addition, the term "above" used in relation to a component, element or material layer formed or located "above" a surface may be used herein to indicate that the component, element or material layer is "indirectly" located (e.g., placed, formed, deposited, etc.) on the surface, wherein one or more additional components, elements or layers are arranged between the surface and the component, element or material layer. However, the term "above" used in relation to a component, element or material layer formed or located "above" a surface may optionally also have a specific meaning, i.e., the component, element or material layer is "directly" located (e.g., placed, formed, deposited, etc.) on the surface, such as in direct contact with the surface.
[0036] In addition, the word "exemplary" is used herein to mean used as an example, instance or illustration. Any aspect or design described herein as "exemplary" is not necessarily to be construed as superior to other aspects or designs. On the contrary, the use of the word exemplary is intended to present concepts in a concrete way. As used in this application, the term "or" is intended to mean an inclusive "or" rather than an exclusive "or". That is, unless otherwise specified or clear from the context, "X adopts A or B" is intended to mean any natural inclusive arrangement. That is, if X adopts A; X adopts B; or X adopts both A and B, then "X adopts A or B" is satisfied under any of the aforementioned instances. In addition, unless otherwise specified or clear from the context that it is for a singular form, the articles "one" and "an" used in this application and the appended claims can generally be interpreted as meaning "one or more". In addition, at least one of A and B or similar expressions generally refer to A or B or both A and B.
[0037] In addition, although a particular feature or aspect of an embodiment of the present disclosure may be disclosed only with respect to one of the multiple embodiments, this feature or aspect may be combined with one or more other features or aspects of other embodiments, which may be desirable and advantageous for any given or specific application. In addition, to the extent that the terms "including," "having," "with," or other variations thereof are used in the detailed description or claims, these terms are intended to be inclusive in a manner similar to the term "including." In addition, it should be understood that embodiments of the present disclosure may be implemented in discrete circuits, partially integrated circuits, or fully integrated circuits or programming devices. In addition, the term "exemplary" is meant only as an example, not the best or optimal. It should also be understood that, for the purpose of simplicity and ease of understanding, the features and / or elements depicted herein are shown as having specific dimensions relative to each other, and the actual dimensions may be significantly different from the dimensions shown herein.
[0038] Detailed Description
[0039] Figures 1A to 1G A side cross-sectional view is shown for explaining an example of a method for manufacturing a semiconductor package.
[0040] Figure 1A A substrate layer 1 is shown comprising electrical contact areas 1A and a plurality of semiconductor dies 2, each of which is electrically connected to one of the contact areas 1A. The substrate layer 1 may be, for example, a laminate tape or a printed circuit board. The semiconductor dies 2 may be, for example, GaN IGBT (insulated gate bipolar transistor) dies comprising source and gate contacts at their lower part and a drain contact at their upper part.
[0041] Figure 1B A heat dissipation member 3 is shown, which includes one or more contact areas 3A and a tape 4 attached to the back side of the heat dissipation member 3 so that the opposite ends of the tape 4 extend beyond the opposite side edges of the heat dissipation member 3. The heat dissipation member 3 must first be able to dissipate heat, and can be conductive (e.g., Cu), non-conductive (e.g., ceramic), or a combination thereof (e.g., a direct copper bonding (DCB) structure). For embodiments in which the heat dissipation member 3 can be non-conductive, there is no need for a predefined area on the heat dissipation member 3 to contact the die, which is different from embodiments in which the heat dissipation member 3 is conductive or a combination. More specifically, the heat dissipation member may include one or more of a lead frame, a direct copper bonding (DCB) structure, an active metal brazing (AMB) structure, a passivated aluminum plate, an insulated metal substrate, a conductive clip, or a ceramic material.
[0042] Figure 1CIt is shown that a connection layer 3B is applied on the contact area 3 A. The connection layer 3B may be, for example, a hybrid Ag sintered layer 3B. This refers to combining sintering technology with conventional die attach epoxy materials, wherein the starting material for the sintering process is an epoxy layer filled with silver particles.
[0043] Figure 1D The front side of the heat sink 3 is shown connected to the semiconductor die 2 by coupling the contact area 3A to the back side electrical contact of the semiconductor die 2 via the connection layer 3B. The use of the tape 4 makes the processing unaffected by the stacking tolerances of the stacked semiconductor die 2, connection layer 3B and heat sink 3.
[0044] Figure 1E The molding tool 5 is shown placed over the heat dissipating member 3 and the substrate 1, wherein the opposite ends of the tape 4 extend beyond the molding tool 5. It can be seen that after applying the molding tool 5, a first portion of the tape 4 is disposed between the molding tool 5 and the heat dissipating member 3, and a second portion of the tape 4 is disposed between the molding tool 5 and the substrate layer 1, so that the space between the molding tool 5 and the substrate layer 1 forms a mold cavity.
[0045] Figure 1F The intermediate product after filling the mold cavity with encapsulating material 6, curing the encapsulating material 6, removing the mold 5 and removing the tape 4 is shown. Some mold flash may remain on the tape 4, but it will not affect the release. As shown by the arrow, the mold flash can be well removed by removing the tape 4.
[0046] Figure 1G After the tape 4 is pulled out, the entire assembly can be singulated into a plurality of substantially identical semiconductor packages, such as Figure 1G shown.
[0047] FIG. 2A to FIG. 2D A top view of a plurality of contact regions arranged in a matrix is shown to illustrate an example of a method for manufacturing a semiconductor package.
[0048] Figure 2A A substrate layer 1 comprising a plurality of electrical contact areas 1A is shown. As already mentioned in connection with Fig. 1 , the substrate layer 1 may be, for example, a laminate tape or a printed circuit board.
[0049] Figure 2A It is also shown that the substrate layer 1 is provided with a plurality of regularly arranged electrical contact areas 1A, in particular, a plurality of electrical contact areas 1A arranged in a matrix. On each of these electrical contact areas 1A, a semiconductor die can be connected to the semiconductor die in a manner similar to that of FIG. Figure 1A Connect in the same way as shown in .
[0050] In a similar way, Figure 2BA heat dissipation member 3 is shown with a plurality of contact areas 3A regularly arranged in a matrix, wherein the contact areas 3A arranged in a matrix correspond to a plurality of electrical contact areas 1A arranged in a matrix. Tapes 4 are applied to the contact areas 3A, wherein opposite ends of the tapes 4 extend beyond opposite ends of the heat dissipation member 3.
[0051] Figure 2C It is shown that a suitable connection layer (such as Figure 1C The assembly after the mixed Ag sintered layer 3B is applied to the contact areas 3A, and the contact areas 3A arranged in a matrix are attached to the electrical contact areas 1A arranged in a matrix.
[0052] Figure 2D The assembly after moulding is shown, wherein the bold outline represents the moulding tool 5. Thereafter, an encapsulating material is filled into the mould cavity and, after curing of the encapsulating material, the moulding tool 5 is removed and the tape 4 is pulled off.
[0053] Semiconductor die( FIG. 2A to FIG. 2D The die (not shown) may be, for example, a GaN IGBT (insulated gate bipolar transistor) die including source and gate contacts on its lower surface and a drain contact on its upper surface.
[0054] FIG. 3A to FIG. 3C A top view (A) of multiple pairs of contact areas arranged in a matrix, a perspective view (B) of a pair of two semiconductor dies disposed on a surface layer, and a top view (C) of a finished package are shown.
[0055] Figure 3A The heat dissipation member 3.1 is shown to have a plurality of contact areas 3.1A regularly arranged in a matrix, wherein FIG. 2A to FIG. 2D Compared to the embodiment of the present invention, it is provided that two electrical contact areas 3.1A will be combined and will respectively contact two semiconductor dies, which likewise become part of a common circuit in the finished package. Two such electrical contact areas 3.1A belonging together in this way are shown in the dashed circle. The tape 4 is applied to the contact area 3.1A, wherein the opposite ends of the tape 4 extend beyond the opposite ends of the heat dissipation member 3.1. The material of the heat dissipation member 3.1 is the same as Figures 1A to 1G The heat dissipation component 3 is the same.
[0056] Figure 3BTwo semiconductor dies 12 attached to the substrate layer 11 are shown, wherein the two semiconductor dies 12 will be connected to two electrical contact areas 3.1A. In the finished semiconductor package, the two semiconductor dies can, for example, form a high-side switch and a low-side switch of a half-bridge circuit. For this purpose, other components such as resistors or capacitors can be arranged on the surface layer 11. The two semiconductor dies 12 can, for example, be GaN IGBT (insulated gate bipolar transistor) dies, which include source contacts and gate contacts on their lower surfaces and drain contacts on their upper surfaces.
[0057] Figure 3C The semiconductor package is shown after singulation of the panel into a plurality of semiconductor packages. The tie bars that previously connected the two electrical contact areas 3.1A are removed after singulation, so that the two electrical contact areas 3.1A are now isolated from each other. It can be seen that a distance different from the distance between the two semiconductor dies 12 can be set between the electrical contact areas 3.1A, which can be a measure designed for application purposes, such as providing sufficient creepage distance.
[0058] 4A to 4H A side cross-sectional view is shown for illustrating an example of a method for manufacturing a semiconductor package including a clip.
[0059] Figure 4A The heat dissipation member 13 includes one or more contact areas 13A and one or more contact elements 13B. Figures 1A to 1G The heat dissipation component 3 is the same.
[0060] Figure 4B The assembly is shown after application of a connection layer 13C onto the contact areas 13A and the contact elements 13B. The connection layer 13C may be, for example, a solder layer or a sintered layer, such as those hybrid sintered layers described previously. The application may be performed, for example, by stencil printing.
[0061] Figure 4C The assembly is shown after applying the semiconductor die 12 to one of the contact elements 13B and to the contact region 13A. The semiconductor die 12 may be, for example, a GaN IGBT (insulated gate bipolar transistor) die, which includes a source contact and a gate contact on its lower surface and a drain contact on its upper surface. The source contact may be connected to the contact region 13A and the gate contact may be connected to the left contact element 13B.
[0062] Figure 4D The assembly is shown after a connection layer 12A has been applied to the upper surface of the semiconductor die 12. The connection layer 12A may be, for example, a solder layer.
[0063] Figure 4EThe assembly is shown after the clip 14 has been applied and connected between the semiconductor die 12 and one of the contact elements 13B located on the right.
[0064] Figure 4F The assembly is shown after the tape 15 has been attached to the back side of the clip 14 so that the opposite ends of the tape 15 extend beyond the opposite side edges of the heat dissipating member 13 .
[0065] Figure 4G The assembly is shown after the upper molding tool 16 is placed over one of the contact elements 13B and the clip 14 and the lower molding tool 17 is placed to the back side of the heat dissipation member 13 so that the first portion of the tape 15 is disposed between the upper molding tool 16 and the clip 14 and the second portion of the tape 15 is disposed between the upper molding tool 16 and the contact element 13B, so that the space between the upper molding tool 16 and the lower molding tool 17 forms a mold cavity.
[0066] Figure 4H The assembly is shown after filling the mold cavity with encapsulation material 18 , removing the upper and lower molding tools 16 , 17 after the encapsulation material 18 has cured, and removing the tape 15 .
[0067] Another type of electrical connector may be used instead of the clip 14 .
[0068] Figure 5A and Figure 5B A side cross-sectional view (A) and a top view (B) of an example of a semiconductor package are shown.
[0069] More specifically, Figure 5A A semiconductor package 10 is shown, which includes: a substrate layer 1; a heat dissipation member 3A; two tie bars 3B connected to opposite sides of the heat dissipation member 3A; a semiconductor die 2 arranged on the heat dissipation member 3A, so that the semiconductor die 2 is connected to the substrate layer 1 in a flip-chip configuration; an encapsulation material 6 covering the upper side of the substrate layer 1 and partially embedding the semiconductor die 2, the heat dissipation member 3A and the two tie bars 3B, wherein the main surface of the heat dissipation member 3A away from the semiconductor die 2 and the side surfaces of the two tie bars 3B are exposed to the outside.
[0070] The substrate layer 1 may be, for example, a laminate tape or a printed circuit board and may include contact areas.
[0071] The semiconductor die 2 may be, for example, a GaN IGBT (insulated gate bipolar transistor) die, which includes a source contact and a gate contact on its lower surface and a drain contact on its upper surface. The source contact may be connected to a first contact region of the substrate layer 1, and the gate contact may be connected to a second contact region of the substrate layer 1. As shown in the figure, the connection may be achieved by solder balls.
[0072] The semiconductor package 10 also includes tape adhesive markings in the form of notches 7 in the encapsulation material 6 at the side edges of the heat dissipation member 3A. These notches 7 are caused by the fact that the tape used in the manufacturing process includes an adhesive layer, and when the copper surface is adhered to the adhesive layer, some adhesive will climb onto the copper sidewalls. After removing the tape and adhesive, the notches 7 remain in the position where the adhesive has penetrated.
[0073] Fig. 6A and Figure 6B A side cross-sectional view (A) and a top view (B) of an example of a semiconductor package including a clip are shown.
[0074] More specifically, Fig. 6A A semiconductor package 20 is shown, which includes: a substrate layer 11, which includes a die pad 11A and a contact element 11B; a semiconductor die 12, which is connected to the die pad 11A in a flip-chip configuration; a clip 14, which is connected between the upper surface of the semiconductor die 12 and the contact element 11B; an encapsulation material 16, which covers the upper surface of the substrate layer 11 and partially embeds the semiconductor die 12; wherein the main surface of the clip 14 away from the semiconductor die 12 is exposed to the outside.
[0075] The substrate layer 11 may be, for example, a laminate tape or a printed circuit board, and may include contact areas 11A and 11B.
[0076] The semiconductor die 12 may be, for example, a GaN IGBT (insulated gate bipolar transistor) die, which includes a source contact and a gate contact on its lower surface and a drain contact on its upper surface. The source contact may be connected to a first contact region 11A of the substrate layer 11, and the gate contact may be connected to a second contact region 11B of the substrate layer 11.
[0077] The semiconductor package 20 also includes adhesive markings in the form of notches 17 in the encapsulation material 16 at the side edges of the electrical connector 14. Figure 5A Like the notches 7 shown, these notches 17 are also caused by the fact that the tape used in the manufacturing process includes an adhesive layer, and when the copper surface is adhered to the adhesive layer, some adhesive will creep onto the copper sidewalls. After removing the tape and adhesive, the notches 17 remain in the locations where the adhesive has penetrated.
[0078] Another type of electrical connector may be used instead of the clip 14 .
[0079] Example
[0080] Specific examples of the present disclosure are described below.
[0081] Example 1 is a method for manufacturing one or more semiconductor packages, the method comprising: providing a substrate layer including one or more electrical contact areas; connecting a semiconductor die to one of the electrical contact areas; providing a heat dissipation component including one or more contact areas; attaching a tape to the back side of the heat dissipation component so that opposite ends of the tape extend beyond opposite side edges of the heat dissipation component; connecting the front side of the heat dissipation component to the semiconductor die by coupling at least one contact area to the semiconductor die; forming a mold cavity by placing a molding tool over the heat dissipation component and the substrate layer, wherein opposite ends of the tape extend beyond the molding tool so that the tape can be removed from outside the molding tool; filling the mold cavity with encapsulation material; and removing the tape.
[0082] Example 2 is the method according to Example 1, further comprising singulating the assembly into two or more semiconductor packages after pulling out the tape.
[0083] Example 3 is a method for manufacturing a plurality of semiconductor packages according to Example 2, the method further comprising providing a substrate layer having a plurality of regularly arranged electrical contact areas.
[0084] Example 4 is a method for manufacturing a plurality of semiconductor packages according to Example 3, further comprising providing a heat dissipation member having a plurality of regularly arranged contact areas.
[0085] Example 5 is the method according to Example 3 or 4, wherein the regularly arranged plurality of contact areas comprises a plurality of contact areas arranged in a matrix.
[0086] Example 6 is the method of example 4 or 5, wherein the plurality of contact regions comprises a plurality of pairs of contact regions.
[0087] Example 7 is a method according to any of the preceding examples, wherein the substrate layer is one or more of a laminate layer, a printed circuit board (PCB), a lead frame, a direct copper bonding (DCB) structure, an active metal brazing (AMB) structure, or an insulated metal substrate (IMS).
[0088] Example 8 is a method according to any of the preceding examples, wherein the heat dissipation component comprises one or more of a lead frame, a direct copper bonding (DCB) structure, an active metal brazing (AMB) structure, a passivated aluminum plate, an insulated metal substrate, a conductive clip, or a ceramic material.
[0089] Example 9 is a method according to any of the preceding examples, further comprising providing the tape so that after the molding tool is placed over the heat dissipation member and the substrate layer, the tape extends outside the molding tool to a length in the range of 2 mm to 4 mm.
[0090] Example 10 is a method according to any of the preceding examples, wherein the semiconductor die comprises one or more of a semiconductor transistor die, a power transistor die, a GaN transistor die, or a SiC transistor die.
[0091] Example 11 is a method comprising: providing a heat dissipation component comprising one or more contact areas and one or more contact elements; applying one or more semiconductor dies to the one or more contact areas; connecting an electrical connector between one of the contact elements and the semiconductor die; attaching a tape to the back side of the electrical connector so that opposite ends of the tape extend beyond opposite side edges of the heat dissipation component; placing an upper molding tool over one of the contact elements and the electrical connector and placing a lower molding tool to the back side of the heat dissipation component so that a first portion of the tape is disposed between the upper molding tool and the electrical connector and a second portion of the tape is disposed between the upper molding tool and the contact element, so that a space between the upper molding tool and the lower molding tool forms a mold cavity; filling the mold cavity with an encapsulation material; and removing the tape.
[0092] Example 12 is a method according to Example 11, which also includes placing two or more semiconductor dies on two or more contact areas; connecting two or more electrical connectors between one of the contact elements and the two or more semiconductor dies; placing an upper molding tool over the electrical connector and the two outermost contact elements; and after pulling out the tape, singulating the assembly into two or more semiconductor packages.
[0093] Example 13 is the method of example 11 or 12, wherein each electrical connector comprises a clip.
[0094] Example 14 is a method according to any of Examples 11-13, wherein the semiconductor die includes one or more of a semiconductor transistor die, a power transistor die, a GaN transistor die, or a SiC transistor die.
[0095] Example 15 is a semiconductor package, comprising: a substrate layer; a heat dissipation member; at least one tie rod connected to a side of the heat dissipation member; a semiconductor die disposed on the heat dissipation member so that the semiconductor die is connected to the substrate layer in a flip-chip configuration; an encapsulation material covering the top of the substrate layer and partially embedding the semiconductor die, the heat dissipation member and the tie rod, wherein the main surface of the heat dissipation member away from the semiconductor die and the side of the tie rod are exposed to the outside.
[0096] Example 16 is the semiconductor package according to Example 15, further comprising two tie bars connected to opposite sides of the heat dissipation member and including sides exposed to the outside.
[0097] Example 17 is the semiconductor package according to Example 15 or 16, further comprising an adhesive marking in the form of a notch in the encapsulation material at a side edge of the heat dissipation member.
[0098] Example 18 is a semiconductor package, comprising: a substrate layer including a die pad and a contact element; a semiconductor die connected to the die pad in a flip-chip configuration; an electrical connector connected between the top of the semiconductor die and the contact element; an encapsulation material covering the top of the substrate layer and partially embedded in the semiconductor die; wherein a main surface of the electrical connector away from the semiconductor die is exposed to the outside.
[0099] Example 19 is the semiconductor package according to Example 18, wherein the electrical connector includes a clip.
[0100] Example 20 is the semiconductor package of Example 18 or 19, further comprising an adhesive marking in the form of a notch in the encapsulation material at a side edge of the electrical connector.
[0101] Although specific embodiments have been shown and described herein, it will be appreciated by those skilled in the art that various alternative and / or equivalent embodiments may be substituted for the specific embodiments shown and described without departing from the scope of the present disclosure. The present application is intended to cover any modifications or variations of the specific embodiments discussed herein. Therefore, the present disclosure is intended to be limited only by the claims and their equivalents.
Claims
1. A method for manufacturing one or more semiconductor packages, the method comprising: - providing a substrate layer (1) comprising one or more electrical contact areas (1A); - connecting the semiconductor die (2) to one of the electrical contact areas (1A); - providing a heat dissipation member (3) comprising one or more contact areas (3A); - attaching a tape (4) to the back side of the heat dissipating member (3) such that opposite ends of the tape (4) extend beyond opposite side edges of the heat dissipating member (3); - connecting the front side of the heat dissipation member (3) to the semiconductor die (2) by coupling at least one contact area to the semiconductor die (2); - forming a mould cavity by placing a moulding tool (5) over the heat dissipating member (3) and the substrate layer (1), wherein opposite ends of the strip (4) extend outside the moulding tool (5) so that the strip (4) can be removed from outside the moulding tool (5); - filling the mold cavity with encapsulating material (6); and - Remove the belt (4).
2. The method according to claim 1, wherein the method is used to manufacture two or more semiconductor packages, wherein: The method further comprises: After the tape (4) has been pulled off, the assembly is singulated into the two or more semiconductor packages.
3. The method according to claim 2, wherein the method is used to manufacture a plurality of semiconductor packages, wherein: The method further comprises: A substrate layer (1) having a plurality of regularly arranged electrical contact areas (1A) is provided.
4. The method according to claim 3, wherein the method is used to manufacture a plurality of semiconductor packages, wherein: The method further comprises: A heat dissipation member (3) having a plurality of regularly arranged contact areas (3A) is provided.
5. The method according to claim 3 or 4, wherein: The regularly arranged plurality of contact areas (3A) include a plurality of contact areas (3A) arranged in a matrix.
6. The method according to claim 4 or 5, wherein: The plurality of contact areas (3.1A) include a plurality of pairs of contact areas (3.1A).
7. A method according to any one of the preceding claims, wherein: The substrate layer (1) is one or more of a laminate layer, a printed circuit board (PCB), a lead frame, a direct copper bonding (DCB) structure, an active metal brazing (AMB) structure or an insulated metal substrate (IMS).
8. A method according to any one of the preceding claims, wherein: The heat dissipation component (3) comprises one or more of a lead frame, a direct copper bonding (DCB) structure, an active metal brazing (AMB) structure, a passivated aluminum plate, an insulated metal substrate, a conductive clip or a ceramic material.
9. A method according to any one of the preceding claims, wherein: The method further comprises: The tape (4) is provided such that after the moulding tool (5) is placed over the heat dissipating member (3) and the substrate layer (1), the length of the tape (4) extending outside the moulding tool (5) is in the range of 2 mm to 4 mm.
10. A method according to any one of the preceding claims, wherein: The semiconductor die (2) includes one or more of a semiconductor transistor die, a power transistor die, a GaN transistor die or a SiC transistor die.
11. A method for manufacturing a plurality of semiconductor packages, the method comprising: - providing a heat dissipation member (13) comprising one or more contact areas (13A) and one or more contact elements (13B); - applying one or more semiconductor dies (12) onto the one or more contact areas (13A); - connecting an electrical connector (14) between one of the contact elements (13B) and the semiconductor die (12); - attaching a tape (15) to the back side of the electrical connector (14) such that opposite ends of the tape (15) extend beyond opposite side edges of the heat dissipating member (13); - placing an upper molding tool (16) over one of the contact elements (13B) and the electrical connector (14), and placing a lower molding tool (17) to the back side of the heat dissipation member (13), so that a first portion of the tape (15) is disposed between the upper molding tool (16) and the electrical connector (14) and a second portion of the tape (15) is disposed between the upper molding tool (16) and the contact element (13B), so that the space between the upper molding tool (16) and the lower molding tool (17) forms a molding cavity; - filling the mould cavity with encapsulating material (18); and - Remove the belt (15).
12. The method according to claim 11, wherein the method is used to manufacture two or more semiconductor packages, wherein: The method further comprises: - placing two or more semiconductor dies (12) on two or more contact areas (13A); - connecting two or more electrical connectors (14) between one of the contact elements (13B) and the two or more semiconductor dies (12); - placing an upper moulding tool (16) over the electrical connector (14) and the two outermost contact elements (13B); and After pulling off the tape (15), singulating the assembly into the two or more semiconductor packages.
13. The method according to claim 11 or 12, wherein: Each electrical connector (14) includes a clip (14).
14. The method according to any one of claims 11 to 13, wherein: The semiconductor die (12) includes one or more of a semiconductor transistor die, a power transistor die, a GaN transistor die, or a SiC transistor die.
15. A semiconductor package (10), comprising: - a substrate layer (1); - heat dissipation member (3A); - at least one tie rod (3B) connected to the side of the heat dissipating member (3A); - a semiconductor die (2) disposed on the heat dissipation member (3A) such that the semiconductor die (2) is connected to the substrate layer (1) in a flip-chip configuration; - an encapsulation material (6) covering the upper side of the substrate layer (1) and partially embedding the semiconductor die (2), the heat dissipation member (3A) and the tie bars (3B), - wherein the main surface of the heat dissipation member (3A) away from the semiconductor die (2) and the side surface of the tie bar (3B) are exposed to the outside.
16. The semiconductor package (10) according to claim 15, wherein: The semiconductor package (10) further comprises: - Two tie rods (3B) connected to opposite sides of the heat dissipating member (3A) and including sides exposed to the outside.
17. The semiconductor package (10) according to claim 15 or 16, wherein: The semiconductor package (10) further comprises: - Adhesive markings in the form of notches (7) in the encapsulation material at the side edges of the heat dissipating member (3A).
18. A semiconductor package (20), comprising: - a substrate layer (11) comprising a die pad (11A) and contact elements (11B); - a semiconductor die (12) connected to the die pad (11A) in a flip chip configuration; - an electrical connector (14) connected between the upper side of the semiconductor die (12) and the contact element (11B); - an encapsulation material (16) covering the upper side of the substrate layer (11) and partially embedding the semiconductor die (12); - wherein a main surface of the electrical connector (14) away from the semiconductor die (12) is exposed to the outside.
19. The semiconductor package (20) according to claim 18, wherein: The electrical connector (14) includes a clip (14).
20. The semiconductor package (20) according to claim 18 or 19, wherein: The semiconductor package (20) further comprises: - Adhesive markings in the form of notches (17) in the encapsulation material (16) at the side edges of the electrical connector (14).