Wafer test result screening method and system with tightened correction

Abstract

The application provides a wafer test result screening method and system with strict correction, which comprises the following steps: identifying layout data of chip layout on a wafer; identifying potential singular points of resource information to obtain singular point layout information of chip layout in a chip placement unit domain, and determining transient response data of deviation correction response of the wafer during chip layout test; generating continuous failure characteristics on adjacent bits of the chip layout, and determining dynamic response data of deviation correction response of the wafer during chip layout test; and determining feedback correction indexes of the wafer during chip layout test according to the transient response data and the dynamic response data, and then filtering chips on the wafer for computer chip design with strict correction. The above scheme screens wafer test results based on feedback correction indexes, and can improve the accuracy of strict correction screening during wafer test while reducing the influence of performance deviation identification deficiency.

Description

Technical Field

[0001] The present application relates to the field of semiconductor product manufacturing technology, and more specifically, to a method and system for rigorous correction screening of wafer test results. Background Art

[0002] Conductor product manufacturing refers to the process of processing semiconductor materials (such as silicon, gallium arsenide, etc.) into electronic components and integrated circuits. This process includes multiple steps, such as wafer manufacturing, doping, oxidation, photolithography, etching, deposition and packaging. Its function is to convert basic materials into functional components that can be used in electronic devices (such as computers, mobile phones, sensors, etc.) to meet the needs of modern electronic technology.

[0003] The existing method for tightening and correcting the screening of wafer test results usually includes three main stages: data collection, analysis and screening. First, in the data collection stage, each chip is fully tested using automated test equipment to collect key performance-related indicators such as voltage, power consumption, temperature and transient response. Then, statistical and data processing techniques are applied to conduct in-depth analysis of the collected data to identify performance indicators related to failure modes. By comparing the current test results with historical data, manufacturers can set strict thresholds based on experience to ensure that only chips that meet high standards are screened out. Finally, the performance data of all chips are compared with the set standards, and any chips that do not meet the standards are screened out. All chips will be marked as failed, but in the existing wafer test results using tightened correction screening, due to the lack of an effective dynamic feedback control mechanism, key operating parameters cannot be monitored in real time. It relies on static thresholds and historical data for evaluation, which limits its ability to adapt to complex production environments. As a result, some failed chips are not accurately eliminated during the testing phase, resulting in insufficient recognition of performance deviations during tightened correction screening of wafers, reducing the accuracy of tightened correction screening during wafer testing. Therefore, how to improve the accuracy of tightened correction screening during wafer testing under the influence of insufficient recognition of performance deviations during tightened correction screening of wafers is a problem faced by the industry. Summary of the Invention

[0004] The present application provides a method and system for tightened correction screening of wafer test results, which can improve the accuracy of tightened correction screening during wafer testing under the influence of insufficient recognition of performance deviations caused by tightened correction screening of wafers.

[0005] In a first aspect, the present application provides a method for screening wafer test results using a stricter correction method, comprising the following steps:

[0006] Perform chip layout testing on wafers used for computer chip design to identify the layout data of the chip layout on the wafer;

[0007] Correcting and constraining the layout data to obtain a constraint distance of chip layout in a chip layout on a wafer, and determining an element offset between chips in a chip placement unit domain according to the constraint distance;

[0008] Obtaining resource information occupied by a wafer used for computer chip design during chip layout planning, identifying potential singular points on the resource information, obtaining singular point layout information of the chip layout in a chip placement unit domain, and determining transient response data for performing deviation correction response during chip layout testing on the wafer using the singular point layout information and the component offset;

[0009] generating continuous failure characteristics on adjacent bits of a chip in a chip layout based on netlist connection information of chip functional connections after chip layout of a wafer used for computer chip design, and determining dynamic response data for deviation correction response during chip layout testing on the wafer based on the continuous failure characteristics;

[0010] A feedback correction index of a wafer used for computer chip design during chip layout testing is determined based on the transient response data and the dynamic response data, and chips on the wafer used for computer chip design that fail are strictly filtered based on the feedback correction index.

[0011] In some embodiments, performing correction and constraint on the layout data to obtain a constraint distance of the chip layout in the chip layout on the wafer specifically includes:

[0012] Determining a layout trajectory of a chip in a chip layout on a wafer according to the layout data;

[0013] Determine the layout constraint information of the chip layout on the wafer;

[0014] The layout trajectory is adjusted using the layout constraint information to obtain a constraint distance of the chip layout in the chip layout diagram on the wafer.

[0015] In some embodiments, determining the component offset between chips in the chip placement unit domain according to the constraint distance specifically includes:

[0016] Determining alignment information of the chip in the chip placement unit using the constraint distance;

[0017] determining a matching position of the chip on the chip placement unit;

[0018] The component offset is determined based on the alignment information and the matching position.

[0019] In some embodiments, identifying potential singular points on the resource information to obtain singular point layout information of the chip layout in the chip placement unit domain specifically includes:

[0020] determining singular point position parameters of chip layout in the chip placement unit domain according to the resource information;

[0021] Determining a layout confidence of a chip layout in a chip placement unit domain using the singular point position parameters;

[0022] The chip placement unit domain is checked using the layout confidence value to obtain singular point layout information of the chip layout in the chip placement unit domain.

[0023] In some embodiments, determining transient response data for performing deviation correction response during chip layout testing on a wafer using the singular point layout information and the component offset specifically includes:

[0024] Determining reference position information for performing deviation correction response during chip layout testing on a wafer based on the singular point layout information;

[0025] Determining layout rules for performing deviation correction responses during chip layout testing on a wafer based on the component offset;

[0026] Transient response data for performing deviation correction response is determined by using the reference position information and the layout rule.

[0027] In some embodiments, determining a feedback correction index of a wafer for computer chip design during chip layout testing based on the transient response data and the dynamic response data specifically includes:

[0028] Determining layout feedback data of a wafer used for computer chip design during chip layout testing using the transient response data;

[0029] Determining, using the dynamic response data, a tightening correction feature of a wafer used for computer chip design during chip layout testing;

[0030] A feedback correction index of the wafer during chip layout testing is determined according to the layout feedback data and the tightening correction feature.

[0031] In some embodiments, the image information is converted into electronic layout data by using dedicated layout extraction software (such as a CAD tool or an EDA tool).

[0032] In a second aspect, the present application provides a system for screening wafer test results with tightened corrections, comprising:

[0033] an identification module for performing chip layout testing on wafers used for computer chip design and identifying layout data of the chip layout on the wafer;

[0034] a processing module configured to correct and constrain the layout data to obtain a constraint distance of a chip layout in a chip layout on a wafer, and determine an element offset between chips in a chip placement unit domain according to the constraint distance;

[0035] The processing module is further configured to obtain resource information occupied by a wafer used for computer chip design during chip layout planning, identify potential singular points on the resource information, obtain singular point layout information of the chip layout in the chip placement unit domain, and determine transient response data for deviation correction response during chip layout testing on the wafer using the singular point layout information and the component offset;

[0036] The processing module is further configured to generate continuous failure characteristics on adjacent bits of a chip in a chip layout based on netlist connection information of chip functional connections after chip layout of a wafer used for computer chip design, and determine dynamic response data for deviation correction response during chip layout testing on the wafer based on the continuous failure characteristics;

[0037] An execution module is configured to determine a feedback correction index of a wafer for computer chip design during chip layout testing based on the transient response data and the dynamic response data, and to strictly filter out failed chips on the wafer for computer chip design based on the feedback correction index.

[0038] In a third aspect, the present application provides a computer device comprising a memory and a processor, wherein the memory stores a code, and the processor is configured to obtain the code and execute the above-mentioned method for tightened correction screening of wafer test results.

[0039] In a fourth aspect, the present application provides a computer-readable storage medium storing a computer program, which, when executed by a processor, implements the above-mentioned method for tightening correction screening of wafer test results.

[0040] The technical solutions provided by the embodiments disclosed in this application have the following beneficial effects:

[0041] The present application provides a method and system for rigorous correction screening of wafer test results. First, a chip layout test is performed on a wafer used for computer chip design to identify the layout data of the chip layout on the wafer. Then, correction constraints are applied to the layout data to obtain the constraint distance of the chip layout in the chip layout on the wafer, and the component offset between chips in the chip placement unit domain is determined based on the constraint distance. Secondly, resource information occupied by the wafer used for computer chip design during chip layout planning is obtained, potential singular points are identified on the resource information, and singular point layout information of the chip layout in the chip placement unit domain is obtained. Through the singular point layout information and the The method comprises the following steps: determining transient response data for performing deviation correction response during chip layout testing on a wafer based on the component offset; then, generating continuous failure characteristics on adjacent bits of a chip in a chip layout diagram based on the netlist connection information of chip functional connections after chip layout of the wafer for computer chip design; and determining dynamic response data for performing deviation correction response during chip layout testing on the wafer based on the continuous failure characteristics; finally, determining feedback correction indicators of the wafer for computer chip design during chip layout testing based on the transient response data and the dynamic response data, and strictly filtering out failed chips on the wafer for computer chip design based on the feedback correction indicators.

[0042] Thus, the present application performs stricter screening during chip layout testing of wafers used for computer chip design. First, by efficiently identifying and analyzing the wafer layout data, the integrity and accuracy of information in the design process are ensured. Then, correction constraints are implemented to make the chip layout more physically compatible, reduce interference between chips, improve the overall stability of the layout, reduce the risk of potential failures, and ensure chip reliability. Third, by identifying potential singularities in resource information, bottlenecks can be proactively identified and avoided during the layout planning stage, thereby optimizing resource allocation and improving the efficiency and controllability of the chip layout process. Then, the generated transient response data provides a dynamic perspective on the performance of the chip under different operating conditions, enabling a better understanding of chip performance, improving the adaptability of the design, and ensuring stability and performance consistency in actual applications. Among them, the analysis of dynamic response data makes it easier to analyze the continuous failure characteristics of adjacent bits of the chip. Finally, by formulating feedback correction indicators, more accurate failure screening can be achieved, improving the accuracy and effectiveness of screening, ensuring that only chips that meet strict standards enter the production process, compensating for the impact of insufficient identification of performance deviations during strict correction screening of wafers, and thereby improving the accuracy of strict correction screening during wafer testing. BRIEF DESCRIPTION OF THE DRAWINGS

[0043] Figure 1 is an exemplary flow chart of a method for screening wafer test results using a stricter correction according to some embodiments of the present application;

[0044] Figure 2 is a schematic diagram of a bathtub curve of chip failure according to some embodiments of the present application;

[0045] Figure 3 is a schematic diagram of the basic process of chip design according to some embodiments of the present application;

[0046] Figure 4 is a schematic structural diagram of a system for screening wafer test results with tightened correction according to some embodiments of the present application;

[0047] Figure 5 It is a structural diagram of a computer device for implementing a stricter correction screening method for wafer test results according to some embodiments of the present application. DETAILED DESCRIPTION

[0048] In order to better understand the technical solution of the present application, the technical solution of the present application will be described in detail below with reference to the accompanying drawings and specific implementation methods.

[0049] refer to Figure 1 , which is an exemplary flow chart of a method for screening wafer test results using stricter correction according to some embodiments of the present application. The method 100 for screening wafer test results using stricter correction mainly includes the following steps:

[0050] In step 101, a chip layout test is performed on a wafer used for computer chip design to identify layout data of the chip layout on the wafer.

[0051] In specific implementation, first, high-precision scanning equipment, such as optical microscopes, electron beam microscopes or laser scanners, is used to scan the entire wafer surface. These devices can capture detailed images of the wafer surface, especially geometric features such as the position, shape and size of the chip; then, after the scanning is completed, the system will generate multiple high-resolution images. In order to ensure the accuracy of the data, image preprocessing is required, including denoising, contrast enhancement and edge detection; finally, the image information can be converted into layout data through dedicated layout extraction software (such as CAD tools or EDA tools), that is, the layout data of the chip layout on the wafer is obtained.

[0052] It should be noted that the layout data of the chip layout on the wafer in this application represents the electronic data of the geometric information and spatial relationship of the chip layout on the wafer. These data usually include the physical position, shape, size of the chip, as well as the distance and arrangement between chips, providing accurate spatial reference for chip manufacturing and testing, ensuring that in the actual manufacturing process, the chips are arranged according to the design specifications to avoid position deviation or interconnection problems.

[0053] In step 102, the layout data is corrected and constrained to obtain a constraint distance of the chip layout in the chip layout layout on the wafer, and the component offset between the chips in the chip placement unit domain is determined according to the constraint distance.

[0054] In some embodiments, reference Figure 2 As shown in the figure, this is a basic process diagram of chip design. First, a layer of photoresist is applied to the surface of the wafer (or substrate) and dried. The dried wafer is transferred to the photolithography machine. Light passes through a mask to project the pattern on the mask onto the photoresist on the surface of the wafer to achieve exposure and stimulate photochemical reaction. The exposed wafer is baked for the second time, which is the so-called post-exposure baking. Post-baking makes the photochemical reaction more complete. Finally, the developer is sprayed onto the photoresist on the surface of the wafer to develop the exposure pattern. After development, the pattern on the mask is It is retained on the photoresist; coating, baking and development are all completed in the spreader and developer, and exposure is completed in the photolithography machine. The spreader and developer and the photolithography machine are generally operated online, and the wafer is transferred between each unit and machine by a robot. The entire exposure and development system is closed, and the wafer is not directly exposed to the surrounding environment to reduce the impact of harmful components in the environment on the photoresist and photochemical reactions. After several processes, grid-shaped grains are formed on the wafer, and the electrical characteristics of each grain are tested by needle testing.

[0055] In some embodiments, reference Figure 3 As shown in the figure, this is a schematic diagram of the chip failure bathtub curve. With the rapid development of the electronics industry towards intelligence, the demand for chips is becoming more and more extensive. The special application scenarios of chips have extremely high requirements for safety and reliability. Therefore, strict screening is performed at the test end to screen out early failure chips; the early failure period is a stage with a relatively high failure rate. The cause of failure is usually design defects, manufacturing abnormalities or material defects in the chip. The purpose of strict testing screening is to screen out defective chips before the chip is shipped. These defective chips are likely to be early failure chips (such as Figure 3 The failure rates of chips on the timeline include early failure rate, accidental failure rate and loss failure rate; common tightened screening includes stacked wafer map, aging and other tightened screening items.

[0056] In some embodiments, the layout data is corrected and constrained to obtain the constraint distance of the chip layout in the chip layout on the wafer by using the following steps:

[0057] Determining a layout trajectory of a chip in a chip layout on a wafer according to the layout data;

[0058] Determine the layout constraint information of the chip layout on the wafer;

[0059] The layout trajectory is adjusted using the layout constraint information to obtain a constraint distance of the chip layout in the chip layout diagram on the wafer.

[0060] In a specific implementation, first, image processing technology is used to extract the geometric shape and position of the chip from the layout data, and the movement trajectory of the chip is calculated. This can be achieved by performing edge detection and tracking algorithms on the chip contours to generate the path of each chip during the layout process, i.e., the layout trajectory. Then, the design rules and manufacturing processes related to the chip layout are analyzed to identify the layout constraint information that needs to be followed, such as minimum spacing, maximum spacing, and electrical isolation requirements. This can be achieved through a systematic analysis of the design documents and process specifications. For example, the minimum spacing requirement is 5 microns, that is, the distance between any two chips cannot be less than this value. Finally, the identified layout constraint information is applied to the layout trajectory of the chip, and an optimization algorithm (such as particle swarm optimization or simulated annealing) is used to adjust the chip position to ensure that the position of each chip meets the constraint requirements. The adjustment can be iteratively performed until the layout of all chips meets the constraint conditions, and the output result is used as the constraint distance of the chip layout in the chip layout on the wafer. In other embodiments, other methods can also be used to determine the constraint distance of the chip layout in the chip layout on the wafer, which is not limited here.

[0061] It should be noted that the layout trajectory in this application represents the path of the chip from the starting position to the final position during the chip layout process on the wafer; the layout constraint information represents various restrictions related to the chip layout specified in the chip design, such as spacing, angles, etc., which can ensure the reasonable layout of the chip and reduce the failure rate; the constraint distance represents the minimum or maximum distance between chips in the chip layout that meets the manufacturing and electrical design requirements, which helps to ensure the rationality of the chip layout and avoid electrical problems caused by improper distance.

[0062] In some embodiments, determining the component offset between chips in the chip placement unit domain according to the constraint distance can be achieved by using the following steps:

[0063] Determining alignment information of the chip in the chip placement unit using the constraint distance;

[0064] determining a matching position of the chip on the chip placement unit;

[0065] The component offset is determined based on the alignment information and the matching position.

[0066] In specific implementation, first, the ideal placement position of each chip is identified, and the alignment information of the chip in the placement unit is determined. This can be achieved through geometric measurement and coordinate system comparison to ensure that each chip can be correctly placed within the specified constraint range. For example, the ideal position of chip A is (100, 200), and the error range allowed by the constraint distance is ±5 microns. The alignment information of chip A will include all possible positions within this range. Then, on the chip placement unit, the matching position of the chip is determined by identifying the relationship between the current chip position and the ideal position. This can be done through image recognition or sensor detection technology, and the placement status of the chip can be monitored in real time. Finally, the alignment information is compared with the matching position, and the deviation between the actual position and the ideal position is calculated. This can be achieved through simple coordinate difference calculation to obtain the specific component offset of each chip. For example, the matching position of chip A is (100.2, 199.8), and the ideal position is (100, 200). The component offset is (0.2, -0.2), which will not be repeated here.

[0067] It should be noted that in this application, the alignment information represents the ideal position and allowable deviation range specified during the chip placement process to ensure the correct alignment of the chip, which can improve the accuracy and reliability of chip placement; the matching position represents the correspondence between the actual chip and the ideal chip position in the chip placement unit; the component offset is a numerical value that describes the difference between the actual chip position and the ideal design position, which can provide a basis for chip position correction and ensure the accuracy of the layout.

[0068] In step 103, resource information occupied by a wafer used for computer chip design during chip layout planning is obtained, potential singularities are identified on the resource information, and singularity layout information of the chip layout in the chip placement unit domain is obtained. Transient response data for deviation correction response during chip layout testing on the wafer is determined based on the singularity layout information and the component offset.

[0069] In specific implementation, obtaining resource information occupied by wafers used for computer chip design during chip layout planning can be achieved in the following manner, namely: first, clarifying the resource types that need to be paid attention to in chip layout, such as power requirements, heat distribution, material usage, and space occupancy, and then using design tools (such as EDA software) to comprehensively analyze the chip design and extract the resource requirements of each chip unit; then, based on the collected data, constructing a resource model of the chip layout, which includes the resource requirements and mutual relationships of each chip unit, and can display the resource occupancy in the layout through a graphical interface; finally, using a simulation tool, analyzing the resource model to evaluate the resource utilization efficiency in the layout planning, for example, simulating the power requirements and heat distribution of the chip under different workloads to identify potential resource bottlenecks, and then compiling the analysis results into a report, and obtaining the resource information occupied during chip layout planning by reading the analysis result report. In other embodiments, other methods can also be used to determine the resource information occupied during chip layout planning, which is not limited here.

[0070] It should be noted that in this application, resource information refers to relevant data such as power supply, thermal management, material usage, space occupancy and interconnection requirements required by each chip unit when planning chip layout, which is used to evaluate the feasibility and performance of the chip design to ensure the rational use of resources during the layout process, avoid potential performance bottlenecks and overheating problems, and thus optimize the overall performance and stability of the chip.

[0071] In some embodiments, identifying potential singular points of the resource information and obtaining singular point layout information of the chip layout in the chip placement unit domain may be achieved by using the following steps:

[0072] determining singular point position parameters of chip layout in the chip placement unit domain according to the resource information;

[0073] Determining a layout confidence of a chip layout in a chip placement unit domain using the singular point position parameters;

[0074] The chip placement unit domain is checked using the layout confidence value to obtain singular point layout information of the chip layout in the chip placement unit domain.

[0075] In the specific implementation, first, based on the resource information, the resource requirements and usage of each chip unit in the layout are analyzed to identify the key locations that may cause performance degradation or failure. The singularity location usually refers to the area with excessive resource utilization, concentrated heat, or excessive power demand, that is, the singularity location parameters are obtained. For example, if the power demand of a certain area exceeds the maximum carrying capacity of the design, the location is identified as a singularity; then, through data analysis and modeling, the layout confidence of each singularity is calculated. Statistical methods or machine learning techniques can be used to quantify the resource allocation, heat distribution, etc. at the singularity to obtain the layout confidence. For example, regression analysis is used to calculate the relationship between the resource utilization and failure rate of a singularity, so as to determine its layout confidence; finally, the calculated layout confidence is applied to the chip placement unit domain, checked, and the area that needs improvement or adjustment is identified. The layout confidence of the singularity position is verified through simulation to ensure that each singularity can operate normally within the design specification. No further details will be given here.

[0076] It should be noted that, in this application, the singularity position parameter represents the key positions and related features that cause performance bottlenecks or failures in the chip layout, which helps to reveal potential problems in the chip layout for subsequent optimization; the layout confidence value represents the indicator used to quantify the performance stability and reliability in the chip layout area in the chip layout, which helps to evaluate the risk level of the singularity and provide a basis for subsequent decision-making; the singularity layout information is a data set that describes the resource usage and potential risks of key positions in the chip layout, which can provide a data basis for subsequent optimization and design adjustments to ensure the reliability of the layout.

[0077] In some embodiments, determining transient response data for deviation correction during chip layout testing on a wafer using the singular point layout information and the component offset can be achieved by using the following steps:

[0078] Determining reference position information for performing deviation correction response during chip layout testing on a wafer based on the singular point layout information;

[0079] Determining layout rules for performing deviation correction responses during chip layout testing on a wafer based on the component offset;

[0080] Transient response data for performing deviation correction response is determined by using the reference position information and the layout rule.

[0081] In the specific implementation, first, based on the singularity layout information, identify the chip positions that need to be focused on during the test process. These positions are usually areas with high resource utilization and may cause performance problems or failures. Use design tools to extract the coordinate information of these reference positions from the singularity layout information, that is, obtain the reference position information. For example, if the singularity layout information indicates that the distance between chip A and chip B is too close, the center point coordinates of the two chips will be used as the reference position information; then, use component offset to analyze the actual distance and ideal distance between each chip, and formulate corresponding layout rules. The rules should include the allowable deviation range, minimum spacing and other design Limitations ensure that areas that require correction can be effectively identified during the test process. For example, if the actual distance between component offset display chip C and chip D is less than the design requirement of 5 microns, corresponding layout rules need to be formulated to enforce this distance. The details will not be repeated here. Finally, dynamic simulation and simulation are performed in combination with reference position information and layout rules to generate transient response data. Numerical calculation methods such as finite element analysis (FEA) or time domain analysis can be used to simulate the behavior of the chip under specific conditions and evaluate its response to deviation correction. For example, simulation software can be used to simulate the transient current response of the chip under different load conditions to evaluate its performance changes.

[0082] It should be noted that in this application, the reference position information represents the key chip position and its coordinate data used for deviation correction in the chip layout test; the layout rules represent the design constraints and standards formulated in the chip layout to ensure performance and reliability; the transient response data is the dynamic behavior data that describes the chip's response to deviation correction under specific conditions, which helps to evaluate and optimize chip performance and improve the stability and reliability of the design.

[0083] In step 104, a continuous failure signature on adjacent bits of a chip in a chip layout is generated based on the netlist connection information of chip functional connections after chip layout of a wafer used for computer chip design. Dynamic response data for deviation correction response during chip layout testing on the wafer is determined based on the continuous failure signature.

[0084] In some embodiments, generating continuous failure features on adjacent bits of a chip in a chip layout based on the netlist connection information of chip functional connections after chip layout of a wafer used for computer chip design can be achieved by the following steps:

[0085] Determine the layout marking data on adjacent bits of the chip in the chip layout layout after the chip layout is performed on the wafer used for computer chip design;

[0086] Determine the netlist connection information of chip functional connections after chip layout;

[0087] Continuous failure features on adjacent bits of a chip in a chip layout are determined based on the layout annotation data and the netlist connection information.

[0088] In the specific implementation, first, the layout annotation data is extracted from the chip layout, including the geometric shape, size and relationship between adjacent bits of each chip. By using graphics processing and CAD tools, the connection lines and annotation information between adjacent chips are identified to understand the spatial relationship of each chip in the layout, that is, the layout annotation data is obtained. For example, the design software is used to extract the position information of each chip and the annotations of their mutual connections, such as chip A is located at (100,200) and the connection characteristics with chip B; then, the netlist information of the chip functional connection is collected and analyzed. This information includes the electrical connection relationship between the functional units of the chip. By establishing and parsing the netlist, the interconnection between the chips and their functional associations are identified. For example, from the design The software extracts the netlist and identifies that the output of chip A is connected to the input of chip B, and these connections are functionally interdependent. Finally, the extracted layout annotation data is combined with the netlist connection information to analyze the failure mode between adjacent bits. This can be done through methods such as fault tree analysis or electrical simulation to identify features that may cause functional failure between adjacent chips under specific conditions, such as signal interference, overload, etc. In other embodiments, other methods can also be used to determine the continuous failure features on adjacent bits of the chip in the chip layout, which is not limited here. For example, chip A and chip B are placed adjacent to each other at high temperature, and an error occurs in a signal pin of chip A, which may cause chip B to fail. At this time, their adjacent relationship is analyzed and the failure features are extracted.

[0089] It should be noted that in this application, the layout annotation data represents the electronic information describing the chip's geometric features, position, and adjacent relationships in the chip layout layout, which can provide the spatial structure and connection status of the chip layout; the netlist connection information is a data structure that describes the electrical connections and logical relationships between the various functional units of the chip, which can clarify the interactions and dependencies between the chip's functional modules; the continuous failure feature represents the feature of functional failure caused by the electrical connections and logical relationships between adjacent chips in the chip layout.

[0090] In some embodiments, determining dynamic response data for performing deviation correction response during chip layout testing on a wafer based on the continuous failure characteristics can be achieved by using the following steps:

[0091] Determining failure distribution nodes during chip layout testing on a wafer using the continuous failure characteristics;

[0092] Determine the amount of adjustment configuration for deviation correction response during on-wafer chip layout testing;

[0093] Dynamic response data of a deviation correction response is determined according to the failure distribution nodes and the adjustment configuration amount.

[0094] In the specific implementation, first, based on the identified continuous failure characteristics, fault records related to the chip layout are collected from the test data, including overheating, signal interference, overload, etc., and the fault tree analysis (FTA) or failure mode and effect analysis (FMEA) method is used to identify the root cause of each failure characteristic. In the simulation environment, different working conditions (such as temperature, frequency, voltage, etc.) are set to simulate the working state of the chip, and the nodes where the failure characteristics appear under these conditions are recorded. According to the simulation results, the specific nodes with high failure probability are determined and marked as failure distribution nodes; then, for each failure distribution node, its electrical characteristics (such as voltage, current, power, etc.) under normal working conditions are evaluated and compared with the design specifications, and the impact of different configuration changes on the failure distribution nodes is analyzed. For example, the power consumption under different voltage conditions is calculated through the voltage-power relationship, and the possible causes are identified. The configuration of thermal failure is then evaluated, and corresponding adjustment configurations are formulated for each failure distribution node based on the evaluation results, including increasing voltage, optimizing signal paths, adding heat dissipation measures, etc., which will not be repeated here; finally, a dynamic test plan is designed to clarify the test parameter range and test conditions, such as different temperatures, frequencies, and load conditions. During the test, a data acquisition system (such as an oscilloscope and logic analyzer) is used to monitor the voltage, temperature, signal amplitude, and frequency of the failure distribution node in real time. Time domain analysis and frequency domain analysis techniques are used to process the collected data, extract the dynamic response characteristics of the node under different conditions, and identify the difference between failure and normal states. According to the analysis results, a dynamic response model is constructed to describe the response characteristics of the node to deviation correction under specific conditions, including reaction time, fluctuation range, etc. The dynamic response data of the deviation correction response is output from the model, which is not limited here.

[0095] It should be noted that the failure distribution node in this application represents a specific location in the chip layout that shows a high failure risk due to continuous failure characteristics, providing a reference point for subsequent correction and optimization; the adjustment configuration amount represents the specific adjustment parameters formulated in the chip layout test to ensure performance and reliability, which helps to optimize the chip operation status and reduce the possibility of failure; the dynamic response data is the real-time behavioral data that describes the chip's response to deviation correction during the test process.

[0096] In step 105, a feedback correction index of the wafer for computer chip design during chip layout testing is determined based on the transient response data and the dynamic response data, and chips on the wafer for computer chip design that fail are strictly filtered based on the feedback correction index.

[0097] In some embodiments, determining the feedback correction index of a wafer used for computer chip design during chip layout testing based on the transient response data and the dynamic response data can be achieved by using the following steps:

[0098] Determining layout feedback data of a wafer used for computer chip design during chip layout testing using the transient response data;

[0099] Determining, using the dynamic response data, a tightening correction feature of a wafer used for computer chip design during chip layout testing;

[0100] A feedback correction index of the wafer during chip layout testing is determined according to the layout feedback data and the tightening correction feature.

[0101] In specific implementation, first, transient response data, including voltage and current fluctuations at each node, is extracted from the test records. Data analysis tools can be used to integrate this data into a structured format, such as an Excel spreadsheet or database. Statistical methods (such as standard deviation and mean) are then used to analyze the changing trends of the transient response data, identifying inter-chip interactions and potential problem areas. Key performance indicators (such as voltage deviation and transient response time) are then selected for extraction to form comprehensive layout feedback data. Next, relevant features are extracted from the dynamic response data, namely, tightening correction features of the wafer during chip layout testing, such as signal stability, power consumption, and temperature variation. The extracted features are then analyzed to identify and classify abnormal behaviors under specific operating conditions, such as overheating or signal distortion. Based on the identified abnormal patterns, necessary correction thresholds are established, such as setting a node temperature limit to no more than a certain value. Finally, the layout feedback data and tightening correction features are comprehensively analyzed to identify correlations between the two. Based on the data analysis results, feedback correction indicators are calculated, such as the required voltage adjustment or signal enhancement measures. These can be quantified by establishing a mathematical model. The calculated feedback correction indicators are compiled into a report, which will not be further described here.

[0102] It should be noted that the layout feedback data in this application refers to key performance data that reflects the actual performance of the chip and its mutual influence during chip layout testing; the tightened correction feature describes the corrective measures that need to be taken due to abnormal behavior of the chip during dynamic testing; and the feedback correction index represents a quantitative indicator generated based on the feedback data and correction features during chip layout testing.

[0103] In specific implementation, the chips on the wafer used for computer chip design that are strictly filtered out according to the feedback correction index can be achieved in the following manner, namely: first, the collected failure records are analyzed to identify the failure mode and its associated feedback correction index, for example, determine which chips frequently fail under specific voltage, temperature or signal conditions, and then, based on the feedback correction index, set a stricter filtering standard, including setting a threshold, such as the maximum allowable voltage deviation, temperature variation range, etc., to ensure that only chips that meet the standard can pass the filtering; finally, the set filtering standard is applied to each chip on the wafer, and the performance data of each chip is checked one by one. If the feedback correction index of a chip exceeds the set threshold, it is marked as a failed chip, and the filtering results are sorted out to generate a detailed report, including the number of failed chips found in the filtering process, the cause of failure and the related feedback correction index, that is, the chips on the wafer used for computer chip design that are strictly filtered out according to the feedback correction index are completed, which will not be repeated here.

[0104] In addition, in another aspect of the present application, in some embodiments, the present application provides a system for screening wafer test results with stricter correction, referring to Figure 4 , this figure is a schematic diagram of the structure of a system for screening wafer test results with tightened correction according to some embodiments of the present application. The system 400 for screening wafer test results with tightened correction includes: an identification module 401, a processing module 402, and an execution module 403, which are described as follows:

[0105] Identification module 401, in this application, identification module 401 is mainly used to perform chip layout testing on wafers used for computer chip design and identify layout data of chip layout on the wafer;

[0106] Processing module 402, in this application, is mainly used to correct the constraints of the layout data, obtain the constraint distance of the chip layout in the chip layout on the wafer, and determine the component offset between chips in the chip placement unit domain based on the constraint distance;

[0107] The processing module 402 is further configured to obtain resource information occupied by a wafer used for computer chip design during chip layout planning, identify potential singular points on the resource information, obtain singular point layout information of the chip layout in the chip placement unit domain, and determine transient response data for performing deviation correction response during chip layout testing on the wafer using the singular point layout information and the component offset.

[0108] The processing module 402 is further configured to generate continuous failure characteristics on adjacent bits of a chip in a chip layout based on netlist connection information of chip functional connections after chip layout of a wafer used for computer chip design, and determine dynamic response data for deviation correction response during chip layout testing on the wafer based on the continuous failure characteristics;

[0109] Execution module 403, in this application, execution module 403 is mainly used to determine the feedback correction index of the wafer used for computer chip design during chip layout testing based on the transient response data and the dynamic response data, and strictly filter the chips on the wafer used for computer chip design that have failed based on the feedback correction index.

[0110] In addition, the present application also provides a computer device, which includes a memory and a processor, wherein the memory stores code, and the processor is configured to obtain the code and execute the above-mentioned tightened correction screening method for wafer test results.

[0111] In some embodiments, reference Figure 5 , which is a schematic diagram of the structure of a computer device for implementing a method for screening wafer test results with stricter correction according to some embodiments of the present application. The method for screening wafer test results with stricter correction in the above embodiment can be achieved by Figure 5 The computer device 500 shown in FIG. 5 is implemented as shown in FIG. 5 . The computer device 500 includes at least one processor 501 , a communication bus 502 , a memory 503 , and at least one communication interface 504 .

[0112] The processor 501 may be a general-purpose central processing unit (CPU), or an application-specific integrated circuit (ASIC) or one or more processors for controlling the execution of the tightened correction screening method for wafer test results in the present application.

[0113] The communication bus 502 may be used to transmit information between the aforementioned components.

[0114] The memory 503 may be a read-only memory (ROM) or other static storage device that can store static information and instructions, a random access memory (RAM) or other dynamic storage device that can store information and instructions, or an electrically erasable programmable read-only memory (EEPROM), a compact disc read-only memory (CD-ROM) or other optical disc storage, an optical disc storage (including a compact disc, laser disc, optical disc, digital versatile disc, Blu-ray disc, etc.), a magnetic disk or other magnetic storage device, or any other medium that can be used to carry or store desired program code in the form of instructions or data structures and can be accessed by a computer, but is not limited thereto. The memory 503 may be independent and connected to the processor 501 via the communication bus 502. The memory 503 may also be integrated with the processor 501.

[0115] Memory 503 is used to store program code for executing the solution of the present application, and is controlled by processor 501 for execution. Processor 501 is used to execute the program code stored in memory 503. The program code may include one or more software modules. The method for screening wafer test results with tightened corrections in the above embodiment can be implemented by processor 501 and one or more software modules in the program code in memory 503.

[0116] The communication interface 504 uses any transceiver or other device for communicating with other devices or communication networks, such as Ethernet, radio access network (RAN), wireless local area network (WLAN), etc.

[0117] In a specific implementation, as an embodiment, a computer device may include multiple processors, each of which may be a single-core (single-CPU) processor or a multi-core (multi-CPU) processor. The processor herein may refer to one or more devices, circuits, and / or processing cores for processing data (e.g., computer program instructions).

[0118] The aforementioned computer device may be a general-purpose computer device or a dedicated computer device. In a specific implementation, the computer device may be a desktop computer, a portable computer, a network server, a personal digital assistant (PDA), a mobile phone, a tablet computer, a wireless terminal device, a communication device, or an embedded device. The embodiments of the present application do not limit the type of computer device.

[0119] In addition, the present application also provides a computer-readable storage medium, which stores a computer program. When the computer program is executed by a processor, it implements the above-mentioned method for tightening correction screening of wafer test results.

[0120] Although the preferred embodiments of the present application have been described, those skilled in the art may make additional changes and modifications to these embodiments once they have learned the basic creative concept. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications that fall within the scope of the present application.

[0121] Obviously, those skilled in the art may make various changes and modifications to this application without departing from the spirit and scope of this application. Thus, if these modifications and variations of this application fall within the scope of the claims of this application and their equivalents, this application is intended to include these modifications and variations.

Claims

1. A method for screening wafer test results with stricter correction, characterized in that: The steps include: Perform chip layout testing on wafers used for computer chip design to identify the layout data of the chip layout on the wafer; Correcting and constraining the layout data to obtain a constraint distance of chip layout in a chip layout on a wafer, and determining an element offset between chips in a chip placement unit domain according to the constraint distance; Obtaining resource information occupied by a wafer used for computer chip design during chip layout planning, identifying potential singular points on the resource information, obtaining singular point layout information of the chip layout in a chip placement unit domain, and determining transient response data for performing deviation correction response during chip layout testing on the wafer using the singular point layout information and the component offset; generating continuous failure characteristics on adjacent bits of a chip in a chip layout based on netlist connection information of chip functional connections after chip layout of a wafer used for computer chip design, and determining dynamic response data for deviation correction response during chip layout testing on the wafer based on the continuous failure characteristics; A feedback correction index of a wafer used for computer chip design during chip layout testing is determined based on the transient response data and the dynamic response data, and chips on the wafer used for computer chip design that fail are strictly filtered based on the feedback correction index.

2. The method according to claim 1, wherein Correcting and constraining the layout data to obtain a constraint distance of the chip layout in the chip layout on the wafer specifically includes: Determining a layout trajectory of a chip in a chip layout on a wafer according to the layout data; Determine the layout constraint information of the chip layout on the wafer; The layout trajectory is adjusted using the layout constraint information to obtain a constraint distance of the chip layout in the chip layout diagram on the wafer.

3. The method according to claim 1, wherein Determining the component offset between chips in the chip placement unit domain according to the constraint distance specifically includes: Determining alignment information of the chip in the chip placement unit using the constraint distance; determining a matching position of the chip on the chip placement unit; The component offset is determined based on the alignment information and the matching position.

4. The method according to claim 1, wherein Identifying potential singular points on the resource information to obtain singular point layout information of the chip layout in the chip placement unit domain specifically includes: determining singular point position parameters of chip layout in the chip placement unit domain according to the resource information; Determining a layout confidence of a chip layout in a chip placement unit domain using the singular point position parameters; The chip placement unit domain is checked using the layout confidence value to obtain singular point layout information of the chip layout in the chip placement unit domain.

5. The method according to claim 1, wherein The transient response data for performing deviation correction response during chip layout testing on a wafer determined by using the singular point layout information and the component offset specifically includes: Determining reference position information for performing deviation correction response during chip layout testing on a wafer based on the singular point layout information; Determining layout rules for performing deviation correction responses during chip layout testing on a wafer based on the component offset; Transient response data for performing deviation correction response is determined by using the reference position information and the layout rule.

6. The method according to claim 1, wherein Determining feedback correction indicators of a wafer for computer chip design during chip layout testing based on the transient response data and the dynamic response data specifically includes: Determining layout feedback data of a wafer used for computer chip design during chip layout testing using the transient response data; Determining, using the dynamic response data, a tightening correction feature of a wafer used for computer chip design during chip layout testing; A feedback correction index of the wafer during chip layout testing is determined according to the layout feedback data and the tightening correction feature.

7. The method according to claim 1, wherein The image information is converted into layout data through electronic design automation tools.

8. A system for screening wafer test results with tightened corrections, characterized in that: include: an identification module for performing chip layout testing on wafers used for computer chip design and identifying layout data of the chip layout on the wafer; a processing module configured to correct and constrain the layout data to obtain a constraint distance of a chip layout in a chip layout on a wafer, and determine an element offset between chips in a chip placement unit domain according to the constraint distance; The processing module is further configured to obtain resource information occupied by a wafer used for computer chip design during chip layout planning, identify potential singular points on the resource information, obtain singular point layout information of the chip layout in the chip placement unit domain, and determine transient response data for deviation correction response during chip layout testing on the wafer using the singular point layout information and the component offset; The processing module is further configured to generate continuous failure characteristics on adjacent bits of a chip in a chip layout based on netlist connection information of chip functional connections after chip layout of a wafer used for computer chip design, and determine dynamic response data for deviation correction response during chip layout testing on the wafer based on the continuous failure characteristics; An execution module is configured to determine a feedback correction index of a wafer for computer chip design during chip layout testing based on the transient response data and the dynamic response data, and to strictly filter out failed chips on the wafer for computer chip design based on the feedback correction index.

9. A computer device, characterized in that: The computer device includes a memory and a processor, wherein the memory stores codes, and the processor is configured to obtain the codes and execute the wafer test result tightening correction screening method according to any one of claims 1 to 7.

10. A computer-readable storage medium storing a computer program, characterized in that: When the computer program is executed by a processor, the method for screening wafer test results with stricter correction according to any one of claims 1 to 7 is implemented.

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