Semiconductor structure and method of manufacturing the same

Abstract

The application provides a semiconductor structure and a manufacturing method thereof. The manufacturing method comprises the following steps: providing a substrate, the substrate comprising a plurality of bit lines and an initial bit line isolation structure covering each bit line, and the substrate further comprising a node contact portion between adjacent initial bit line isolation structures; removing part of the initial bit line isolation structure to obtain an intermediate bit line isolation structure; depositing an isolation material layer on the substrate, the isolation material layer filling a gap between adjacent intermediate bit line isolation structures; removing the isolation material layer on the node contact portion to obtain a final bit line isolation structure with an isolation widened portion on the intermediate bit line isolation structure; and forming a plurality of spaced landing pads on the isolation widened portion and the node contact portion.

Description

Technical Field

[0001] The present application relates to the field of semiconductor manufacturing, and in particular to a semiconductor structure and a manufacturing method thereof. Background Art

[0002] In semiconductor manufacturing, the size of landing pads influences electrical transmission performance. Due to the shape of the bitline structure beneath the landing pads, short circuits between adjacent landing pads and pad delamination are common, impacting both electrical transmission performance and product yield. Summary of the Invention

[0003] In view of this, the main purpose of this application is to provide a semiconductor structure and a manufacturing method thereof.

[0004] To achieve the above objectives, the technical solution of this application is implemented as follows:

[0005] An embodiment of the present application provides a method for manufacturing a semiconductor structure, comprising:

[0006] Providing a substrate, the substrate comprising a plurality of bit lines and an initial bit line isolation structure covering each of the bit lines, the substrate further comprising a node contact portion located between adjacent initial bit line isolation structures;

[0007] removing a portion of the initial bit line isolation structure to obtain an intermediate bit line isolation structure;

[0008] Depositing an isolation material layer on the substrate, wherein the isolation material layer fills the gap between adjacent intermediate bit line isolation structures;

[0009] removing the isolation material layer on the node contact portion to obtain a final bit line isolation structure having an isolation widening portion, wherein the isolation widening portion is located on the intermediate bit line isolation structure;

[0010] A plurality of landing pads are formed on the isolation widening portion and the node contact portion.

[0011] In some embodiments, the initial bit line isolation structure includes a first isolation layer, an intermediate isolation layer, and a second isolation layer, wherein the first isolation layer covers the bit line, the intermediate isolation layer is located on a side of the first isolation layer away from the bit line, and the second isolation layer is located on a side of the intermediate isolation layer away from the bit line;

[0012] The removing part of the initial bit line isolation structure comprises:

[0013] At least a portion of the second isolation layer is removed.

[0014] In some embodiments, the material of the isolation material layer is the same as that of the second isolation layer.

[0015] In some embodiments, removing the isolation material layer on the node contact portion to obtain a final bit line isolation structure having an isolation widening portion, wherein the isolation widening portion is located on the intermediate bit line isolation structure, includes:

[0016] The isolation material layer is subjected to chemical mechanical polishing treatment, and the isolation material layer located on the node contact portion is etched away so that the difference between the bottom width and the top width of the bit line structure in a direction parallel to the plane where the substrate is located is within a preset range. The bit line structure includes the bit line and the ultimate bit line isolation structure covering the bit line.

[0017] In some embodiments, the predetermined range is greater than or equal to 0 and less than or equal to 0.5 nanometers.

[0018] In some embodiments, forming a plurality of landing pads spaced apart on the isolation widening portion and the node contact portion includes:

[0019] Depositing a contact material layer and a landing material layer on the isolation widening portion and the node contact portion in sequence, wherein the contact material layer continuously covers the surface of the isolation widening portion and the surface of the node contact portion, and the landing material layer covers the contact material layer and at least fills the groove formed by the contact material layer;

[0020] Part of the landing material layer and part of the contact material layer between adjacent isolation widening portions are removed to obtain a plurality of landing pads arranged at intervals.

[0021] In some embodiments, the landing pad includes a first sub-pad, a second sub-pad, and a third sub-pad connecting the first sub-pad and the second sub-pad, the first sub-pad is located on the top surface of the isolation widening portion, the second sub-pad is located on the top surface of the node contact portion, and the third sub-pad is located on the side of the isolation widening portion; wherein the third sub-pad is arranged perpendicularly or substantially perpendicularly to the first sub-pad, the second sub-pad is arranged parallel to the first sub-pad, and the surface of the second sub-pad in contact with one of the ultimate bit line isolation structures is a plane.

[0022] An embodiment of the present application also provides a semiconductor structure, comprising a substrate and a plurality of spaced-apart landing pads, the substrate comprising a plurality of bit lines and an ultimate bit line isolation structure covering each of the bit lines, the substrate further comprising a node contact portion located between adjacent ultimate bit line isolation structures, wherein the ultimate bit line isolation structure has an isolation widening portion, the bit line and the ultimate bit line isolation structure constitute a bit line structure, and in a direction parallel to the plane of the substrate, the difference between the bottom width and the top width of the bit line structure is within a preset range; the plurality of spaced-apart landing pads are located on the isolation widening portion and the node contact portion.

[0023] In some embodiments, the predetermined range is greater than or equal to 0 and less than or equal to 0.5 nanometers.

[0024] In some embodiments, the landing pad includes a first sub-pad, a second sub-pad, and a third sub-pad connecting the first sub-pad and the second sub-pad, the first sub-pad is located on the top surface of the isolation widening portion, the second sub-pad is located on the top surface of the node contact portion, and the third sub-pad is located on the side of the isolation widening portion; wherein the third sub-pad is arranged perpendicularly or substantially perpendicularly to the first sub-pad, the second sub-pad is arranged parallel to the first sub-pad, and the surface of the second sub-pad in contact with one of the ultimate bit line isolation structures is a plane.

[0025] An embodiment of the present application provides a method for manufacturing a semiconductor structure, comprising: providing a substrate, the substrate including a plurality of bit lines and an initial bit line isolation structure covering each bit line, the substrate also including a node contact portion located between adjacent initial bit line isolation structures; removing portions of the initial bit line isolation structure to obtain an intermediate bit line isolation structure; depositing an isolation material layer on the substrate, the isolation material layer filling gaps between adjacent intermediate bit line isolation structures; removing the isolation material layer located on the node contact portion to obtain a final bit line isolation structure having an isolation widening portion, the isolation widening portion located on the intermediate bit line isolation structure; and forming a plurality of spaced landing pads on the isolation widening portion and the node contact portion. By filling the gaps between adjacent intermediate bit line isolation structures with the isolation material layer to obtain the final bit line isolation structure having the isolation widening portion, the present application improves the shape of the top of the final bit line isolation structure, thereby better securing the landing pads on the top of the final bit line isolation structure, preventing short circuits between adjacent landing pads and landing pad peeling, reducing the failure rate, and thereby improving the electrical transmission performance and product yield of the product and enhancing the stability of the overall process. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] Figure 1a to Figure 1g A schematic diagram of the basic structure of each component in the manufacturing process flow of a semiconductor structure in the related art;

[0027] Figure 2 A flowchart of a method for manufacturing a semiconductor structure provided in an embodiment of the present application;

[0028] Figure 3a to Figure 3f A schematic diagram of the basic structure of each component in the manufacturing process flow of the semiconductor structure provided in an embodiment of the present application. DETAILED DESCRIPTION

[0029] The following describes exemplary embodiments of the present application in more detail with reference to the accompanying drawings. Although exemplary embodiments of the present application are shown in the accompanying drawings, it should be understood that the present application can be implemented in various forms and should not be limited by the specific embodiments described herein. Instead, these embodiments are provided to enable a more thorough understanding of the present application and to fully convey the scope of the present application to those skilled in the art.

[0030] In the following description, numerous specific details are provided to provide a more thorough understanding of the present application. However, it will be apparent to those skilled in the art that the present application can be practiced without one or more of these details. In other instances, certain technical features known in the art are not described to avoid confusion with the present application; that is, all features of actual embodiments are not described herein, nor are well-known functions and structures described in detail.

[0031] In the drawings, the sizes of layers, regions, elements and their relative sizes may be exaggerated for clarity. Like reference numerals denote like elements throughout.

[0032] It should be understood that spatial relational terms such as "under", "beneath", "below", "under", "above", "above", etc., may be used herein for convenience of description to describe the relationship of one element or feature shown in the figures to other elements or features. It should be understood that in addition to the orientations shown in the figures, the spatial relational terms are intended to also include different orientations of the device in use and operation. For example, if the device in the drawings is turned over, then the elements or features described as "under the other elements" or "beneath" or "beneath" will be oriented as "on" the other elements or features. Thus, the exemplary terms "under" and "under" may include both upper and lower orientations. The device may be oriented otherwise (rotated 90 degrees or in other orientations) and the spatial descriptors used herein are interpreted accordingly.

[0033] The purpose of the terms used herein is only to describe specific embodiments and is not intended to limit the present application. When used herein, the singular forms "a", "an", and "the" are intended to include the plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "comprising" and / or "including", when used in this specification, determine the presence of the features, integers, steps, operations, elements and / or parts, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups. When used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0034] In order to enable a more detailed understanding of the features and technical contents of the embodiments of the present application, the implementation of the embodiments of the present application is described in detail below with reference to the accompanying drawings. The attached drawings are for reference only and are not used to limit the embodiments of the present application.

[0035] like Figure 1a to Figure 1g As shown in FIG. 1 , a basic structural diagram of each component in the manufacturing process flow of a semiconductor structure in the related art is shown. In the manufacturing process flow of a semiconductor structure in the related art, first, as shown in FIG. Figure 1a As shown, a substrate 100 is provided. The substrate 100 includes a substrate 11, a plurality of bit lines 12 located on the substrate 11, and an initial bit line isolation structure 13 covering each bit line 12. The substrate 100 also includes a node contact 14 located between adjacent initial bit line isolation structures 13. The substrate 11 includes an active area 110 and an isolation structure 111 located between adjacent active areas 110. The bit lines 12 are connected to the active areas 110 via the bit line contact structures. The node contacts 14 are connected to the active areas 110 and are insulated from the bit lines 12. The initial bit line isolation structure 13 includes a first isolation layer 130, an intermediate isolation layer 131, and a second isolation layer 132. The first isolation layer 130 covers the bit lines 12. The intermediate isolation layer 131 is located on a side of the first isolation layer 130 away from the bit lines 12. The second isolation layer 132 is located on a side of the intermediate isolation layer 131 away from the bit lines 12.

[0036] Next, if Figure 1b As shown, a portion of the initial bit line isolation structure 13 is removed to obtain an intermediate bit line isolation structure 15. Specifically, when a portion of the initial bit line isolation structure 13 is removed, the uniformity of the removal of the initial bit line isolation structure 13 may be inconsistent, resulting in inconsistent top widths of the intermediate bit line isolation structure 15. The top widths of some intermediate bit line isolation structures 15 are particularly small (e.g., Figure 1b ).

[0037] Next, if Figure 1cAs shown, a relatively thin isolation material layer 16 is deposited on the substrate 100. The isolation material layer 16 is located on the surfaces of the intermediate bit line isolation structure 15 and the node contact portion 14. The isolation material layer 16 is used to compensate for damage to the top of the intermediate bit line isolation structure 15 caused by the removal of a portion of the initial bit line isolation structure 13. Due to the relatively thin isolation material layer 16 deposited in the related art, the top width of the marked bit line isolation structure X remains relatively small.

[0038] Next, if Figure 1d As shown, the isolation material layer 16 on the node contact 14 is removed, leaving only the isolation material layer 16 on the surface of the intermediate bit line isolation structure 15. The isolation material layer 16 on the surface of the intermediate bit line isolation structure 15 is combined with the intermediate bit line isolation structure 15 to form the final bit line isolation structure 17. It will be understood that since the landing pad 18 to be fabricated subsequently needs to be connected to the node contact 14, the isolation material layer 16 on the node contact 14 needs to be removed.

[0039] Next, if Figure 1e As shown, a contact material layer 180 and a landing material layer 181 are sequentially deposited on the isolation material layer 16 and the node contact portion 14 , wherein the contact material layer 180 continuously covers the surface of the isolation material layer 16 and the surface of the node contact portion 14 , and the landing material layer 181 covers the contact material layer 180 and at least fills the groove formed by the contact material layer 180 .

[0040] Next, if Figure 1f As shown, a portion of the landing material layer 181 and a portion of the contact material layer 180 between adjacent final bit line isolation structures 17 are removed to obtain a plurality of contact layers 1801 spaced apart and a landing layer 1811 located on the contact layer 1801, wherein one contact layer 1801 and the landing layer 1811 located on the contact layer 1801 are combined to form a landing pad 18. It is understandable that, due to the small top width of the mark bit line isolation structure X, the contact material layer 180 located on the mark bit line isolation structure X is not within the target etching area. When the contact material layer 180 is removed, the contact layer 1801 located on the mark bit line isolation structure X is not etched and disconnected from the contact layer 1801 on the adjacent final bit line isolation structure 17, resulting in a short circuit between the landing pad 18 located on the mark bit line isolation structure X and the adjacent landing pad 18.

[0041] In addition, if Figure 1g As shown, since the top width of the mark bit line isolation structure X is relatively small, the landing pad 18 located on the mark bit line isolation structure X may be peeled off during the formation process.

[0042] In summary, it can be understood that due to the poor uniformity of the top width of the final bitline isolation structure 17 at the bottom of the landing pad 18, short circuits between adjacent landing pads 18 and peeling of landing pads 18 often occur during the manufacturing process, affecting the electrical transmission performance and product yield of the product. The embodiments of the present application can solve the above-mentioned defects.

[0043] like Figure 2 FIG. 1 is a flow chart of a method for manufacturing a semiconductor structure provided in an embodiment of the present application, wherein the method comprises:

[0044] S1. Providing a substrate, wherein the substrate includes a plurality of bit lines and an initial bit line isolation structure covering each of the bit lines, and the substrate further includes a node contact portion located between adjacent initial bit line isolation structures;

[0045] S2, removing part of the initial bit line isolation structure to obtain an intermediate bit line isolation structure;

[0046] S3, depositing an isolation material layer on the substrate, wherein the isolation material layer fills the gap between adjacent middle bit line isolation structures;

[0047] S4, removing the isolation material layer located on the node contact portion to obtain a final bit line isolation structure having an isolation widening portion, wherein the isolation widening portion is located on the intermediate bit line isolation structure;

[0048] S5. Form a plurality of landing pads spaced apart from each other on the isolation widening portion and the node contact portion.

[0049] It can be understood that the present application compensates for the uniformity of the top width of the intermediate bit line isolation structure by filling the gap between adjacent intermediate bit line isolation structures with an isolation material layer, thereby obtaining a final bit line isolation structure with an isolation widening portion. The isolation widening portion increases the width of the top of the final bit line isolation structure so that the landing pad can be better fixed on the top of the final bit line isolation structure, avoiding short circuits between adjacent landing pads and landing pad peeling, reducing the failure rate, thereby improving the product's electrical transmission performance and product yield, and improving the stability of the overall process.

[0050] Next, combine Figure 3a to Figure 3f The method for manufacturing the semiconductor structure provided in the embodiment of the present application is described in detail. Figure 3a to Figure 3f A schematic diagram of the basic structure of each component in the manufacturing process flow of the semiconductor structure provided in an embodiment of the present application.

[0051] In step S1, Figure 3aAs shown, a substrate 100 is provided. The substrate 100 includes a substrate 11, a plurality of bit lines 12 located on the substrate 11, and an initial bit line isolation structure 13 covering each bit line 12. The substrate 100 also includes a node contact 14 located between adjacent initial bit line isolation structures 13. The substrate 11 includes an active area 110 and an isolation structure 111 located between adjacent active areas 110. The bit lines 12 are connected to the active areas 110 via the bit line contact structures. The node contacts 14 are connected to the active areas 110 and are insulated from the bit lines 12. The initial bit line isolation structure 13 includes a first isolation layer 130, an intermediate isolation layer 131, and a second isolation layer 132. The first isolation layer 130 covers the bit lines 12. The intermediate isolation layer 131 is located on a side of the first isolation layer 130 away from the bit lines 12. The second isolation layer 132 is located on a side of the intermediate isolation layer 131 away from the bit lines 12.

[0052] It should be noted that the material of the substrate 11 is, for example, silicon, the material of the isolation structure 111 is, for example, silicon oxide, the material of the node contact portion 14 is, for example, polysilicon, the material of the bit line 12 includes a conductive material, the material of the first isolation layer 130 and the second isolation layer 132 is, for example, silicon nitride, and the material of the intermediate isolation layer 131 is, for example, silicon oxide.

[0053] In step S2, if Figure 3b As shown, an etching process is used to remove part of the initial bit line isolation structure 13 to obtain an intermediate bit line isolation structure 15. Specifically, when removing part of the initial bit line isolation structure 13, there may be a situation where the removal uniformity of the initial bit line isolation structure 13 is inconsistent, resulting in inconsistent top widths of the intermediate bit line isolation structure 15. The top widths of some intermediate bit line isolation structures 15 are particularly small (e.g., Figure 3b ).

[0054] In some embodiments, removing a portion of the initial bit line isolation structure 13 includes removing at least a portion of the second isolation layer 132 .

[0055] It should be noted that, when removing part of the initial bit line isolation structure 13, only part of the second isolation layer 132 may be removed, or part of the second isolation layer 132 and part of the intermediate isolation layer 131 may be removed. Figure 3b In the figure, a portion of the second isolation layer 132 and a portion of the middle isolation layer 131 are removed as an example. In addition, a portion of the first isolation layer 130 in the bit line isolation structure X is also removed. This is an accidental removal, as the first isolation layer 130 is not the target removal object.

[0056] In step S3, if Figure 3c As shown, an isolation material layer 16 is deposited on the substrate 100 , and the isolation material layer 16 fills the gaps between adjacent middle bit line isolation structures 15 .

[0057] It can be understood that the isolation material layer 16 is used to compensate for the damage to the top of the intermediate bit line isolation structure 15 caused by removing part of the initial bit line isolation structure 13, and because the isolation material layer 16 deposited in the present application fills the gap between adjacent intermediate bit line isolation structures 15, the top width of the intermediate bit line isolation structure 15 does not have the problem of poor uniformity.

[0058] In some embodiments, the material of the isolation material layer 16 is the same as the material of the second isolation layer 132. For example, the material of the isolation material layer 16 and the material of the second isolation layer 132 are both silicon nitride.

[0059] In step S4, Figure 3d As shown, an etching process is used to remove the isolation material layer 16 located on the node contact portion 14 to obtain a final bit line isolation structure 17 having an isolation widening portion 19. The isolation widening portion 19 is located on the intermediate bit line isolation structure 15. The isolation widening portion 19 and the intermediate bit line isolation structure 15 are combined to form the final bit line isolation structure 17. It will be appreciated that because the landing pad 18 to be fabricated subsequently needs to be connected to the node contact portion 14, the isolation material layer 16 located on the node contact portion 14 needs to be removed. In some embodiments, because the node contact portion 14 is easily oxidized, it is also necessary to etch away the oxide on the surface of the node contact portion 14.

[0060] It is understood that because the isolation material layer 16 deposited in this application fills the gaps between adjacent intermediate bitline isolation structures 15, when only the isolation material layer 16 located on the node contacts 14 is removed, the isolation material layer 16 located on the intermediate bitline isolation structures 15 remains, forming the isolation widening portion 19. The isolation widening portion 19 compensates for the uneven top width of the intermediate bitline isolation structures 15, thereby ensuring better anchoring of the subsequently formed landing pad 18 on top of the final bitline isolation structure 17. Furthermore, this removal of the isolation material layer 16 located on the node contacts 14 can be performed simultaneously in the array region and the peripheral region.

[0061] In some embodiments, the removal of the isolation material layer 16 on the node contact portion 14 to obtain a final bit line isolation structure 17 having an isolation widening portion 19 , wherein the isolation widening portion 19 is located on the intermediate bit line isolation structure 15 , includes:

[0062] The isolation material layer 16 is subjected to chemical mechanical polishing treatment, and the isolation material layer 16 located on the node contact portion 14 is etched away, so that the difference between the bottom width and the top width of the bit line structure in a direction parallel to the plane of the substrate 100 is within a preset range. The bit line structure includes the bit line 12 and the ultimate bit line isolation structure 17 covering the bit line 12.

[0063] It will be appreciated that this embodiment performs a chemical mechanical polishing process on the isolation material layer 16 to make the surface of the isolation material layer 16 more planar, facilitating the deposition of subsequent film layers. Furthermore, this embodiment ensures that the difference between the bottom width a and the top width b of the resulting bitline structure is within a predetermined range, thereby making the top width of the bitline structure controllable and uniform, thereby preventing failure of the subsequently formed landing pad 18.

[0064] In some embodiments, the predetermined range is greater than or equal to 0 and less than or equal to 0.5 nanometers. For example, the difference between the bottom width a and the top width b of the bitline structure is 0.2 nanometers. It is understood that the smaller the difference between the bottom width a and the top width b of the bitline structure, the lower the risk of landing pad 18 failure.

[0065] In step S5, Figure 3f As shown, a plurality of landing pads 18 arranged at intervals are formed on the isolation widening portion 19 and the node contact portion 14 .

[0066] It can be understood that since the ultimate bit line isolation structure 17 includes the intermediate bit line isolation structure 15 and the isolation widening portion 19 located on the intermediate bit line isolation structure 15, the width of the top of the ultimate bit line isolation structure 17 is relatively large, and the width uniformity of the top of the ultimate bit line isolation structure 17 is relatively good, so it will not cause a short circuit between the landing pad 18 located on the marking bit line isolation structure X and the adjacent landing pad 18, nor will it cause the landing pad 18 located on the marking bit line isolation structure X to peel off during the formation process.

[0067] In some embodiments, as Figure 3e As shown, a plurality of landing pads 18 spaced apart are formed on the isolation widening portion 19 and the node contact portion 14, including:

[0068] A contact material layer 180 and a landing material layer 181 are sequentially deposited on the isolation widening portion 19 and the node contact portion 14 , wherein the contact material layer 180 continuously covers the surface of the isolation widening portion 19 and the surface of the node contact portion 14 , and the landing material layer 181 covers the contact material layer 180 and at least fills the groove formed by the contact material layer 180 ;

[0069] Part of the landing material layer 181 and part of the contact material layer 180 between adjacent isolation widening portions 19 are removed to obtain a plurality of landing pads 18 arranged at intervals.

[0070] It is understandable that if Figure 3f As shown, a landing pad 18 includes a contact layer 1801 and a landing layer 1811 located on the contact layer 1801, wherein the contact layer 1801 is obtained by removing part of the contact material layer 180 between adjacent ultimate bit line isolation structures 17, and the landing layer 1811 is obtained by removing part of the landing material layer 181 between adjacent ultimate bit line isolation structures 17.

[0071] It should be noted that the material of the contact material layer 180 is, for example, titanium nitride, and the contact material layer 180 is for achieving ohmic contact; the material of the landing material layer 181 is, for example, tungsten.

[0072] It is understandable that since the top width of the final bit line isolation structure 17 becomes larger, that is, the volume occupied by the final bit line isolation structure 17 becomes larger, the amount of the landing material layer 181 can be reduced, thereby saving production costs.

[0073] In some embodiments, as Figure 3f As shown, the landing pad 18 includes a first sub-pad 182, a second sub-pad 183 and a third sub-pad 184 connecting the first sub-pad 182 and the second sub-pad 183, the first sub-pad 182 is located on the top surface of the isolation widening portion 19, the second sub-pad 183 is located on the top surface of the node contact portion 14, and the third sub-pad 184 is located on the side of the isolation widening portion 19; wherein the third sub-pad 184 is arranged perpendicularly or substantially perpendicularly to the first sub-pad 182, the second sub-pad 183 is arranged parallel to the first sub-pad 182, and the surface of the second sub-pad 183 in contact with one of the ultimate bit line isolation structures 17 is a plane.

[0074] It is understood that the shape of the landing pad 18 in the embodiment of the present application is different from that of the landing pad 18 in the related art because the final bit line isolation structure 17 in the present application has a different shape than that in the related art. However, the contact area between the landing pad 18 and the node contact portion 14 in the embodiment of the present application remains unchanged.

[0075] In some embodiments, the edge of the landing pad 18 on the isolated widening portion 19 is flush with the edge of the isolated widening portion 19 .

[0076] Next, if Figure 3fAs shown, an embodiment of the present application further provides a semiconductor structure, including a substrate 100 and a plurality of spaced landing pads 18, the substrate 100 including a plurality of bit lines 12 and an ultimate bit line isolation structure 17 covering each of the bit lines 12, the substrate 100 also including a node contact portion 14 located between adjacent ultimate bit line isolation structures 17, wherein the ultimate bit line isolation structure 17 has an isolation widening portion 19, the bit lines 12 and the ultimate bit line isolation structure 17 constitute a bit line structure, and in a direction parallel to the plane of the substrate 100, the difference between the bottom width and the top width of the bit line structure is within a preset range; the plurality of spaced landing pads 18 are located on the isolation widening portion 19 and the node contact portion 14.

[0077] It is understood that by providing the final bitline isolation structure 17 with an isolation widening portion 19, the present application improves the shape of the top of the final bitline isolation structure 17, thereby facilitating better securing of the landing pad 18 on the top of the final bitline isolation structure 17. This prevents short circuits between adjacent landing pads 18 and the occurrence of peeling of landing pads 18, thereby reducing the failure rate, thereby improving the product's electrical transmission performance and product yield, and enhancing the stability of the overall process. Furthermore, by ensuring that the difference between the bottom width a and the top width b of the bitline structure is within a preset range, the top width of the bitline structure is controllable and uniform, further preventing landing pad 18 failure.

[0078] In some embodiments, the predetermined range is greater than or equal to 0 and less than or equal to 0.5 nanometers. For example, the difference between the bottom width a and the top width b of the bitline structure is 0.2 nanometers. It is understood that the smaller the difference between the bottom width a and the top width b of the bitline structure, the lower the risk of landing pad 18 failure.

[0079] In some embodiments, the landing pad 18 includes a first sub-pad 182, a second sub-pad 183, and a third sub-pad 184 connecting the first sub-pad 182 and the second sub-pad 183, wherein the first sub-pad 182 is located on the top surface of the isolation widening portion 19, the second sub-pad 183 is located on the top surface of the node contact portion 14, and the third sub-pad 184 is located on the side of the isolation widening portion 19; wherein the third sub-pad 184 is arranged perpendicularly or substantially perpendicularly to the first sub-pad 182, the second sub-pad 183 is arranged parallel to the first sub-pad 182, and the surface of the second sub-pad 183 in contact with one of the ultimate bit line isolation structures 17 is a plane.

[0080] It is understood that the shape of the landing pad 18 in the embodiment of the present application is different from that of the landing pad 18 in the related art because the final bit line isolation structure 17 in the present application has a different shape than that in the related art. However, the contact area between the landing pad 18 and the node contact portion 14 in the embodiment of the present application remains unchanged.

[0081] In some embodiments, the edge of the landing pad 18 on the isolated widening portion 19 is flush with the edge of the isolated widening portion 19 .

[0082] In summary, the present invention provides a semiconductor structure and a manufacturing method thereof, the manufacturing method comprising: providing a substrate, the substrate comprising a plurality of bit lines and an initial bit line isolation structure covering each bit line, the substrate further comprising a node contact portion located between adjacent initial bit line isolation structures; removing a portion of the initial bit line isolation structure to obtain an intermediate bit line isolation structure; depositing an isolation material layer on the substrate, the isolation material layer filling the gap between adjacent intermediate bit line isolation structures; removing the isolation material layer located on the node contact portion to obtain a final bit line isolation structure having an isolation widening portion, the isolation widening portion being located on the intermediate bit line isolation structure; forming a substrate on the isolation widening portion and the node contact portion. Multiple landing pads are arranged at intervals; the present application obtains a final bit line isolation structure with an isolation widening portion by filling the gaps between adjacent intermediate bit line isolation structures with an isolation material layer, thereby improving the shape of the top of the final bit line isolation structure so that the landing pad can be better fixed on the top of the final bit line isolation structure, avoiding short circuits between adjacent landing pads and landing pad peeling, reducing the failure rate, thereby improving the product's electrical transmission performance and product yield, improving the stability of the overall process, and solving the technical problems of short circuits between adjacent landing pads and landing pad peeling, which affect the product's electrical transmission performance and product yield.

[0083] The above description is merely a specific embodiment of the present application, but the scope of protection of the present application is not limited thereto. Any changes or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in this application should be included in the scope of protection of this application. Therefore, the scope of protection of this application should be based on the scope of protection of the claims.

Claims

1. A method for manufacturing a semiconductor structure, characterized in that: include: Providing a substrate, the substrate comprising a plurality of bit lines and an initial bit line isolation structure covering each of the bit lines, the substrate further comprising a node contact portion located between adjacent initial bit line isolation structures; removing a portion of the initial bit line isolation structure to obtain an intermediate bit line isolation structure; Depositing an isolation material layer on the substrate, wherein the isolation material layer fills the gap between adjacent intermediate bit line isolation structures; removing the isolation material layer on the node contact portion to obtain a final bit line isolation structure having an isolation widening portion, wherein the isolation widening portion is located on the intermediate bit line isolation structure; forming a plurality of landing pads spaced apart on the isolation widening portion and the node contact portion; The step of removing the isolation material layer on the node contact portion to obtain a final bit line isolation structure having an isolation widening portion, wherein the isolation widening portion is located on the intermediate bit line isolation structure, comprises: The isolation material layer is subjected to chemical mechanical polishing treatment, and the isolation material layer located on the node contact portion is etched away so that the difference between the bottom width and the top width of the bit line structure in a direction parallel to the plane where the substrate is located is within a preset range. The bit line structure includes the bit line and the ultimate bit line isolation structure covering the bit line.

2. The manufacturing method according to claim 1, characterized in that The initial bit line isolation structure includes a first isolation layer, an intermediate isolation layer, and a second isolation layer, wherein the first isolation layer covers the bit line, the intermediate isolation layer is located on a side of the first isolation layer away from the bit line, and the second isolation layer is located on a side of the intermediate isolation layer away from the bit line; The removing part of the initial bit line isolation structure comprises: At least a portion of the second isolation layer is removed.

3. The manufacturing method according to claim 2, characterized in that The material of the isolation material layer is the same as that of the second isolation layer.

4. The manufacturing method according to claim 1, characterized in that The preset range is greater than or equal to 0 and less than or equal to 0.5 nanometers.

5. The manufacturing method according to any one of claims 1 to 3, characterized in that: The step of forming a plurality of landing pads spaced apart on the isolation widening portion and the node contact portion comprises: Depositing a contact material layer and a landing material layer on the isolation widening portion and the node contact portion in sequence, wherein the contact material layer continuously covers the surface of the isolation widening portion and the surface of the node contact portion, and the landing material layer covers the contact material layer and at least fills the groove formed by the contact material layer; Part of the landing material layer and part of the contact material layer between adjacent isolation widening portions are removed to obtain a plurality of landing pads arranged at intervals.

6. The manufacturing method according to claim 5, characterized in that The landing pad includes a first sub-pad, a second sub-pad, and a third sub-pad connecting the first sub-pad and the second sub-pad, wherein the first sub-pad is located on a top surface of the isolation widening portion, the second sub-pad is located on a top surface of the node contact portion, and the third sub-pad is located on a side surface of the isolation widening portion; The third sub-pad is arranged perpendicularly or substantially perpendicularly to the first sub-pad, the second sub-pad is arranged parallel to the first sub-pad, and the surface of the second sub-pad in contact with one of the ultimate bit line isolation structures is a plane.

7. A semiconductor structure, characterized in that The semiconductor structure is manufactured by the manufacturing method according to claim 1, comprising: a substrate comprising a plurality of bit lines and a final bit line isolation structure covering each of the bit lines, the substrate further comprising a node contact portion located between adjacent final bit line isolation structures, wherein the final bit line isolation structure has an isolation widening portion, the bit lines and the final bit line isolation structure constitute a bit line structure, and in a direction parallel to a plane of the substrate, a difference between a bottom width and a top width of the bit line structure is within a preset range; A plurality of landing pads are spaced apart and located on the isolation widening portion and the node contact portion.

8. The semiconductor structure according to claim 7, wherein: The preset range is greater than or equal to 0 and less than or equal to 0.5 nanometers.

9. The semiconductor structure according to claim 7 or 8, characterized in that: The landing pad includes a first sub-pad, a second sub-pad, and a third sub-pad connecting the first sub-pad and the second sub-pad, wherein the first sub-pad is located on a top surface of the isolation widening portion, the second sub-pad is located on a top surface of the node contact portion, and the third sub-pad is located on a side surface of the isolation widening portion; The third sub-pad is arranged perpendicularly or substantially perpendicularly to the first sub-pad, the second sub-pad is arranged parallel to the first sub-pad, and the surface of the second sub-pad in contact with one of the ultimate bit line isolation structures is a plane.

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