Packaging structure suitable for multiple types of MOS chips

Abstract

The invention discloses a packaging structure suitable for multiple MOS chips, and relates to the technical field of semiconductor packaging, the packaging structure suitable for multiple MOS chips comprises a chip packaging frame, one side of the top end of the chip packaging frame is provided with an insulating cushion block, and the other side of the top end of the chip packaging frame is provided with a chip packaging assembly. A copper sheet matched with the chip packaging assembly is arranged at the top end of the insulating cushion block, an epoxy molding compound matched with the chip packaging frame is arranged on the outer side of the top end of the copper sheet, and a third picture tin layer is arranged between one side of the bottom end of the copper sheet and the chip packaging frame; the chip packaging assembly comprises an MOS tube bare chip arranged on one side of the top end of the chip packaging frame, a first tin drawing layer is arranged between the MOS tube bare chip and the chip packaging frame, and a second tin drawing layer is arranged between the MOS tube bare chip and the copper sheet. According to the invention, the problem of non-uniform tin thickness between the copper sheet and the MOS tube bare chip is solved, and the production cost is saved.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor packaging technology, and in particular to a packaging structure applicable to multiple MOS chips. Background Art

[0002] With the rapid development of automotive electronics, industrial control, new energy and other fields, the performance requirements for power devices are increasing, especially in automotive-grade applications, which puts forward more stringent requirements on the reliability of MOS tube packaging. In the development of power device packaging technology, the design of the packaging structure must not only meet the requirements of electrical performance and heat dissipation performance, but also ensure that the cost is controllable; among them, the lead frame as a packaging form of the carrier occupies an important position in the field of power device packaging because of its large heat dissipation area and good electrical characteristics; at the same time, with the development of electronic products towards miniaturization and thinness, the package size continues to shrink, which puts forward higher requirements on the packaging process, especially in terms of the thickness control and uniformity of the upper and lower tin layers of the chip. These factors directly affect the reliability and performance of the product.

[0003] At present, power device packaging generally adopts a packaging form that combines lead frame and copper sheet. The heat dissipation efficiency is improved by retaining a large heat dissipation area at the bottom of the lead frame, and the copper sheet is used to achieve electrical connection and heat conduction. This packaging structure has significant advantages in performance, size and price, and can better balance the heat dissipation performance and cost control requirements. In actual production, due to the diversity of MOS chip sizes and the complex and changeable layout of the gate bus pattern on the chip, the industry generally adopts the solution of preparing concave points on the copper sheet, and avoids the gate bus pressure concentration point through the concave point design, so as to reduce the stress damage to the gate bus during the packaging process. This solution solves the problem of gate bus stress concentration to a certain extent through one-to-one customized design, that is, a single copper sheet corresponds to a single chip supporting packaging route.

[0004] However, the existing packaging technology solutions have limitations in many aspects. First, as the package size continues to decrease, product reliability faces severe challenges, especially in the moisture sensitivity level test, most products are difficult to meet the MSL-3 level requirements, not to mention the higher level MSL-1 standard; second, although the one-to-one customized packaging solution can solve the problem of gate bus stress concentration, this method requires the development of corresponding dedicated copper sheets and molds for each chip, which not only greatly increases the mold investment cost, but also complicates production management and reduces manufacturing efficiency; in addition, since each chip requires an independent packaging process and quality control standards, this method also brings about problems such as frequent production line switching and difficult inventory management. These shortcomings seriously restrict the reduction of product costs and the improvement of production efficiency, and it is difficult to meet the market's growing demand for high-performance, low-cost packaging devices.

[0005] Currently, no effective solution has been proposed for the problems in the related technologies. Summary of the invention

[0006] In response to the problems in the related art, the present invention proposes a packaging structure suitable for multiple MOS chips, which solves the problem of uneven tin thickness between the copper sheet and the MOS tube bare chip, solves the EMC void defect through the waist-shaped through-hole design, can greatly reduce the manufacturing cost investment of the packaging structure, is easy to automate and batch integrate, and saves production costs, thereby solving the problems in the prior art that the packaging structure has low reliability, is difficult to pass the humidity sensitivity level test, and has high cost, difficult management, and low production efficiency for customized packaging of a single copper sheet for a single chip.

[0007] To this end, the specific technical solution adopted by the present invention is as follows:

[0008] A MOS chip packaging structure applicable to multiple types includes a chip packaging frame, an insulating pad is arranged on one side of the top of the chip packaging frame, a chip packaging component is arranged on the other side of the top of the chip packaging frame, and a copper sheet matching the chip packaging component is arranged on the top of the insulating pad.

[0009] Furthermore, an epoxy molding compound matching the chip packaging frame is arranged on the outer side of the top end of the copper sheet, and a third tin layer is arranged between one side of the bottom end of the copper sheet and the chip packaging frame.

[0010] Furthermore, the chip packaging assembly includes a MOS tube bare chip arranged on one side of the top of the chip packaging frame, and a first tin layer is arranged between the MOS tube bare chip and the chip packaging frame, and a second tin layer is arranged between the MOS tube bare chip and the copper sheet.

[0011] Furthermore, the chip packaging frame includes a base island arranged at the bottom end of the insulating pad, the top of the base island is connected to the middle of the bottom end of the copper sheet through the chip packaging component, and a pin is arranged on one side of the base island.

[0012] Furthermore, the insulating pad is fixedly connected to the base island through red glue, the base island is fixedly connected to the MOS tube bare chip through the first tin layer, and the pin is fixedly connected to the copper sheet through the third tin layer.

[0013] Furthermore, the copper sheet includes a chip connection portion arranged on the top of the insulating spacer, the chip connection portion is arranged as a planar structure, and a pin connection portion is arranged on one side of the chip connection portion.

[0014] Furthermore, a plurality of equally spaced first waist-shaped through holes are provided on one side of the top of the chip connection portion, a plurality of equally spaced second waist-shaped through holes are provided on the other side of the top of the chip connection portion, and a half waist-shaped through hole is provided on one side of the pin connection portion.

[0015] Furthermore, a first contact plane matching with the MOS tube bare chip is arranged at the bottom of the chip connection part, an overflow groove is opened on one side of the first contact plane, and a second contact plane matching with the third tin layer is arranged on one side of the bottom of the pin connection part.

[0016] Furthermore, the distances between the two ends of the first waist-shaped through hole and the overflow groove are equal, and the horizontal spacing between the semi-waist-shaped through hole and the pin is greater than the first preset distance.

[0017] Furthermore, the height of the insulating spacer is equal to the sum of the heights of the first tin-drawing layer, the MOS tube bare chip and the second tin-drawing layer, and the horizontal distance between the insulating spacer and the MOS tube bare chip is greater than the second preset distance.

[0018] The beneficial effects of the present invention are:

[0019] The present invention solves the problem of uneven tin thickness between the copper sheet and the bare chip of the MOS tube, avoids the disadvantage that the tin under the gate bus is too thin and easily forms a stress concentration point, the waist-shaped through-hole design of the copper sheet solves the tin cavity defect under the copper sheet, and the semi-waist-shaped plastic encapsulation material exhaust hole at the chip connection part of the copper sheet can solve the EMC cavity defect; in addition, the copper sheet adopts a non-bending plane design structure to simplify the stress condition. Through the simple and reliable copper sheet design, the production cost investment of the packaging structure can be greatly reduced, which is convenient for automation and batch integration, saving production costs and improving product competitiveness. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0021] Figure 1 It is a structural schematic diagram of a packaging structure applicable to multiple MOS chips according to an embodiment of the present invention;

[0022] Figure 2 It is a partial structural schematic diagram of a packaging structure applicable to multiple MOS chips according to an embodiment of the present invention;

[0023] Figure 3 It is a structural schematic diagram of a packaging structure and a fixture applicable to multiple MOS chips according to an embodiment of the present invention;

[0024] Figure 4 It is a structural schematic diagram of a chip packaging frame applicable to multiple MOS chip packaging structures according to an embodiment of the present invention;

[0025] Figure 5 It is a structural schematic diagram of another angle of a chip packaging frame in a plurality of MOS chip packaging structures according to an embodiment of the present invention;

[0026] Figure 6 is a partial structural schematic diagram from another angle of a packaging structure applicable to multiple MOS chips according to an embodiment of the present invention;

[0027] Figure 7 This is a schematic diagram of the structure of a copper sheet in a packaging structure applicable to multiple MOS chips according to an embodiment of the present invention;

[0028] Figure 8 It is a structural schematic diagram of another angle of a copper sheet in a packaging structure applicable to multiple MOS chips according to an embodiment of the present invention;

[0029] Fig. 9 It is a schematic diagram of the pits and gate bus of MOS tube bare chips of different sizes in the existing packaging structure;

[0030] Fig.10 It is a schematic diagram of the contact between the pits of the bare chip of the MOS tube and the gate bus in the existing packaging structure;

[0031] Fig.11 It is a schematic diagram of the exhaust principle of copper sheets in a plurality of MOS chip packaging structures according to an embodiment of the present invention;

[0032] Fig.12 It is a schematic diagram of stress analysis of copper sheets in a plurality of MOS chip packaging structures according to an embodiment of the present invention.

[0033] In the figure:

[0034] 1. Chip packaging frame; 101. Base island; 102. Pin; 2. Insulating pad; 3. Copper sheet; 301. Chip connection part; 3011. First contact plane; 3012. Overflow groove; 3013. Second contact plane; 302. Pin connection part; 303. First waist-shaped through hole; 304. Second waist-shaped through hole; 305. Half waist-shaped through hole; 4. Second tin layer; 5. MOS tube bare chip; 6. First tin layer; 7. Epoxy molding compound; 8. Third tin layer; 9. First fixture; 10. Second fixture. DETAILED DESCRIPTION

[0035] To further illustrate each embodiment, the present invention provides drawings, which are part of the disclosure of the present invention and are mainly used to illustrate the embodiments and can be used in conjunction with the relevant descriptions in the specification to explain the operating principles of the embodiments. With reference to these contents, ordinary technicians in the field should be able to understand other possible implementations and advantages of the present invention. The components in the figures are not drawn to scale, and similar component symbols are generally used to represent similar components.

[0036] According to an embodiment of the present invention, a packaging structure applicable to multiple MOS chips is provided.

[0037] The present invention is further described with reference to the accompanying drawings and specific embodiments. Figure 1-Figure 8 As shown, according to one embodiment of the present invention, a MOS chip packaging structure applicable to multiple types is provided, and the MOS chip packaging structure applicable to multiple types includes a chip packaging frame 1, an insulating pad 2 is arranged on one side of the top of the chip packaging frame 1, a chip packaging component is arranged on the other side of the top of the chip packaging frame 1, and a copper sheet 3 matching the chip packaging component is arranged on the top of the insulating pad 2.

[0038] In one embodiment, an epoxy molding compound 7 matching with the chip packaging frame 1 is disposed on the outer side of the top end of the copper sheet 3 , and a third tin layer 8 is disposed between one side of the bottom end of the copper sheet 3 and the chip packaging frame 1 .

[0039] In one embodiment, the chip packaging assembly includes a MOS tube bare chip 5 arranged on one side of the top of the chip packaging frame 1, and a first tin layer 6 is arranged between the MOS tube bare chip 5 and the chip packaging frame 1, and a second tin layer 4 is arranged between the MOS tube bare chip 5 and the copper sheet 3.

[0040] It should be noted that the epoxy molding compound 7 (Epoxy Molding Compound, EMC), the full name of which is epoxy resin molding compound, is a thermosetting chemical material used for semiconductor packaging. It is made of epoxy resin as the base resin, high-performance phenolic resin as the curing agent, and fillers such as silicon micropowder, as well as a variety of additives. Its main function is to protect the semiconductor chip from the influence of the external environment (water vapor, temperature, pollution, etc.), and to achieve composite functions such as thermal conductivity, insulation, moisture resistance, pressure resistance, and support; the copper sheet 3 (Clip) adopts a preparation process using continuous die stamping or cold heading, and is used to connect the MOS tube source and the frame LEADPAD, carry the working current of the device, and has the characteristics of low impedance, strong heat dissipation, and not easy to deform. The materials generally used are C194, A194, pure copper, silicon brass, silicon bronze, etc.; the MOS tube bare chip 5 (Die) is a single chip that has not been packaged, cut from a silicon wafer, and contains all the functional circuits of the chip; the chip packaging frame 1 (Lead Frame) is the packaging frame that carries the chip, and its material is the same or similar to that of the copper sheet 3, and its characteristics are small impedance, small thermal resistance, and high hardness and deformation resistance; Dimple is a convex surface and cross-sectional structure, which can be a truncated cone, a square cone, or a hemispherical shape; the gate bus is a collection of gate-level fingers of the power MOSFET; the above are all existing technologies and will not be elaborated here.

[0041] In one embodiment, the chip packaging frame 1 includes a base island 101 disposed at the bottom of the insulating spacer 2 , the top of the base island 101 is connected to the middle of the bottom of the copper sheet 3 through the chip packaging component, and a pin 102 is disposed on one side of the base island 101 .

[0042] In one embodiment, the insulating spacer 2 is fixedly connected to the base island 101 through red glue, the base island 101 is fixedly connected to the MOS tube bare chip 5 through the first tin layer 6, and the pin 102 is fixedly connected to the copper sheet 3 through the third tin layer 8.

[0043] It should be noted that the tin painting process is to melt the tin wire and then send the molten tin to the specified position through a carefully designed dispensing head. This position is related to the number and inner diameter of the dispensing head. Since the tinning process is simpler and has lower costs than the solder paste coating process, the amount of tin output is not easy to control during tinning. Therefore, the thickness of the tin layer cannot be fixed when the Clip is loaded after tinning, especially when passing through the reflow soldering furnace, the problem of uneven thickness of tin melting again is particularly prominent. Therefore, the thickness of the solder paste should be guaranteed as much as possible through the fixture during tinning, and the excess tin will overflow into the blank area or the overflow groove 3012. This is a prior art and will not be elaborated here.

[0044] Specifically, in the prior art, the thickness of the tin layer between the MOS tube bare chip 5 and the copper sheet 3, and the thickness of the tin layer between the copper sheet 3 and the chip packaging frame 1 are uneven, which will lead to the reliability failing to meet the automotive regulations, and even the solder thickness is too thin and uneven, thereby causing the gate bus on the MOS tube bare chip 5 to short-circuit and burst due to overcurrent.

[0045] Specifically, in order to solve the problem of uneven tin thickness between the copper sheet 3 and the MOS tube bare chip 5 in the prior art, the present invention first fixes the insulating pad 2 on the chip packaging frame 1 with red glue, and forms a second tin layer 6 on the surface of the chip packaging frame 1 by tinning to load the MOS tube bare chip 5; the surface of the MOS tube bare chip 5 forms a first tin layer 4 by tinning to load the copper sheet 3; then, the first fixture 9 and the second fixture 10 are used to press the two ends of the copper sheet 3, and the second fixture 10 on the right side provides a height limit to ensure that the tin thickness on the upper surface of the MOS tube bare chip 5 is uniform; finally, vacuum reflow soldering curing and annealing are performed to complete the preparation of the packaging structure.

[0046] It should also be noted that red glue has excellent thixotropic properties and air-free state, and can be used for bonding SMD parts on printed circuit boards before wave soldering. It is particularly suitable for use in situations requiring medium- and high-speed dispensing, high glue dot shape, high wet strength, and good electrical properties. After curing, the red glue has a lower shear strength of 12-18MPa, which is much smaller than the stress after solder curing, and thus will not cause delamination failure.

[0047] In one embodiment, the copper sheet 3 includes a chip connection portion 301 disposed on the top of the insulating spacer 2 . The chip connection portion 301 is configured as a planar structure, and a pin connection portion 302 is disposed on one side of the chip connection portion 301 .

[0048] Specifically, in the prior art, different sizes of Die concave points and Die graphics are as follows: Fig. 9 As shown in FIG. 1 , if a fixed position dimple is used, it is difficult to ensure that the dimple avoids the gate bus area, resulting in the tin under the gate bus being too thin and easily forming a stress concentration point. Fig.10 shown.

[0049] Specifically, the present invention eliminates the dimple design, eliminates the phenomenon of dimple pressing the gate bus, and can ensure uniform solder thickness between the MOS tube bare chip and the copper sheet 3, thereby preventing the Die electrical performance breakdown failure caused by gate bus stress concentration.

[0050] In one embodiment, a plurality of equally spaced first waist-shaped through holes 303 are opened on one side of the top of the chip connection part 301 , a plurality of equally spaced second waist-shaped through holes 304 are opened on the other side of the top of the chip connection part 301 , and a half waist-shaped through hole 305 is opened on one side of the pin connection part 302 .

[0051] In one embodiment, a first contact plane 3011 cooperating with the MOS tube bare chip 5 is provided at the bottom end of the chip connection part 301, an overflow groove 3012 is opened on one side of the first contact plane 3011, and a second contact plane 3013 cooperating with the third tin layer 8 is provided on one side of the bottom end of the pin connection part 302.

[0052] In one embodiment, the distances between the two ends of the first waist-shaped through hole 303 and the overflow groove 3012 are equal, and the horizontal distance between the semi-waist-shaped through hole 305 and the pin 102 is greater than the first preset distance.

[0053] In one embodiment, the height of the insulating spacer 2 is equal to the sum of the heights of the first tin layer 6, the MOS tube bare chip 5 and the second tin layer 4, and the horizontal distance between the insulating spacer 2 and the MOS tube bare chip 5 is greater than the second preset distance.

[0054] Specifically, the present invention solves the tin void defect below the copper sheet 3 by designing a waist-shaped through hole on the copper sheet 3 .

[0055] Specifically, when part of the tinning process is too thick or too much, the excess solder and air can be discharged upward from the bottom of the hole through the waist-shaped through hole in the tinning process to avoid the formation of large particle voids (Void) between the copper sheet 3 and the MOS tube bare chip 5, and to avoid the chip packaging structure from causing excessive on-resistance (Rdson) due to excessive thermal resistance, thereby degrading product performance.

[0056] Specifically, the half-waist-shaped plastic encapsulation material vent hole 304 at the chip connection portion 301 of the copper sheet 3 of the present invention can solve the EMC void defect; when the copper sheet 3 in the prior art is not provided with a vent hole, the EMC will have voids or material shortages.

[0057] Specifically, Fig.11 As shown, when the EMC is squeezed into the bottom of the copper sheet 3 from the left and right sides, a fixed cavity is formed between the bottom of the copper sheet 3 and the mold cavity. When the air in the cavity is not completely discharged, the EMC mixed with air and moisture will form a bonding surface at the central chip connection part 301 of the copper sheet 3. The air and moisture solidified at the bonding surface are likely to form material shortages and large internal voids (Void). The present invention provides a semi-waist-shaped plastic encapsulation material exhaust hole 304 on the copper sheet 3. The semi-waist-shaped plastic encapsulation material exhaust hole 304 needs to at least partially face the distance between the leadFrame base island and the pin paddle, which can easily guide defects such as material shortages and Voids to the overflow area outside the package, thereby avoiding defects during the product molding process.

[0058] Specifically, in the present invention, the exhaust holes ensure that the left and right sides are located in the middle of the glue inlet, so that water vapor and air bubbles gather at the junction of the parting lines and are discharged upward through the holes to avoid EMC material shortage and void defects. >0.11 ensures that the leadframe and the exhaust holes have a facing area, the air is discharged in the shortest distance, and the exhaust resistance is minimized.

[0059] Specifically, the copper sheet 3 adopts a non-bending flat design structure to simplify the stress condition.

[0060] Specifically, Fig.12 As shown, the Clip of the present invention adopts a non-bending flat design structure, which can greatly decompose and optimize the effect of thermal expansion stress on the Die when the Clip is working. If a traditional arch-shaped bending design structure is adopted, as shown in the figure below, the thermal stress of the raised part and the EMC thermal stress under the Clip are superimposed and then transmitted to the Die through the bending point of the Clip, thereby aggravating the stress concentration of the Die.

[0061] Specifically, in the above embodiment, the size of the excess tin overflow holes 302 and 303 of the copper sheet 3 is 0.2*1, and the pinch is 1.12; the size of the insulating spacer 2 is 4*0.9*0.16 (the thickness is controlled according to the thickness of the MOS tube bare chip 5 and the tin thickness); the size of the semi-waist plastic packaging material exhaust hole 304 of the copper sheet 3 is 0.5*0.2, and the distance from the base island of the chip packaging frame 1 and the pin paddle is greater than 0.11; the spacing between the insulating spacer 2 and the MOS tube bare chip 5 is greater than 0.12.

[0062] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims

1. A packaging structure applicable to multiple MOS chips, characterized in that: The MOS chip packaging structure applicable to various types comprises a chip packaging frame (1), an insulating pad (2) is arranged on one side of the top of the chip packaging frame (1), a chip packaging component is arranged on the other side of the top of the chip packaging frame (1), and a copper sheet (3) matching the chip packaging component is arranged on the top of the insulating pad (2).

2. The packaging structure for multiple MOS chips according to claim 1, characterized in that: An epoxy molding compound (7) matching the chip packaging frame (1) is arranged on the outer side of the top end of the copper sheet (3), and a third tin layer (8) is arranged between one side of the bottom end of the copper sheet (3) and the chip packaging frame (1).

3. The packaging structure applicable to multiple MOS chips according to claim 2, characterized in that: The chip packaging component comprises a MOS tube bare chip (5) arranged on one side of the top end of the chip packaging frame (1), a first tin layer (6) is arranged between the MOS tube bare chip (5) and the chip packaging frame (1), and a second tin layer (4) is arranged between the MOS tube bare chip (5) and the copper sheet (3).

4. The packaging structure applicable to multiple MOS chips according to claim 3, characterized in that: The chip packaging frame (1) comprises a base island (101) arranged at the bottom end of the insulating pad (2); the top end of the base island (101) is connected to the middle part of the bottom end of the copper sheet (3) through a chip packaging component; and a pin (102) is arranged on one side of the base island (101).

5. The packaging structure applicable to multiple MOS chips according to claim 4, characterized in that: The insulating pad (2) is fixedly connected to the base island (101) via red glue, the base island (101) is fixedly connected to the MOS tube bare chip (5) via the first tin layer (6), and the pin (102) is fixedly connected to the copper sheet (3) via the third tin layer (8).

6. The packaging structure applicable to multiple MOS chips according to claim 4, characterized in that: The copper sheet (3) comprises a chip connection portion (301) arranged at the top of the insulating spacer (2); the chip connection portion (301) is arranged as a planar structure, and a pin connection portion (302) is arranged on one side of the chip connection portion (301).

7. The packaging structure applicable to multiple MOS chips according to claim 6, characterized in that: A plurality of first waist-shaped through holes (303) arranged at equal distances are provided on one side of the top of the chip connection part (301), a plurality of second waist-shaped through holes (304) arranged at equal distances are provided on the other side of the top of the chip connection part (301), and a half waist-shaped through hole (305) is provided on one side of the pin connection part (302).

8. The packaging structure applicable to multiple MOS chips according to claim 7, characterized in that: The bottom end of the chip connection portion (301) is provided with a first contact plane (3011) that matches the MOS tube bare chip (5), one side of the first contact plane (3011) is provided with an overflow groove (3012), and the bottom end of the pin connection portion (302) is provided with a second contact plane (3013) that matches the third tin layer (8).

9. The packaging structure applicable to multiple MOS chips according to claim 8, characterized in that: The distances between the two ends of the first waist-shaped through hole (303) and the overflow groove (3012) are equal, and the horizontal distance between the semi-waist-shaped through hole (305) and the pin (102) is greater than a first preset distance.

10. The packaging structure applicable to multiple MOS chips according to claim 4, characterized in that: The height of the insulating spacer (2) is equal to the sum of the heights of the first tin-drawing layer (6), the MOS tube bare chip (5) and the second tin-drawing layer (4), and the horizontal spacing between the insulating spacer (2) and the MOS tube bare chip (5) is greater than a second preset distance.

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