Semiconductor device and manufacturing method thereof

Abstract

The invention provides a semiconductor device and a manufacturing method thereof. The semiconductor device comprises a substrate; the capacitor structure comprises a lower pole plate, a dielectric layer and an upper pole plate which are formed on the substrate from bottom to top, and the lower pole plate extends to the periphery of the upper pole plate; the conductive structure is formed on the portion, on the periphery of the upper pole plate, of the lower pole plate, the inductance structure is formed on the upper pole plate, the conductive structure is connected with the lower pole plate, and the inductance structure is connected with the upper pole plate. According to the technical scheme, the problem that the combination of a capacitor structure and an inductor structure occupies too large chip area is solved.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor integrated circuit manufacturing, and in particular to a semiconductor device and a manufacturing method thereof. Background Art

[0002] In RF products, capacitors and inductors are often used in combination. However, there are the following problems:

[0003] (1) The capacitors and inductors are arranged horizontally on the chip, occupying a large chip area (e.g., occupying about 30% of the chip area in total);

[0004] (2) In order to prevent the generation of parasitic capacitance and signal interference to capacitors and inductors, metal interconnects, virtual metal layers, and device structures must not be designed directly below capacitors and inductors, resulting in a waste of chip area.

[0005] Therefore, it is necessary to improve the structure combining capacitors and inductors to solve the above problems. Summary of the invention

[0006] The object of the present invention is to provide a semiconductor device and a method for manufacturing the same, which solves the problem that the combination of a capacitor structure and an inductor structure occupies too large a chip area.

[0007] To achieve the above object, the present invention provides a semiconductor device, comprising:

[0008] substrate;

[0009] A capacitor structure, comprising a lower plate, a dielectric layer and an upper plate formed on the substrate from bottom to top, wherein the lower plate extends to the periphery of the upper plate;

[0010] A conductive structure and an inductor structure, wherein the conductive structure is formed on the lower plate outside the upper plate, the inductor structure is formed on the upper plate, the conductive structure is connected to the lower plate, and the inductor structure is connected to the upper plate.

[0011] Optionally, the inductor structure is a serpentine winding structure.

[0012] Optionally, the conductive structure is electrically connected to the lower electrode plate through a plurality of first conductive plugs, and the inductive structure is electrically connected to the upper electrode plate through a plurality of second conductive plugs.

[0013] Optionally, the second conductive plugs are arranged in an array, and the inductor structure is wound from above the outermost second conductive plug to above the innermost second conductive plug, so that the inductor structure can be wound multiple times.

[0014] Optionally, the conductive structure surrounds the inductive structure in a non-closed manner.

[0015] The present invention also provides a method for manufacturing a semiconductor device, comprising:

[0016] providing a substrate;

[0017] Forming a capacitor structure, the capacitor structure comprising a lower plate, a dielectric layer and an upper plate formed on the substrate from bottom to top, the lower plate extending to the periphery of the upper plate;

[0018] A conductive structure is formed on the lower electrode plate outside the upper electrode plate, and an inductor structure is formed on the upper electrode plate, wherein the conductive structure is connected to the lower electrode plate, and the inductor structure is connected to the upper electrode plate.

[0019] Optionally, the inductor structure is a serpentine winding structure.

[0020] Optionally, the conductive structure is electrically connected to the lower electrode plate through a plurality of first conductive plugs, and the inductive structure is electrically connected to the upper electrode plate through a plurality of second conductive plugs.

[0021] Optionally, the second conductive plugs are arranged in an array, and the inductor structure is wound from above the outermost second conductive plug to above the innermost second conductive plug, so that the inductor structure can be wound multiple times.

[0022] Optionally, the conductive structure surrounds the inductive structure in a non-closed manner.

[0023] Compared with the prior art, the technical solution of the present invention has the following beneficial effects:

[0024] 1. The semiconductor device of the present invention comprises: a substrate; a capacitor structure, comprising a lower plate, a dielectric layer and an upper plate formed on the substrate from bottom to top, wherein the lower plate extends to the periphery of the upper plate; a conductive structure and an inductive structure, wherein the conductive structure is formed on the lower plate at the periphery of the upper plate, the inductive structure is formed on the upper plate, the conductive structure is connected to the lower plate, and the inductive structure is connected to the upper plate. The problem that the combination of the capacitor structure and the inductive structure occupies too much chip area is solved.

[0025] 2. The manufacturing method of the semiconductor device of the present invention comprises: providing a substrate; forming a capacitor structure, the capacitor structure comprising a lower plate, a dielectric layer and an upper plate formed on the substrate from bottom to top, the lower plate extending to the periphery of the upper plate; forming a conductive structure on the lower plate at the periphery of the upper plate, and forming an inductor structure on the upper plate, the conductive structure being connected to the lower plate, and the inductor structure being connected to the upper plate. The problem that the capacitor structure and the inductor structure are combined and occupy too much chip area is solved. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] Figure 1 is a schematic top view of a semiconductor device according to an embodiment of the present invention;

[0027] Figure 2 yes Figure 1 The schematic cross-sectional view of the semiconductor device shown is along the AA' direction;

[0028] Figure 3 yes Figure 1 A schematic top view of an inductor structure and a conductive structure in the semiconductor device shown;

[0029] Figure 4 The flowchart of the method for manufacturing a semiconductor device according to an embodiment of the present invention is shown.

[0030] Among them, Figure 1 to Figure 4 The reference numerals are described as follows:

[0031] 111 - lower electrode plate; 112 - dielectric layer; 113 - upper electrode plate; 121 - first conductive plug; 122 - conductive structure; 131 - second conductive plug; 132 - inductor structure. DETAILED DESCRIPTION

[0032] In order to make the purpose, advantages and features of the present invention more clear, the semiconductor device and the manufacturing method thereof proposed by the present invention are further described in detail below. It should be noted that the drawings are all in a very simplified form and are not in precise proportions, which are only used to conveniently and clearly assist in explaining the purpose of the embodiments of the present invention.

[0033] An embodiment of the present invention provides a semiconductor device, comprising: a substrate; a capacitor structure, comprising a lower plate, a dielectric layer and an upper plate formed from bottom to top on the substrate, the lower plate extending to the periphery of the upper plate; a conductive structure and an inductive structure, the conductive structure being formed on the lower plate at the periphery of the upper plate, the inductive structure being formed on the upper plate, the conductive structure being connected to the lower plate, and the inductive structure being connected to the upper plate.

[0034] See below Figure 1 to Figure 3 The semiconductor device provided by this embodiment is described in detail.

[0035] The base (not shown) may include a substrate and a first insulating medium layer located on the substrate.

[0036] A metal interconnect structure may be formed in the first insulating dielectric layer.

[0037] The material of the substrate can be any suitable base material known to those skilled in the art, for example, it can be at least one of the following materials: silicon, germanium, silicon germanium, carbon silicon, carbon germanium silicon, indium arsenide, gallium arsenide, indium phosphide or semiconductor on insulator (SOI, such as silicon on insulator), etc.

[0038] A device structure such as a transistor may be formed on the substrate, the first insulating dielectric layer covers the device structure, and the metal interconnection structure may be electrically connected to the device structure.

[0039] The capacitor structure is formed on the first insulating dielectric layer.

[0040] The capacitor structure includes a lower plate 111 , a dielectric layer 112 , and an upper plate 113 formed on the substrate from bottom to top, and the lower plate 111 extends to the periphery of the upper plate 113 .

[0041] Among them, the dielectric layer 112 can be located only between the lower electrode plate 111 and the upper electrode plate 113, that is, the dielectric layer 112 and the upper electrode plate 113 are stacked on part of the lower electrode plate 111; or, the dielectric layer 112 can extend to the periphery of the upper electrode plate 113, that is, the dielectric layer 112 is located on the entire lower electrode plate 111, and the upper electrode plate 113 is located on part of the dielectric layer 112.

[0042] The material of the lower electrode plate 111 is metal nitride, metal or polysilicon, and the material of the upper electrode plate 113 is metal nitride, metal or polysilicon. The materials of the lower electrode plate 111 and the upper electrode plate 113 can be the same or different.

[0043] When the material of the lower plate 111 and the upper plate 113 is metal nitride or metal, the capacitor structure is a MIM capacitor; when the material of the lower plate 111 and the upper plate 113 is polysilicon, the capacitor structure is a PIP capacitor; when the material of one of the lower plate 111 and the upper plate 113 is metal nitride or metal and the material of the other plate is polysilicon, the capacitor structure is a PIM capacitor.

[0044] The material of the dielectric layer 112 is preferably a high-K (relative dielectric constant) dielectric, such as at least one of zinc oxide, hafnium oxide, titanium oxide, and zirconium oxide. It should be noted that the material of the dielectric layer 112 can also be at least one of silicon oxide, silicon oxynitride, silicon nitride, and ONO (silicon oxide-silicon nitride-silicon oxide).

[0045] The conductive structure 122 is formed on the lower electrode plate 111 outside the upper electrode plate 113 , and the inductor structure 132 is formed on the upper electrode plate 113 .

[0046] The conductive structure 122 is connected to the lower electrode plate 111 , and the inductor structure 132 is connected to the upper electrode plate 113 .

[0047] The inductor structure 132 is a serpentine winding structure.

[0048] In one embodiment, the conductive structure 122 is electrically connected to the lower plate 111 through a plurality of first conductive plugs 121; the inductor structure 132 is electrically connected to the upper plate 113 through a plurality of second conductive plugs 131. The plurality of first conductive plugs 121 and the plurality of second conductive plugs 131 are manufactured simultaneously, and the conductive structure 122 and the inductor structure 132 are manufactured simultaneously. In other embodiments, the first conductive plugs 121 and the second conductive plugs 131 may not be formed, and the conductive structure 122 is directly connected to the lower plate 111, and the inductor structure 132 is directly connected to the upper plate 113.

[0049] The second conductive plugs 131 are arranged in an array, and the inductor structure 132 is wound from the outermost second conductive plug 131 to the innermost second conductive plug 131 , so that the inductor structure 132 can be wound multiple times.

[0050] The conductive structure 122 surrounds the inductor structure 132 in a non-enclosed manner, so that the inductor structure 132 can be connected.

[0051] The conductive structure 122 and the inductor structure 132 are located in the same layer, and the conductive structure 122 surrounds the inductor structure 132 in a non-enclosed manner.

[0052] exist Figure 1 to Figure 3 In the illustrated embodiment, the plurality of second conductive plugs 131 form a rectangular array, the plurality of first conductive plugs 121 surround the plurality of second conductive plugs 131 on three sides, and the conductive structure 122 surrounds the inductor structure 132 on three sides, so that as many of the first conductive plugs 121 as possible are arranged on the lower plate 111 outside the upper plate 113, thereby reducing the contact resistance between the lower plate 111 and the plurality of first conductive plugs 121. In other embodiments, the conductive structure 122 may also surround the inductor structure 132 on four sides, and only a gap needs to be left for connecting the inductor structure 132.

[0053] The projections of the multiple first conductive plugs 121 in the direction perpendicular to the substrate surface can be completely located within the projection range of the conductive structure 122 in the direction perpendicular to the substrate surface, and the projections of the multiple second conductive plugs 131 in the direction perpendicular to the substrate surface can be completely located within the projection range of the inductive structure 132 in the direction perpendicular to the substrate surface.

[0054] A second insulating dielectric layer (not shown) may be formed on the substrate, and the second insulating dielectric layer covers the capacitor structure, the conductive structure 122 and the inductor structure 132 .

[0055] A conductive interconnect structure (not shown) may also be formed in the second insulating dielectric layer on the conductive structure 122 and the inductive structure 132 , and the conductive interconnect structure is used to connect the conductive structure 122 and the inductive structure 132 , respectively.

[0056] From the above content, it can be seen that since the inductor structure 132 is formed on the upper electrode plate 113 in the capacitor structure, the capacitor structure and the inductor structure 132 are vertical structures electrically connected up and down, and the lower electrode plate 111 is electrically connected from the conductive structure 122, that is, the capacitor structure and the inductor structure 132 share the same horizontal area of ​​the chip, thereby significantly reducing the chip area occupied by the combination of the capacitor structure and the inductor structure 132.

[0057] In order to prevent the generation of parasitic capacitance and signal interference to the capacitor structure and the inductor structure 132, it is required that no metal interconnect structure, virtual metal layer and device structure should be formed directly below the capacitor structure and the inductor structure 132, resulting in a waste of chip area. However, in the present invention, since the capacitor structure and the inductor structure 132 share the same horizontal area of ​​the chip, the metal interconnect structure, virtual metal layer and device structure can be set in the saved chip area, thereby reducing the waste of chip area.

[0058] In the existing capacitor structure, in order to make the capacitor structure have a high quality factor, it is necessary to reduce the contact resistance between the upper plate and the multiple conductive plugs on the upper plate. Therefore, the number of conductive plugs needs to be increased to increase the total contact area between all the conductive plugs and the upper plate, and then a large-area metal block needs to be formed on the conductive plug to connect all the conductive plugs. However, there are challenges in the manufacturing process of the large-area metal block: on the one hand, the large-area metal block is manufactured together with other film layer structures in the same layer, and the etching rate of forming the large-area metal block is greater than the etching rate of forming other small-area film layer structures, resulting in that when the large-area metal block is just etched, the other small-area film layer structures have been over-etched, thereby affecting the formation of the other small-area film layer structures; on the other hand, in the process of manufacturing the conductive interconnect structure above the large-area metal block, when the metal on the surface of the insulating dielectric layer on the large-area metal block is ground, there will also be a grinding load effect, resulting in metal residual defects on the surface of the insulating dielectric layer in the area where the large-area metal block is not formed, that is, there is a problem of uneven grinding. In the present invention, the inductor structure 132 is formed on the upper electrode plate 113, that is, the upper electrode plate 113 is connected through the inductor structure 132, and the inductor structure 132 is not a whole large-area metal layer, but a serpentine winding structure, so that when etching to form the inductor structure 132, a small-area structure is also etched, that is, the etching rate of forming the inductor structure 132 is consistent with the etching rate of other film layer structures located on the same layer of the inductor structure 132, and will not affect the production of other film layer structures; and in the process of producing the conductive interconnect structure above the inductor structure 132, when the metal on the surface of the second insulating dielectric layer on the inductor structure 132 is ground, the load effect of grinding can be reduced, avoiding the presence of metal residual defects on the surface of the second insulating dielectric layer in the area where the inductor structure 132 is not formed, thereby improving the uniformity of grinding. Therefore, when the number of the second conductive plugs 131 under the inductor structure 132 is increased in order to improve the quality factor of the capacitor structure, only the number of turns of the inductor structure 132 will be increased without increasing the process difficulty.

[0059] Furthermore, in the existing capacitor structure, if a capacitor structure with a larger capacitance value is to be obtained, the area of ​​the upper electrode plate needs to be increased, which results in an increase in the area of ​​the metal block, which in turn makes the manufacturing process of the metal block more difficult. Therefore, in order to increase the capacitance value of the capacitor structure while avoiding increasing the area of ​​the metal block, a larger capacitance value can only be obtained by designing multiple capacitor structures in parallel on the horizontal plane of the chip, resulting in an increase in the occupied chip area. In the present invention, when the area of ​​the upper electrode plate 113 is increased in order to increase the capacitance value of the capacitor structure, since the inductor structure 132 is not a large-area metal layer of a whole piece, the process difficulty of manufacturing the inductor structure 132 will not be increased, and there is no need to design multiple capacitor structures in parallel.

[0060] In summary, the present invention provides a semiconductor device, comprising: a substrate; a capacitor structure, comprising a lower plate, a dielectric layer and an upper plate formed on the substrate from bottom to top, the lower plate extending to the periphery of the upper plate; a conductive structure and an inductive structure, the conductive structure being formed on the lower plate at the periphery of the upper plate, the inductive structure being formed on the upper plate, the conductive structure being connected to the lower plate, and the inductive structure being connected to the upper plate. The semiconductor device provided by the present invention solves the problem that the combination of the capacitor structure and the inductive structure occupies too much chip area.

[0061] Based on the same inventive concept, an embodiment of the present invention provides a method for manufacturing a semiconductor device, referring to Figure 4 ,from Figure 4 It can be seen that the method for manufacturing the semiconductor device includes:

[0062] Step S1, providing a substrate;

[0063] Step S2, forming a capacitor structure, wherein the capacitor structure includes a lower plate, a dielectric layer and an upper plate formed on the substrate from bottom to top, wherein the lower plate extends to the periphery of the upper plate;

[0064] Step S3, forming a conductive structure on the lower electrode plate outside the upper electrode plate, and forming an inductor structure on the upper electrode plate, wherein the conductive structure is connected to the lower electrode plate, and the inductor structure is connected to the upper electrode plate.

[0065] See below Figure 1 to Figure 3 The method for manufacturing the semiconductor device provided in this embodiment is described in detail.

[0066] According to step S1, a substrate (not shown) is provided.

[0067] The base may include a substrate and a first insulating medium layer located on the substrate.

[0068] A metal interconnect structure may be formed in the first insulating dielectric layer.

[0069] The material of the substrate can be any suitable base material known to those skilled in the art, for example, it can be at least one of the following materials: silicon, germanium, silicon germanium, carbon silicon, carbon germanium silicon, indium arsenide, gallium arsenide, indium phosphide or semiconductor on insulator (SOI, such as silicon on insulator), etc.

[0070] A device structure such as a transistor may be formed on the substrate, the first insulating dielectric layer covers the device structure, and the metal interconnection structure may be electrically connected to the device structure.

[0071] According to step S2 , a capacitor structure is formed. The capacitor structure includes a lower plate 111 , a dielectric layer 112 , and an upper plate 113 formed on the substrate from bottom to top. The lower plate 111 extends to the periphery of the upper plate 113 .

[0072] The capacitor structure is formed on the first insulating dielectric layer.

[0073] Among them, the dielectric layer 112 can be located only between the lower electrode plate 111 and the upper electrode plate 113, that is, the dielectric layer 112 and the upper electrode plate 113 are stacked on part of the lower electrode plate 111; or, the dielectric layer 112 can extend to the periphery of the upper electrode plate 113, that is, the dielectric layer 112 is located on the entire lower electrode plate 111, and the upper electrode plate 113 is located on part of the dielectric layer 112.

[0074] Taking the example that the dielectric layer 112 is only located between the lower plate 111 and the upper plate 113, the steps of forming the capacitor structure may include: first, forming a lower plate material layer, a dielectric material layer and an upper plate material layer from bottom to top on the substrate; then, etching the upper plate material layer and the dielectric material layer to expose the lower plate material layer, and the remaining upper plate material layer and the dielectric material layer serve as the upper plate 113 and the dielectric layer 112 respectively; then, etching the exposed portion of the lower plate material layer to expose the substrate, and the remaining lower plate material layer serves as the lower plate 111.

[0075] The material of the lower electrode plate 111 is metal nitride, metal or polysilicon, and the material of the upper electrode plate 113 is metal nitride, metal or polysilicon. The materials of the lower electrode plate 111 and the upper electrode plate 113 can be the same or different.

[0076] When the material of the lower plate 111 and the upper plate 113 is metal nitride or metal, the capacitor structure is a MIM capacitor; when the material of the lower plate 111 and the upper plate 113 is polysilicon, the capacitor structure is a PIP capacitor; when the material of one of the lower plate 111 and the upper plate 113 is metal nitride or metal and the material of the other plate is polysilicon, the capacitor structure is a PIM capacitor.

[0077] The material of the dielectric layer 112 is preferably a high-K (relative dielectric constant) dielectric, such as at least one of zinc oxide, hafnium oxide, titanium oxide, and zirconium oxide. It should be noted that the material of the dielectric layer 112 can also be at least one of silicon oxide, silicon oxynitride, silicon nitride, and ONO (silicon oxide-silicon nitride-silicon oxide).

[0078] According to step S3 , a conductive structure 122 is formed on the lower electrode plate 111 outside the upper electrode plate 113 , and an inductor structure 132 is formed on the upper electrode plate 113 .

[0079] The conductive structure 122 is connected to the lower electrode plate 111 , and the inductor structure 132 is connected to the upper electrode plate 113 .

[0080] The inductor structure 132 is a serpentine winding structure.

[0081] In one embodiment, the conductive structure 122 is electrically connected to the lower plate 111 through a plurality of first conductive plugs 121; the inductor structure 132 is electrically connected to the upper plate 113 through a plurality of second conductive plugs 131. The plurality of first conductive plugs 121 and the plurality of second conductive plugs 131 are manufactured simultaneously, and the conductive structure 122 and the inductor structure 132 are manufactured simultaneously. In other embodiments, the first conductive plugs 121 and the second conductive plugs 131 may not be formed, and the conductive structure 122 is directly connected to the lower plate 111, and the inductor structure 132 is directly connected to the upper plate 113.

[0082] The second conductive plugs 131 are arranged in an array, and the inductor structure 132 is wound from the outermost second conductive plug 131 to the innermost second conductive plug 131 , so that the inductor structure 132 can be wound multiple times.

[0083] The conductive structure 122 surrounds the inductor structure 132 in a non-enclosed manner, so that the inductor structure 132 can be connected.

[0084] The conductive structure 122 and the inductor structure 132 are located in the same layer, and the conductive structure 122 surrounds the inductor structure 132 in a non-enclosed manner.

[0085] exist Figure 1 to Figure 3 In the illustrated embodiment, the plurality of second conductive plugs 131 form a rectangular array, the plurality of first conductive plugs 121 surround the plurality of second conductive plugs 131 on three sides, and the conductive structure 122 surrounds the inductor structure 132 on three sides, so that as many of the first conductive plugs 121 as possible are arranged on the lower plate 111 outside the upper plate 113, thereby reducing the contact resistance between the lower plate 111 and the plurality of first conductive plugs 121. In other embodiments, the conductive structure 122 may also surround the inductor structure 132 on four sides, and only a gap needs to be left for connecting the inductor structure 132.

[0086] The projections of the multiple first conductive plugs 121 in the direction perpendicular to the substrate surface can be completely located within the projection range of the conductive structure 122 in the direction perpendicular to the substrate surface, and the projections of the multiple second conductive plugs 131 in the direction perpendicular to the substrate surface can be completely located within the projection range of the inductive structure 132 in the direction perpendicular to the substrate surface.

[0087] A second insulating dielectric layer (not shown) may be formed on the substrate, and the second insulating dielectric layer covers the capacitor structure, the conductive structure 122, and the inductor structure 132. The conductive structure 122 and the inductor structure 132 may be formed by etching the second insulating dielectric layer and depositing metal material in the through holes and / or grooves formed by etching.

[0088] A conductive interconnect structure (not shown) may also be formed in the second insulating dielectric layer on the conductive structure 122 and the inductive structure 132 , and the conductive interconnect structure is used to connect the conductive structure 122 and the inductive structure 132 , respectively.

[0089] From the above content, it can be seen that since the inductor structure 132 is formed on the upper electrode plate 113 in the capacitor structure, the capacitor structure and the inductor structure 132 are vertical structures electrically connected up and down, and the lower electrode plate 111 is electrically connected from the conductive structure 122, that is, the capacitor structure and the inductor structure 132 share the same horizontal area of ​​the chip, thereby significantly reducing the chip area occupied by the combination of the capacitor structure and the inductor structure 132.

[0090] In order to prevent the generation of parasitic capacitance and signal interference to the capacitor structure and the inductor structure 132, it is required that no metal interconnect structure, virtual metal layer and device structure should be formed directly below the capacitor structure and the inductor structure 132, resulting in a waste of chip area. However, in the present invention, since the capacitor structure and the inductor structure 132 share the same horizontal area of ​​the chip, the metal interconnect structure, virtual metal layer and device structure can be set in the saved chip area, thereby reducing the waste of chip area.

[0091] In the existing capacitor structure, in order to make the capacitor structure have a high quality factor, it is necessary to reduce the contact resistance between the upper plate and the multiple conductive plugs on the upper plate. Therefore, the number of conductive plugs needs to be increased to increase the total contact area between all the conductive plugs and the upper plate, and then a large-area metal block needs to be formed on the conductive plug to connect all the conductive plugs. However, there are challenges in the manufacturing process of the large-area metal block: on the one hand, the large-area metal block is manufactured together with other film layer structures in the same layer, and the etching rate of forming the large-area metal block is greater than the etching rate of forming other small-area film layer structures, resulting in that when the large-area metal block is just etched, the other small-area film layer structures have been over-etched, thereby affecting the formation of the other small-area film layer structures; on the other hand, in the process of manufacturing the conductive interconnect structure above the large-area metal block, when the metal on the surface of the insulating dielectric layer on the large-area metal block is ground, there will also be a grinding load effect, resulting in metal residual defects on the surface of the insulating dielectric layer in the area where the large-area metal block is not formed, that is, there is a problem of uneven grinding. In the present invention, the inductor structure 132 is formed on the upper electrode plate 113, that is, the upper electrode plate 113 is connected through the inductor structure 132, and the inductor structure 132 is not a whole large-area metal layer, but a serpentine winding structure, so that when etching to form the inductor structure 132, a small-area structure is also etched, that is, the etching rate of forming the inductor structure 132 is consistent with the etching rate of other film layer structures located on the same layer of the inductor structure 132, and will not affect the production of other film layer structures; and in the process of producing the conductive interconnect structure above the inductor structure 132, when the metal on the surface of the second insulating dielectric layer on the inductor structure 132 is ground, the load effect of grinding can be reduced, avoiding the presence of metal residual defects on the surface of the second insulating dielectric layer in the area where the inductor structure 132 is not formed, thereby improving the uniformity of grinding. Therefore, when the number of the second conductive plugs 131 under the inductor structure 132 is increased in order to improve the quality factor of the capacitor structure, only the number of turns of the inductor structure 132 will be increased without increasing the process difficulty.

[0092] Furthermore, in the existing capacitor structure, if a capacitor structure with a larger capacitance value is to be obtained, the area of ​​the upper electrode plate needs to be increased, which results in an increase in the area of ​​the metal block, which in turn makes the manufacturing process of the metal block more difficult. Therefore, in order to increase the capacitance value of the capacitor structure while avoiding increasing the area of ​​the metal block, a larger capacitance value can only be obtained by designing multiple capacitor structures in parallel on the horizontal plane of the chip, resulting in an increase in the occupied chip area. In the present invention, when the area of ​​the upper electrode plate 113 is increased in order to increase the capacitance value of the capacitor structure, since the inductor structure 132 is not a large-area metal layer of a whole piece, the process difficulty of manufacturing the inductor structure 132 will not be increased, and there is no need to design multiple capacitor structures in parallel.

[0093] In summary, the present invention provides a method for manufacturing a semiconductor device, comprising: providing a substrate; forming a capacitor structure, the capacitor structure comprising a lower plate, a dielectric layer and an upper plate formed on the substrate from bottom to top, the lower plate extending to the periphery of the upper plate; forming a conductive structure on the lower plate at the periphery of the upper plate, and forming an inductor structure on the upper plate, the conductive structure being connected to the lower plate, and the inductor structure being connected to the upper plate. The method for manufacturing a semiconductor device provided by the present invention solves the problem that the combination of the capacitor structure and the inductor structure occupies too much chip area.

[0094] The above description is only a description of the preferred embodiments of the present invention, and is not intended to limit the scope of the present invention. Any changes or modifications made by a person skilled in the art in the field of the present invention based on the above disclosure shall fall within the scope of protection of the claims.

Claims

1. A semiconductor device, characterized in that: include: substrate; A capacitor structure, comprising a lower plate, a dielectric layer and an upper plate formed on the substrate from bottom to top, wherein the lower plate extends to the periphery of the upper plate; A conductive structure and an inductor structure, wherein the conductive structure is formed on the lower plate outside the upper plate, the inductor structure is formed on the upper plate, the conductive structure is connected to the lower plate, and the inductor structure is connected to the upper plate.

2. The semiconductor device according to claim 1, wherein The inductor structure is a serpentine winding structure.

3. The semiconductor device according to claim 1, wherein The conductive structure is electrically connected to the lower electrode plate through a plurality of first conductive plugs, and the inductive structure is electrically connected to the upper electrode plate through a plurality of second conductive plugs.

4. The semiconductor device according to claim 3, characterized in that The second conductive plugs are arranged in an array, and the inductor structure is wound from above the outermost second conductive plugs to above the innermost second conductive plugs one by one, so that the inductor structure can be wound multiple times.

5. The semiconductor device according to claim 1, wherein: The conductive structure surrounds the inductive structure in a non-closed manner.

6. A method for manufacturing a semiconductor device, characterized in that: include: providing a substrate; Forming a capacitor structure, the capacitor structure comprising a lower plate, a dielectric layer and an upper plate formed on the substrate from bottom to top, the lower plate extending to the periphery of the upper plate; A conductive structure is formed on the lower electrode plate outside the upper electrode plate, and an inductor structure is formed on the upper electrode plate, wherein the conductive structure is connected to the lower electrode plate, and the inductor structure is connected to the upper electrode plate.

7. The method for manufacturing a semiconductor device according to claim 6, wherein: The inductor structure is a serpentine winding structure.

8. The method for manufacturing a semiconductor device according to claim 6, wherein: The conductive structure is electrically connected to the lower electrode plate through a plurality of first conductive plugs, and the inductive structure is electrically connected to the upper electrode plate through a plurality of second conductive plugs.

9. The method for manufacturing a semiconductor device according to claim 8, wherein: The second conductive plugs are arranged in an array, and the inductor structure is wound from above the outermost second conductive plugs to above the innermost second conductive plugs one by one, so that the inductor structure can be wound multiple times.

10. The method for manufacturing a semiconductor device according to claim 6, wherein: The conductive structure surrounds the inductive structure in a non-closed manner.

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