Control circuit, switched capacitor converter, chip and electronic equipment

Abstract

The present application provides a control circuit, a switched capacitor converter, a chip, and an electronic device. The control circuit includes: a control voltage output circuit and a level conversion circuit. The control voltage output circuit can obtain a control voltage based on a reference voltage and a feedback voltage, and transmit the control voltage to the level conversion circuit so that the level conversion circuit can obtain the control voltage. In this way, the level conversion circuit can convert the control voltage to the voltage domain of the first drive circuit, so that the control voltage can control the input voltage of the first drive circuit. Furthermore, the control circuit can use the control voltage to control the turn-on voltage of the first power tube to control the input current, or output current, or output voltage, thereby changing the impedance of the switched capacitor converter. This can prevent the switched capacitor converter from experiencing overvoltage, overcurrent, or other dangerous operating conditions under abnormal operating conditions.

Description

Technical Field

[0001] The present application relates to the technical field of power management chips, and in particular to a control circuit, a switched capacitor converter, a chip, and an electronic device. Background Art

[0002] A switched capacitor converter (also known as a charge pump) can convert an input voltage into a first output voltage and a second output voltage to meet load requirements. Since switched capacitor converters are typically used in high-power charging applications, they often require limiting their input current, output current, or output voltage. Otherwise, the switching power converter may experience overvoltage, overcurrent, or other dangerous operating conditions due to heat generation under abnormal operating conditions. Summary of the Invention

[0003] The present application provides a control circuit, a switched capacitor converter, a chip, and an electronic device that can control the input current, output current, or output voltage to avoid overvoltage and overcurrent problems or other dangerous operating conditions in the switched capacitor converter under abnormal working conditions.

[0004] In a first aspect, the present application provides a control circuit, which is applied to a switched capacitor converter, wherein the switched capacitor converter includes: a first power transistor and a first drive circuit. The control circuit includes: a control voltage output circuit and a level conversion circuit;

[0005] The first input terminal of the control voltage output circuit is used to receive a reference voltage, and the second input terminal of the control voltage output circuit is used to receive a feedback voltage, wherein the feedback voltage is used to represent a conversion condition of an input current, an output current, or an output voltage of the switched capacitor converter. The output terminal of the control voltage output circuit is electrically connected to the input terminal of the level conversion circuit, the output terminal of the level conversion circuit is electrically connected to the input terminal of the first drive circuit, the output terminal of the first drive circuit is electrically connected to the gate of the first power transistor, and the ground terminal of the first drive circuit is electrically connected to the source of the first power transistor.

[0006] The control voltage output circuit is configured to obtain a control voltage according to the reference voltage and the feedback voltage, and transmit the control voltage to the level conversion circuit, wherein the control voltage is used to control the input voltage of the first driving circuit;

[0007] The level conversion circuit is used to convert the control voltage into the voltage domain of the first drive circuit, so that the control circuit uses the control voltage to control the turn-on voltage of the first power tube to control the input current, or the output current, or the output voltage.

[0008] Through the control circuit provided in the first aspect, the control voltage output circuit can obtain a control voltage based on the reference voltage and the feedback voltage, and transmit the control voltage to the level conversion circuit so that the level conversion circuit can obtain the control voltage. In this way, the level conversion circuit can convert the control voltage to the voltage domain where the first drive circuit is located, so that the control voltage can control the input voltage of the first drive circuit. Furthermore, the control circuit can use the control voltage to control the turn-on voltage of the first power tube to control the input current, or output current, or output voltage, and change the impedance of the switched capacitor converter. Thus, it is possible to avoid overvoltage, overcurrent, or other dangerous operating conditions in the switched capacitor converter under abnormal operating conditions.

[0009] In one possible design, the level conversion circuit includes: a current mirror, a voltage conversion current circuit, a first transistor, and a first resistor;

[0010] The input end of the voltage-to-current conversion circuit is electrically connected to the output end of the control voltage output circuit, the output end of the voltage-to-current conversion circuit is electrically connected to the source of the first transistor, the gate of the first transistor is used to receive a control signal, and the control signal is used to control the conduction or shutoff of the first transistor, the drain of the first transistor is electrically connected to the input end of the current mirror, the output end of the current mirror is electrically connected to the first end of the first resistor and the input end of the first drive circuit respectively, and the second end of the first resistor is electrically connected to the ground end of the first drive circuit;

[0011] The voltage-to-current conversion circuit is configured to convert the control voltage into a first current and transmit the first current to the current mirror via the first transistor;

[0012] The current mirror is used to mirror the first current to the first resistor so that the voltage across the first resistor is the control voltage, and the control voltage is within the voltage domain.

[0013] In one possible design, the voltage-to-current conversion circuit includes: a second transistor and a second resistor;

[0014] The gate of the second transistor is electrically connected to the output end of the control voltage output circuit, the drain of the second transistor is electrically connected to the source of the first transistor, the source of the second transistor is electrically connected to the first end of the second resistor, and the second end of the second resistor is grounded.

[0015] In one possible design, the current mirror includes: a first P-type transistor and a second P-type transistor;

[0016] The source of the first P-type transistor and the source of the second P-type transistor are both used to access a first power supply voltage, the gate of the first P-type transistor, the drain of the first P-type transistor and the gate of the second P-type transistor are all electrically connected to the drain of the first transistor, and the drain of the second P-type transistor is electrically connected to the first end of the first resistor.

[0017] In one possible design, the level conversion circuit includes: a charge pump;

[0018] The input end of the charge pump is electrically connected to the output end of the control voltage output circuit, and the output end of the charge pump is electrically connected to the input end of the first driving circuit;

[0019] The charge pump is configured to store charge corresponding to the control voltage using a first capacitor in the charge pump in a first stage, and to release the charge stored in the first capacitor in a second stage, so as to convert the control voltage into the voltage domain.

[0020] In one possible design, the level conversion circuit further includes: a buffer, wherein the unity gain of the buffer is 1;

[0021] The positive phase input terminal of the buffer is electrically connected to the output terminal of the control voltage output circuit, and the negative phase input terminal of the buffer is electrically connected to the output terminal of the buffer and the input terminal of the charge pump respectively;

[0022] The buffer is used to proportionally amplify the control voltage to eliminate interference signals generated by the first switch tube in the charge pump during the on-off process.

[0023] In one possible design, the charge pump includes: a first switch tube, a second switch tube, a third switch tube, a fourth switch tube and a first capacitor;

[0024] A first end of the first switching transistor is electrically connected to the output end of the control voltage output circuit, a second end of the first switching transistor is electrically connected to the first end of the third switching transistor, and a second end of the third switching transistor is electrically connected to the input end of the first drive circuit. A first end of the second switching transistor is grounded, a second end of the second switching transistor is electrically connected to the first end of the fourth switching transistor, and a second end of the fourth switching transistor is electrically connected to the ground end of the first drive circuit. An upper plate of the first capacitor is electrically connected between the second end of the first switching transistor and the first end of the third switching transistor, and a lower plate of the first capacitor is electrically connected between the second end of the second switching transistor and the first end of the fourth switching transistor. Control ends of the first switching transistor, the second switching transistor, the third switching transistor, and the fourth switching transistor are all used to receive control signals, and the control signals are used to control the switching transistors to be turned on or off.

[0025] In one possible design, the level conversion circuit includes: a voltage-to-current conversion circuit, a current mirror, a first voltage output circuit, and an error amplifier;

[0026] A first end of the voltage-to-current conversion circuit is electrically connected to an input end of the current mirror, an input end of the first drive circuit, and an output end of the error amplifier, respectively; a second end of the voltage-to-current conversion circuit is electrically connected to a ground end of the first drive circuit; an output end of the current mirror is electrically connected to an input end of the first voltage output circuit; an output end of the first voltage output circuit is electrically connected to a first input end of the error amplifier; and a second input end of the error amplifier is electrically connected to an output end of the control voltage output circuit;

[0027] The voltage-to-current conversion circuit is configured to convert an input voltage of the first driving circuit into a first current and transmit the first current to the current mirror;

[0028] The current mirror is used to mirror the first current to the first voltage output circuit;

[0029] The first voltage output circuit is configured to generate the first voltage according to the first current and transmit the first voltage to the error amplifier, wherein the first voltage is used to represent a change in the input voltage of the first driving circuit;

[0030] The error amplifier is configured to maintain a stable input voltage of the first driving circuit according to the control voltage and the first voltage, so that the control voltage is converted into the voltage domain.

[0031] In one possible design, the level conversion circuit further includes: a sample-and-hold circuit;

[0032] The input end of the sample and hold circuit is electrically connected to the output end of the first voltage output circuit, and the output end of the sample and hold circuit is electrically connected to the first input end of the error amplifier;

[0033] The sampling and holding circuit is used to sample and hold the first voltage when the first power tube is turned on to obtain a second voltage, and transmit the second voltage to the error amplifier so that the error amplifier keeps the input voltage of the first drive circuit stable based on the control voltage and the second voltage.

[0034] In one possible design, the sample-and-hold circuit includes: a first switch tube and a first capacitor;

[0035] The first end of the first switching tube is electrically connected to the output end of the first voltage output circuit, the control end of the first switching tube is used to receive a first control signal, and the first control signal is used to control the conduction or shutdown of the first switching tube. The second end of the first switching tube is electrically connected to the first input end of the error amplifier, the upper plate of the first capacitor is electrically connected between the second end of the first switching tube and the first input end of the error amplifier, and the lower plate of the first capacitor is grounded.

[0036] In one possible design, the error amplifier includes: a first differential transconductance amplifier, a first P-type transistor, a second P-type transistor, a first transistor, a second transistor, a third transistor, and a fourth transistor;

[0037] The source of the first P-type transistor and the source of the second P-type transistor are both used to access a first power supply voltage. The gate of the first P-type transistor, the drain of the first P-type transistor, and the gate of the second P-type transistor are all electrically connected to the drain of the first transistor. The source of the first transistor is electrically connected to the drain of the third transistor. The drain of the second P-type transistor is electrically connected to the drain of the second transistor and the first end of the voltage-to-current conversion circuit, respectively. The source of the second transistor is electrically connected to the drain of the fourth transistor. The gate of the fourth transistor is electrically connected to the second output end of the first differential transconductance amplifier. The gate of the third transistor is electrically connected to the first output end of the first differential transconductance amplifier. The positive input end of the first differential transconductance amplifier is electrically connected to the output end of the control voltage output circuit. The negative input end of the first differential transconductance amplifier is electrically connected to the output end of the first voltage output circuit. The gate of the first transistor and the gate of the second transistor are both used to access a second control signal. The second control signal is used to control the conduction or shutoff of the first transistor and the second transistor. The source of the third transistor and the source of the fourth transistor are both grounded.

[0038] In one possible design, the first voltage output circuit includes: a fifth transistor and a first resistor;

[0039] The gate of the fifth transistor is electrically connected to the first input terminal of the error amplifier, the drain of the fifth transistor and the output terminal of the current mirror respectively, the source of the fifth transistor is electrically connected to the first end of the first resistor, and the second end of the first resistor is grounded.

[0040] In one possible design, the voltage-to-current conversion circuit includes: a sixth transistor and a second resistor;

[0041] The gate of the sixth transistor is electrically connected to the input end of the first drive circuit and the output end of the error amplifier respectively, the drain of the sixth transistor is electrically connected to the input end of the current mirror, the source of the sixth transistor is electrically connected to the first end of the second resistor, and the second end of the second resistor is electrically connected to the ground end of the first drive circuit.

[0042] In one possible design, the control voltage output circuit includes: a second differential transconductance amplifier, a current source, an N-type transistor, and a second capacitor;

[0043] The positive input terminal of the second differential transconductance amplifier is used to access the reference voltage, the negative input terminal of the second differential transconductance amplifier is used to access the feedback voltage, the output terminal of the second differential transconductance amplifier is electrically connected to the gate of the N-type transistor, the input terminal of the current source is used to access the second power supply voltage, the output terminal of the current source is electrically connected to the drain of the N-type transistor, the upper plate of the second capacitor is electrically connected between the output terminal of the current source and the drain of the N-type transistor, the upper plate of the second capacitor is also electrically connected to the input terminal of the level conversion circuit, and the lower plate of the second capacitor and the source of the N-type transistor are both grounded;

[0044] The second differential transconductance amplifier is configured to control the N-type transistor to be turned on according to the reference voltage and the feedback voltage, so as to convert the voltage difference between the reference voltage and the feedback voltage into a current, thereby generating the control voltage.

[0045] In a second aspect, the present application provides a switched capacitor converter, comprising: a first power transistor, a plurality of second power transistors, a first drive circuit, a plurality of second drive circuits, a plurality of flying capacitors, and the control circuit of the first aspect and any possible design of the first aspect;

[0046] The first driving circuit is used to drive the first power tube to switch between on and off;

[0047] The second driving circuit is used to drive the second power tube to switch between on and off;

[0048] The first power tube and the plurality of second power tubes are configured to control the plurality of flying capacitors to switch between charging and discharging when switching between on and off, so as to convert the input voltage of the switched capacitor converter into a plurality of output voltages;

[0049] The control circuit is used to control the turn-on voltage of the first power tube to control the input current, output current, or output voltage of the switched capacitor converter.

[0050] The beneficial effects of the switched capacitor converter provided in the second aspect and each possible design of the second aspect can be referred to the beneficial effects brought about by the first aspect and each possible implementation method of the first aspect, and will not be repeated here.

[0051] In a third aspect, the present application provides a chip comprising: the control circuit in the above-mentioned first aspect and each possible design of the above-mentioned first aspect, and / or the switched capacitor converter in the above-mentioned first aspect.

[0052] In a fourth aspect, the present application provides an electronic device, comprising: the chip in the third aspect above.

[0053] The above description is only an overview of the technical solutions of the embodiments of the present application. In order to more clearly understand the technical means of the embodiments of the present application, they can be implemented in accordance with the contents of the specification. In order to make the above and other purposes, features and advantages of the embodiments of the present application more obvious and easy to understand, the specific implementation methods of the present application are listed below. BRIEF DESCRIPTION OF THE DRAWINGS

[0054] In order to more clearly illustrate the technical solutions of the embodiments of the present application, a brief introduction will be given below to the drawings required for use in the description of the embodiments. Obviously, the drawings described below are some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0055] Figure 1 A schematic diagram of the structure of a control circuit provided in an embodiment of the present application;

[0056] Figure 2 A schematic diagram of the structure of another control circuit provided in an embodiment of the present application;

[0057] Figure 3 A schematic diagram of the structure of another control circuit provided in an embodiment of the present application;

[0058] Figure 4A schematic diagram of the structure of another control circuit provided in an embodiment of the present application;

[0059] Figure 5 for Figure 1-Figure 4 A schematic diagram of the relationship between the gate voltage of the first power tube and the input voltage of the first driving circuit;

[0060] Figure 6 A schematic structural diagram of a switched capacitor converter provided in an embodiment of the present application. DETAILED DESCRIPTION

[0061] In this application, "at least one" refers to one or more, and "plurality" refers to two or more. "And / or" describes the association relationship of associated objects, indicating that three relationships may exist. For example, A and / or B can represent: the existence of A alone, the existence of A and B at the same time, and the existence of B alone, where A and B can be singular or plural. The character " / " generally indicates that the objects associated before and after are in an "or" relationship. "At least one of the following" or similar expressions refers to any combination of these items, including any combination of single or plural items. For example, at least one of a alone, b alone, or c alone can represent: a alone, b alone, c alone, a and b in combination, a and c in combination, b and c in combination, or a, b, and c in combination, where a, b, and c can be single or multiple. In addition, the terms "first" and "second" are used for descriptive purposes only and are not to be understood as indicating or implying relative importance.

[0062] The directions or positional relationships indicated by terms such as "center", "longitudinal", "lateral", "up", "down", "left", "right", "front", and "back" are based on the directions or positional relationships shown in the accompanying drawings and are only for the convenience of describing the present application and simplifying the description. They do not indicate or imply that the device or element referred to must have a specific direction, be constructed and operated in a specific direction. Therefore, they should not be understood as limiting the present application.

[0063] The terms "connected" and "connect" should be interpreted broadly. For example, "connected" or "connected" in a circuit structure can refer not only to a physical connection, but also to an electrical connection or a signal connection. For example, it can be a direct connection, i.e., a physical connection, or an indirect connection through at least one intermediate component, as long as the circuit is interconnected. It can also refer to internal connectivity between two components. Signal connection can refer not only to signal connection through circuits but also to signal connection through media, such as radio waves. Those skilled in the art will understand the specific meanings of the above terms in this application on a case-by-case basis.

[0064] Reference Figure 1 , Figure 1This is a schematic diagram of the structure of a control circuit provided in an embodiment of the present application. Figure 1 As shown, the control circuit 100 may include: a control voltage output circuit 110 and a level conversion circuit 120 .

[0065] The first input terminal of the control voltage output circuit 110 is used to connect to the reference voltage VREF, and the second input terminal of the control voltage output circuit 110 is used to connect to the feedback voltage VFB. The feedback voltage VFB is used to represent the conversion of the input current, output current, or output voltage of the switched capacitor converter 1000. The output terminal of the control voltage output circuit 110 is electrically connected to the input terminal of the level conversion circuit 120, and the output terminal of the level conversion circuit 120 is electrically connected to the input terminal of the first drive circuit 200. The output terminal of the first drive circuit 200 is electrically connected to the gate of the first power tube Q1, and the ground terminal of the first drive circuit 200 is electrically connected to the source of the first power tube Q1.

[0066] The control voltage output circuit 110 and the level conversion circuit 120 may be provided separately or integrated, and this embodiment of the present application does not specifically limit this.

[0067] The feedback voltage VFB is obtained by detecting the input current, output current, or output voltage of the switched capacitor converter 1000 through a corresponding detection circuit.

[0068] The control circuit 100 is a circuit that implements a current stabilization function for the input current or output current of the switched capacitor converter 1000 and a voltage stabilization function for the output voltage of the switched capacitor converter 1000 , that is, a Regulation control circuit.

[0069] The control voltage output circuit 110 can obtain the control voltage VCOMP according to the reference voltage VREF and the feedback voltage VFB, and can transmit the control voltage VCOMP to the level conversion circuit 120 so that the level conversion circuit 120 can obtain the control voltage VCOMP.

[0070] The control voltage VCOMP is used to control the input voltage VC of the first driving circuit 200. That is, the control voltage VCOMP is used to control the voltage difference VC-HVSS between the input voltage VC of the first driving circuit 200 and the voltage HVSS at the ground terminal of the first driving circuit 200. The voltage at the input terminal of the first driving circuit 200 is the input voltage VC of the first driving circuit 200.

[0071] In this way, the level shifter circuit 120 can shift the control voltage VCOMP to the voltage domain of the first driver circuit 200 so that the voltage difference VC-HVSS between the input voltage VC of the first driver circuit 200 and the ground voltage HVSS of the first driver circuit 200 is equal to the control voltage VCOMP.

[0072] Since the maximum gate voltage that the first power transistor Q1 can reach when turned on is the input voltage VC of the first driving circuit 200, and the source voltage of the first power transistor Q1 is equal to the voltage HVSS at the ground terminal of the first driving circuit 200, the control circuit 100 can use the control voltage VCOMP to control the voltage difference VC-HVSS between the input voltage VC of the first driving circuit 200 and the voltage HVSS at the ground terminal of the first driving circuit 200.

[0073] Furthermore, the control circuit 100 can use the control voltage VCOMP to control the turn-on voltage of the first power transistor Q1, thereby controlling the input current, output current, or output voltage, thereby changing the impedance of the switched capacitor converter 1000 and implementing closed-loop negative feedback. This prevents the switched capacitor converter 1000 from experiencing overvoltage, overcurrent, or other dangerous operating conditions under abnormal operating conditions.

[0074] When the feedback voltage VFB represents the conversion of the input current of the switched capacitor converter 1000, the control circuit 100 can use the control voltage VCOMP to control the input current of the switched capacitor converter 1000. When the feedback voltage VFB represents the conversion of the output current of the switched capacitor converter 1000, the control circuit 100 can use the control voltage VCOMP to control the output current of the switched capacitor converter 1000. When the feedback voltage VFB represents the conversion of the output voltage of the switched capacitor converter 1000, the control circuit 100 can use the control voltage VCOMP to control the output voltage of the switched capacitor converter 1000.

[0075] The control circuit, switched capacitor converter, chip, and electronic device provided by the present application can obtain a control voltage based on a reference voltage and a feedback voltage, and transmit the control voltage to a level conversion circuit so that the level conversion circuit can obtain the control voltage. In this way, the level conversion circuit can convert the control voltage to the voltage domain where the first drive circuit is located, so that the control voltage can control the voltage difference between the input voltage of the first drive circuit and the voltage at the ground end of the first drive circuit. Furthermore, the control circuit can use the control voltage to control the turn-on voltage of the first power tube to control the input current, or output current, or output voltage, and change the impedance of the switched capacitor converter. Thus, it is possible to avoid overvoltage, overcurrent, or other dangerous operating conditions in the switched capacitor converter under abnormal working conditions.

[0076] Based on the description of the above embodiments, the level conversion circuit 120 can be implemented in a variety of feasible ways.

[0077] As a feasible implementation of the level conversion circuit 120, refer to Figure 2 , Figure 2 This is a schematic diagram of another control circuit provided in an embodiment of the present application. Figure 2 As shown, the level conversion circuit 120 may include: a current mirror 121, a voltage conversion current circuit 122, a first transistor ML1 and a first resistor R1.

[0078] The input end of the voltage conversion current circuit 122 is electrically connected to the output end of the control voltage output circuit 110, and the output end of the voltage conversion current circuit 122 is electrically connected to the source of the first transistor ML1. The gate of the first transistor ML1 is used to receive a control signal, and the control signal is used to control the conduction or shutdown of the first transistor ML1. The drain of the first transistor ML1 is electrically connected to the input end of the current mirror 121. The output end of the current mirror 121 is electrically connected to the first end of the first resistor R1 and the input end of the first drive circuit 200 respectively. The second end of the first resistor R1 is electrically connected to the ground end of the first drive circuit 200.

[0079] The input end of the voltage-to-current conversion circuit 122 is the input end of the level conversion circuit 120 , and the first end of the first resistor R1 is the output end of the level conversion circuit 120 .

[0080] The first transistor ML1 is a high-voltage transistor, used to withstand a high voltage, ie, a first power supply voltage HVDD.

[0081] The voltage-to-current conversion circuit 122 can convert the control voltage VCOMP into a first current I1 . Furthermore, the voltage-to-current conversion circuit 122 can transmit the first current I1 to the current mirror 121 through the first transistor ML1 , so that the current mirror 121 can obtain the first current I1 .

[0082] In this way, the current mirror 121 can mirror the first current I1 to the first resistor R1, causing the first current I1 to pass through the first resistor R1. Furthermore, the voltage at the first end of the first resistor R1 becomes the input voltage VC of the first driver circuit 200, making the voltage across the first resistor R1 the control voltage VCOMP, which is within the voltage domain. Consequently, the level shifter 120 can shift the control voltage VCOMP to the voltage domain of the first driver circuit 200, achieving analog voltage shifting.

[0083] In summary, the voltage-to-current circuit can convert the control voltage into a first current and transmit the first current to the current mirror via the first transistor, allowing the current mirror to obtain the first current. In this way, the current mirror can mirror the first current to the first resistor, so that the voltage across the first resistor is the control voltage, placing the control voltage within the voltage domain. Consequently, the level conversion circuit can convert the control voltage into the voltage domain.

[0084] Based on the description of the above embodiment, a possible implementation of the voltage-to-current circuit 122 is exemplified. Figure 2 As shown, the voltage-to-current conversion circuit 122 may include: a second transistor MN1 and a second resistor R2.

[0085] The gate of the second transistor MN1 is electrically connected to the output end of the control voltage output circuit 110, the drain of the second transistor MN1 is electrically connected to the source of the first transistor ML1, the source of the second transistor MN1 is electrically connected to the first end of the second resistor R2, and the second end of the second resistor R2 is grounded.

[0086] The gate of the second transistor MN1 is the input terminal of the voltage-to-current conversion circuit 122 , and the drain of the second transistor MN1 is the output terminal of the voltage-to-current conversion circuit 122 .

[0087] Exemplarily, the second transistor MN1 is a depletion-type native transistor.

[0088] The first current I1 can be expressed by formula (1):

[0089] I1=VCOMP / r2 (1)

[0090] Wherein, I1 is the first current, VCOMP is the control voltage, and r2 is the resistance value of the second resistor R2.

[0091] Since the resistance of the first resistor R1 is equal to the resistance of the second resistor R2 , the voltage across the first resistor R1 is the control voltage VCOMP.

[0092] Based on the description of the above embodiment, a possible implementation of the current mirror 121 is exemplified. Figure 2 As shown, the current mirror 121 may include a first P-type transistor MP1 and a second P-type transistor MP2.

[0093] The source of the first P-type transistor MP1 and the source of the second P-type transistor MP2 are both used to access the first power supply voltage HVDD, the gate of the first P-type transistor MP1, the drain of the first P-type transistor MP1, and the gate of the second P-type transistor MP2 are all electrically connected to the drain of the first transistor ML1, and the drain of the second P-type transistor MP2 is electrically connected to the first end of the first resistor R1.

[0094] The drain of the first P-type transistor MP1 is the input end of the current mirror 121 , and the drain of the second P-type transistor MP2 is the output end of the current mirror 121 .

[0095] As another feasible implementation of the level conversion circuit 120, refer to Figure 3 , Figure 3 This is a structural diagram of another control circuit provided in an embodiment of the present application. Figure 3 As shown, the level conversion circuit 120 may include a charge pump 121 .

[0096] An input terminal of the charge pump 121 is electrically connected to an output terminal of the control voltage output circuit 110 , and an output terminal of the charge pump 121 is electrically connected to an input terminal of the first driving circuit 200 .

[0097] The input end of the charge pump 121 is the input end of the level conversion circuit 120 , and the output end of the charge pump 121 is the output end of the level conversion circuit 120 .

[0098] In the first phase, the charge pump 121 can use the first capacitor Cpump in the charge pump 121 to store charge, so that the voltage on the first capacitor Cpump is the control voltage. Furthermore, in the second phase, the charge pump 121 can release the charge stored in the first capacitor Cpump, so that the charge stored in the capacitor Cpump can be transferred between the input voltage VC of the first drive circuit 200 and the voltage HVSS at the ground terminal of the first drive circuit 200. Furthermore, the charge pump 121 can convert the control voltage VCOMP into the voltage domain. Consequently, the level shifter circuit 120 can convert the control voltage VCOMP into the voltage domain.

[0099] In summary, the charge pump can use the first capacitor in the charge pump to store the charge corresponding to the control voltage in the first phase, and release the charge stored in the first capacitor in the second phase, converting the control voltage into the voltage domain. Thus, the level shifting circuit can convert the control voltage into the voltage domain.

[0100] Based on the description of the above embodiment, a possible implementation of the charge pump 121 is exemplified. Figure 3As shown, the charge pump 121 may include: a first switch tube SW1, a second switch tube SW2, a third switch tube SW3, a fourth switch tube SW4 and a first capacitor Cpump.

[0101] A first end of the first switch SW1 is electrically connected to the output end of the control voltage output circuit 110. A second end of the first switch SW1 is electrically connected to the first end of the third switch SW3. The second end of the third switch SW3 is electrically connected to the input end of the first drive circuit 200. A first end of the second switch SW2 is grounded. A second end of the second switch SW2 is electrically connected to the first end of the fourth switch SW4. The second end of the fourth switch SW4 is electrically connected to the ground end of the first drive circuit 200. An upper plate of the first capacitor Cpump is electrically connected between the second end of the first switch SW1 and the first end of the third switch SW3. A lower plate of the first capacitor Cpump is electrically connected between the second end of the second switch SW2 and the first end of the fourth switch SW4. The control ends of the first switch SW1, the second switch SW2, the third switch SW3, and the fourth switch SW4 are all used to receive control signals, which are used to control the conduction or shutdown of the switches.

[0102] The first end of the first switch tube SW1 is the input end of the charge pump 121 , and the second end of the third switch tube SW3 is the output end of the charge pump 121 .

[0103] The first switch transistor SW1 , the second switch transistor SW2 , the third switch transistor SW3 and the fourth switch transistor SW4 may include but are not limited to gallium nitride transistors, insulated gate bipolar transistors and metal-oxide semiconductor field effect transistors.

[0104] For example, when the first switch transistor SW1, the second switch transistor SW2, the third switch transistor SW3, and the fourth switch transistor SW4 are gallium nitride transistors, the control end of the first switch transistor SW1, the control end of the second switch transistor SW2, the control end of the third switch transistor SW3, and the control end of the fourth switch transistor SW4 refer to the gates of the gallium nitride transistors, the first end of the first switch transistor SW1, the first end of the second switch transistor SW2, the first end of the third switch transistor SW3, and the first end of the fourth switch transistor SW4 can be the drain or source of the gallium nitride transistor, and correspondingly, the second end of the first switch transistor SW1, the second end of the second switch transistor SW2, the second end of the third switch transistor SW3, and the second end of the fourth switch transistor SW4 can be the source or drain of the gallium nitride transistor.

[0105] For example, when the first switch transistor SW1, the second switch transistor SW2, the third switch transistor SW3, and the fourth switch transistor SW4 are metal-oxide semiconductor field-effect transistors, the control end of the first switch transistor SW1, the control end of the second switch transistor SW2, the control end of the third switch transistor SW3, and the control end of the fourth switch transistor SW4 refer to the gates of the metal-oxide semiconductor field-effect transistors, the first end of the first switch transistor SW1, the first end of the second switch transistor SW2, the first end of the third switch transistor SW3, and the first end of the fourth switch transistor SW4 may be the drain or source of the metal-oxide semiconductor field-effect transistors, and correspondingly, the second end of the first switch transistor SW1, the second end of the second switch transistor SW2, the second end of the third switch transistor SW3, and the second end of the fourth switch transistor SW4 may be the source or drain of the metal-oxide semiconductor field-effect transistors.

[0106] For example, when the first switch transistor SW1, the second switch transistor SW2, the third switch transistor SW3, and the fourth switch transistor SW4 are field-controlled thyristors, the control end of the first switch transistor SW1, the control end of the second switch transistor SW2, the control end of the third switch transistor SW3, and the control end of the fourth switch transistor SW4 refer to the gates of the field-controlled thyristors, the first end of the first switch transistor SW1, the first end of the second switch transistor SW2, the first end of the third switch transistor SW3, and the first end of the fourth switch transistor SW4 may be the drain or source of the field-controlled thyristors, and correspondingly, the second end of the first switch transistor SW1, the second end of the second switch transistor SW2, the second end of the third switch transistor SW3, and the second end of the fourth switch transistor SW4 may be the source or drain of the field-controlled thyristors.

[0107] In the first phase, the first and second switches SW1 and SW2 are turned on, while the third and fourth switches SW3 and SW4 are turned off. At this point, the first capacitor Cpump can store charge, making the voltage on the first capacitor Cpump equal to the control voltage VCOMP. In the second phase, the first and second switches SW1 and SW2 are turned off, while the third and fourth switches SW3 and SW4 are turned on. At this point, the first capacitor Cpump can release charge, allowing the stored charge to be transferred between the input voltage VC of the first drive circuit 200 and the voltage HVSS at the ground terminal of the first drive circuit 200.

[0108] Based on the description of the above embodiment, a possible implementation of the level conversion circuit 120 is exemplified. Figure 3 As shown, the level conversion circuit 120 may further include a buffer 122 .

[0109] The unity gain of the buffer 122 is 1.

[0110] A positive phase input terminal of the buffer 122 is electrically connected to the output terminal of the control voltage output circuit 110 , and a negative phase input terminal of the buffer 122 is electrically connected to the output terminal of the buffer 122 and the input terminal of the charge pump 121 , respectively.

[0111] The non-inverting input terminal of the buffer 122 is the input terminal of the level conversion circuit 120 , and the output terminal of the charge pump 121 is the output terminal of the level conversion circuit 120 .

[0112] Buffer 122 can proportionally amplify control voltage VCOMP to generate an amplified control voltage Vcomp_b. Because buffer 122 has a unity gain of 1, the amplitude of amplified control voltage Vcomp_b is equal to the amplitude of control voltage VCOMP. This eliminates interference signals during the turn-on and turn-off processes of first switch SW1 in charge pump 121, eliminating interference such as clock feedthrough and improving the control accuracy of control circuit 100.

[0113] As another feasible implementation of the level conversion circuit 120, refer to Figure 4 , Figure 4 This is a structural diagram of another control circuit provided in an embodiment of the present application. Figure 4 As shown, the level conversion circuit 120 may include: a voltage-to-current conversion circuit 121 , a current mirror 122 , a first voltage output circuit 123 and an error amplifier 124 .

[0114] The level conversion circuit 120 is implemented based on negative feedback.

[0115] The first end of the voltage conversion current circuit 121 is electrically connected to the input end of the current mirror 122, the input end of the first drive circuit 200 and the output end of the error amplifier 124 respectively, the second end of the voltage conversion current circuit 121 is electrically connected to the ground end of the first drive circuit 200, the output end of the current mirror 122 is electrically connected to the input end of the first voltage output circuit 123, the output end of the first voltage output circuit 123 is electrically connected to the first input end of the error amplifier 124, and the second input end of the error amplifier 124 is electrically connected to the output end of the control voltage output circuit 110.

[0116] The second input terminal of the error amplifier 124 is the input terminal of the level conversion circuit 120 , and the first terminal of the voltage-to-current conversion circuit 121 is the output terminal of the level conversion circuit 120 .

[0117] The voltage-to-current conversion circuit 121 can convert the input voltage VC of the first driving circuit 200 into a first current I1 . Furthermore, the voltage-to-current conversion circuit 121 can transmit the first current I1 to the current mirror 122 so that the current mirror 122 can obtain the first current I1 .

[0118] In this way, the current mirror 122 can mirror the first current I1 to the first voltage output circuit 123. Thus, the first voltage output circuit 123 can generate a first voltage V1 based on the first current I1. Furthermore, the first voltage output circuit 123 can transmit the first voltage V1 to the error amplifier 124, so that the error amplifier 124 can obtain the first voltage V1.

[0119] The first voltage V1 is used to represent the change of the input voltage VC of the first driving circuit 200 .

[0120] Furthermore, the error amplifier 124 can maintain the voltage difference VC-HVSS stable according to the control voltage VCOMP and the first voltage V1, so that the voltage difference VC-HVSS is equal to the control voltage VCOMP. Thus, the level shifting circuit 120 can convert the control voltage VCOMP into the voltage domain to achieve analog voltage shifting.

[0121] In summary, the voltage-to-current circuit can convert the input voltage of the first drive circuit into a first current and transmit the first current to the current mirror, allowing the current mirror to obtain the first current. In this way, the current mirror can mirror the first current to the first voltage output circuit. In this way, the first voltage output circuit can generate a first voltage based on the first current to represent the change in the input voltage of the first drive circuit, and transmit the first voltage to the error amplifier, allowing the error amplifier to obtain the first voltage. Furthermore, the error amplifier can maintain a stable voltage difference based on the control voltage and the first voltage, thereby converting the control voltage into the voltage domain.

[0122] Based on the description of the above embodiment, a possible implementation of the error amplifier 124 is exemplified. Figure 4 As shown, the error amplifier 124 may include a first differential transconductance amplifier Gm1 , a first P-type transistor MP1 , a second P-type transistor MP2 , a first transistor ML1 , a second transistor ML2 , a third transistor MN1 , and a fourth transistor MN2 .

[0123] The source of the first P-type transistor MP1 and the source of the second P-type transistor MP2 are both used to access the first power supply voltage. The gate of the first P-type transistor MP1, the drain of the first P-type transistor MP1, and the gate of the second P-type transistor MP2 are all electrically connected to the drain of the first transistor ML1. The source of the first transistor ML1 is electrically connected to the drain of the third transistor MN1. The drain of the second P-type transistor MP2 is electrically connected to the drain of the second transistor ML2 and the first end of the voltage conversion current circuit 121 respectively. The source of the second transistor ML2 is electrically connected to the drain of the fourth transistor MN2. The gate of the fourth transistor MN2 is electrically connected to the first differential transconductance amplifier. The second output terminal of Gm1 is electrically connected, the gate of the third transistor MN1 is electrically connected to the first output terminal of the first differential transconductance amplifier Gm1, the positive input terminal of the first differential transconductance amplifier Gm1 is electrically connected to the output terminal of the control voltage output circuit 110, and the negative input terminal of the first differential transconductance amplifier Gm1 is electrically connected to the output terminal of the first voltage output circuit 123. The gate of the first transistor ML1 and the gate of the second transistor ML2 are both used to receive a second control signal, and the second control signal is used to control the conduction or shutoff of the first transistor ML1 and the second transistor ML2. The source of the third transistor MN1 and the source of the fourth transistor MN2 are both grounded.

[0124] The positive input terminal of the first differential transconductance amplifier Gm1 is the second input terminal of the error amplifier 124 , the negative input terminal of the first differential transconductance amplifier Gm1 is the first input terminal of the error amplifier 124 , and the drain of the second P-type transistor MP2 is the output terminal of the error amplifier 124 .

[0125] The first transistor ML1 and the second transistor ML2 are high-voltage transistors and are used to withstand a high voltage, ie, a first power supply voltage HVDD.

[0126] Based on the description of the above embodiment, a possible implementation of the first voltage output circuit 123 is exemplified. Figure 4 As shown, the first voltage output circuit 123 may include: a fifth transistor MN3 and a first resistor R1.

[0127] The gate of the fifth transistor MN3 is electrically connected to the first input terminal of the error amplifier 124, the drain of the fifth transistor MN3 and the output terminal of the current mirror 122 respectively. The source of the fifth transistor MN3 is electrically connected to the first end of the first resistor R1. The second end of the first resistor R1 is grounded.

[0128] The drain of the fifth transistor MN3 is the input terminal of the first voltage output circuit 123 , and the gate of the fifth transistor MN3 is the output terminal of the first voltage output circuit 123 .

[0129] The first current I1 can generate a first voltage V1 after passing through the fifth transistor MN3 and the first resistor R1. The first voltage V1 can be expressed by formula (2):

[0130] V1=I1*r1+Vth1 (2)

[0131] Wherein, V1 is the first voltage, I1 is the first current, r1 is the resistance of the first resistor R1, and Vth1 is the threshold voltage of the fifth transistor MN3.

[0132] Based on the description of the above embodiment, a possible implementation of the voltage-to-current circuit 121 is exemplified. Figure 4 As shown, the voltage-to-current conversion circuit 121 may include: a sixth transistor MN4 and a second resistor R2.

[0133] A gate of the sixth transistor MN4 is electrically connected to the input terminal of the first driving circuit 200 and the output terminal of the error amplifier 124, respectively. A drain of the sixth transistor MN4 is electrically connected to the input terminal of the current mirror 122. A source of the sixth transistor MN4 is electrically connected to the first end of the second resistor R2. A second end of the second resistor R2 is electrically connected to the ground terminal of the first driving circuit 200.

[0134] The gate of the sixth transistor MN4 is the first terminal of the voltage-to-current conversion circuit 121 , and the second terminal of the second resistor R2 is the second terminal of the voltage-to-current conversion circuit 121 .

[0135] The input voltage VC of the first driving circuit 200 can be converted into a first current I1 through the sixth transistor MN4 and the second resistor R2. The first current I1 can be expressed by formula (3):

[0136] I1=(VC-Vth2) / r2 (3)

[0137] Wherein, I1 is the first current, VC is the input voltage of the first driving circuit 200 , Vth2 is the threshold voltage of the sixth transistor MN4 , and r2 is the resistance value of the second resistor R2 .

[0138] Since the resistance of the first resistor R1 is equal to the resistance of the second resistor R2 , the first voltage V1 is equal to the input voltage VC of the first driving circuit 200 .

[0139] Based on the description of the above embodiment, another possible implementation of the level conversion circuit 120 is exemplified. Figure 4 As shown, the level conversion circuit 120 may further include a sample and hold circuit 125 .

[0140] An input terminal of the sample and hold circuit 125 is electrically connected to an output terminal of the first voltage output circuit 123 , and an output terminal of the sample and hold circuit 125 is electrically connected to a first input terminal of the error amplifier 124 .

[0141] When the first power transistor Q1 is turned on, the sample-and-hold circuit 125 can sample and hold the first voltage V1 to obtain a second voltage V2. Furthermore, the sample-and-hold circuit 125 can transmit the second voltage V2 to the error amplifier 124, allowing the error amplifier 124 to obtain the second voltage V2. In this way, the error amplifier 124 can maintain a stable voltage difference VC-HVSS based on the control voltage VCOMP and the second voltage V2, thereby improving the stability of the error amplifier 124. This improves the control accuracy of the control circuit 100 over the turn-on voltage of the first power transistor Q1.

[0142] Based on the description of the above embodiment, a possible implementation of the sampling and holding circuit 125 is exemplified. Figure 4 As shown, the sample and hold circuit 125 may include: a first switch tube S1 and a first capacitor C1.

[0143] A first end of the first switch tube S1 is electrically connected to the output end of the first voltage output circuit 123. A control end of the first switch tube S1 is used to receive a first control signal, and the first control signal is used to control the conduction or shutdown of the first switch tube S1. A second end of the first switch tube S1 is electrically connected to the first input end of the error amplifier 124. An upper plate of the first capacitor C1 is electrically connected between the second end of the first switch tube S1 and the first input end of the error amplifier 124. A lower plate of the first capacitor C1 is grounded.

[0144] The first end of the first switch tube S1 is the input end of the sample and hold circuit 125 , and the upper plate of the first capacitor C1 is the output end of the sample and hold circuit 125 .

[0145] Based on the description of the above embodiment, a possible implementation of the control voltage output circuit 110 is exemplified. Figure 1-3 As shown, the control voltage output circuit 110 may include: a second differential transconductance amplifier Gm2 , a current source 111 , an N-type transistor N1 , and a second capacitor Cp.

[0146] The positive input terminal of the second differential transconductance amplifier Gm2 is used to access the reference voltage VREF, the negative input terminal of the second differential transconductance amplifier Gm2 is used to access the feedback voltage VFB, the output terminal of the second differential transconductance amplifier Gm2 is electrically connected to the gate of the N-type transistor N1, the input terminal of the current source 111 is used to access the second power supply voltage VDD, the output terminal of the current source 111 is electrically connected to the drain of the N-type transistor N1, the upper plate of the second capacitor Cp is electrically connected between the output terminal of the current source 111 and the drain of the N-type transistor N1, the upper plate of the second capacitor Cp is also electrically connected to the input terminal of the level conversion circuit 120, and the lower plate of the second capacitor Cp and the source of the N-type transistor N1 are both grounded.

[0147] Among them, the positive input terminal of the second differential transconductance amplifier Gm2 is the first input terminal of the control voltage output circuit 110, the negative input terminal of the second differential transconductance amplifier Gm2 is the second input terminal of the control voltage output circuit 110, and the upper plate of the second capacitor Cp is the output terminal of the control voltage output circuit 110.

[0148] The second differential transconductance amplifier Gm2 amplifies the voltage difference between the reference voltage VREF and the feedback voltage VFB and controls the N-type transistor N1 to conduct. Thus, the voltage difference between the reference voltage VREF and the feedback voltage VFB is converted into a current and compared with the reference current output by the current source 111 to generate the control voltage VCOMP.

[0149] Based on the description of the above embodiment, a possible implementation of the first driving circuit 200 is exemplified. Figure 1-4 As shown, the first driving circuit 200 may include a transistor MPB, a transistor MNA, a transistor MNB and a capacitor C1.

[0150] The source of the transistor MPB is used to access the first power supply voltage HVDD, the drain of the transistor MPB is electrically connected to the drain of the transistor MNA, the gate of the transistor MNA is electrically connected to the output end of the level conversion circuit 120, the source of the transistor MNA is electrically connected to the drain of the transistor MNB, the upper plate of the capacitor C1 is electrically connected between the gate of the transistor MNA and the output end of the level conversion circuit 120, and the lower plate of the capacitor C1 and the source of the transistor MNB are both electrically connected to the source of the first power tube Q1.

[0151] The following combination Figure 5 , Figure 5 for Figure 1-Figure 4 Schematic diagram of the relationship between the gate voltage of the first power tube and the input voltage of the first driving circuit. Detailed description of the relationship between the gate voltage VGATE of the first power tube Q1 and the input voltage VC of the first driving circuit 200. The content is as follows:

[0152] like Figure 5 As shown, when the first power tube Q1 is turned on, the transistor MPB is turned on and the transistor MNB is turned off, so that the gate voltage VGATE of the first power tube Q1 increases, and the maximum voltage that the gate voltage VGATE of the first power tube Q1 can reach is the input voltage VC of the first driving circuit 200.

[0153] When the first power transistor Q1 is turned off, the transistor MPB is turned off and the transistor MNB is turned on, so that the gate voltage VGATE of the first power transistor Q1 decreases and is pulled down to the voltage HVSS of the ground terminal of the first driving circuit 200 .

[0154] The present application also provides a switched capacitor converter 1000. Figure 6 , Figure 6 This is a schematic diagram of the structure of a switched capacitor converter provided in an embodiment of the present application. Figure 6 As shown, the switched capacitor converter 1000 may include: a first power transistor Q1 , a plurality of second power transistors, a first drive circuit 200 , a plurality of second drive circuits, a plurality of flying capacitors CF, and a control circuit 100 .

[0155] The first driving circuit 200 can drive the first power tube Q1 to switch between on and off.

[0156] The second driving circuit can drive the second power tube to switch between on and off.

[0157] When the first power tube Q1 and the plurality of second power tubes are switched between on and off, the plurality of flying capacitors CF can be controlled to switch between charging and discharging, so as to convert the input voltage of the switched capacitor converter 1000 into a plurality of output voltages.

[0158] The control circuit 100 can control the turn-on voltage of the first power transistor Q1 to control the input current, output current, or output voltage of the switched capacitor converter 1000 .

[0159] The plurality of flying capacitors CF may include a flying capacitor CF1A, a flying capacitor CF1B, a flying capacitor CF2A, and a flying capacitor CF2B.

[0160] There are two first power transistors Q1, namely the first power transistor Q1A and the first power transistor Q1B. Correspondingly, there are two first drive circuits 200 and two control circuits 100. For ease of explanation, Figure 6 Only the first driving circuit 100 corresponding to the first power tube Q1B and the control circuit 100 are shown.

[0161] Among them, the multiple second power tubes may include: power tube Q2A, power tube Q2B, power tube Q3A, power tube Q3B, power tube Q4A, power tube Q4B, power tube Q5A, power tube Q5B, power tube Q6A, power tube Q6B, power tube Q7A, power tube Q7B, power tube Q8A and power tube Q8B.

[0162] The drain of the first power tube Q1A and the drain of the first power tube Q1B are both used to access the input voltage VIN of the switched capacitor converter 1000. The source of the first power tube Q1B is electrically connected to the drain of the power tube Q3B, the source of the power tube Q3B is electrically connected to the drain of the power tube Q5B, the source of the first power tube Q1B is electrically connected to the drain of the power tube Q3A, the source of the power tube Q3A is electrically connected to the drain of the power tube Q5A, and the source of the power tube Q2A is electrically connected to the drain of the power tube Q3B. The first output terminal O1 of the switched capacitor converter 1000 is electrically connected between the source of the power tube Q3B and the drain of the power tube Q5B. The first output terminal O1 of the switched capacitor converter 1000 is also electrically connected between the source of the power tube Q3A and the drain of the power tube Q5A.

[0163] A first plate of flying capacitor CF1A is electrically connected between the source of the first power transistor Q1B and the drain of the power transistor Q3B. A second plate of flying capacitor CF1A is electrically connected between the drain of the power transistor Q2A and the source of the power transistor Q4A. A first plate of flying capacitor CF1B is electrically connected between the source of the first power transistor Q1B and the drain of the power transistor Q3A. A second plate of flying capacitor CF1B is electrically connected between the drain of the power transistor Q2B and the source of the power transistor Q4B.

[0164] The drain of the power transistor Q4A is electrically connected to the first plate of the flying capacitor CF2A, the second plate of the flying capacitor CF2A is electrically connected to the drain of the power transistor Q8A, the source of the power transistor Q8A is grounded, the source of the power transistor Q5A and the drain of the power transistor Q6A are both electrically connected between the drain of the power transistor Q4A and the first plate of the flying capacitor CF2A, the source of the power transistor Q7A is electrically connected between the second plate of the flying capacitor CF2A and the drain of the power transistor Q8A, and the source of the power transistor Q6A and the drain of the power transistor Q7A are both electrically connected to the second output terminal O2 of the switched capacitor converter 1000.

[0165] The drain of the power tube Q4B is electrically connected to the first plate of the flying capacitor CF2B, the second plate of the flying capacitor CF2B is electrically connected to the source of the power tube Q8B, the source of the power tube Q8B is grounded, the source of the power tube Q5B and the drain of the power tube Q6B are both electrically connected between the drain of the power tube Q4B and the first plate of the flying capacitor CF2B, the source of the power tube Q7B is electrically connected between the second plate of the flying capacitor CF2B and the source of the power tube Q8B, and the source of the power tube Q6B and the drain of the power tube Q7B are both electrically connected to the second output terminal O2 of the switched capacitor converter 1000.

[0166] The gate of the first power tube Q1 is electrically connected to the output end of the first driving circuit 200 , and the gate of the second power tube is electrically connected to the gate of the second driving circuit.

[0167] exist Figure 6 In the figure, CF1HA represents the first plate voltage of flying capacitor CF1A, CF1LA represents the second plate voltage of flying capacitor CF1A. CF1HB represents the first plate voltage of flying capacitor CF1B, and CF1LB represents the second plate voltage of flying capacitor CF1B. CF2HA represents the first plate voltage of flying capacitor CF2A, CF2LA represents the second plate voltage of flying capacitor CF2A. CF2HB represents the first plate voltage of flying capacitor CF2B, and CF2LB represents the second plate voltage of flying capacitor CF2B.

[0168] When the first power transistor Q1 is the first power transistor Q1A, the voltage HVSS at the ground terminal of the first driving circuit 200 is the second plate voltage CF1LB of the flying capacitor CF1B. When the first power transistor Q1 is the first power transistor Q1B, the voltage HVSS at the ground terminal of the first driving circuit 200 is the first plate voltage CF1HA of the flying capacitor CF1A.

[0169] In the first phase Φ1, the first power tube Q1B, the power tube Q2B, the power tube Q6B, the power tube Q8B, the power tube Q3A, the power tube Q4A, the power tube Q5A and the power tube Q7A are turned on; the first power tube Q1A, the power tube Q2A, the power tube Q8A, the power tube Q3B, the power tube Q4B, the power tube Q5B and the power tube Q7B are turned off.

[0170] In the second phase Φ2, the first power tube Q1B, the power tube Q2B, the power tube Q6B, the power tube Q8B, the power tube Q3A, the power tube Q4A, the power tube Q5A and the power tube Q7A are turned off; the first power tube Q1A, the power tube Q2A, the power tube Q8A, the power tube Q3B, the power tube Q4B, the power tube Q5B and the power tube Q7B are turned on.

[0171] In the case where there is no load on the first output terminal O1 and the second output terminal O2, the bus voltage, input voltage, first output voltage and second output voltage of the switched capacitor converter 1000 can be expressed by formula (4):

[0172] VBUS=VIN=2*VO1=4*VO2 (4)

[0173] VBUS is the bus voltage of the switching power converter 1000 , VIN is the input voltage, VO1 is the first output voltage, and VO2 is the second output voltage.

[0174] The first output voltage is the voltage of the first output terminal O1 , the second output voltage is the voltage of the second output terminal O2 , and the input voltage is the voltage of the input terminal of the switched capacitor converter 1000 .

[0175] In some examples, the switched capacitor converter 1000 may further include: a switch tube QB.

[0176] The source of the switch tube QB is used to access the bus voltage VBUS, and the drain of the switch tube QB is electrically connected to the input voltage VIN.

[0177] The parasitic diode of the switch tube QB is directed from the bus voltage VBUS to the input voltage VIN.

[0178] When the switched capacitor converter 1000 is operating normally, the switch QB is turned on. When the switched capacitor converter 1000 is operating abnormally, the switch QB is turned off to prevent a reverse current path from the input voltage VIN to the bus voltage VBUS.

[0179] The present application also provides a chip, including: Figure 1-4 The control circuit 100 provided in the embodiment, and / or, Figure 6 The embodiment provides a switched capacitor converter 1000 .

[0180] The control circuit and the switched capacitor converter may be integrated into one chip or into different chips, which is not specifically limited in the embodiments of the present application.

[0181] The chip provided in the embodiment of the present application has the same beneficial effects as the drive control circuit provided in the embodiment of the present application, and will not be repeated here.

[0182] An embodiment of the present application also provides an electronic device, including: a chip.

[0183] In this application, electronic devices may include but are not limited to: tablet computers, sensors, medical devices and wireless communication devices.

[0184] The electronic device provided in the embodiment of the present application has the same beneficial effects as the chip provided in the embodiment of the present application, which will not be repeated here.

[0185] Finally, it should be noted that the above embodiments are merely specific implementations of this application, but the scope of protection of this application is not limited thereto. Any changes or substitutions within the technical scope disclosed in this application should be included in the scope of protection of this application. Therefore, the scope of protection of this application should be based on the scope of protection of the claims.

Claims

1. A control circuit, characterized in that: The control circuit is applied to a switched capacitor converter, and the switched capacitor converter includes: a first power tube and a first drive circuit; the control circuit includes: a control voltage output circuit and a level conversion circuit; The first input terminal of the control voltage output circuit is used to receive a reference voltage, and the second input terminal of the control voltage output circuit is used to receive a feedback voltage, wherein the feedback voltage is used to represent a conversion condition of an input current, an output current, or an output voltage of the switched capacitor converter. The output terminal of the control voltage output circuit is electrically connected to the input terminal of the level conversion circuit, the output terminal of the level conversion circuit is electrically connected to the input terminal of the first drive circuit, the output terminal of the first drive circuit is electrically connected to the gate of the first power transistor, and the ground terminal of the first drive circuit is electrically connected to the source of the first power transistor. The control voltage output circuit is configured to obtain a control voltage according to the reference voltage and the feedback voltage, and transmit the control voltage to the level conversion circuit, wherein the control voltage is used to control the input voltage of the first driving circuit; The level conversion circuit is used to convert the control voltage into the voltage domain of the first drive circuit, so that the control circuit uses the control voltage to control the turn-on voltage of the first power tube to control the input current, or the output current, or the output voltage.

2. The control circuit according to claim 1, wherein: The level conversion circuit includes: a current mirror, a voltage conversion current circuit, a first transistor and a first resistor; The input end of the voltage-to-current conversion circuit is electrically connected to the output end of the control voltage output circuit, the output end of the voltage-to-current conversion circuit is electrically connected to the source of the first transistor, the gate of the first transistor is used to receive a control signal, and the control signal is used to control the conduction or shutoff of the first transistor, the drain of the first transistor is electrically connected to the input end of the current mirror, the output end of the current mirror is electrically connected to the first end of the first resistor and the input end of the first drive circuit respectively, and the second end of the first resistor is electrically connected to the ground end of the first drive circuit; The voltage-to-current conversion circuit is configured to convert the control voltage into a first current and transmit the first current to the current mirror via the first transistor; The current mirror is used to mirror the first current to the first resistor so that the voltage across the first resistor is the control voltage, and the control voltage is within the voltage domain.

3. The control circuit according to claim 2, characterized in that: The voltage-to-current conversion circuit includes: a second transistor and a second resistor; The gate of the second transistor is electrically connected to the output end of the control voltage output circuit, the drain of the second transistor is electrically connected to the source of the first transistor, the source of the second transistor is electrically connected to the first end of the second resistor, and the second end of the second resistor is grounded.

4. The control circuit according to claim 2, characterized in that: The current mirror comprises: a first P-type transistor and a second P-type transistor; The source of the first P-type transistor and the source of the second P-type transistor are both used to access a first power supply voltage, the gate of the first P-type transistor, the drain of the first P-type transistor and the gate of the second P-type transistor are all electrically connected to the drain of the first transistor, and the drain of the second P-type transistor is electrically connected to the first end of the first resistor.

5. The control circuit according to claim 1, wherein: The level conversion circuit includes: a charge pump; The input end of the charge pump is electrically connected to the output end of the control voltage output circuit, and the output end of the charge pump is electrically connected to the input end of the first driving circuit; The charge pump is configured to store charge corresponding to the control voltage using a first capacitor in the charge pump in a first stage, and to release the charge stored in the first capacitor in a second stage, so as to convert the control voltage into the voltage domain.

6. The control circuit according to claim 5, characterized in that: The level conversion circuit further includes: a buffer, wherein the unit gain of the buffer is 1; The positive phase input terminal of the buffer is electrically connected to the output terminal of the control voltage output circuit, and the negative phase input terminal of the buffer is electrically connected to the output terminal of the buffer and the input terminal of the charge pump respectively; The buffer is used to proportionally amplify the control voltage to eliminate interference signals generated by the first switch tube in the charge pump during the on-off process.

7. The control circuit according to claim 5, characterized in that: The charge pump includes: a first switch tube, a second switch tube, a third switch tube, a fourth switch tube and a first capacitor; A first end of the first switching transistor is electrically connected to the output end of the control voltage output circuit, a second end of the first switching transistor is electrically connected to the first end of the third switching transistor, and a second end of the third switching transistor is electrically connected to the input end of the first drive circuit. A first end of the second switching transistor is grounded, a second end of the second switching transistor is electrically connected to the first end of the fourth switching transistor, and a second end of the fourth switching transistor is electrically connected to the ground end of the first drive circuit. An upper plate of the first capacitor is electrically connected between the second end of the first switching transistor and the first end of the third switching transistor, and a lower plate of the first capacitor is electrically connected between the second end of the second switching transistor and the first end of the fourth switching transistor. Control ends of the first switching transistor, the second switching transistor, the third switching transistor, and the fourth switching transistor are all used to receive control signals, and the control signals are used to control the switching transistors to be turned on or off.

8. The control circuit according to claim 1, wherein: The level conversion circuit includes: a voltage-to-current conversion circuit, a current mirror, a first voltage output circuit and an error amplifier; A first end of the voltage-to-current conversion circuit is electrically connected to an input end of the current mirror, an input end of the first drive circuit, and an output end of the error amplifier, respectively; a second end of the voltage-to-current conversion circuit is electrically connected to a ground end of the first drive circuit; an output end of the current mirror is electrically connected to an input end of the first voltage output circuit; an output end of the first voltage output circuit is electrically connected to a first input end of the error amplifier; and a second input end of the error amplifier is electrically connected to an output end of the control voltage output circuit; The voltage-to-current conversion circuit is configured to convert an input voltage of the first driving circuit into a first current and transmit the first current to the current mirror; The current mirror is used to mirror the first current to the first voltage output circuit; The first voltage output circuit is configured to generate the first voltage according to the first current and transmit the first voltage to the error amplifier, wherein the first voltage is used to represent a change in the input voltage of the first driving circuit; The error amplifier is configured to maintain a stable input voltage of the first driving circuit according to the control voltage and the first voltage, so that the control voltage is converted into the voltage domain.

9. The control circuit according to claim 8, characterized in that: The level conversion circuit further includes: a sampling and holding circuit; The input end of the sample and hold circuit is electrically connected to the output end of the first voltage output circuit, and the output end of the sample and hold circuit is electrically connected to the first input end of the error amplifier; The sampling and holding circuit is used to sample and hold the first voltage when the first power tube is turned on to obtain a second voltage, and transmit the second voltage to the error amplifier so that the error amplifier keeps the input voltage of the first drive circuit stable based on the control voltage and the second voltage.

10. The control circuit according to claim 9, characterized in that: The sampling and holding circuit includes: a first switch tube and a first capacitor; The first end of the first switching tube is electrically connected to the output end of the first voltage output circuit, the control end of the first switching tube is used to receive a first control signal, and the first control signal is used to control the conduction or shutdown of the first switching tube. The second end of the first switching tube is electrically connected to the first input end of the error amplifier, the upper plate of the first capacitor is electrically connected between the second end of the first switching tube and the first input end of the error amplifier, and the lower plate of the first capacitor is grounded.

11. The control circuit according to claim 8, characterized in that: The error amplifier includes: a first differential transconductance amplifier, a first P-type transistor, a second P-type transistor, a first transistor, a second transistor, a third transistor and a fourth transistor; The source of the first P-type transistor and the source of the second P-type transistor are both used to access a first power supply voltage. The gate of the first P-type transistor, the drain of the first P-type transistor, and the gate of the second P-type transistor are all electrically connected to the drain of the first transistor. The source of the first transistor is electrically connected to the drain of the third transistor. The drain of the second P-type transistor is electrically connected to the drain of the second transistor and the first end of the voltage-to-current conversion circuit, respectively. The source of the second transistor is electrically connected to the drain of the fourth transistor. The gate of the fourth transistor is electrically connected to the second output end of the first differential transconductance amplifier. The gate of the third transistor is electrically connected to the first output end of the first differential transconductance amplifier. The positive input end of the first differential transconductance amplifier is electrically connected to the output end of the control voltage output circuit. The negative input end of the first differential transconductance amplifier is electrically connected to the output end of the first voltage output circuit. The gate of the first transistor and the gate of the second transistor are both used to access a second control signal. The second control signal is used to control the conduction or shutoff of the first transistor and the second transistor. The source of the third transistor and the source of the fourth transistor are both grounded.

12. The control circuit according to claim 8, characterized in that: The first voltage output circuit includes: a fifth transistor and a first resistor; The gate of the fifth transistor is electrically connected to the first input terminal of the error amplifier, the drain of the fifth transistor and the output terminal of the current mirror respectively, the source of the fifth transistor is electrically connected to the first end of the first resistor, and the second end of the first resistor is grounded.

13. The control circuit according to claim 8, characterized in that: The voltage-to-current conversion circuit includes: a sixth transistor and a second resistor; The gate of the sixth transistor is electrically connected to the input end of the first drive circuit and the output end of the error amplifier respectively, the drain of the sixth transistor is electrically connected to the input end of the current mirror, the source of the sixth transistor is electrically connected to the first end of the second resistor, and the second end of the second resistor is electrically connected to the ground end of the first drive circuit.

14. The control circuit according to any one of claims 1 to 13, characterized in that: The control voltage output circuit includes: a second differential transconductance amplifier, a current source, an N-type transistor and a second capacitor; The positive input terminal of the second differential transconductance amplifier is used to access the reference voltage, the negative input terminal of the second differential transconductance amplifier is used to access the feedback voltage, the output terminal of the second differential transconductance amplifier is electrically connected to the gate of the N-type transistor, the input terminal of the current source is used to access the second power supply voltage, the output terminal of the current source is electrically connected to the drain of the N-type transistor, the upper plate of the second capacitor is electrically connected between the output terminal of the current source and the drain of the N-type transistor, the upper plate of the second capacitor is also electrically connected to the input terminal of the level conversion circuit, and the lower plate of the second capacitor and the source of the N-type transistor are both grounded; The second differential transconductance amplifier is configured to control the N-type transistor to be turned on according to the reference voltage and the feedback voltage, so as to convert the voltage difference between the reference voltage and the feedback voltage into a current, thereby generating the control voltage.

15. A switched capacitor converter, characterized in that: The switched capacitor converter comprises: a first power tube, a plurality of second power tubes, a first drive circuit, a plurality of second drive circuits, a plurality of flying capacitors, and a control circuit according to any one of claims 1 to 14; The first driving circuit is used to drive the first power tube to switch between on and off; The second driving circuit is used to drive the second power tube to switch between on and off; The first power tube and the plurality of second power tubes are configured to control the plurality of flying capacitors to switch between charging and discharging when switching between on and off, so as to convert the input voltage of the switched capacitor converter into a plurality of output voltages; The control circuit is used to control the turn-on voltage of the first power tube to control the input current, output current, or output voltage of the switched capacitor converter.

16. A chip, characterized in that: include: The control circuit according to any one of claims 1 to 14, and / or the switched capacitor converter according to claim 15.

17. An electronic device, characterized in that: include: The chip as claimed in claim 16.

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